Changes between Version 34 and Version 35 of InterconnexionNetworks

Timestamp:

Jun 1, 2011, 4:28:53 PM (13 years ago)

Author:

alain

Comment:

t

InterconnexionNetworks

@@ -60 +60 @@
  * The '''global interconnect''' is implemented as one DSPIN network, supporting two virtual sub-networks, and the coherence sub-network supports a broadcast service for single flit VCI commands. 
 
-=== 3.1  VCI Address generation on the direct network ===
+=== 3.1  VCI address & data on the direct network ===
 
-On the direct network, the addresses are controlled by the software.
+On the direct network, the addresses and data are controlled by the software.
 
 === 3.2  VCI Address generation on the coherence network ===
 
-On the coherence network, the addresses are defined by the hardware with the following policy:
+On the coherence network, the addresses and data are defined by the hardware with the following policy:
+
+For all command packets (update, invalidate, and cleanup), the line index (up to 34 bits if we use 40 bits adresses) is transported in the WDATA and BE fields of the first VCI flit. The WDATA field contains the 32 LSB bits of the line index, and the BE field contain the 2 MSB bits of the line index. The multicast invalidate, broadcast invalidate, and cleanup packets contain one single VCI flit. The multi-cast update packets contain (2+N) flits : the WDATA field of the second flit contains the index of the first word to be updated in the cache line. The following flits (at most 16 flits) contains the values to be written.
 
  * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[3] (0 for INVAL, 1 for UPDATE). DATA/INSTRUCTION caches are distinguished by the bit ADDRESS[2] (0 for DATA, 1 for INSTRUCTION).