Changes between Version 14 and Version 15 of VirtualMemory

Timestamp:

Jun 30, 2009, 10:54:06 AM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -103 +103 @@
 
 The generic MMU is implemented as an hardware component in the L1 cache controller. 
+
 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
 sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes :
@@ -109 +110 @@
  * number of associative ways = 4 ways
 
+The data cache L1 implement a writhe-through policy, in order to simplify the cache-coherence protocol.
+It contains a write-buffer and that is in charge to build write burst, withe the following constraints :
+ * the burst length is variable
+ * the maximal burst length is 8 32 bits words
+ * all addresses in a burst belongs to the same "half cache line" (32 bytes aligned)
+ * each adress in a burst can have a different Byte Ebable value (including the 0 value)
+ 
 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
 These TLBs are implemented as set-associative caches (16 sets of 4 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor. The figure below illustrate the general structure of the TSAR L1 caches.