Changes between Version 25 and Version 26 of VirtualMemory

Timestamp:

Jul 10, 2009, 9:34:32 AM (15 years ago)

Author:

choichil

Comment:

--

VirtualMemory

@@ -104 +104 @@
 == 2.  MMU/processor interface ==
 
-In order to be used with the various (32 bits, single instruction issue) processor cores available in the SoCLib library, the TSAR generic MMU defines a generic processor/MMU interface for daata and instructions. 
+In order to be used with the various (32 bits, single instruction issue) processor cores available in the SoCLib library, the TSAR generic MMU defines a generic processor/MMU interface for data and instructions. 
 
 === 2.1  Instruction MMU interface ===
@@ -123 +123 @@
 }}}
 
-The  addr virtual address is a 32 bits word adress. It is coded on 30 bits. 
+The  addr virtual address is a 32 bits word address. It is coded on 30 bits. 
 
 The possible values for the Execution Mode are defined below :
@@ -153 +153 @@
 }}}
 
-The  addr virtual address is a 32 bits word adress. It is coded on 30 bits. 
+The  addr virtual address is a 32 bits word address. It is coded on 30 bits. 
 
 The wdata field is only significant for be-masked bytes:
@@ -193 +193 @@
 
 The data cache L1 implement a writhe-through policy, in order to simplify the cache-coherence protocol.
-It contains a write-buffer that is in charge to build write burst, withe the following constraints :
+It contains a write-buffer that is in charge to build write burst, with the following constraints :
  * the burst length is variable
  * the maximal burst length is 8 32 bits words
  * all addresses in a burst belongs to the same "half cache line" (32 bytes aligned)
- * each adress in a burst can have a different Byte Ebable value (including the 0 value)
+ * each address in a burst can have a different Byte Enable value (including the 0 value)
  
 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
@@ -223 +223 @@
 The error type is written in the INS_ERROR_TYPE & DATA_ERROR_TYPE registers, as described below:
 
-|| Exeption type                              || code    || cause                                                         || severity ||
+|| Exception type                              || code    || cause                                                         || severity ||
 ||                                                       ||              ||                                                                    ||                      ||
 ||MMU_PT1_UNMAPPED                || 0x001 || Page fault on Table1 (invalid PTE)        || non fatal error ||