Changes between Version 34 and Version 35 of VirtualMemory

Timestamp:

Sep 11, 2009, 10:04:26 AM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -271 +271 @@
 || MMU_IBVAR                          ||  13      || Instruction Bad Virtual Address Register  || R      ||
 || MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register             || R      || 
-
-The MMU Mode Register has four bits and these 16 values are described as below :
+|| MMU_PARAMS                      ||  14      || Caches & TLBs hardware parameters        || R      || 
+
+The MMU_MODE register has four bits and these 16 values are described as below :
 
 ||   MODE3   ||    MODE2   ||     MODE1   ||     MODE0    ||    description                                                                     ||
@@ -293 +294 @@
 ||     1     ||      1     ||      1      ||       0      || Data cache deactivated, TLBs and instruction cache actived                         ||
 ||     1     ||      1     ||      1      ||       1      || TLBs and caches actived                                                            ||
+
+The MMU_PARAMS register define the instruction and data caches & TLBs characteristics:
+  ||NWAYS_TLB_D||NSETS_TLB_D||NWAYS_CAHE_D||NSETS_CACHE_D||NWAYS_TLB_I||NSETS_TLB_I||NWAYS_CAHE_I||NSETS_CACHE_I||NWORDS||
+ * NWAYS_TLB (3 bits) : Ln(number of associative ways for the TLB)
+ * NSETS_TLB (4 bits) : Ln(number of associative ways for the TLB)
+ * NWAYS_CACHE = Ln(number of associative ways for the TLB)
+ * NSETS_CACHE (4 bits) : Ln(number of associative ways for the TLB)
+ * NWORDS_CACHE Ln(number of associative ways for the TLB)