Changes between Version 39 and Version 40 of VirtualMemory

Timestamp:

Oct 29, 2009, 7:01:10 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -223 +223 @@
 
 The hardware MMU can signal exceptions by rising the general instruction_bus_error and data_bus_error signals (for an instruction or data accesss respectively). 
-The access type (Read or Write) and the error type is written in the INS_ERROR_TYPE & DATA_ERROR_TYPE registers, as described below:
+The access type (Read or Write) and the error type is written in the MMU_IETR & MMU_DETR registers, as described below:
 
 || Exception type                                            || code      || cause                                                                                    || severity           ||
@@ -273 +273 @@
 || MMU_PARAMS                      ||  15      || Caches & TLBs hardware parameters        || R      || 
 || MMU_RELEASE                      ||  16      || Generic MMU release number                    || R      ||
+|| MMU_
 
 '''Note''': A change to this table should be kept in sync with https://www.soclib.fr/trac/dev/wiki/Component/Iss2Api
+
+==== 3.3.1 MMU_PTPR ====
 
 The '''MMU_PTPR''' register contains the base address of the currently used first level page table.
@@ -282 +285 @@
 || 00000 || BASE_ADDRESS[39:13] ||
 
-The '''MMU_MODE''' register has four bits and these 16 values are described as below :
-
-||   MODE3   ||    MODE2   ||     MODE1   ||     MODE0    ||    description                                                                     ||
-|| (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) ||                                                                                    ||
-||           ||            ||             ||              ||                                                                                    ||
-||     0     ||      0     ||      0      ||       0      || TLBs and caches deactivated                                                        ||
-||     0     ||      0     ||      0      ||       1      || TLBs and instruction cache deactivated, data cache actived                         ||
-||     0     ||      0     ||      1      ||       0      || TLBs and data cache deactivated, instruction cache actived                         ||
-||     0     ||      0     ||      1      ||       1      || TLBs deactivated, caches actived                                                   ||
-||     0     ||      1     ||      0      ||       0      || Instruction TLB and caches deactivated, data TLB actived                           ||
-||     0     ||      1     ||      0      ||       1      || Instruction TLB and instruction cache deactivated, data TLB and data cache actived ||
-||     0     ||      1     ||      1      ||       0      || Instruction TLB and data cache deactivated, data TLB and instruction cache actived ||
-||     0     ||      1     ||      1      ||       1      || Instruction TLB deactivated, data TLB and caches actived                           ||
-||     1     ||      0     ||      0      ||       0      || Data TLB and caches deactivated, instruction TLB actived                           ||
-||     1     ||      0     ||      0      ||       1      || Data TLB and instruction cache deactivated, instruction TLB and data cache actived ||
-||     1     ||      0     ||      1      ||       0      || Data TLB and data cache deactivated, instruction TLB and instruction cache actived ||
-||     1     ||      0     ||      1      ||       1      || Data TLB deactivated, instruction TLB and caches actived                           ||
-||     1     ||      1     ||      0      ||       0      || Caches deactivated, TLBs actived                                                   ||
-||     1     ||      1     ||      0      ||       1      || Instruction cache deactivated, TLBs and data cache actived                         ||
-||     1     ||      1     ||      1      ||       0      || Data cache deactivated, TLBs and instruction cache actived                         ||
-||     1     ||      1     ||      1      ||       1      || TLBs and caches actived                                                            ||
+=== 3.3.2 MMU_MODE ===
+
+The '''MMU_MODE''' register has four bits and these 16 values are described as below.
+A device is activated when the corresponding bit is set to 1.
+||   MODE3   ||    MODE2   ||     MODE1   ||     MODE0    ||
+|| (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) ||
+
+=== 3.3.3 MMU_ICACHE_FLUSH & MMU_DCACHE_FLUSH ===
+
+Writing any value  in the '''MMU_ICACHE_FLUSH''' register (resp. '''MMU_DCACHE_FLUSH''' register) invalidates all cache lines stored in the  instruction cache (resp. data cache). 
+
+=== 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ===
+
+The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated.
+
+=== 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ===
+
+The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated.
+
+=== 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ===
+
+The value written in the 32 bits '''MMU_ICACHE_PREFETCH''' register (resp. '''MMU_DCACHE_PREFETCH''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) does not contain the corresponding cache line, this cache line is fetched from memory. 
+
+=== 3.3.x MMU_PARAMS ===
 
 The '''MMU_PARAMS''' register define the instruction and data caches & TLBs characteristics :