Changes between Version 40 and Version 41 of VirtualMemory

Timestamp:

Oct 29, 2009, 8:10:38 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -257 +257 @@
 ||                                                ||             ||                                                                         ||            ||
 || MMU_PTPR                           ||    0       || Page Table Pointer Register                       || R/W   ||
-|| MMU_MODE                        ||    1       || Data & Inst TLBs and caches Mode Register                || R/W   ||
+|| MMU_MODE                        ||    1       ||  Mode Register                                             || R/W   ||
 || MMU_ICACHE_FLUSH          ||    2      || Instruction Cache flush                            || W       ||
 || MMU_DCACHE_FLUSH        ||      3       || Data Cache flush                                          || W       ||
@@ -267 +267 @@
 || MMU_DCACHE_PREFETCH ||    9       || Data Cache line prefetch                             || W     ||
 || MMU_SYNC                           ||  10      || Complete pending writes                            || W     ||
-|| MMU_IETR                                ||  11      || Instruction Exception Type Register          || R      ||
+|| MMU_IETR                                ||  11      || Instruction Exception Type Register           || R      ||
 || MMU_DETR                           ||  12      || Data Exception Type Register                        || R      ||
-|| MMU_IBVAR                          ||  13      || Instruction Bad Virtual Address Register  || R      ||
-|| MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register             || R      || 
-|| MMU_PARAMS                      ||  15      || Caches & TLBs hardware parameters        || R      || 
-|| MMU_RELEASE                      ||  16      || Generic MMU release number                    || R      ||
-|| MMU_
+|| MMU_IBVAR                          ||  13      || Instruction Bad Virtual Address Register   || R      ||
+|| MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register               || R      || 
+|| MMU_PARAMS                      ||  15      || Caches & TLBs hardware parameters           || R      || 
+|| MMU_RELEASE                      ||  16      || Generic MMU release number                       || R      ||
+|| MMU_WORD_LO                  ||  17      || Lowest part of a double word                        || R/W ||
+|| MMU_WORD_HI                    ||  18      || Highest part of a double word                        || R/W ||
+|| MMU_DOUBLE_LL                ||  21      ||  Double word linked load                                  || W     ||
+|| MMU_DOUBLE_SC                ||  21      ||  Double word store conditional                       || W     ||
+|| MMU_ICACHE_PA_INV         ||  19      || Instruction cache inval physical adressing    || W    || 
+|| MMU_DCACHE_PA_INV       ||  20      || Data cache inval physical addressing             || W     || 
 
 '''Note''': A change to this table should be kept in sync with https://www.soclib.fr/trac/dev/wiki/Component/Iss2Api
@@ -285 +290 @@
 || 00000 || BASE_ADDRESS[39:13] ||
 
-=== 3.3.2 MMU_MODE ===
+==== 3.3.2 MMU_MODE ====
 
 The '''MMU_MODE''' register has four bits and these 16 values are described as below.
@@ -292 +297 @@
 || (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) ||
 
-=== 3.3.3 MMU_ICACHE_FLUSH & MMU_DCACHE_FLUSH ===
+==== 3.3.3 MMU_ICACHE_FLUSH & MMU_DCACHE_FLUSH ====
 
 Writing any value  in the '''MMU_ICACHE_FLUSH''' register (resp. '''MMU_DCACHE_FLUSH''' register) invalidates all cache lines stored in the  instruction cache (resp. data cache). 
 
-=== 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ===
-
-The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated.
-
-=== 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ===
-
-The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated.
-
-=== 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ===
+==== 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ====
+
+The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor.
+
+==== 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ====
+
+The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor.
+
+==== 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ====
 
 The value written in the 32 bits '''MMU_ICACHE_PREFETCH''' register (resp. '''MMU_DCACHE_PREFETCH''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) does not contain the corresponding cache line, this cache line is fetched from memory. 
-
-=== 3.3.x MMU_PARAMS ===
+This is a non-blocking request for the processor.
+
+==== 3.3.7 MMU_SYNC ====
+
+Writing any value in this '''MMU_SYNC''' register will force execution of posted write requests.
+This is a blocking request for the processor.
+
+==== 3.3.8 MMU_IETR & MMU_DETR ====
+
+MMU exceptions are reported in these two registers, as described in section 3.2.
+
+==== 3.3.9 MMU_IBVAR & MMU_DBVAR ====
+
+Faulty virtual adresses will be written in these two registers. 
+
+==== 3.3.10 MMU_PARAMS ====
 
 The '''MMU_PARAMS''' register define the instruction and data caches & TLBs characteristics :
@@ -323 +342 @@
  * NBL (4 bits) : Ln(number of bytes per Data or Instruction cache line)
 
+==== 3.3.11 MMU_RELEASE ====
+
 The '''MMU_RELEASE''' register contains the release number for a given hardware implementation :
 || SPECIFICATION_INDEX || IMPLEMENTATION_INDEX ||
  * SPECIFICATION_INDEX (16 bits)
  * IMPLEMENTATION_INDEX (16 bits)
+
+==== 3.3.12 MMU_WORD_HI & MMU_WORD_LO ====
+
+The two 32 bits '''MMU_DOUBLE_HI''' & MMU_DOUBLE_LO''' registers implement a double word data storage.
+They are used to support cache line invalidation in physical adressing (section 3.3.15), and to support
+double words LL & SC accesses (section 3.3.13 & section 3.3.14).
+
+==== 3.3.13 MMU_DOUBLE_LL ====
+
+The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking transaction for the processor.
+
+==== 3.4.14 MMU_DOUBLE_SC ====
+
+The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking transaction for the processor. 
+
+==== 3.4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ====
+
+Writing any value in the '''MMU_ICACHE_PA_INV''' register (resp. '''MMU_DCACHE_PA_INV''' register) can invalidate a cache line in the instruction cache (resp. data cache).
+The values stored in the MMU_WORD_HI & MMU_WORD_LO registers is interpreted as a physical address.
+If the instruction cache (resp. data cache) contains a cache line corresponding to this address, it is invalidated.
+This is a blocking request for the processor.
+