[1] | 1 | /* |
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| 2 | * hal_special.c - implementation of Generic Special Register Access API for TSAR-MIPS32 |
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| 3 | * |
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[101] | 4 | * Author Alain Greiner (2016,2017) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH.. |
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| 9 | * |
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| 10 | * ALMOS-MKH. is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH. is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | |
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[457] | 25 | #include <hal_kernel_types.h> |
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[1] | 26 | #include <hal_special.h> |
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[619] | 27 | #include <hal_exception.h> |
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[101] | 28 | #include <core.h> |
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| 29 | #include <thread.h> |
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[1] | 30 | |
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| 31 | /**** Forward declarations ****/ |
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| 32 | |
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| 33 | struct thread_s; |
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| 34 | |
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[623] | 35 | |
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| 36 | ////////////////////////////////////////////////////////////////////////////////// |
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| 37 | // Extern global variables |
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| 38 | ////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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| 40 | extern cxy_t local_cxy; |
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| 41 | extern void hal_kentry_enter( void ); |
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| 42 | |
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| 43 | ///////////////////////////////////////////////////////////////////////////////// |
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| 44 | // For the TSAR architecture, this function register the physical address of |
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| 45 | // the first level page table (PT1) in the PTPR register. |
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| 46 | // It activates the intructions MMU, and de-activates the data MMU. |
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| 47 | ///////////////////////////////////////////////////////////////////////////////// |
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| 48 | void hal_mmu_init( gpt_t * gpt ) |
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| 49 | { |
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| 50 | |
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| 51 | // set PT1 base address in mmu_ptpr register |
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| 52 | uint32_t ptpr = (((uint32_t)gpt->ptr) >> 13) | (local_cxy << 19); |
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| 53 | asm volatile ( "mtc2 %0, $0 \n" : : "r" (ptpr) ); |
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| 54 | |
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| 55 | // set ITLB | ICACHE | DCACHE bits in mmu_mode register |
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| 56 | asm volatile ( "ori $26, $0, 0xB \n" |
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| 57 | "mtc2 $26, $1 \n" ); |
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| 58 | } |
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| 59 | |
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| 60 | //////////////////////////////////////////////////////////////////////////////// |
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| 61 | // For the TSAR architecture, this function registers the address of the |
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| 62 | // hal_kentry_enter() function in the MIPS32 cp0_ebase register. |
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| 63 | //////////////////////////////////////////////////////////////////////////////// |
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| 64 | void hal_set_kentry( void ) |
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| 65 | { |
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| 66 | uint32_t kentry = (uint32_t)(&hal_kentry_enter); |
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| 67 | |
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| 68 | asm volatile("mtc0 %0, $15, 1" : : "r" (kentry) ); |
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| 69 | } |
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| 70 | |
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[570] | 71 | //////////////////////////////// |
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[481] | 72 | inline gid_t hal_get_gid( void ) |
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[1] | 73 | { |
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| 74 | uint32_t proc_id; |
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| 75 | |
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| 76 | asm volatile ("mfc0 %0, $15, 1" : "=&r" (proc_id)); |
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| 77 | |
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[16] | 78 | return (proc_id & 0x3FF); // 4/4/2 format for TSAR |
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[1] | 79 | } |
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| 80 | |
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[570] | 81 | /////////////////////////////////// |
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[481] | 82 | inline reg_t hal_time_stamp( void ) |
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[121] | 83 | { |
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[296] | 84 | reg_t count; |
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[121] | 85 | |
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[279] | 86 | asm volatile ("mfc0 %0, $9" : "=&r" (count)); |
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[121] | 87 | |
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| 88 | return count; |
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| 89 | } |
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| 90 | |
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[570] | 91 | /////////////////////////////// |
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[481] | 92 | inline reg_t hal_get_sr( void ) |
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[279] | 93 | { |
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[296] | 94 | reg_t sr; |
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[279] | 95 | |
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| 96 | asm volatile ("mfc0 %0, $12" : "=&r" (sr)); |
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| 97 | |
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| 98 | return sr; |
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| 99 | } |
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| 100 | |
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[570] | 101 | /////////////////////////////// |
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[481] | 102 | uint64_t hal_get_cycles( void ) |
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[1] | 103 | { |
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[95] | 104 | uint64_t cycles; // absolute time to be returned |
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| 105 | uint32_t last_count; // last registered cycles count |
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| 106 | uint32_t current_count; // current cycles count |
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| 107 | uint32_t elapsed; |
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| 108 | |
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| 109 | core_t * core = CURRENT_THREAD->core; |
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| 110 | |
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| 111 | // get last registered time stamp |
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| 112 | last_count = core->time_stamp; |
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| 113 | |
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| 114 | // get current time stamp from hardware register |
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[121] | 115 | current_count = hal_time_stamp(); |
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[95] | 116 | |
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| 117 | // compute number of elapsed cycles, taking into account 32 bits register wrap |
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| 118 | if(current_count < last_count) elapsed = (0xFFFFFFFF - last_count) + current_count; |
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| 119 | else elapsed = current_count - last_count; |
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| 120 | |
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| 121 | // compute absolute time |
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| 122 | cycles = core->cycles + elapsed; |
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| 123 | |
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| 124 | // update core time |
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| 125 | core->time_stamp = current_count; |
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| 126 | core->cycles = cycles; |
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| 127 | |
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[124] | 128 | hal_fence(); |
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[95] | 129 | |
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[1] | 130 | return cycles; |
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| 131 | } |
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| 132 | |
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[570] | 133 | /////////////////////////////////////////////////////// |
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[481] | 134 | inline struct thread_s * hal_get_current_thread( void ) |
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[1] | 135 | { |
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| 136 | void * thread_ptr; |
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| 137 | |
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[279] | 138 | asm volatile ("mfc0 %0, $4, 2" : "=&r" (thread_ptr)); |
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[1] | 139 | |
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| 140 | return thread_ptr; |
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| 141 | } |
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| 142 | |
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| 143 | /////////////////////////////////////////////////////// |
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| 144 | void hal_set_current_thread( struct thread_s * thread ) |
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| 145 | { |
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[279] | 146 | asm volatile ("mtc0 %0, $4, 2" : : "r" (thread)); |
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[1] | 147 | } |
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| 148 | |
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[570] | 149 | /////////////////////////// |
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[481] | 150 | void hal_fpu_enable( void ) |
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[1] | 151 | { |
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[459] | 152 | // set CU1 bit (FPU enable) in c0_sr |
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[1] | 153 | asm volatile |
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| 154 | ( ".set noat \n" |
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| 155 | "lui $27, 0x2000 \n" |
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| 156 | "mfc0 $1, $12 \n" |
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| 157 | "or $27, $1, $27 \n" |
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| 158 | "mtc0 $27, $12 \n" |
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| 159 | ".set at \n" ); |
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[459] | 160 | |
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| 161 | // set CU1 bit in calling thread UZONE |
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| 162 | uint32_t * uzone = CURRENT_THREAD->uzone_current; |
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| 163 | uzone[34] |= 0x20000000; |
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[1] | 164 | } |
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| 165 | |
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[570] | 166 | //////////////////////////// |
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[481] | 167 | void hal_fpu_disable( void ) |
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[1] | 168 | { |
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[459] | 169 | // reset CU1 bit (FPU enable) in c0_sr |
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[1] | 170 | asm volatile |
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| 171 | ( ".set noat \n" |
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| 172 | "lui $27, 0xDFFF \n" |
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| 173 | "ori $27, $27, 0xFFFF \n" |
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| 174 | "mfc0 $1, $12 \n" |
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| 175 | "and $27, $1, $27 \n" |
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| 176 | "mtc0 $27, $12 \n" |
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| 177 | ".set at \n"); |
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[459] | 178 | |
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| 179 | // reset CU1 bit in calling thread UZONE |
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| 180 | uint32_t * uzone = CURRENT_THREAD->uzone_current; |
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| 181 | uzone[34] &= 0xDFFFFFFF; |
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[1] | 182 | } |
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| 183 | |
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[619] | 184 | /////////////////////////// |
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| 185 | uint32_t hal_get_sp( void ) |
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[1] | 186 | { |
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| 187 | register uint32_t sp; |
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| 188 | |
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[279] | 189 | asm volatile ("or %0, $0, $29" : "=&r" (sp)); |
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[1] | 190 | |
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| 191 | return sp; |
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| 192 | } |
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| 193 | |
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[619] | 194 | ///////////////////////////////////// |
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| 195 | uint32_t hal_set_sp( void * new_val ) |
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[1] | 196 | { |
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| 197 | register uint32_t sp; |
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| 198 | |
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| 199 | asm volatile |
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| 200 | ( "or %0, $0, $29 \n" |
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| 201 | "or $29, $0, %1 \n" |
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| 202 | : "=&r" (sp) : "r" (new_val) ); |
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| 203 | |
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| 204 | return sp; |
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| 205 | } |
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| 206 | |
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[619] | 207 | /////////////////////////// |
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| 208 | uint32_t hal_get_ra( void ) |
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| 209 | { |
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| 210 | register uint32_t ra; |
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| 211 | |
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| 212 | asm volatile ("or %0, $0, $31" : "=&r" (ra)); |
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| 213 | |
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| 214 | return ra; |
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| 215 | } |
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| 216 | |
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[570] | 217 | ////////////////////////////////// |
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[481] | 218 | uint32_t hal_get_bad_vaddr( void ) |
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[1] | 219 | { |
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| 220 | register uint32_t bad_va; |
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| 221 | |
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| 222 | asm volatile |
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| 223 | ( "mfc0 %0, $8 \n" |
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| 224 | : "=&r" (bad_va) ); |
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| 225 | |
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| 226 | return bad_va; |
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| 227 | } |
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| 228 | |
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| 229 | //////////////////////////////////////////// |
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| 230 | uint32_t hal_uncached_read( uint32_t * ptr ) |
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| 231 | { |
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| 232 | register uint32_t val; |
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| 233 | |
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| 234 | asm volatile |
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| 235 | ( "ll %0, (%1) \n" |
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| 236 | : "=&r"(val) : "r" (ptr) ); |
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| 237 | |
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| 238 | return val; |
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| 239 | } |
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| 240 | |
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| 241 | ////////////////////////////////////////// |
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| 242 | void hal_invalid_dcache_line( void * ptr ) |
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| 243 | { |
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| 244 | asm volatile |
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| 245 | ( "cache %0, (%1) \n" |
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| 246 | "sync \n" |
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| 247 | : : "i" (0x11) , "r" (ptr) ); |
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| 248 | } |
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| 249 | |
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[570] | 250 | ///////////////////////////// |
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| 251 | inline void hal_fence( void ) |
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[1] | 252 | { |
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[407] | 253 | asm volatile ("sync"); |
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[1] | 254 | } |
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| 255 | |
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[570] | 256 | ///////////////////////////// |
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| 257 | inline void hal_rdbar( void ) |
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[1] | 258 | { |
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| 259 | asm volatile( "" ::: "memory" ); |
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| 260 | } |
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| 261 | |
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[570] | 262 | /////////////////////////// |
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[481] | 263 | void hal_core_sleep( void ) |
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[1] | 264 | { |
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[624] | 265 | while( 1 ) asm volatile ("wait"); |
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[1] | 266 | } |
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| 267 | |
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| 268 | ////////////////////////////////////// |
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| 269 | void hal_fixed_delay( uint32_t delay ) |
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| 270 | { |
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| 271 | asm volatile |
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[407] | 272 | ( ".set noreorder \n" |
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[1] | 273 | "or $27, %0, $0 \n" |
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[407] | 274 | "1: \n" |
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[1] | 275 | "addi $27, $27, -1 \n" |
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[407] | 276 | "nop \n" |
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[1] | 277 | "bne $27, $0, 1b \n" |
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| 278 | "nop \n" |
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[407] | 279 | ".set reorder \n" |
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| 280 | : : "r" (delay>>2) : "$27" ); |
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[1] | 281 | } |
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| 282 | |
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[16] | 283 | ////////////////////////////////////////////////// |
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| 284 | void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code, |
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| 285 | intptr_t * mmu_ins_bad_vaddr, |
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| 286 | intptr_t * mmu_dat_excp_code, |
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| 287 | intptr_t * mmu_dat_bad_vaddr ) |
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| 288 | { |
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| 289 | asm volatile |
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| 290 | ( "mfc2 %0, $11 \n" |
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| 291 | "mfc2 %1, $13 \n" |
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| 292 | "mfc2 %2, $12 \n" |
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| 293 | "mfc2 %3, $14 \n" |
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[406] | 294 | : "=&r"(*mmu_ins_excp_code), |
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| 295 | "=&r"(*mmu_ins_bad_vaddr), |
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| 296 | "=&r"(*mmu_dat_excp_code), |
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| 297 | "=&r"(*mmu_dat_bad_vaddr) ); |
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[16] | 298 | } |
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[406] | 299 | |
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