Changeset 166


Ignore:
Timestamp:
Jul 10, 2017, 10:14:27 AM (4 years ago)
Author:
max@…
Message:

identify the cpu features

Location:
trunk/hal/x86_64/core
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • trunk/hal/x86_64/core/hal_cpu.S

    r145 r166  
    2323#include <hal_boot.h>
    2424#include <hal_segmentation.h>
     25#include <hal_register.h>
    2526
    2627ASM_ENTRY(lgdt)
     
    99100        ret
    100101
     102ASM_ENTRY(rcr4)
     103        movq    %cr4,%rax
     104        ret
     105
     106ASM_ENTRY(lcr4)
     107        movq    %rdi,%cr4
     108        ret
     109
     110ASM_ENTRY(cpuid)
     111        movq    %rbx,%r8
     112        movq    %rdi,%rax
     113        movq    %rsi,%rcx
     114        movq    %rdx,%rsi
     115        cpuid
     116        movl    %eax,0(%rsi)
     117        movl    %ebx,4(%rsi)
     118        movl    %ecx,8(%rsi)
     119        movl    %edx,12(%rsi)
     120        movq    %r8,%rbx
     121        ret
     122
     123/*
     124 * To flush all TLB entries, we must re-set the CR4_PGE flag in %cr4.
     125 */
     126ASM_ENTRY(tlbflushg)
     127        movq    %cr4,%rax
     128        movq    %rax,%rdx
     129        andq    $~CR4_PGE,%rdx
     130        movq    %rdx,%cr4
     131        movq    %rax,%cr4
     132        ret
     133
     134ASM_ENTRY(tlbflush)
     135        movq    %cr3,%rax
     136        movq    %rax,%cr3
     137        ret
     138
    101139ASM_ENTRY(x86_stop) /* debug only */
    102140        int     $0x0b
  • trunk/hal/x86_64/core/hal_init.c

    r165 r166  
    2727#include <hal_apic.h>
    2828#include <hal_internal.h>
     29#include <hal_register.h>
     30
    2931#include <hal_remote.h>
    3032#include <hal_irqmask.h>
     
    4648static void gdt_create();
    4749static void idt_create();
     50void cpu_identify();
    4851void cpu_attach();
    4952
     
    250253}
    251254
     255/* -------------------------------------------------------------------------- */
     256
    252257void init_x86_64(paddr_t firstpa)
    253258{
     
    262267        gdt_create();
    263268        idt_create();
     269
     270        /* Identify the features of the cpu */
     271        cpu_identify();
    264272
    265273        /* Attach cpu0 */
     
    477485/* -------------------------------------------------------------------------- */
    478486
     487uint64_t cpu_features[4] __in_kdata;
     488
     489void cpu_identify()
     490{
     491        /*
     492         * desc[0] = eax
     493         * desc[1] = ebx
     494         * desc[2] = ecx
     495         * desc[3] = edx
     496         */
     497        uint32_t desc[4];
     498        char vendor[13];
     499        size_t lvl;
     500
     501        /*
     502         * Get information from the standard cpuid leafs
     503         */
     504        cpuid(0, 0, (uint32_t *)&desc);
     505
     506        lvl = (uint64_t)desc[0];
     507        x86_printf("-> cpuid standard level: %z\n", lvl);
     508
     509        memcpy(vendor + 0, &desc[1], sizeof(uint32_t));
     510        memcpy(vendor + 8, &desc[2], sizeof(uint32_t));
     511        memcpy(vendor + 4, &desc[3], sizeof(uint32_t));
     512        vendor[12] = '\0';
     513        x86_printf("-> CPU vendor: '%s'\n", vendor);
     514
     515        if (lvl >= 1) {
     516                cpuid(1, 0, (uint32_t *)&desc);
     517                cpu_features[0] = desc[3];
     518                cpu_features[1] = desc[2];
     519        }
     520
     521        /*
     522         * Get information from the extended cpuid leafs
     523         */
     524        cpuid(0x80000000, 0, desc);
     525
     526        lvl = (uint64_t)desc[0];
     527        x86_printf("-> cpuid extended level: %Z\n", lvl);
     528}
     529
     530/* -------------------------------------------------------------------------- */
     531
    479532void cpu_attach(size_t lid)
    480533{
     
    482535        cpu_load_idt();
    483536        cpu_create_tss(lid);
    484 }
    485 
     537
     538        if (cpu_features[0] & CPUID_PSE) {
     539                lcr4(rcr4() | CR4_PSE);
     540                tlbflushg();
     541        } else {
     542                /*
     543                 * amd64 supports PSE by default, if it's not here we have a
     544                 * problem
     545                 */
     546                x86_panic("PSE not supported");
     547        }
     548}
     549
  • trunk/hal/x86_64/core/hal_internal.h

    r145 r166  
    1616 *
    1717 * You should have received a copy of the GNU General Public License
    18  * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
     18 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
    1919 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
    2020 */
     
    4242void mfence();
    4343vaddr_t rcr2(void);
     44uint64_t rcr4(void);
     45void lcr4(uint64_t);
     46void cpuid(uint32_t eax, uint32_t ecx, uint32_t *desc);
     47void tlbflushg();
     48void tlbflush();
    4449
    4550uint32_t atomic_cas_32(volatile uint32_t *ptr, uint32_t exp, uint32_t new);
  • trunk/hal/x86_64/core/hal_register.h

    r145 r166  
    8787#define         APICBASE_PHYSADDR       0xfffff000      /* physical address */
    8888
     89/*
     90 * CPUID
     91 */
     92/* Fn00000001 %edx features */
     93#define CPUID_FPU       0x00000001      /* processor has an FPU? */
     94#define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
     95#define CPUID_DE        0x00000004      /* has debugging extension */
     96#define CPUID_PSE       0x00000008      /* has 4MB page size extension */
     97#define CPUID_TSC       0x00000010      /* has time stamp counter */
     98#define CPUID_MSR       0x00000020      /* has mode specific registers */
     99#define CPUID_PAE       0x00000040      /* has phys address extension */
     100#define CPUID_MCE       0x00000080      /* has machine check exception */
     101#define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
     102#define CPUID_APIC      0x00000200      /* has enabled APIC */
     103#define CPUID_B10       0x00000400      /* reserved, MTRR */
     104#define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
     105#define CPUID_MTRR      0x00001000      /* has memory type range register */
     106#define CPUID_PGE       0x00002000      /* has page global extension */
     107#define CPUID_MCA       0x00004000      /* has machine check architecture */
     108#define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
     109#define CPUID_PAT       0x00010000      /* Page Attribute Table */
     110#define CPUID_PSE36     0x00020000      /* 36-bit PSE */
     111#define CPUID_PN        0x00040000      /* processor serial number */
     112#define CPUID_CFLUSH    0x00080000      /* CLFLUSH insn supported */
     113#define CPUID_B20       0x00100000      /* reserved */
     114#define CPUID_DS        0x00200000      /* Debug Store */
     115#define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
     116#define CPUID_MMX       0x00800000      /* MMX supported */
     117#define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
     118#define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
     119#define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
     120#define CPUID_SS        0x08000000      /* self-snoop */
     121#define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
     122#define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
     123#define CPUID_IA64      0x40000000      /* IA-64 architecture */
     124#define CPUID_SBF       0x80000000      /* signal break on FERR */
     125
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