Ignore:
Timestamp:
Mar 6, 2019, 4:37:15 PM (3 years ago)
Author:
alain
Message:

Introduce three new types of vsegs (KCODE,KDATA,KDEV)
to map the kernel vsegs in the process VSL and GPT.
This now used by both the TSAR and the I86 architectures.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/hal/tsar_mips32/core/hal_gpt.c

    r611 r623  
    141141#endif
    142142
    143     // check page size
    144     assert( (CONFIG_PPM_PAGE_SIZE == 4096) ,
    145     "for TSAR, the page size must be 4 Kbytes\n" );
     143// check page size
     144assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "for TSAR, the page size must be 4 Kbytes\n" );
    146145
    147146    // allocates 2 physical pages for PT1
     
    287286    vpn_t      vpn;
    288287
    289     assert( (process != NULL) , "NULL process pointer\n");
     288// check argument
     289assert( (process != NULL) , "NULL process pointer\n");
    290290
    291291    // get pointer on gpt
     
    295295    pt1 = (uint32_t *)gpt->ptr;
    296296
    297     printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n",
     297    printk("\n***** Tsar Page Table for process %x : &gpt = %x / &pt1 = %x\n\n",
    298298    process->pid , gpt , pt1 );
    299299
     
    334334
    335335
     336/////////////////////////////////////////////////////////////////////////////////////
     337// FOr the TSAR architecture, this function allocates a first level PT1 (8 Kbytes),
     338// and maps one single big page for the kerne code segment in slot[0].
     339/////////////////////////////////////////////////////////////////////////////////////
     340void hal_gpt_build_kpt( cxy_t   cxy,
     341                        gpt_t * gpt )
     342{
     343    error_t error;
     344
     345    // allocate memory for one gpt
     346    error = hal_gpt_create( gpt );
     347
     348    if( error )
     349    {
     350        printk("\n[PANIC] in %s : cannot allocate kernel GPT in cluster %x\n",
     351        __FUNCTION__ , cxy );
     352        hal_core_sleep();
     353    }
     354
     355    // compute attr and ppn for one PTE1
     356    uint32_t attr  = 0xCA800000;           // bits : V,T,C,X,G
     357    uint32_t ppn   = (cxy << 20) >> 9;
     358
     359    // set PTE1
     360    error = hal_gpt_set_pte( XPTR( cxy , gpt ) , 0 , attr , ppn );
     361
     362    if( error )
     363    {
     364        printk("\n[PANIC] in %s : cannot initialize kernel GPT in cluster %x\n",
     365        __FUNCTION__ , cxy );
     366        hal_core_sleep();
     367    }
     368}
     369
    336370//////////////////////////////////////////
    337371error_t hal_gpt_set_pte( xptr_t    gpt_xp,
     
    390424        if( small == 0 )     // map a big page in PT1
    391425    {
    392         assert( (pte1 == 0) ,
    393                 "try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 );
    394      
     426
     427// check PT1 entry not mapped
     428assert( (pte1 == 0) , "try to set a big page in a mapped PT1 entry\n" );
     429
     430// check VPN aligned
     431assert( (ix2 == 0) , "illegal vpn for a big page\n" );
     432
     433// check PPN aligned
     434assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" );
     435
    395436        // set the PTE1 value in PT1
    396437        pte1 = (tsar_attr  & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
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