Changeset 658 for trunk/hal/tsar_mips32/drivers/soclib_nic.h
- Timestamp:
- Oct 10, 2020, 3:48:50 PM (4 years ago)
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- 1 edited
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trunk/hal/tsar_mips32/drivers/soclib_nic.h (modified) (4 diffs)
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trunk/hal/tsar_mips32/drivers/soclib_nic.h
r451 r658 2 2 * soclib_nic.h - SOCLIB_NIC (Network Interface Controler) driver definition. 3 3 * 4 * Author Alain Greiner (2016 )4 * Author Alain Greiner (2016,2017,2018,2019,2020) 5 5 * 6 6 * Copyright (c) UPMC Sorbonne Universites … … 30 30 /******************************************************************************************** 31 31 * This driver supports the Soclib VciMasterNic component, that is a GMII compliant 32 * multi-channels Gigabit Ethernet controler. 33 * 34 * The VciMasterNic component supports up to 4 channels, indexed by the source IP address 35 * for the RX packets, and by the destination IP address for the TX packets. 32 * multi-channels Gigabit Ethernet controler with a DMA capability. 33 * 34 * To improve the throughput, this component supports several channels. 35 * The channel index is derived from the (source) remote IP address and port 36 * for the received (RX) packets, and from the (destination) remote IP address 37 * and port for the sent (TX) packets. The actual number of channels is an 38 * hardware parameter that cannot be larger than 8. 39 * 40 * The Ethernet packet length can have any value, in range [42,1538] bytes. 36 41 * 37 * The Ethernet packet length can have any value, between 64 to 1538 bytes. 38 * The data transfer unit between software and the NIC is a 4 Kbytes "container", 39 * containing an integer number of variable size packets. 40 * 41 * The max number of packets in a container is 66 packets. 42 * The first 34 words of a container are the container header : 43 * 44 * word0 | NB_WORDS | NB_PACKETS | 45 * word1 | PLEN[0] | PLEN[1] | 46 * ... | ....... | ........ | 47 * word33 | PLEN[64] | PLEN[65] | 48 * 49 * - NB_PACKETS is the actual number of packets in the container. 50 * - NB_WORDS is the number of useful words in the container. 51 * - PLEN[i] is the number of bytes for the packet[i]. 52 * 53 * Packets are stored in the (1024 - 34) following words, and the packets are word-aligned. 54 * 55 * The TX and RX queues are implemented as chained buffers, where each buffer is a 4 Kbytes 56 * container. Each container is protected by a SET/RESET synchronisation variable. 57 * The structure implementing the chbuf descriptor is described below. 58 * 59 * To access both the container status, and the data contained in the container, the NIC 60 * uses two physical addresses, that are packed in a 64 bits "container descriptor". 61 * - desc[25:0] contain bits[31:6] of the status physical address. 62 * - desc[51:26] contain bits[31:6] of the buffer physical address. 63 * - desc[63:52] contain the common 12 physical address extension bits. 64 *******************************************************************************************/ 65 66 /******************************************************************************************** 67 * Addressable registers offsets 42 * For each channel, the received packets (RX) and the sent packets (TX) are stored 43 * in two memory mapped software FIFOs, called NIC_TX_QUEUE and NIC_RX_QUEUE, implemented 44 * as chained buffers (chbuf). Each slot in these FIFOs is a container, containing one 45 * single packet. The number of containers, defining the queue depth, is a software defined 46 * parameter. The data transfer unit between is a container (one single packet). 47 * 48 * - The "container" structure contains a 2040 bytes data buffer, the packet length, and 49 * the container state : full (owned by the reader) / empty (owned by the writer). 50 * For each container, the state variable is used as a SET/RESET flip-flop to synchronize 51 * the software server thread, and the hardware NIC DMA engines. 52 * 53 * - The "chbuf" descriptor contains an array of local pointers on the containers, used 54 * by the software driver, an array of physical addresses, used by the DMA engines and 55 * two "pointers", defining the current container to be written (wid) by the writer, 56 * and the current container to be read (rid) by the reader. 57 * 58 * WARNING : Both the chbuf descriptor (containing the <rid> and wid> indexes), and the 59 * containers themselve containing the <data> and the <sts> are shared variables 60 * accessed by the server threads (accessing the L2 caches), and by the NIC_DMA 61 * engines (accessing directly the L3 caches). 62 * Therefore, the L2/L3 cache coherence must be handled by this NIC driver for 63 * the INIT, READ & WRITE commands, using the MMC SYNC & INVAL commands. 64 *******************************************************************************************/ 65 66 /******************************************************************************************** 67 * This section defines the NIC device addressable registers offsets: 68 * - The 8 channels registers are stored in the first 512 bytes (8 * 64 bytes). 69 * - The global registers are stored in the next 256 bytes (global offset is 512 bytes). 70 * All values defined below are number of words (one word = 4 bytes). 68 71 *******************************************************************************************/ 69 72 70 73 enum SoclibMasterNicGlobalRegisters 71 74 { 72 NIC_G_RUN = 0, /*! read_write : NIC component activated */ 73 NIC_G_NB_CHANNELS = 1, /*! read_only : number of channels */ 74 NIC_G_BC_ENABLE = 2, /*! read_write : broadcast enabled if non zero */ 75 NIC_G_PERIOD = 3, /*! read-write : container status poll period */ 76 NIC_G_MAC_4 = 4, /*! read-write : mac address 32 LSB bits */ 77 NIC_G_MAC_2 = 5, /*! read-write : mac address 16 MSB bits */ 75 NIC_G_CHANNELS = 1, /*! read_only : number of channels */ 76 NIC_G_NPKT_RESET = 2, /*! write-only : reset packets counters */ 78 77 79 78 NIC_G_NPKT_RX_G2S_RECEIVED = 10, /*! number of packets received */ 80 79 NIC_G_NPKT_RX_G2S_DISCARDED = 11, /*! number of RX packets discarded by RX_G2S */ 80 81 81 NIC_G_NPKT_RX_DES_SUCCESS = 12, /*! number of RX packets transmited by RX_DES */ 82 82 NIC_G_NPKT_RX_DES_TOO_SMALL = 13, /*! number of discarded too small RX packets */ … … 84 84 NIC_G_NPKT_RX_DES_MFIFO_FULL = 15, /*! number of discarded RX packets fifo full */ 85 85 NIC_G_NPKT_RX_DES_CRC_FAIL = 16, /*! number of discarded RX packets CRC32 */ 86 NIC_G_NPKT_RX_DISPATCH_RECEIVED = 17, /*! number of packets received by RX_DISPATCH */ 87 NIC_G_NPKT_RX_DISPATCH_BROADCAST = 18, /*! number of broadcast RX packets received */ 88 NIC_G_NPKT_RX_DISPATCH_DST_FAIL = 19, /*! number of discarded RX packets for DST MAC */ 89 NIC_G_NPKT_RX_DISPATCH_CH_FULL = 20, /*! number of discarded RX packets cont full */ 90 91 NIC_G_NPKT_TX_DISPATCH_RECEIVED = 41, /*! number of packets received by TX_DISPATCH */ 92 NIC_G_NPKT_TX_DISPATCH_TOO_SMALL = 42, /*! number of discarded too small TX packets */ 93 NIC_G_NPKT_TX_DISPATCH_TOO_BIG = 43, /*! number of discarded too big TX packets */ 94 NIC_G_NPKT_TX_DISPATCH_SRC_FAIL = 44, /*! number of discarded TX packets for SRC MAC */ 95 NIC_G_NPKT_TX_DISPATCH_BROADCAST = 45, /*! number of broadcast TX packets received */ 96 NIC_G_NPKT_TX_DISPATCH_TRANSMIT = 46, /*! number of transmit TX packets */ 97 98 NIC_GLOBAL_SPAN = 64 /*! 256 bytes for global registers */ 86 87 NIC_G_NPKT_RX_DISP_RECEIVED = 17, /*! number of packets received by RX_DISPATCH */ 88 NIC_G_NPKT_RX_DISP_DST_FAIL = 18, /*! number of discarded RX packets for DST MAC */ 89 NIC_G_NPKT_RX_DISP_CH_FULL = 19, /*! number of discarded RX packets cont full */ 90 91 NIC_G_NPKT_TX_DISP_RECEIVED = 41, /*! number of packets received by TX_DISPATCH */ 92 NIC_G_NPKT_TX_DISP_TOO_SMALL = 42, /*! number of discarded too small TX packets */ 93 NIC_G_NPKT_TX_DISP_TOO_BIG = 43, /*! number of discarded too big TX packets */ 94 NIC_G_NPKT_TX_DISP_TRANSMIT = 44, /*! number of discarded TX packets for SRC MAC */ 95 96 NIC_GLOBAL_OFFSET = 128, /*! 512 bytes reserved for channel registers */ 99 97 }; 100 98 101 99 enum SoclibMasterNicChannelRegisters 102 100 { 103 NIC_RX_ STATUS = 0, /*! read-only : RX channel status*/104 NIC_RX_CHBUF_DESC_L 0 = 1, /*! read-write : RX chbuf descriptor 32 LSB bits */105 NIC_RX_CHBUF_DESC_HI = 2, /*! read-write : RX chbuf descriptor 32 MSB bits */ 101 NIC_RX_CHANNEL_RUN = 0, /*! write-only : RX channel activation/desactivation */ 102 NIC_RX_CHBUF_DESC_LO = 1, /*! read-write : RX chbuf descriptor 32 LSB bits */ 103 NIC_RX_CHBUF_DESC_HI = 2, /*! read-write : RX chbuf descriptor 32 MSB bits */ 106 104 NIC_RX_CHBUF_NBUFS = 3, /*! read-write : RX chbuf depth (number of buffers) */ 107 108 NIC_TX_STATUS = 8, /*! read-only : TX channel status */ 109 NIC_TX_CHBUF_DESC_L0 = 9, /*! read-write : TX chbuf descriptor 32 LSB bits */ 110 NIC_TX_CHBUF_DESC_HI = 10, /*! read-write : TX chbuf descriptor 32 MSB bits */ 105 NIC_RX_CHANNEL_STATE = 4, /*! read-only : RX channel status */ 106 107 NIC_TX_CHANNEL_RUN = 8, /*! write-only : TX channel activation */ 108 NIC_TX_CHBUF_DESC_LO = 9, /*! read-write : TX chbuf descriptor 32 LSB bits */ 109 NIC_TX_CHBUF_DESC_HI = 10, /*! read-write : TX chbuf descriptor 32 MSB bits */ 111 110 NIC_TX_CHBUF_NBUFS = 11, /*! read-write : TX chbuf depth (number of buffers) */ 111 NIC_TX_CHANNEL_STATE = 12, /*! read-only : TX channel status */ 112 112 113 113 NIC_CHANNEL_SPAN = 16 /*! 64 bytes per channel */ 114 114 }; 115 116 117 118 /******************************************************************************************** 119 * This structure defines the chained buffer descriptor, used to implement both 120 * the RX and TX packets queues. Each buffer in a chbuf is a 4 Kbytes container 121 * containing a variable number of packets. All containers are allocated in 122 * the same cluster as the associated NIC device descriptor. The chbuf descriptor contains: 123 * - an array of container pointers cont[], used by the kernet threads to access the 124 * packets contained in the containers. 125 * - an array of set/reset Boolean full[] used by both the software threads and 126 * by the hardware FSMs for lock-less synchronisation. 127 * - an array of containers descriptors containing the physical addresses of the 128 * "full[i]" and "cont[i]" variables, used by the DMA FSMs. 129 * Moreover, It contains three pointers (cont_id, pkt_id, and word_id) that are private 130 * variables used by the software thread to scan the chbuf. 131 *******************************************************************************************/ 115 116 /******************************************************************************************** 117 * Return values for the RX/TX channel master FSM status 118 *******************************************************************************************/ 119 120 enum SoclibMasterNicStatusValues 121 { 122 NIC_CHANNEL_STATUS_IDLE = 0, 123 NIC_CHANNEL_STATUS_ERROR = 1, 124 NIC_CHANNEL_STATUS_BUSY = 2, // busy for any value >= 2 125 }; 126 127 /******************************************************************************************** 128 * This structure defines the chbuf descriptor, used to implement both the RX and TX packets 129 * queues. Each container contains one single packet, and has only two states (full/empty). 130 * All containers are allocated in the same cluster as the associated NIC chdev descriptor. 131 * The chbuf descriptor contains: 132 * - an array of containers physical addresses cont_pad[], used by the DMA engines. 133 * - an array of container pointers cont_ptr[], used by the kernel threads. 134 * - two indexes rid and wid, defining the next container for read & write respectively. 135 * WARNING : dont modify this structure, used by the DMA engines. 136 *******************************************************************************************/ 137 138 #define SOCLIB_NIC_CHBUF_DEPTH 8 132 139 133 140 typedef struct nic_chbuf_s 134 141 { 135 uint32_t * cont[CONFIG_NIC_CHBUF_DEPTH]; /*! container virtual base address */ 136 uint32_t full[CONFIG_NIC_CHBUF_DEPTH]; /*! Boolean : container full if non zero */ 137 uint64_t desc[CONFIG_NIC_CHBUF_DEPTH]; /*! container & status physical addresses */ 138 uint32_t cont_id; /*! current container index */ 139 uint32_t pkt_id; /*! current packet index in container */ 140 uint32_t word_id; /*! first word of current packet */ 142 uint32_t wid; /*! current container write index */ 143 uint32_t rid; /*! current container read index */ 144 uint64_t cont_pad[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers physical base addresses */ 145 uint32_t * cont_ptr[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers virtual base addresses */ 141 146 } 142 147 nic_chbuf_t; 143 148 144 149 /******************************************************************************************** 145 * SOCLIB_NIC driver access functions 146 *******************************************************************************************/ 147 148 /******************************************************************************************** 149 * This function initializes the SOCLIB_NIC hardware registers, allocates memory for 150 * the RX and TX containers, allocates and initializes the RX and TX chbuf descriptors. 150 * This structure defines the container descriptor format. 151 *******************************************************************************************/ 152 153 typedef struct nic_cont_s 154 { 155 uint8_t buf[2040]; /*! Ethernet packet (42 to 1538 bytes */ 156 uint32_t length; /*! actual packet length in bytes */ 157 uint32_t state; /*! zero == empty / non zero == full */ 158 } 159 nic_cont_t; 160 161 /******************************************************************************************** 162 * Driver access functions 163 *******************************************************************************************/ 164 165 /******************************************************************************************** 166 * This function initializes the SOCLIB_NIC hardware registers, for one NIC chdev 167 * (one direction of one channel). It allocates memory for the RX and TX containers, 168 * it allocates and initializes the RX and TX chbuf descriptors. 151 169 * It allocates one WTI mailbox for the IRQ signaling availability of an RX full container, 152 170 * or a TX empty container, and route the WTI IRQ to the core running the server thread. 171 * It activates the TX and RX DMA engines. 153 172 ******************************************************************************************** 154 173 * @ chdev : pointer on NIC chdev descriptor. … … 157 176 158 177 /******************************************************************************************** 159 * This function implement the READ / WRITE / READABLE / WRITABLE commands for TX/RX queues. 160 * These command don't access the NIC peripheral but only the TX and TX chbufs. 161 * It must be executed by a dedicated kernel thread running in the cluster containing 162 * the CHBUF implementing the TX/RX queues. 163 * It implements also the SET_MAC, SET_BC, SET_RUN configuration commands, that directly 164 * access the NIC peripheral registers. 165 * - READABLE 166 * Returns in the command "status" a non zero value if a packet is available in RX queue. 167 * Update the RX queue read pointer if required. 168 * - READ 169 * Move a packet from the RX queue to the command "buffer", and returns the packet 170 * "length" in the command. The READABLE command must be called before the READ command. 171 * - WRITABLE 172 * Returns in the command "status" a non zero value if a packet with a given "length" 173 * can be written in the TX queue. Update the RX queue read pointer if required. 174 * - WRITE 178 * 1) This function implement the READ & WRITE commands, used by the local server threads 179 * to access the NIC_TX & NIC_RX packets queues. These commands don't access the NIC 180 * registers but only the TX and RX chbufs implementing the queues: 181 * 182 * <READ> 183 * Move a packet from the NIC_RX queue to the command "buffer". 184 * Return 0 in "status" if queue empty / return length in "status" if success. 185 * 186 * <WRITE> 175 187 * Move a packet of a given "length" from the command "buffer" to the TX queue. 176 * The WRITABLE command must be called before the WRITE command. 177 * - SET_MAC 178 * Set the values defined in the "length" and "status" command arguments, 179 * into the NIC_C_MAC4 and NIG_G_MAC2 registers. 180 * - SET_BC 181 * Enable/disable broadcast packets, as defined in the "status" command argument, 182 * into the NIC_G_BC_ENABLE register. 183 * - SET_RUN 184 * Enable/disable NIC, as defined in the "status" command argument, 185 * into the NIC_G_RUN register. 186 * @ dev_xp : extended pointer on the generic NIC device descriptor. 187 ******************************************************************************************** 188 $ @ thread_xp : extended pointer on client thread (containing the command arguments). 188 * Return 0 in "status" if queue full / return length in "status" if success. 189 * 190 * 2) It implements the GET_KEY / SET_RUN / GET_INSTRU / CLEAR_INSTRU commands, 191 * directly called by any thread running in any cluster to access the NIC registers : 192 * 193 * <GET_KEY> 194 * Return in "status" argument the channel index (key) computed from the IP address 195 * defined in the "buffer" argument, and from the port defined by the "length" argument. 196 * 197 * <SET_RUN> 198 * Enable/disable the NIC_TX_CHANNEL_RUN & NIC_RX_CHANNEL_RUN registers.The channel 199 * is defined in the "length" argument / run value defined in the "status" argument. 200 * 201 * <GET_INSTRU> 202 * Display on kernel TXT0 the contaent of all NIC instrumentation registers. 203 * 204 * <CLEAR_INSTRU> 205 * Reset all NIC instrumentation registers. 206 * 207 * Note (i) For the NIC device, the command arguments are always registered in the calling 208 * thread descriptor (i.e. the calling thread is always the client thread). 209 * Note (ii) The actual command mnemonics are defined in the <dev_nic.h> file. 189 210 *******************************************************************************************/ 190 211 extern void soclib_nic_cmd( xptr_t thread_xp ); 191 212 192 213 /******************************************************************************************** 193 * This ISR acknowledge the NIC_RX or NIC_TX channel ISR signaling that a new container 194 * has beeen moved, and reactivate the corresponding server thread. 195 * In case of address error reported by the NIC controler in accessing the kernel chbuf, 196 * it goes to kernel panic. 214 * This ISR is executed when a new RX container has been moved to an empty TX queue, 215 * or when a TX container has been removed from a full TX queue. In both cases, it 216 * reactivate the corresponding server thread from the BLOCKED_ISR condition. 217 * It is also executed in case of error reported by the DMA engines accessing the TX or RX 218 * queues. It simply print an error message on the kernel terminal. 219 * TODO improve this error handling... 197 220 ******************************************************************************************** 198 221 * @ chdev : local pointer on NIC chdev descriptor.
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