Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r98 r101 35 35 { 36 36 // ------------------------------------------------------------------- 37 // -----[ next state ]------------------------------------------------ 38 // ------------------------------------------------------------------- 39 for (uint32_t i=0; i<_param->_nb_context; i++) 40 { 41 // uint32_t x = _param->_link_context_to_decod_unit [i]; 42 43 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 44 // Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 45 46 context_state_t state = reg_STATE [i]; 47 48 switch (state) 49 { 50 case CONTEXT_STATE_OK : 51 { 52 // nothing, wait an event 53 break; 54 } 55 case CONTEXT_STATE_KO_EXCEP : 56 { 57 // Wait end of all instruction 58 if (inst_all == 0) 59 state = CONTEXT_STATE_KO_EXCEP_ADDR; 60 break; 61 } 62 case CONTEXT_STATE_KO_EXCEP_ADDR : 63 { 64 // nothing, wait the update of internal register (pc) 65 break; 66 } 67 case CONTEXT_STATE_KO_MISS_WAITEND : 68 { 69 // Wait end of all instruction 70 if (inst_all == 0) 71 72 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 73 state = CONTEXT_STATE_KO_MISS_ADDR; 74 break; 75 } 76 case CONTEXT_STATE_KO_EXCEP_SPR : 77 { 78 // nothing, wait the update of internal register (epcr, eear, sr, esr) 79 break; 80 } 81 case CONTEXT_STATE_KO_MISS_ADDR : 82 { 83 // nothing, wait the update of internal register (pc) 84 break; 85 } 86 // case CONTEXT_STATE_KO_PSYNC : 87 // { 88 // // Wait end of all instruction 89 // if (inst_all == 0) 90 // state = CONTEXT_STATE_KO_PSYNC_FLUSH; 91 // break; 92 // } 93 case CONTEXT_STATE_KO_PSYNC_FLUSH : 94 { 95 // nothing, wait end of flush (ifetch) 96 if (inst_all == 0) 97 // state = CONTEXT_STATE_KO_PSYNC_ADDR; 98 state = CONTEXT_STATE_OK; 99 100 break; 101 } 102 case CONTEXT_STATE_KO_PSYNC_ADDR : 103 { 104 // nothing, wait the pc write 105 break; 106 } 107 // case CONTEXT_STATE_KO_CSYNC : 108 // { 109 // // Wait end of all instruction 110 // if (inst_all == 0) 111 // state = CONTEXT_STATE_KO_CSYNC_FLUSH; 112 // break; 113 // } 114 case CONTEXT_STATE_KO_CSYNC_FLUSH : 115 { 116 // nothing, wait end of flush (all internal structure) 117 if (inst_all == 0) 118 state = CONTEXT_STATE_KO_CSYNC_ADDR; 119 break; 120 } 121 case CONTEXT_STATE_KO_CSYNC_ADDR : 122 { 123 // nothing, wait the pc write 124 break; 125 } 126 // case CONTEXT_STATE_KO_MSYNC : 127 // { 128 // // Wait end of memory instruction 129 // if (inst_mem == 0) 130 // state = CONTEXT_STATE_KO_MSYNC_ISSUE; 131 // break; 132 // } 133 // case CONTEXT_STATE_KO_MSYNC_ISSUE : 134 // { 135 // // Wait the msync issue 136 // if (inst_mem != 0) 137 // state = CONTEXT_STATE_KO_MSYNC_EXEC; 138 // break; 139 // } 140 case CONTEXT_STATE_KO_MSYNC_EXEC : 141 { 142 // Wait the end of msync 143 if (inst_all == 0) 144 state = CONTEXT_STATE_OK; 145 break; 146 } 147 // case CONTEXT_STATE_KO_SPR : 148 // { 149 // // Wait end of all instruction 150 // if (inst_all == 0) 151 // state = CONTEXT_STATE_KO_SPR_ISSUE; 152 // break; 153 // } 154 // case CONTEXT_STATE_KO_SPR_ISSUE : 155 // { 156 // // Wait the spr_access issue 157 // if (inst_all != 0) 158 // state = CONTEXT_STATE_KO_SPR_EXEC; 159 // break; 160 // } 161 case CONTEXT_STATE_KO_SPR_EXEC : 162 { 163 // Wait the spr_access execution 164 if (inst_all == 0) 165 state = CONTEXT_STATE_OK; 166 break; 167 } 168 169 default : 170 { 171 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); 172 } 173 } 174 reg_STATE [i] = state; 175 } 176 177 // ------------------------------------------------------------------- 37 178 // -----[ BRANCH_EVENT ]---------------------------------------------- 38 179 // ------------------------------------------------------------------- … … 57 198 58 199 // priority : miss > excep > spr/sync 59 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0);200 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 60 201 uint8_t priority1 = 2; // miss 61 202 … … 71 212 { 72 213 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 73 reg_STATE [i] = CONTEXT_STATE_KO_MISS; 214 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_ADDR; 215 reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 74 216 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 75 217 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next … … 107 249 108 250 // miss > excep > spr/sync 109 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);251 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 110 252 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 111 253 … … 120 262 if (is_valid) 121 263 { 264 log_printf(TRACE,Context_State,FUNCTION," * is_valid"); 265 122 266 // decod : 123 267 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) … … 130 274 case EVENT_TYPE_EXCEPTION : 131 275 { 276 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); 277 132 278 state_next = CONTEXT_STATE_KO_EXCEP; 133 279 … … 136 282 case EVENT_TYPE_SPR_ACCESS : 137 283 { 138 state_next = CONTEXT_STATE_KO_SPR ; 284 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); 285 286 // state_next = CONTEXT_STATE_KO_SPR ; 287 state_next = CONTEXT_STATE_KO_SPR_EXEC; 139 288 address++; // take next address 140 if (is_delay_slot)141 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");289 // if (is_delay_slot) 290 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 142 291 break; 143 292 } 144 293 case EVENT_TYPE_MSYNC : 145 294 { 146 state_next = CONTEXT_STATE_KO_MSYNC; 295 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); 296 297 // state_next = CONTEXT_STATE_KO_MSYNC; 298 state_next = CONTEXT_STATE_KO_MSYNC_EXEC; 147 299 address++; // take next address 148 if (is_delay_slot)149 throw ERRORMORPHEO(FUNCTION,"SPR accessin delay slot, not supported.\n");300 // if (is_delay_slot) 301 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); 150 302 break; 151 303 } 152 304 case EVENT_TYPE_PSYNC : 153 305 { 154 state_next = CONTEXT_STATE_KO_PSYNC; 306 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); 307 308 // state_next = CONTEXT_STATE_KO_PSYNC; 309 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; 155 310 address++; // take next address 156 311 if (is_delay_slot) 157 throw ERRORMORPHEO(FUNCTION," SPR accessin delay slot, not supported.\n");312 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); 158 313 break; 159 314 } 160 315 case EVENT_TYPE_CSYNC : 161 316 { 162 state_next = CONTEXT_STATE_KO_CSYNC; 317 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); 318 319 // state_next = CONTEXT_STATE_KO_CSYNC; 320 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; 163 321 address++; // take next address 164 322 if (is_delay_slot) 165 throw ERRORMORPHEO(FUNCTION," SPR accessin delay slot, not supported.\n");323 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); 166 324 break; 167 325 } … … 210 368 211 369 // miss > excep > spr/sync 212 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);370 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 213 371 uint8_t priority1 = 1; // exception 214 372 … … 277 435 278 436 // // miss > excep > spr/sync 279 // uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);437 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 280 438 // uint8_t priority1 = 2; // miss 281 439 … … 323 481 } 324 482 case CONTEXT_STATE_KO_MISS_ADDR : 483 // { 484 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 485 // break; 486 // } 325 487 case CONTEXT_STATE_KO_PSYNC_ADDR : 326 488 case CONTEXT_STATE_KO_CSYNC_ADDR : … … 357 519 reg_STATE [i] = CONTEXT_STATE_OK; 358 520 } 359 360 // -------------------------------------------------------------------361 // -----[ next state ]------------------------------------------------362 // -------------------------------------------------------------------363 for (uint32_t i=0; i<_param->_nb_context; i++)364 {365 // uint32_t x = _param->_link_context_to_decod_unit [i];366 367 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);368 Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);369 370 context_state_t state = reg_STATE [i];371 372 switch (state)373 {374 case CONTEXT_STATE_OK :375 {376 // nothing, wait an event377 break;378 }379 case CONTEXT_STATE_KO_EXCEP :380 {381 // Wait end of all instruction382 if (inst_all == 0)383 state = CONTEXT_STATE_KO_EXCEP_ADDR;384 break;385 }386 case CONTEXT_STATE_KO_MISS :387 {388 // Wait end of all instruction389 if (inst_all == 0)390 state = CONTEXT_STATE_KO_MISS_ADDR;391 break;392 }393 case CONTEXT_STATE_KO_EXCEP_ADDR :394 {395 // nothing, wait the update of internal register (pc)396 break;397 }398 case CONTEXT_STATE_KO_EXCEP_SPR :399 {400 // nothing, wait the update of internal register (epcr, eear, sr, esr)401 break;402 }403 case CONTEXT_STATE_KO_MISS_ADDR :404 {405 // nothing, wait the update of internal register (pc)406 break;407 }408 case CONTEXT_STATE_KO_PSYNC :409 {410 // Wait end of all instruction411 if (inst_all == 0)412 // state = CONTEXT_STATE_KO_PSYNC_FLUSH;413 state = CONTEXT_STATE_KO_PSYNC_ADDR ;414 break;415 }416 // case CONTEXT_STATE_KO_PSYNC_FLUSH :417 // {418 // // nothing, wait end of flush (ifetch)419 // break;420 // }421 case CONTEXT_STATE_KO_PSYNC_ADDR :422 {423 // nothing, wait the pc write424 break;425 }426 case CONTEXT_STATE_KO_CSYNC :427 {428 // Wait end of all instruction429 if (inst_all == 0)430 state = CONTEXT_STATE_KO_CSYNC_ADDR ;431 // state = CONTEXT_STATE_KO_CSYNC_FLUSH;432 break;433 }434 // case CONTEXT_STATE_KO_CSYNC_FLUSH :435 // {436 // // nothing, wait end of flush (all internal structure)437 // break;438 // }439 case CONTEXT_STATE_KO_CSYNC_ADDR :440 {441 // nothing, wait the pc write442 break;443 }444 case CONTEXT_STATE_KO_MSYNC :445 {446 // Wait end of memory instruction447 if (inst_mem == 0)448 state = CONTEXT_STATE_KO_MSYNC_ISSUE;449 break;450 }451 case CONTEXT_STATE_KO_MSYNC_ISSUE :452 {453 // Wait the msync issue454 if (inst_mem != 0)455 state = CONTEXT_STATE_KO_MSYNC_EXEC;456 break;457 }458 case CONTEXT_STATE_KO_MSYNC_EXEC :459 {460 // Wait the end of msync461 if (inst_mem == 0)462 state = CONTEXT_STATE_OK;463 break;464 }465 case CONTEXT_STATE_KO_SPR :466 {467 // Wait end of all instruction468 if (inst_all == 0)469 state = CONTEXT_STATE_KO_SPR_ISSUE;470 break;471 }472 case CONTEXT_STATE_KO_SPR_ISSUE :473 {474 // Wait the spr_access issue475 if (inst_all != 0)476 state = CONTEXT_STATE_KO_SPR_EXEC;477 break;478 }479 case CONTEXT_STATE_KO_SPR_EXEC :480 {481 // Wait the spr_access execution482 if (inst_all == 0)483 state = CONTEXT_STATE_OK;484 break;485 }486 487 default :488 {489 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));490 }491 }492 reg_STATE [i] = state;493 }494 521 495 522 for (uint32_t i=0; i<_param->_nb_context; ++i)
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