Changeset 84 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
- Timestamp:
- May 13, 2008, 8:04:50 PM (16 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
r82 r84 115 115 const int32_t percent_transaction_address = 75; 116 116 const int32_t percent_transaction_predict = 75; 117 const int32_t percent_transaction_event = 10;117 const int32_t percent_transaction_event = 5; 118 118 119 119 SC_START(0); … … 136 136 TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event 137 137 138 Tcontrol_t p_val = false; 139 Tcontrol_t c_val = false; 140 Tcontrol_t n_val = false; 141 142 Tgeneral_data_t p_addr = 0x100; 143 Tgeneral_data_t c_addr = 0x100; 144 Tgeneral_data_t n_addr = 0x100; 138 uint32_t jump = 7 ;// packet 139 uint32_t nb_packet = 1; 140 141 Tcontrol_t c_val = false; 142 Tcontrol_t n_val = false; 143 Tcontrol_t nn_val = false; 144 145 Tgeneral_data_t c_addr = 0x100; 146 Tgeneral_data_t n_addr = 0x100; 147 Tgeneral_data_t nn_addr = 0x100; 148 145 149 Tcontrol_t c_enable [_param->_nb_instruction]; 146 150 Tcontrol_t n_enable [_param->_nb_instruction]; 147 151 148 Tcontrol_t c_is_ds_take = 0; 149 Tinst_ifetch_ptr_t c_ifetch_ptr = 0; 150 Tbranch_state_t c_branch_state = BRANCH_STATE_NONE; 151 Tprediction_ptr_t c_branch_ptr = 0; 152 153 Tcontrol_t n_is_ds_take = 0; 154 Tinst_ifetch_ptr_t n_ifetch_ptr = 0; 155 Tbranch_state_t n_branch_state = BRANCH_STATE_NONE; 156 Tprediction_ptr_t n_branch_ptr = 0; 152 Tcontrol_t c_is_ds_take = 0; 153 Tcontrol_t n_is_ds_take = 0; 154 Tcontrol_t nn_is_ds_take = 0; 157 155 158 156 c_enable [0] = 1; … … 164 162 { 165 163 in_EVENT_VAL ->write(1); 166 in_EVENT_ADDRESS->write( c_addr);164 in_EVENT_ADDRESS->write(n_addr); 167 165 SC_START(1); 168 166 } while (out_EVENT_ACK->read() == false); 169 167 in_EVENT_VAL ->write(0); 170 168 169 n_val = 1; 170 171 171 LABEL("Loop of Test"); 172 172 … … 175 175 LABEL("Iteration %d",iteration); 176 176 177 in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); 177 // PREDICT 178 { 179 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 180 181 SC_START(0); 182 183 Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); 184 185 uint32_t begin = addr%_param->_nb_instruction; 186 uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); 187 Tcontrol_t take = (nb_packet%jump)==0; 188 189 if (take) 190 addr += 0x100; 191 else 192 addr += end-begin+1; 193 194 for (uint32_t i=0; i<_param->_nb_instruction; i++) 195 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 196 in_PREDICT_PC_NEXT ->write(addr); 197 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); 198 in_PREDICT_INST_IFETCH_PTR ->write(0); 199 in_PREDICT_BRANCH_STATE ->write(0); 200 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); 201 } 202 203 // ADDRESS 204 { 205 in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); 206 } 207 178 208 in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); 179 in_EVENT_ADDRESS->write(rand() << 2); 180 181 uint32_t begin = rand() % _param->_nb_instruction; 182 uint32_t end = (begin + (rand() % _param->_nb_instruction)); 183 end = (end > _param->_nb_instruction)?_param->_nb_instruction:end; 184 185 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 186 for (uint32_t i=0; i<_param->_nb_instruction; i++) 187 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 188 in_PREDICT_PC_NEXT ->write(rand() << 2); 189 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(rand()%2); 190 in_PREDICT_INST_IFETCH_PTR ->write(begin); 191 in_PREDICT_BRANCH_STATE ->write(c_addr%SIZE_BRANCH_STATE); 192 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction); 193 209 in_EVENT_ADDRESS->write(0x100); 210 211 //------------------------------------------------- 194 212 SC_START(0); 195 196 LABEL("---------------------"); 197 LABEL(" * pc-4 : %d %.8x",p_val, p_addr); 198 LABEL(" * pc : %d %.8x",c_val, c_addr); 199 LABEL(" * pc+4 : %d %.8x",n_val, n_addr); 200 LABEL("---------------------"); 213 //------------------------------------------------- 201 214 202 215 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) … … 204 217 LABEL("PREDICT : Transaction accepted"); 205 218 206 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),p_addr); 207 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),c_addr); 208 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take); 219 if (c_val) 220 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); 221 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); 222 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); 223 224 nn_val = true; 225 nn_addr = in_PREDICT_PC_NEXT ->read(); 226 nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); 227 228 for (uint32_t i=0; i<_param->_nb_instruction; i++) 229 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); 209 230 } 210 231 211 232 if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) 212 233 { … … 218 239 TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); 219 240 if (_param->_have_port_instruction_ptr) 220 TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(), c_ifetch_ptr);221 TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(), c_branch_state);241 TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); 242 TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); 222 243 if (_param->_have_port_branch_update_prediction_id) 223 TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr ); 224 225 p_val = true; 226 c_val = n_val; 227 228 p_addr = c_addr; 229 230 if (n_val) 244 TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); 245 246 c_val = 0; 247 nb_packet ++; 248 } 249 250 251 if (not c_val) 252 { 253 if (n_val and nn_val) 231 254 { 232 c_addr = n_addr; 233 234 c_ifetch_ptr = n_ifetch_ptr ; 235 c_branch_state = n_branch_state; 236 c_branch_ptr = n_branch_ptr ; 237 c_is_ds_take = n_is_ds_take ; 255 c_val = 1; 256 c_addr = n_addr; 257 c_is_ds_take = n_is_ds_take; 238 258 239 259 for (uint32_t i=0; i<_param->_nb_instruction; i++) 240 260 c_enable [i] = n_enable [i]; 261 262 n_val = 1; 263 n_addr = nn_addr; 264 n_is_ds_take = nn_is_ds_take; 265 266 nn_val = 0; 241 267 } 242 243 n_val = false;244 245 LABEL(" * pc-4 : %d %.8x",p_val, p_addr);246 LABEL(" * pc : %d %.8x",c_val, c_addr);247 LABEL(" * pc+4 : %d %.8x",n_val, n_addr);248 }249 250 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())251 {252 LABEL("PREDICT : Update information");253 254 if (c_val)255 {256 LABEL(" * current is valid -> new next");257 n_val = true;258 259 for (uint32_t i=0; i<_param->_nb_instruction; i++)260 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();261 n_addr = in_PREDICT_PC_NEXT ->read();262 n_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();263 n_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();264 n_branch_state = in_PREDICT_BRANCH_STATE ->read();265 n_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();266 }267 else268 {269 LABEL(" * current is not valid -> new current");270 c_val = true;271 272 for (uint32_t i=0; i<_param->_nb_instruction; i++)273 c_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();274 c_addr = in_PREDICT_PC_NEXT ->read();275 c_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();276 c_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();277 c_branch_state = in_PREDICT_BRANCH_STATE ->read();278 c_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();279 }280 281 LABEL(" * pc-4 : %d %.8x",p_val, p_addr);282 LABEL(" * pc : %d %.8x",c_val, c_addr);283 LABEL(" * pc+4 : %d %.8x",n_val, n_addr);284 285 268 } 286 269 … … 289 272 LABEL("EVENT : Transaction accepted"); 290 273 291 c_val = true; 292 n_val = false; 293 294 c_addr = in_EVENT_ADDRESS->read(); 295 c_ifetch_ptr = 0; 296 c_branch_state = BRANCH_STATE_NONE; 297 c_branch_ptr = 0; 298 c_is_ds_take = 0; 299 300 c_enable [0] = 1; 274 c_val = false; 275 n_val = true; 276 nn_val = false; 277 278 n_addr = in_EVENT_ADDRESS->read(); 279 n_is_ds_take = 0; 280 281 n_enable [0] = 1; 301 282 for (uint32_t i=1; i<_param->_nb_instruction; i++) 302 c_enable [i] = 0; 303 304 LABEL(" * pc-4 : %d %.8x",p_val, p_addr); 305 LABEL(" * pc : %d %.8x",c_val, c_addr); 306 LABEL(" * pc+4 : %d %.8x",n_val, n_addr); 283 n_enable [i] = 0; 307 284 } 285 286 287 { 288 string str_c_enable = ""; 289 string str_n_enable = ""; 290 291 for (uint32_t i=0; i<_param->_nb_instruction; i++) 292 { 293 str_c_enable += " " + toString(c_enable [i]); 294 str_n_enable += " " + toString(n_enable [i]); 295 } 296 297 LABEL("-----------------------------------"); 298 LABEL(" * nb_packet : %d",nb_packet); 299 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); 300 if (nn_val) 301 { 302 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); 303 } 304 else 305 { 306 LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); 307 } 308 LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); 309 LABEL("-----------------------------------"); 310 } 311 308 312 SC_START(1); 313 309 314 } 310 315
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