Changeset 105 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
- Timestamp:
- Feb 5, 2009, 12:18:31 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r101 r105 266 266 const int32_t percent_transaction_update = 75; 267 267 const int32_t percent_transaction_branch_event = 75; 268 const int32_t percent_transaction_event = 75; 268 269 269 270 const bool test1 = true; … … 271 272 const bool test3 = true; 272 273 const bool test4 = true; 274 const bool test5 = true; 273 275 274 276 std::list<request_t> ufpt; … … 961 963 SC_START(1); 962 964 in_EVENT_VAL [context]->write(1); 963 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);965 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 964 966 965 967 SC_START(1); … … 1407 1409 SC_START(1); 1408 1410 in_EVENT_VAL [context]->write(1); 1409 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);1411 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 1410 1412 1411 1413 SC_START(1); … … 2036 2038 SC_START(1); 2037 2039 in_EVENT_VAL [context]->write(1); 2038 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);2040 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 2039 2041 2040 2042 SC_START(1); … … 2128 2130 } 2129 2131 2132 } 2133 } 2134 2135 //--------------------------------------------------------------------- 2136 //--------------------------------------------------------------------- 2137 // COMMIT MISS : with RAS in UPFT and UPT 2138 //--------------------------------------------------------------------- 2139 //--------------------------------------------------------------------- 2140 if (test5) 2141 { 2142 uint32_t context = rand() % _param->_nb_context; 2143 uint32_t have_ufpt_ras = false; 2144 uint32_t have_upt_ras = false; 2145 2146 { 2147 LABEL("PREDICT - fill the queue"); 2148 uint32_t port = rand() % _param->_nb_inst_predict; 2149 2150 LABEL(" * context : %d",context); 2151 LABEL(" * port : %d",port); 2152 2153 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2154 { 2155 request_t request; 2156 request.context = context; 2157 request.address_src = rand(); 2158 request.address_dest = rand(); 2159 2160 request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET; 2161 2162 request.take = 1; 2163 request.take_good = 1; 2164 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 2165 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 2166 request.is_accurate = true ; 2167 request.miss_ifetch = false; 2168 request.miss_decod = false; 2169 request.miss_commit = false; 2170 request.history = i; 2171 request.ras_address = rand(); 2172 request.ras_index = rand()%_param->_size_ras_index[context]; 2173 request.ufpt_ptr = ufpt_top [context]; 2174 // request.upt_ptr; 2175 2176 bool have_transaction = false; 2177 do 2178 { 2179 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 2180 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 2181 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2182 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2183 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 2184 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 2185 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 2186 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 2187 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 2188 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 2189 2190 if (_param->_have_port_depth) 2191 { 2192 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2193 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2194 } 2195 SC_START(0); // fct melay 2196 2197 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 2198 port, 2199 in_PREDICT_VAL [port]->read(), 2200 out_PREDICT_ACK [port]->read(), 2201 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 2202 2203 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 2204 { 2205 LABEL("PREDICT [%d] - Transaction accepted",port); 2206 have_transaction = true; 2207 2208 if (_param->_have_port_depth) 2209 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 2210 2211 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 2212 } 2213 2214 SC_START(1); // transition 2215 2216 } while (not have_transaction); 2217 2218 ufpt.push_back(request); // to update 2219 2220 in_PREDICT_VAL [port]->write(0); 2221 2222 if (_param->_have_port_depth) 2223 { 2224 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2225 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2226 } 2227 } 2228 } 2229 2230 { 2231 LABEL("DECOD"); 2232 uint32_t port = rand() % _param->_nb_inst_decod; 2233 2234 LABEL(" * context : %d",context); 2235 LABEL(" * port : %d",port); 2236 2237 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2238 { 2239 request_t request = ufpt.front(); 2240 2241 bool have_transaction = false; 2242 do 2243 { 2244 in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod); 2245 in_DECOD_CONTEXT_ID [port]->write(request.context ); 2246 in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2247 in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2248 in_DECOD_BTB_CONDITION [port]->write(request.condition ); 2249 in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); 2250 in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); 2251 in_DECOD_RAS_INDEX [port]->write(request.ras_index ); 2252 in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); 2253 in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); 2254 in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); 2255 in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); 2256 2257 have_upt_ras |= (update_ras(request.condition)); 2258 2259 SC_START(0); // fct melay 2260 2261 LABEL("DECOD [%d] %d - %d", 2262 port, 2263 in_DECOD_VAL [port]->read(), 2264 out_DECOD_ACK [port]->read()); 2265 2266 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) 2267 { 2268 LABEL("DECOD [%d] - Transaction accepted",port); 2269 have_transaction = true; 2270 2271 request.upt_ptr = upt_top [context]; 2272 upt.push_back(request); 2273 ufpt.pop_front(); 2274 2275 upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; 2276 } 2277 2278 SC_START(1); // transition 2279 2280 } while (not have_transaction); 2281 2282 in_DECOD_VAL [port]->write(0); 2283 2284 if (_param->_have_port_depth) 2285 { 2286 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2287 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2288 } 2289 } 2290 } 2291 2292 { 2293 LABEL("PREDICT - fill the queue"); 2294 uint32_t port = rand() % _param->_nb_inst_predict; 2295 2296 LABEL(" * context : %d",context); 2297 LABEL(" * port : %d",port); 2298 2299 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2300 { 2301 request_t request; 2302 request.context = context; 2303 request.address_src = rand(); 2304 request.address_dest = rand(); 2305 request.address_good = request.address_dest; 2306 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 2307 2308 have_ufpt_ras |= (update_ras(request.condition)); 2309 2310 request.take = 1; 2311 request.take_good = 1; 2312 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 2313 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 2314 request.is_accurate = true ; 2315 request.miss_ifetch = false; 2316 request.miss_decod = false; 2317 request.miss_commit = true; 2318 request.history = i; 2319 request.ras_address = rand(); 2320 request.ras_index = rand()%_param->_size_ras_index[context]; 2321 request.ufpt_ptr = ufpt_top [context]; 2322 // request.upt_ptr; 2323 2324 bool have_transaction = false; 2325 do 2326 { 2327 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 2328 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 2329 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2330 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2331 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 2332 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 2333 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 2334 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 2335 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 2336 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 2337 2338 if (_param->_have_port_depth) 2339 { 2340 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2341 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2342 } 2343 SC_START(0); // fct melay 2344 2345 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 2346 port, 2347 in_PREDICT_VAL [port]->read(), 2348 out_PREDICT_ACK [port]->read(), 2349 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 2350 2351 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 2352 { 2353 LABEL("PREDICT [%d] - Transaction accepted",port); 2354 have_transaction = true; 2355 2356 if (_param->_have_port_depth) 2357 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 2358 2359 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 2360 } 2361 2362 SC_START(1); // transition 2363 2364 } while (not have_transaction); 2365 2366 ufpt.push_back(request); // to update 2367 2368 in_PREDICT_VAL [port]->write(0); 2369 2370 if (_param->_have_port_depth) 2371 { 2372 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2373 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2374 } 2375 } 2376 } 2377 2378 uint32_t nb_branch_before_event = 0; 2379 { 2380 // middle 2381 std::list<request_t>::iterator it_event = upt.begin(); 2382 for (uint32_t i=0; i < (upt.size()>>1); ++i) 2383 { 2384 nb_branch_before_event ++; 2385 it_event ++; 2386 } 2387 for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it) 2388 it->miss_commit = true; 2389 2390 bool have_transaction = false; 2391 2392 do 2393 { 2394 PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event); 2395 PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION); 2396 PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr); 2397 2398 SC_START(0); 2399 2400 if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context])) 2401 { 2402 LABEL("EVENT [%d] - Transaction accepted",context); 2403 2404 have_transaction = true; 2405 } 2406 2407 SC_START(1); 2408 } 2409 while (not have_transaction); 2410 PORT_WRITE(in_EVENT_VAL [context],0); 2411 2412 upt_top_event [it_event->context] = upt_top [it_event->context]; 2413 upt_top [it_event->context] = it_event->upt_ptr; 2414 } 2415 2416 { 2417 LABEL("BRANCH_COMPLETE - Hit ifetch"); 2418 2419 uint32_t port = rand() % _param->_nb_inst_branch_complete; 2420 2421 LABEL(" * port : %d",port); 2422 2423 std::list<request_t>::iterator it_upt = upt.begin(); 2424 2425 for (uint32_t i=0; i<nb_branch_before_event; ++i) 2426 { 2427 bool have_transaction = false; 2428 2429 do 2430 { 2431 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 2432 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context ); 2433 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 2434 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); 2435 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 2436 2437 if (_param->_have_port_depth) 2438 { 2439 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2440 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2441 } 2442 SC_START(0); 2443 2444 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 2445 2446 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 2447 { 2448 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 2449 LABEL(" * CONTEXT_ID : %d" ,it_upt->context ); 2450 LABEL(" * DEPTH : %d" ,it_upt->upt_ptr ); 2451 LABEL(" * CONDITION : %d" ,it_upt->condition ); 2452 LABEL(" * ADDRESS : %.8x",it_upt->address_dest); 2453 LABEL(" * FLAG : %d" ,it_upt->flag ); 2454 LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence ); 2455 2456 have_transaction = true; 2457 2458 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); 2459 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take ); 2460 it_upt->take_good = it_upt->take; 2461 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); 2462 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2463 2464 it_upt++; 2465 } 2466 2467 SC_START(1); 2468 2469 } while (not have_transaction); 2470 2471 in_BRANCH_COMPLETE_VAL [port]->write(0); 2472 2473 if (_param->_have_port_depth) 2474 { 2475 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2476 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2477 } 2478 } 2479 } 2480 2481 if (have_ufpt_ras) 2482 { 2483 LABEL("UPDATE - Update UPFT"); 2484 2485 uint32_t port = 0; 2486 2487 LABEL(" * port : %d",port); 2488 std::list<request_t>::iterator it_ufpt = ufpt.end(); 2489 -- it_ufpt; 2490 2491 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2492 { 2493 bool have_transaction = false; 2494 2495 do 2496 { 2497 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2498 2499 // if (_param->_have_port_depth) 2500 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 2501 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 2502 2503 SC_START(0); 2504 2505 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2506 2507 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2508 { 2509 LABEL("UPDATE [%d] - Transaction accepted",port); 2510 have_transaction = true; 2511 2512 if (_param->_have_port_context_id) 2513 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context); 2514 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or 2515 it_ufpt->miss_decod or 2516 it_ufpt->miss_commit )); 2517 // if (update_btb(it_ufpt->condition) or 2518 // update_dir(it_ufpt->condition)) 2519 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good); 2520 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0); 2521 // if (update_btb(it_ufpt->condition)) 2522 // { 2523 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src); 2524 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest); 2525 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition); 2526 // } 2527 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0); 2528 2529 // if (update_dir(it_ufpt->condition)) 2530 // if (_param->_have_port_history) 2531 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history); 2532 // TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition)); 2533 if (update_ras(it_ufpt->condition)) 2534 { 2535 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2536 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition)); 2537 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 2538 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 2539 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 2540 } 2541 } 2542 2543 SC_START(1); 2544 } while (not have_transaction); 2545 2546 -- it_ufpt; 2547 2548 2549 in_UPDATE_ACK [port]->write(0); 2550 // if (_param->_have_port_depth) 2551 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 2552 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 2553 } 2554 } 2555 ufpt.clear(); 2556 2557 { 2558 LABEL("UPDATE - upt (after event)"); 2559 2560 uint32_t port = 0; 2561 2562 LABEL(" * port : %d",port); 2563 2564 std::list<request_t>::iterator it_upt = upt.end(); 2565 2566 // for (uint32_t i=0; i<upt.size(); i++) 2567 2568 uint32_t size = upt.size(); 2569 2570 LABEL(" * size : %d",size); 2571 LABEL(" * nb_branch_before_event : %d",nb_branch_before_event); 2572 2573 for (uint32_t i=nb_branch_before_event; i<size; ++i) 2574 { 2575 --it_upt; 2576 2577 bool have_transaction = false; 2578 2579 if (need_update(it_upt->condition)) 2580 do 2581 { 2582 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2583 2584 // if (_param->_have_port_depth) 2585 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2586 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2587 2588 SC_START(0); 2589 2590 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2591 2592 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2593 { 2594 LABEL("UPDATE [%d] - Transaction accepted",port); 2595 LABEL(" * address_src : %.8x",it_upt->address_src); 2596 LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read()); 2597 2598 have_transaction = true; 2599 2600 bool btb_val = ((update_btb(it_upt->condition))); 2601 bool dir_val = (update_dir(it_upt->condition) and 2602 not (it_upt->miss_ifetch or it_upt->miss_decod)); 2603 bool ras_val = update_ras(it_upt->condition); 2604 2605 if (_param->_have_port_context_id) 2606 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 2607 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 2608 // TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val); 2609 2610 // if (btb_val) 2611 // { 2612 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 2613 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2614 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 2615 // } 2616 // TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val); 2617 2618 // if (dir_val) 2619 // { 2620 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 2621 // if (_param->_have_port_history) 2622 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 2623 // } 2624 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val); 2625 2626 if (ras_val) 2627 { 2628 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2629 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 2630 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2631 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2632 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2633 } 2634 // -- it_upt; 2635 } 2636 2637 SC_START(1); 2638 } while (not have_transaction); 2639 2640 upt.pop_back(); 2641 in_UPDATE_ACK [port]->write(0); 2642 // if (_param->_have_port_depth) 2643 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2644 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2645 } 2646 } 2647 2648 /* 2649 { 2650 LABEL("BRANCH_EVENT - have miss decod"); 2651 2652 uint32_t port = context; 2653 2654 { 2655 bool have_transaction = false; 2656 2657 do 2658 { 2659 in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event); 2660 2661 SC_START(0); 2662 2663 LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read()); 2664 2665 if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read()) 2666 { 2667 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 2668 have_transaction = true; 2669 2670 LABEL(" * event.address_src : %.8x,",event.address_src ); 2671 LABEL(" * event.address_good : %.8x,",event.address_good); 2672 LABEL(" * event.take : %.8x,",event.take ); 2673 2674 TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); 2675 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 2676 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good); 2677 if (event.take_good) 2678 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good); 2679 2680 event.address_src = 0; 2681 event.take = 0; 2682 event.address_dest = 0; 2683 } 2684 2685 SC_START(1); 2686 } while (not have_transaction); 2687 2688 in_BRANCH_EVENT_ACK [port]->write(0); 2689 } 2690 } 2691 2692 { 2693 LABEL("EVENT_STATE"); 2694 2695 SC_START(1); 2696 in_EVENT_VAL [context]->write(1); 2697 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 2698 2699 SC_START(1); 2700 in_EVENT_VAL [context]->write(0); 2701 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 2702 } 2703 */ 2704 2705 { 2706 LABEL("UPDATE - upt (before event)"); 2707 2708 uint32_t port = 0; 2709 2710 LABEL(" * port : %d",port); 2711 LABEL(" * size : %d",upt.size()); 2712 std::list<request_t>::iterator it_upt = upt.begin(); 2713 2714 for (uint32_t i=0; i<upt.size(); i++) 2715 { 2716 bool have_transaction = false; 2717 2718 do 2719 { 2720 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2721 2722 // if (_param->_have_port_depth) 2723 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2724 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2725 2726 SC_START(0); 2727 2728 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2729 2730 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2731 { 2732 LABEL("UPDATE [%d] - Transaction accepted",port); 2733 have_transaction = true; 2734 2735 if (_param->_have_port_context_id) 2736 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 2737 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 2738 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 2739 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 2740 if (update_btb(it_upt->condition)) 2741 { 2742 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 2743 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2744 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 2745 } 2746 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 2747 2748 if (update_dir(it_upt->condition)) 2749 if (_param->_have_port_history) 2750 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 2751 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 2752 if (update_ras(it_upt->condition)) 2753 { 2754 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2755 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 2756 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2757 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2758 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2759 } 2760 2761 ++ it_upt; 2762 } 2763 2764 SC_START(1); 2765 } while (not have_transaction); 2766 2767 in_UPDATE_ACK [port]->write(0); 2768 // if (_param->_have_port_depth) 2769 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2770 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2771 } 2772 } 2773 2774 upt.clear(); 2775 2776 // Wait Garbage Collector 2777 { 2778 LABEL("GARBAGE COLLECTOR"); 2779 LABEL(" * upt bottom : %d",upt_bottom [context]); 2780 LABEL(" * upt top : %d",upt_top [context]); 2781 2782 upt_top [context] = (upt_top_event [context]); 2783 upt_bottom [context] = (upt_top [context]); 2784 2785 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 2786 (upt_top [context] != out_DEPTH_MAX [context]->read())) 2787 { 2788 SC_START(1); 2789 } 2130 2790 } 2131 2791 }
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