Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

Timestamp:

Jan 15, 2009, 6:19:08 PM (15 years ago)

Author:

rosiere

Message:

1) Add soc test
2) fix bug (Pc management, Decod and execute, Update prediction ...)

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (8 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

@@ -24 +24 @@
   void Load_store_unit::function_speculative_load_commit_genMoore (void)
   {
-    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
 
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -44 +45 @@
     // Test store and load queue
 
-    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test MEMORY_OUT");
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Load  queue");
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
     for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
 //     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
@@ -71 +72 @@
                                                              _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
                                                              _load_queue [internal_MEMORY_OUT_PTR]._access_size);
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data : %.8x",data_new);
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
             log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
             log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
@@ -91 +93 @@
     if (not internal_MEMORY_OUT_VAL)
       {
-        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Store queue");
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
         if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
           {
@@ -143 +145 @@
     Tdcache_data_t    dcache_req_wdata     ;
 
-    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test DCACHE_REQ");
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
 
     internal_DCACHE_REQ_VAL = 0;
@@ -152 +154 @@
     if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
       {
-        log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
+        log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
 
         internal_DCACHE_REQ_VAL          = 1;
@@ -169 +171 @@
 
         dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
-        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb;
+        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
         dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
+
+//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
+//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
+        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
+
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
         dcache_req_wdata      = 0;
@@ -210 +217 @@
     PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
     
-    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    log_end(Load_store_unit,FUNCTION);
   };