Changeset 3 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp
- Timestamp:
- Mar 6, 2007, 3:34:04 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp
r2 r3 7 7 */ 8 8 9 #define NB_ITERATION 19 #define NB_ITERATION 512 10 10 11 11 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h" 12 12 #include "Include/Test.h" 13 13 #include "Include/BitManipulation.h" 14 14 void test (string name, 15 15 morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param) … … 28 28 * Déclarations des signaux 29 29 *********************************************************************/ 30 sc_clock * CLOCK ("clock", 1.0, 0.5);30 sc_clock * CLOCK; 31 31 32 32 sc_signal<Tcontrol_t> * PREDICT_VAL [param._nb_prediction]; … … 41 41 sc_signal<Tbht_history_t> * BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete]; 42 42 sc_signal<Tpht_history_t> * BRANCH_COMPLETE_PHT_HISTORY [param._nb_branch_complete]; 43 sc_signal<Tcontrol_t> * BRANCH_COMPLETE_ HIT[param._nb_branch_complete];43 sc_signal<Tcontrol_t> * BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete]; 44 44 45 45 // Rename signal … … 75 75 rename = "BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); 76 76 BRANCH_COMPLETE_PHT_HISTORY [i] = new sc_signal<Tpht_history_t> (rename.c_str()); 77 rename = "BRANCH_COMPLETE_ HIT_"+toString(i);78 BRANCH_COMPLETE_ HIT[i] = new sc_signal<Tcontrol_t> (rename.c_str());77 rename = "BRANCH_COMPLETE_DIRECTION_" +toString(i); 78 BRANCH_COMPLETE_DIRECTION [i] = new sc_signal<Tcontrol_t> (rename.c_str()); 79 79 } 80 80 … … 86 86 87 87 (*(_Two_Level_Branch_Predictor->in_CLOCK)) (*(CLOCK)); 88 89 90 91 92 93 94 95 96 if (param._have_pht) 97 98 88 89 for (uint32_t i=0; i<param._nb_prediction; i++) 90 { 91 (*(_Two_Level_Branch_Predictor-> in_PREDICT_VAL [i])) (*(PREDICT_VAL [i])); 92 (*(_Two_Level_Branch_Predictor->out_PREDICT_ACK [i])) (*(PREDICT_ACK [i])); 93 (*(_Two_Level_Branch_Predictor-> in_PREDICT_ADDRESS [i])) (*(PREDICT_ADDRESS [i])); 94 if (param._have_bht) 95 (*(_Two_Level_Branch_Predictor->out_PREDICT_BHT_HISTORY [i])) (*(PREDICT_BHT_HISTORY [i])); 96 if (param._have_pht) 97 (*(_Two_Level_Branch_Predictor->out_PREDICT_PHT_HISTORY [i])) (*(PREDICT_PHT_HISTORY [i])); 98 } 99 99 100 100 for (uint32_t i=0; i<param._nb_branch_complete; i++) … … 105 105 if (param._have_bht) 106 106 (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*(BRANCH_COMPLETE_BHT_HISTORY [i])); 107 if (param._have_ bht)107 if (param._have_pht) 108 108 (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_PHT_HISTORY [i])) (*(BRANCH_COMPLETE_PHT_HISTORY [i])); 109 (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_ HIT [i])) (*(BRANCH_COMPLETE_HIT[i]));109 (*(_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_DIRECTION [i])) (*(BRANCH_COMPLETE_DIRECTION [i])); 110 110 } 111 111 … … 121 121 122 122 srand(seed); 123 124 const uint32_t num_port_predict = rand()%param._nb_prediction; 125 const uint32_t num_port_branch_complete = rand()%param._nb_branch_complete; 126 const Taddress_t address = rand()%param._size_address; 127 Tcontrol_t direction; 123 128 124 129 sc_start(0); … … 133 138 134 139 // Step 1 135 BRANCH_COMPLETE_VAL [0]->write(1); 136 BRANCH_COMPLETE_HIT [0]->write(0); 140 BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1); 141 BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(0); 142 143 if (param._have_pht) 144 { 145 // Step 1.1 -> pattern_history_table 146 147 // Step 1.1.1 compute number of group. 148 uint32_t size_address_shift=0; 149 150 if (param._have_bht) 151 size_address_shift=param._param_two_level_branch_predictor_glue->_pht_size_address_shift; 152 153 uint32_t nb_group = (1<<size_address_shift); 154 uint32_t nb_reg_by_group = (1<<(param._pht_size_address-size_address_shift)); 155 156 _Two_Level_Branch_Predictor->vhdl_testbench_label("Init pht"); 157 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init pht" << endl; 158 159 BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(0); 160 161 // Step 1.1.2 for all group ... 162 for (uint32_t i=0; i<nb_group; i++) 163 { 164 if (param._have_bht) 165 BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(i); 166 167 for (uint32_t j=0; j<nb_reg_by_group; j++) 168 { 169 BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(j); 170 171 sc_start(1); 172 173 // wait ackwolegde 174 while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) 175 sc_start(1); 176 } 177 } 178 } 137 179 138 180 if (param._have_bht) 139 181 { 140 BRANCH_COMPLETE_BHT_HISTORY [0]->write(0); 182 // Step 1.2 -> branch_history_table 183 BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(0); 141 184 142 185 _Two_Level_Branch_Predictor->vhdl_testbench_label("Init bht"); … … 145 188 for (uint32_t i=0; i<param._bht_nb_shifter; i++) 146 189 { 147 BRANCH_COMPLETE_ADDRESS [ 0]->write(i);190 BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(i); 148 191 149 192 sc_start(1); … … 151 194 152 195 // wait ackwolegde 153 while (BRANCH_COMPLETE_ACK [ 0] -> read() == 0)196 while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) 154 197 sc_start(1); 155 198 } 156 199 157 if (param._have_pht) 158 { 159 BRANCH_COMPLETE_BHT_HISTORY [0]->write(0); 160 BRANCH_COMPLETE_PHT_HISTORY [0]->write(0); 161 162 _Two_Level_Branch_Predictor->vhdl_testbench_label("Init bht"); 163 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init bht" << endl; 164 165 for (uint32_t i=0; i<param._bht_nb_shifter; i++) 166 { 167 BRANCH_COMPLETE_ADDRESS [0]->write(i); 168 169 sc_start(1); 170 } 200 // Step 2 201 BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0); 202 PREDICT_ADDRESS [num_port_predict ]->write(address); 203 BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(address); 204 205 _Two_Level_Branch_Predictor->vhdl_testbench_label("Loop of Test"); 206 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl 207 << " * predict_address : " << hex << address << dec << endl; 208 209 // A lot of prediction 210 Tbht_history_t bht_history = 0; 211 Tpht_history_t pht_history [1<<param._bht_size_shifter]; 212 213 for (uint32_t i=0; i<static_cast<uint32_t>(1<<param._bht_size_shifter); i++) 214 pht_history [i] = 0; 215 216 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 217 { 218 _Two_Level_Branch_Predictor->vhdl_testbench_label("Iteration "+toString(iteration)); 219 220 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Predict : bht_history " << bht_history << " - pht_history " << pht_history[bht_history] << endl; 221 222 // Ask a new prediction 223 PREDICT_VAL [num_port_predict ]->write(1); 224 225 sc_start(1); 171 226 172 227 // wait ackwolegde 173 while ( BRANCH_COMPLETE_ACK [0] -> read() == 0)228 while (PREDICT_ACK [num_port_predict] -> read() == 0) 174 229 sc_start(1); 175 } 176 177 178 179 // Step 2 180 _Two_Level_Branch_Predictor->vhdl_testbench_label("Loop of Test"); 181 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 182 183 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 184 { 185 _Two_Level_Branch_Predictor->vhdl_testbench_label("Iteration "+toString(iteration)); 230 PREDICT_ACK [num_port_predict ]->write(0); 231 232 sc_start(0); 233 234 // Test 235 if (param._have_bht) 236 TEST(Tbht_history_t,bht_history ,PREDICT_BHT_HISTORY[num_port_predict]->read()); 237 if (param._have_pht) 238 TEST(Tpht_history_t,pht_history[bht_history],PREDICT_PHT_HISTORY[num_port_predict]->read()); 239 240 // update 241 direction = ((rand()%2)==1); 242 243 BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1); 244 if (param._have_bht) 245 BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(bht_history ); 246 247 248 if (param._have_pht) 249 BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(pht_history[bht_history]); 250 BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(direction); 251 252 if (param._have_pht) 253 if (direction == 0) 254 { 255 if (pht_history[bht_history] > 0) 256 pht_history[bht_history] --; 257 } 258 else 259 { 260 if (pht_history[bht_history] < (static_cast<Tpht_history_t>(1<<param._pht_size_counter)-1)) 261 pht_history[bht_history] ++; 262 } 263 264 if (param._have_bht) 265 bht_history = (((bht_history) << 1) | direction) & gen_mask<Tbht_history_t>(param._bht_size_shifter); 186 266 187 267 sc_start(1); 268 269 // wait ackwolegde 270 while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0) 271 sc_start(1); 272 273 BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0); 188 274 } 189 275
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