Changeset 57 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp

Timestamp:

Sep 28, 2007, 2:58:08 PM (17 years ago)

Author:

rosiere

Message:

• VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
• SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
• Séminaire interne

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp

@@ -53 +53 @@
         
         _link_port_read_to_bank_read     = new uint32_t [_nb_port_read ];
-//      _link_port_read_to_num_bank      = new uint32_t [_nb_port_read ];
         _link_port_write_to_bank_write   = new uint32_t [_nb_port_write];
-//      _link_port_write_to_num_bank     = new uint32_t [_nb_port_write];
 
-//      uint32_t _nb_port_bank_by_bank_read_port  [_nb_port_read_by_bank ];
-//      uint32_t _nb_port_bank_by_bank_write_port [_nb_port_write_by_bank];
-        
         // init
-//      for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
-//        _nb_port_bank_by_bank_read_port  [i] = 0;
-        
-        for (uint32_t i=0; i<_nb_port_read         ;i++)
+        for (uint32_t i=0; i<_nb_port_read ;i++)
           {
             uint32_t x = i%_nb_port_read_by_bank;
             _link_port_read_to_bank_read [i] = x;
-//          _link_port_read_to_num_bank  [i] = _nb_port_bank_by_bank_read_port [x];
-//          _nb_port_bank_by_bank_read_port    [x] ++;
           }
-
-        // init
-//      for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
-//        _nb_port_bank_by_bank_write_port [i] = 0;
-        
-        for (uint32_t i=0; i<_nb_port_write         ;i++)
+        for (uint32_t i=0; i<_nb_port_write;i++)
           {
             uint32_t x = i%_nb_port_write_by_bank;
             _link_port_write_to_bank_write   [i] = x;
-//          _link_port_write_to_num_bank     [i] = _nb_port_bank_by_bank_write_port [x];
-//          _nb_port_bank_by_bank_write_port       [x] ++;
           }
 
@@ -87 +70 @@
         log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_bank_read");
         for (uint32_t i=0; i<_nb_port_read         ;i++)
+          {
           log_printf(NONE,RegisterFile_Multi_Banked,"Parameters","   * Read  in  [%d] to out    [%d]",i,_link_port_read_to_bank_read          [i]);
-//      log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_num_bank  ");
-//      for (uint32_t i=0; i<_nb_port_read         ;i++)
-//        log_printf(NONE,RegisterFile_Multi_Banked,"Parameters","   * Read  in  [%d] to bank   [%d]",i,_link_port_read_to_num_bank         [i]);
-
+          printf("   * Read  in  [%d] to out    [%d]\n",i,_link_port_read_to_bank_read          [i]);
+          }
         log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_bank_write");
         for (uint32_t i=0; i<_nb_port_write        ;i++)
-          log_printf(NONE,RegisterFile_Multi_Banked,"Parameters","   * Write in  [%d] to out    [%d]",i,_link_port_write_to_bank_write          [i]);
-//      log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_num_bank  ");
-//      for (uint32_t i=0; i<_nb_port_write        ;i++)
-//        log_printf(NONE,RegisterFile_Multi_Banked,"Parameters","   * Write in  [%d] to bank   [%d]",i,_link_port_write_to_num_bank         [i]);
+          {
+            log_printf(NONE,RegisterFile_Multi_Banked,"Parameters","   * Write in  [%d] to out    [%d]",i,_link_port_write_to_bank_write          [i]);
+            printf("   * Write in  [%d] to out    [%d]\n",i,_link_port_write_to_bank_write          [i]);
+          }
       }
     // else : don't allocate