Changeset 98 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
- Timestamp:
- Dec 31, 2008, 11:18:08 AM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r97 r98 51 51 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 52 52 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); 53 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);53 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 54 54 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 55 55 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); … … 129 129 INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context); 130 130 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 131 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 131 if (_param->_have_port_depth) 132 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 132 133 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 133 134 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); … … 217 218 srand(seed); 218 219 220 const int32_t percent_transaction_branch_event = 75; 219 221 const int32_t percent_transaction_decod_event = 75; 220 222 const int32_t percent_transaction_commit_event = 75; 221 223 //const int32_t percent_transaction_branch_complete = 75; 222 224 const int32_t percent_transaction_event = 75; 223 225 const int32_t percent_transaction_spr = 75; … … 239 241 in_DECOD_EVENT_VAL [i]->write(0); 240 242 in_COMMIT_EVENT_VAL ->write(0); 241 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 242 in_BRANCH_COMPLETE_VAL [i]->write(0); 243 // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 244 // in_BRANCH_COMPLETE_VAL [i]->write(0); 245 for (uint32_t i=0; i<_param->_nb_context; i++) 246 in_BRANCH_EVENT_VAL [i]->write(0); 243 247 244 248 for (uint32_t i=0; i<_param->_nb_context; i++) … … 525 529 in_NB_INST_COMMIT_MEM [context]->write(1); 526 530 527 uint32_t port = rand()%_param->_nb_inst_branch_complete; 528 529 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 531 // uint32_t port = rand()%_param->_nb_inst_branch_complete; 532 533 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 534 // if (_param->_have_port_depth) 535 // in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 536 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 537 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); 538 // in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 539 // in_BRANCH_COMPLETE_TAKE [port]->write(0); 540 541 // TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 542 543 // do 544 // { 545 // in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 546 547 // SC_START(1); 548 // } 549 // while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 550 // out_BRANCH_COMPLETE_ACK [port]->read())); 551 // in_BRANCH_COMPLETE_VAL [port]->write(0); 552 553 uint32_t port = context; 554 530 555 if (_param->_have_port_depth) 531 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 532 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 533 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); 534 in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 535 in_BRANCH_COMPLETE_TAKE [port]->write(0); 536 537 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 538 539 do 540 { 541 in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 542 543 SC_START(1); 544 } 545 while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 546 out_BRANCH_COMPLETE_ACK [port]->read())); 547 in_BRANCH_COMPLETE_VAL [port]->write(0); 556 in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 557 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400); 558 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500); 559 in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0); 560 561 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 562 563 do 564 { 565 in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); 566 567 SC_START(1); 568 } 569 while (not ( in_BRANCH_EVENT_VAL [port]->read() and 570 out_BRANCH_EVENT_ACK [port]->read())); 571 in_BRANCH_EVENT_VAL [port]->write(0); 548 572 549 573 LABEL("miss (wait end)"); … … 595 619 in_NB_INST_COMMIT_MEM [context]->write(1); 596 620 597 uint32_t port = rand()%_param->_nb_inst_branch_complete; 598 599 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 600 if (_param->_have_port_depth) 601 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 602 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 603 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); 604 in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 605 in_BRANCH_COMPLETE_TAKE [port]->write(1); 606 607 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 608 609 do 610 { 611 in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 612 613 SC_START(1); 614 } 615 while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 616 out_BRANCH_COMPLETE_ACK [port]->read())); 617 in_BRANCH_COMPLETE_VAL [port]->write(0); 621 // uint32_t port = rand()%_param->_nb_inst_branch_complete; 622 623 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 624 // if (_param->_have_port_depth) 625 // in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 626 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 627 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); 628 // in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 629 // in_BRANCH_COMPLETE_TAKE [port]->write(1); 630 631 // TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 632 633 // do 634 // { 635 // in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 636 637 // SC_START(1); 638 // } 639 // while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 640 // out_BRANCH_COMPLETE_ACK [port]->read())); 641 // in_BRANCH_COMPLETE_VAL [port]->write(0); 642 643 uint32_t port = context; 644 645 in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 646 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600); 647 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700); 648 in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1); 649 650 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 651 652 do 653 { 654 in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); 655 656 SC_START(1); 657 } 658 while (not ( in_BRANCH_EVENT_VAL [port]->read() and 659 out_BRANCH_EVENT_ACK [port]->read())); 660 in_BRANCH_EVENT_VAL [port]->write(0); 618 661 619 662 LABEL("miss (wait end)"); … … 1238 1281 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context); 1239 1282 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 1240 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);1283 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 1241 1284 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 1242 1285 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
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