Changeset 98 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp

Timestamp:

Dec 31, 2008, 11:18:08 AM (15 years ago)

Author:

rosiere

Message:

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (modified) (4 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp

@@ -281 +281 @@
               log_printf(TRACE,Commit_unit,FUNCTION,"  * RETIRE            [%d][%d]",x,y);
 
-#ifdef STATISTICS
-              if (usage_is_set(_usage,USE_STATISTICS))
-                (*_stat_nb_inst_retire [x]) ++;
-#endif
-
 #ifdef DEBUG_TEST
               if (not PORT_READ(in_RETIRE_ACK [x][y]))
@@ -291 +286 @@
 #endif
 
-
               entry_t *  entry        =  _rob [i].front();
-              
+#ifdef STATISTICS
+              if (usage_is_set(_usage,USE_STATISTICS))
+                {
+                  rob_state_t state = entry->state;
+                  
+                  if (state == ROB_END_OK)
+                    (*_stat_nb_inst_retire_ok [x]) ++;
+                  else
+                    (*_stat_nb_inst_retire_ko [x]) ++;
+                }
+#endif
+
               Tcontext_t front_end_id = entry->front_end_id;
               Tcontext_t context_id   = entry->context_id  ;
@@ -478 +483 @@
              it++)
           {
-            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
+            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
                        x,
                        (*it)->front_end_id            ,
@@ -487 +492 @@
                        (*it)->operation               ,
                        (*it)->address                 ,
+                       (*it)->address << 2            ,
                        (*it)->is_delay_slot           ,
                        (*it)->use_store_queue         ,