source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 853

Last change on this file since 853 was 853, checked in by cfuguet, 8 years ago

reconf: introducing assert to detect early watchdog timeout.

  • Introducing an assert in the vci_cc_vcache_wrapper component. An early watchdog timeout arises when the timeout threshold is less than the max latency of a read miss transaction.
File size: 35.8 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param,
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67    typedef typename vci_param::fast_trdid_t trdid_t;
68
69    enum icache_fsm_state_e
70    {
71        ICACHE_IDLE,
72        // handling XTN processor requests
73        ICACHE_XTN_TLB_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH,
75        ICACHE_XTN_CACHE_FLUSH_GO,
76        ICACHE_XTN_TLB_INVAL,
77        ICACHE_XTN_CACHE_INVAL_VA,
78        ICACHE_XTN_CACHE_INVAL_PA,
79        ICACHE_XTN_CACHE_INVAL_GO,
80        // handling tlb miss
81        ICACHE_TLB_WAIT,
82        // handling cache miss
83        ICACHE_MISS_SELECT,
84        ICACHE_MISS_CLEAN,
85        ICACHE_MISS_WAIT,
86        ICACHE_MISS_DATA_UPDT,
87        ICACHE_MISS_DIR_UPDT,
88        // handling unc read
89        ICACHE_UNC_WAIT,
90        // handling coherence requests
91        ICACHE_CC_CHECK,
92        ICACHE_CC_UPDT,
93        ICACHE_CC_INVAL,
94    };
95
96    enum dcache_fsm_state_e
97    {
98        DCACHE_IDLE,
99        // handling itlb & dtlb miss
100        DCACHE_TLB_MISS,
101        DCACHE_TLB_PTE1_GET,
102        DCACHE_TLB_PTE1_SELECT,
103        DCACHE_TLB_PTE1_UPDT,
104        DCACHE_TLB_PTE2_GET,
105        DCACHE_TLB_PTE2_SELECT,
106        DCACHE_TLB_PTE2_UPDT,
107        DCACHE_TLB_LR_UPDT,
108        DCACHE_TLB_LR_WAIT,
109        DCACHE_TLB_RETURN,
110        // handling processor XTN requests
111        DCACHE_XTN_SWITCH,
112        DCACHE_XTN_SYNC,
113        DCACHE_XTN_IC_INVAL_VA,
114        DCACHE_XTN_IC_FLUSH,
115        DCACHE_XTN_IC_INVAL_PA,
116        DCACHE_XTN_IC_PADDR_EXT,
117        DCACHE_XTN_IT_INVAL,
118        DCACHE_XTN_DC_FLUSH,
119        DCACHE_XTN_DC_FLUSH_GO,
120        DCACHE_XTN_DC_INVAL_VA,
121        DCACHE_XTN_DC_INVAL_PA,
122        DCACHE_XTN_DC_INVAL_END,
123        DCACHE_XTN_DC_INVAL_GO,
124        DCACHE_XTN_DT_INVAL,
125        //handling dirty bit update
126        DCACHE_DIRTY_GET_PTE,
127        DCACHE_DIRTY_WAIT,
128        // handling processor miss requests
129        DCACHE_MISS_SELECT,
130        DCACHE_MISS_CLEAN,
131        DCACHE_MISS_WAIT,
132        DCACHE_MISS_DATA_UPDT,
133        DCACHE_MISS_DIR_UPDT,
134        // handling processor unc, ll and sc requests
135        DCACHE_UNC_WAIT,
136        DCACHE_LL_WAIT,
137        DCACHE_SC_WAIT,
138        // handling coherence requests
139        DCACHE_CC_CHECK,
140        DCACHE_CC_UPDT,
141        DCACHE_CC_INVAL,
142        // handling TLB inval (after a coherence or XTN request)
143        DCACHE_INVAL_TLB_SCAN,
144    };
145
146    enum cmd_fsm_state_e
147    {
148        CMD_IDLE,
149        CMD_INS_MISS,
150        CMD_INS_UNC,
151        CMD_DATA_MISS,
152        CMD_DATA_UNC_READ,
153        CMD_DATA_UNC_WRITE,
154        CMD_DATA_WRITE,
155        CMD_DATA_LL,
156        CMD_DATA_SC,
157        CMD_DATA_CAS,
158    };
159
160    enum rsp_fsm_state_e
161    {
162        RSP_IDLE,
163        RSP_INS_MISS,
164        RSP_INS_UNC,
165        RSP_DATA_MISS,
166        RSP_DATA_UNC,
167        RSP_DATA_LL,
168        RSP_DATA_WRITE,
169    };
170
171    enum cc_receive_fsm_state_e
172    {
173        CC_RECEIVE_IDLE,
174        CC_RECEIVE_BRDCAST_HEADER,
175        CC_RECEIVE_BRDCAST_NLINE,
176        CC_RECEIVE_INS_INVAL_HEADER,
177        CC_RECEIVE_INS_INVAL_NLINE,
178        CC_RECEIVE_INS_UPDT_HEADER,
179        CC_RECEIVE_INS_UPDT_NLINE,
180        CC_RECEIVE_DATA_INVAL_HEADER,
181        CC_RECEIVE_DATA_INVAL_NLINE,
182        CC_RECEIVE_DATA_UPDT_HEADER,
183        CC_RECEIVE_DATA_UPDT_NLINE,
184        CC_RECEIVE_INS_UPDT_DATA,
185        CC_RECEIVE_DATA_UPDT_DATA,
186    };
187
188    enum cc_send_fsm_state_e
189    {
190        CC_SEND_IDLE,
191        CC_SEND_CLEANUP_1,
192        CC_SEND_CLEANUP_2,
193        CC_SEND_MULTI_ACK,
194    };
195
196    /* transaction type, pktid field */
197    enum transaction_type_e
198    {
199        // b3 unused
200        // b2 READ / NOT READ
201        // if READ
202        //  b1 DATA / INS
203        //  b0 UNC / MISS
204        // else
205        //  b1 accÚs table llsc type SW / other
206        //  b2 WRITE/CAS/LL/SC
207        TYPE_DATA_UNC       = 0x0,
208        TYPE_READ_DATA_MISS = 0x1,
209        TYPE_READ_INS_UNC   = 0x2,
210        TYPE_READ_INS_MISS  = 0x3,
211        TYPE_WRITE          = 0x4,
212        TYPE_CAS            = 0x5,
213        TYPE_LL             = 0x6,
214        TYPE_SC             = 0x7
215    };
216
217    /* SC return values */
218    enum sc_status_type_e
219    {
220        SC_SUCCESS = 0x00000000,
221        SC_FAIL    = 0x00000001
222    };
223
224    // cc_send_type
225    typedef enum
226    {
227        CC_TYPE_CLEANUP,
228        CC_TYPE_MULTI_ACK,
229    } cc_send_t;
230
231    // cc_receive_type
232    typedef enum
233    {
234        CC_TYPE_CLACK,
235        CC_TYPE_BRDCAST,
236        CC_TYPE_INVAL,
237        CC_TYPE_UPDT,
238    } cc_receive_t;
239
240    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
241    enum
242    {
243        INS_TLB_MASK    = 0x8,
244        DATA_TLB_MASK   = 0x4,
245        INS_CACHE_MASK  = 0x2,
246        DATA_CACHE_MASK = 0x1,
247    };
248
249    // Error Type
250    enum mmu_error_type_e
251    {
252        MMU_NONE                      = 0x0000, // None
253        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
254        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
255        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
256        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
257        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
258        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
259        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
260        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
261        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
262        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
263        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
264        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
265        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
266        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
267        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
268        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
269        MMU_READ_DATA_TIMEOUT         = 0x1200, // Read & Watchdog timeout
270    };
271
272    // miss types for data cache
273    enum dcache_miss_type_e
274    {
275        PTE1_MISS,
276        PTE2_MISS,
277        PROC_MISS,
278    };
279
280    // this enumeration type extends the ExternalAcessTypes defined in iss2.h
281    enum xtn_cop2_extension_e {
282        XTN_WDT_MAX = 26,              // Read & Write the watchdog timer threshold
283    };
284
285public:
286    sc_in<bool>                                p_clk;
287    sc_in<bool>                                p_resetn;
288    sc_in<bool>                                p_irq[iss_t::n_irq];
289    soclib::caba::VciInitiator<vci_param>      p_vci;
290    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
291    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
292    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
293
294private:
295
296    // STRUCTURAL PARAMETERS
297    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
298
299    const size_t   m_srcid;
300    const size_t   m_cc_global_id;
301    const size_t   m_nline_width;
302    const size_t   m_itlb_ways;
303    const size_t   m_itlb_sets;
304    const size_t   m_dtlb_ways;
305    const size_t   m_dtlb_sets;
306    const size_t   m_icache_ways;
307    const size_t   m_icache_sets;
308    const paddr_t  m_icache_yzmask;
309    const size_t   m_icache_words;
310    const size_t   m_dcache_ways;
311    const size_t   m_dcache_sets;
312    const paddr_t  m_dcache_yzmask;
313    const size_t   m_dcache_words;
314    const size_t   m_x_width;
315    const size_t   m_y_width;
316    const size_t   m_proc_id;
317    const uint32_t m_max_frozen_cycles;
318    const size_t   m_paddr_nbits;
319    uint32_t       m_debug_start_cycle;
320    bool           m_debug_ok;
321
322    uint32_t       m_dcache_paddr_ext_reset;
323    uint32_t       m_icache_paddr_ext_reset;
324
325    ////////////////////////////////////////
326    // Communication with processor ISS
327    ////////////////////////////////////////
328    typename iss_t::InstructionRequest  m_ireq;
329    typename iss_t::InstructionResponse m_irsp;
330    typename iss_t::DataRequest         m_dreq;
331    typename iss_t::DataResponse        m_drsp;
332
333    /////////////////////////////////////////////
334    // debug variables
335    /////////////////////////////////////////////
336    bool                                m_debug_previous_i_hit;
337    bool                                m_debug_previous_d_hit;
338    bool                                m_debug_icache_fsm;
339    bool                                m_debug_dcache_fsm;
340    bool                                m_debug_cmd_fsm;
341    uint32_t                            m_previous_status;
342
343
344    ///////////////////////////////
345    // Software visible REGISTERS
346    ///////////////////////////////
347    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
348    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
349    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
350    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
351    sc_signal<uint32_t>     r_mmu_ibvar;                  // mmu bad instruction address
352    sc_signal<uint32_t>     r_mmu_dbvar;                  // mmu bad data address
353    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
354    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
355    uint32_t                r_mmu_params;                // read-only
356    uint32_t                r_mmu_release;                // read_only
357
358
359    //////////////////////////////
360    // ICACHE FSM REGISTERS
361    //////////////////////////////
362    sc_signal<int>          r_icache_fsm;               // state register
363    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
364    sc_signal<paddr_t>      r_icache_vci_paddr;          // physical address
365    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
366
367    // icache miss handling
368    sc_signal<size_t>       r_icache_miss_way;            // selected way for cache update
369    sc_signal<size_t>       r_icache_miss_set;            // selected set for cache update
370    sc_signal<size_t>       r_icache_miss_word;            // word index ( cache update)
371    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
372    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
373
374    // coherence request handling
375    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
376    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
377    sc_signal<size_t>       r_icache_cc_word;            // word counter for cc update
378    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
379
380    // coherence clack handling
381    sc_signal<bool>         r_icache_clack_req;         // clack request
382    sc_signal<size_t>       r_icache_clack_way;            // clack way
383    sc_signal<size_t>       r_icache_clack_set;            // clack set
384
385    // icache flush handling
386    sc_signal<size_t>       r_icache_flush_count;        // slot counter used for cache flush
387
388    // communication between ICACHE FSM and VCI_CMD FSM
389    sc_signal<bool>         r_icache_miss_req;           // cached read miss
390    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
391
392    // communication between ICACHE FSM and DCACHE FSM
393    sc_signal<bool>            r_icache_tlb_miss_req;       // (set icache/reset dcache)
394    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
395
396    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
397    sc_signal<bool>         r_icache_cleanup_victim_req;
398    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
399
400    // communication between ICACHE FSM and CC_SEND FSM
401    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
402    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
403    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
404    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
405    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
406
407    // Physical address extension for data access
408    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
409
410    ///////////////////////////////
411    // DCACHE FSM REGISTERS
412    ///////////////////////////////
413    sc_signal<int>          r_dcache_fsm;               // state register
414    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
415    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
416    // registers written in P0 stage (used in P1 stage)
417    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
418    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
419    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
420    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
421    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
422    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
423    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
424    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
425    sc_signal<size_t>       r_dcache_save_cache_word;    // selected word (from dcache)
426    // registers used by the Dirty bit sub-fsm
427    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
428    sc_signal<size_t>       r_dcache_dirty_way;            // way to invalidate in dcache
429    sc_signal<size_t>       r_dcache_dirty_set;            // set to invalidate in dcache
430
431    // communication between DCACHE FSM and VCI_CMD FSM
432    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
433    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
434    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
435    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
436    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
437    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
438    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
439    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
440    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
441    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
442    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
443    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
444    sc_signal<trdid_t>      r_dcache_vci_miss_trdid;    // miss dcache trdid (for debug)
445
446    // register used for XTN inval
447    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
448    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
449
450    // handling dcache miss
451    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
452    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
453    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
454    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
455    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
456    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
457
458    // Watchdog timer (WDT) for MISS timeout exception (black-hole detection)
459    sc_signal<uint32_t>     r_dcache_miss_wdt_max;      // wdt triggering value
460    sc_signal<uint32_t>     r_dcache_miss_wdt;          // wdt counter
461    sc_signal<trdid_t>      r_dcache_wdt_timeout;       // timeout counter (for debug)
462
463    // handling coherence requests
464    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
465    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
466    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
467    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
468
469    // coherence clack handling
470    sc_signal<bool>         r_dcache_clack_req;         // clack request
471    sc_signal<size_t>       r_dcache_clack_way;         // clack way
472    sc_signal<size_t>       r_dcache_clack_set;         // clack set
473
474    // dcache flush handling
475    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
476
477    // ll response handling
478    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
479
480    // used by the TLB miss sub-fsm
481    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
482    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
483    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
484    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
485    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
486    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
487    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
488    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
489    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
490    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
491
492    // ITLB and DTLB invalidation
493    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
494    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
495
496    // communication between DCACHE FSM and ICACHE FSM
497    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
498    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
499
500    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
501    sc_signal<bool>         r_dcache_cleanup_victim_req;
502    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
503
504    // communication between DCACHE FSM and CC_SEND FSM
505    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
506    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
507    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
508    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
509    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
510
511    // dcache directory extension
512    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
513    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
514
515    // Physical address extension for data access
516    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
517
518    ///////////////////////////////////
519    // VCI_CMD FSM REGISTERS
520    ///////////////////////////////////
521    sc_signal<int>          r_vci_cmd_fsm;
522    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
523    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
524    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
525    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
526
527    ///////////////////////////////////
528    // VCI_RSP FSM REGISTERS
529    ///////////////////////////////////
530    sc_signal<int>          r_vci_rsp_fsm;
531    sc_signal<size_t>       r_vci_rsp_cpt;
532    sc_signal<bool>         r_vci_rsp_ins_error;
533    sc_signal<bool>         r_vci_rsp_data_error;
534    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
535    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
536
537    ///////////////////////////////////
538    //  CC_SEND FSM REGISTER
539    ///////////////////////////////////
540    sc_signal<int>          r_cc_send_fsm;                  // state register
541    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
542
543    ///////////////////////////////////
544    //  CC_RECEIVE FSM REGISTER
545    ///////////////////////////////////
546    sc_signal<int>          r_cc_receive_fsm;               // state register
547    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
548
549    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
550    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
551    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
552    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
553    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
554
555    // communication between CC_RECEIVE FSM and ICACHE FSM
556    sc_signal<bool>         r_cc_receive_icache_req;          // cc_receive to icache request
557    sc_signal<int>          r_cc_receive_icache_type;         // cc_receive type of request
558    sc_signal<size_t>       r_cc_receive_icache_way;          // cc_receive to icache way
559    sc_signal<size_t>       r_cc_receive_icache_set;          // cc_receive to icache set
560    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
561    sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
562
563    // communication between CC_RECEIVE FSM and DCACHE FSM
564    sc_signal<bool>         r_cc_receive_dcache_req;          // cc_receive to dcache request
565    sc_signal<int>          r_cc_receive_dcache_type;         // cc_receive type of request
566    sc_signal<size_t>       r_cc_receive_dcache_way;          // cc_receive to dcache way
567    sc_signal<size_t>       r_cc_receive_dcache_set;          // cc_receive to dcache set
568    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index
569    sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
570
571    ///////////////////////////////////
572    //  DSPIN CLACK INTERFACE REGISTER
573    ///////////////////////////////////
574    sc_signal<bool>         r_dspin_clack_req;
575    sc_signal<uint64_t>     r_dspin_clack_flit;
576
577    //////////////////////////////////////////////////////////////////
578    // processor, write buffer, caches , TLBs
579    //////////////////////////////////////////////////////////////////
580
581    iss_t                     r_iss;
582    MultiWriteBuffer<paddr_t> r_wbuf;
583    GenericCache<paddr_t>     r_icache;
584    GenericCache<paddr_t>     r_dcache;
585    GenericTlb<paddr_t>       r_itlb;
586    GenericTlb<paddr_t>       r_dtlb;
587
588    //////////////////////////////////////////////////////////////////
589    // llsc registration buffer
590    //////////////////////////////////////////////////////////////////
591
592    sc_signal<paddr_t>        r_dcache_llsc_paddr;
593    sc_signal<uint32_t>       r_dcache_llsc_key;
594    sc_signal<uint32_t>       r_dcache_llsc_count;
595    sc_signal<bool>           r_dcache_llsc_valid;
596
597    ////////////////////////////////
598    // Activity counters
599    ////////////////////////////////
600    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
601    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
602    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
603    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
604
605    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
606    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
607    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
608    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
609
610    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
611    uint32_t m_cpt_total_cycles;            // total number of cycles
612
613    // Cache activity counters
614    uint32_t m_cpt_data_read;               // total number of read data
615    uint32_t m_cpt_data_write;              // total number of write data
616    uint32_t m_cpt_data_miss;               // number of read miss
617    uint32_t m_cpt_ins_miss;                // number of instruction miss
618    uint32_t m_cpt_unc_read;                // number of read uncached
619    uint32_t m_cpt_write_cached;            // number of cached write
620    uint32_t m_cpt_ins_read;                // number of instruction read
621    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
622
623    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
624    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
625    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
626    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
627
628    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
629    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
630    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
631    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
632    uint32_t m_cpt_icache_unc_transaction;
633
634    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
635    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
636    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
637    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
638    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
639    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
640
641    // TLB activity counters
642    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
643    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
644    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
645    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
646    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
647
648    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
649    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
650    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
651    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
652    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
653    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
654    uint32_t m_cpt_tlb_occup_dcache;
655
656    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
657    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
658    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
659    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
660    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
661    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
662    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
663
664    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
665    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
666    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
667    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
668    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
669    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
670    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
671    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
672
673    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
674    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
675    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
676    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
677    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
678    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
679    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
680    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
681
682    // coherence activity counters
683    uint32_t m_cpt_cc_update_icache;        // number of coherence update instruction commands
684    uint32_t m_cpt_cc_update_dcache;        // number of coherence update data commands
685    uint32_t m_cpt_cc_inval_icache;         // number of coherence inval instruction commands
686    uint32_t m_cpt_cc_inval_dcache;         // number of coherence inval data commands
687    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast commands
688
689    uint32_t m_cost_updt_data_frz;          // number of frozen cycles related to coherence update data packets
690    uint32_t m_cost_inval_ins_frz;          // number of frozen cycles related to coherence inval instruction packets
691    uint32_t m_cost_inval_data_frz;         // number of frozen cycles related to coherence inval data packets
692    uint32_t m_cost_broadcast_frz;          // number of frozen cycles related to coherence broadcast packets
693
694    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence cleanup packets
695    uint32_t m_cpt_cc_cleanup_data;         // number of coherence cleanup packets
696
697    uint32_t m_cpt_icleanup_transaction;    // number of instruction cleanup transactions
698    uint32_t m_cpt_dcleanup_transaction;    // number of instructinumber of data cleanup transactions
699    uint32_t m_cost_icleanup_transaction;   // cumulated duration for VCI instruction cleanup transactions
700    uint32_t m_cost_dcleanup_transaction;   // cumulated duration for VCI data cleanup transactions
701
702    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
703    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
704
705    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
706    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
707
708    // FSM activity counters
709    uint32_t m_cpt_fsm_icache     [64];
710    uint32_t m_cpt_fsm_dcache     [64];
711    uint32_t m_cpt_fsm_cmd        [64];
712    uint32_t m_cpt_fsm_rsp        [64];
713    uint32_t m_cpt_fsm_cc_receive [64];
714    uint32_t m_cpt_fsm_cc_send    [64];
715
716    uint32_t m_cpt_stop_simulation;       // used to stop simulation if frozen
717    bool     m_monitor_ok;                // used to debug cache output
718    uint32_t m_monitor_base;
719    uint32_t m_monitor_length;
720
721protected:
722    SC_HAS_PROCESS(VciCcVCacheWrapper);
723
724public:
725    VciCcVCacheWrapper(
726        sc_module_name                      name,
727        const int                           proc_id,
728        const soclib::common::MappingTable  &mtd,
729        const soclib::common::IntTab        &srcid,
730        const size_t                        cc_global_id,
731        const size_t                        itlb_ways,
732        const size_t                        itlb_sets,
733        const size_t                        dtlb_ways,
734        const size_t                        dtlb_sets,
735        const size_t                        icache_ways,
736        const size_t                        icache_sets,
737        const size_t                        icache_words,
738        const size_t                        dcache_ways,
739        const size_t                        dcache_sets,
740        const size_t                        dcache_words,
741        const size_t                        wbuf_nlines,
742        const size_t                        wbuf_nwords,
743        const size_t                        x_width,
744        const size_t                        y_width,
745        const uint32_t                      max_frozen_cycles,
746        const uint32_t                      debug_start_cycle,
747        const bool                          debug_ok );
748
749    ~VciCcVCacheWrapper();
750
751    void print_cpi();
752    void print_stats();
753    void clear_stats();
754    void print_trace(size_t mode = 0);
755    void cache_monitor(paddr_t addr);
756    void start_monitor(paddr_t,paddr_t);
757    void stop_monitor();
758    inline void iss_set_debug_mask(uint v)
759    {
760        r_iss.set_debug_mask(v);
761    }
762
763    /////////////////////////////////////////////////////////////
764    // Set the m_dcache_paddr_ext_reset attribute
765    //
766    // The r_dcache_paddr_ext register will be initialized after
767    // reset with the m_dcache_paddr_ext_reset value
768    /////////////////////////////////////////////////////////////
769    inline void set_dcache_paddr_ext_reset(uint32_t v)
770    {
771        m_dcache_paddr_ext_reset = v;
772    }
773
774    /////////////////////////////////////////////////////////////
775    // Set the m_icache_paddr_ext_reset attribute
776    //
777    // The r_icache_paddr_ext register will be initialized after
778    // reset with the m_icache_paddr_ext_reset value
779    /////////////////////////////////////////////////////////////
780    inline void set_icache_paddr_ext_reset(uint32_t v)
781    {
782        m_icache_paddr_ext_reset = v;
783    }
784
785private:
786    void transition();
787    void genMoore();
788
789    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
790    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
791};
792
793}}
794
795#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
796
797// Local Variables:
798// tab-width: 4
799// c-basic-offset: 4
800// c-file-offsets:((innamespace . 0)(inline-open . 0))
801// indent-tabs-mode: nil
802// End:
803
804// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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