Context Navigation

source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 845

Last change on this file since 845 was 845, checked in by cfuguet, 10 years ago

reconf: introducing watchdog timer in the vci_cc_vcache_wrapper

The watchdog timer (r_dcache_miss_wdt) starts counting when there is a READ MISS in the cache.

It triggers an error to the processor when the waiting cycles are greater than a threshold defined in the reg r_dcache_miss_wdt_max.

File size: 243.4 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64
65	"ICACHE_CC_CHECK",
66	"ICACHE_CC_UPDT",
67	"ICACHE_CC_INVAL",
68	};
69
70	const char * dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IC_PADDR_EXT",
90	"DCACHE_XTN_IT_INVAL",
91	"DCACHE_XTN_DC_FLUSH",
92	"DCACHE_XTN_DC_FLUSH_GO",
93	"DCACHE_XTN_DC_INVAL_VA",
94	"DCACHE_XTN_DC_INVAL_PA",
95	"DCACHE_XTN_DC_INVAL_END",
96	"DCACHE_XTN_DC_INVAL_GO",
97	"DCACHE_XTN_DT_INVAL",
98
99	"DCACHE_DIRTY_GET_PTE",
100	"DCACHE_DIRTY_WAIT",
101
102	"DCACHE_MISS_SELECT",
103	"DCACHE_MISS_CLEAN",
104	"DCACHE_MISS_WAIT",
105	"DCACHE_MISS_DATA_UPDT",
106	"DCACHE_MISS_DIR_UPDT",
107
108	"DCACHE_UNC_WAIT",
109	"DCACHE_LL_WAIT",
110	"DCACHE_SC_WAIT",
111
112	"DCACHE_CC_CHECK",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_INVAL",
115
116	"DCACHE_INVAL_TLB_SCAN",
117	};
118
119	const char * cmd_fsm_state_str[] = {
120	"CMD_IDLE",
121	"CMD_INS_MISS",
122	"CMD_INS_UNC",
123	"CMD_DATA_MISS",
124	"CMD_DATA_UNC_READ",
125	"CMD_DATA_UNC_WRITE",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char * vci_pktid_type_str[] = {
133	"TYPE_DATA_UNC",
134	"TYPE_READ_DATA_MISS",
135	"TYPE_READ_INS_UNC",
136	"TYPE_READ_INS_MISS",
137	"TYPE_WRITE",
138	"TYPE_CAS",
139	"TYPE_LL",
140	"TYPE_SC",
141	};
142
143	const char * vci_cmd_type_str[] = {
144	"NOP or STORE_COND",
145	"READ",
146	"WRITE",
147	"LOCKED_READ"
148	};
149
150	const char * rsp_fsm_state_str[] = {
151	"RSP_IDLE",
152	"RSP_INS_MISS",
153	"RSP_INS_UNC",
154	"RSP_DATA_MISS",
155	"RSP_DATA_UNC",
156	"RSP_DATA_LL",
157	"RSP_DATA_WRITE",
158	};
159
160	const char * cc_receive_fsm_state_str[] = {
161	"CC_RECEIVE_IDLE",
162	"CC_RECEIVE_BRDCAST_HEADER",
163	"CC_RECEIVE_BRDCAST_NLINE",
164	"CC_RECEIVE_INS_INVAL_HEADER",
165	"CC_RECEIVE_INS_INVAL_NLINE",
166	"CC_RECEIVE_INS_UPDT_HEADER",
167	"CC_RECEIVE_INS_UPDT_NLINE",
168	"CC_RECEIVE_INS_UPDT_DATA",
169	"CC_RECEIVE_DATA_INVAL_HEADER",
170	"CC_RECEIVE_DATA_INVAL_NLINE",
171	"CC_RECEIVE_DATA_UPDT_HEADER",
172	"CC_RECEIVE_DATA_UPDT_NLINE",
173	"CC_RECEIVE_DATA_UPDT_DATA",
174	};
175
176	const char * cc_send_fsm_state_str[] = {
177	"CC_SEND_IDLE",
178	"CC_SEND_CLEANUP_1",
179	"CC_SEND_CLEANUP_2",
180	"CC_SEND_MULTI_ACK",
181	};
182	}
183
184	#define tmpl(...) \
185	template<typename vci_param, \
186	size_t dspin_in_width, \
187	size_t dspin_out_width, \
188	typename iss_t> __VA_ARGS__ \
189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
190
191	using namespace soclib::common;
192
193	/////////////////////////////////
194	tmpl(/**/)::VciCcVCacheWrapper(
195	sc_module_name name,
196	const int proc_id,
197	const MappingTable &mtd,
198	const IntTab &srcid,
199	const size_t cc_global_id,
200	const size_t itlb_ways,
201	const size_t itlb_sets,
202	const size_t dtlb_ways,
203	const size_t dtlb_sets,
204	const size_t icache_ways,
205	const size_t icache_sets,
206	const size_t icache_words,
207	const size_t dcache_ways,
208	const size_t dcache_sets,
209	const size_t dcache_words,
210	const size_t wbuf_nlines,
211	const size_t wbuf_nwords,
212	const size_t x_width,
213	const size_t y_width,
214	const uint32_t max_frozen_cycles,
215	const uint32_t debug_start_cycle,
216	const bool debug_ok)
217	: soclib::caba::BaseModule(name),
218
219	p_clk("p_clk"),
220	p_resetn("p_resetn"),
221	p_vci("p_vci"),
222	p_dspin_m2p("p_dspin_m2p"),
223	p_dspin_p2m("p_dspin_p2m"),
224	p_dspin_clack("p_dspin_clack"),
225
226	m_cacheability_table( mtd.getCacheabilityTable()),
227	m_srcid(mtd.indexForId(srcid)),
228	m_cc_global_id(cc_global_id),
229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
230	m_itlb_ways(itlb_ways),
231	m_itlb_sets(itlb_sets),
232	m_dtlb_ways(dtlb_ways),
233	m_dtlb_sets(dtlb_sets),
234	m_icache_ways(icache_ways),
235	m_icache_sets(icache_sets),
236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
237	m_icache_words(icache_words),
238	m_dcache_ways(dcache_ways),
239	m_dcache_sets(dcache_sets),
240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
241	m_dcache_words(dcache_words),
242	m_x_width(x_width),
243	m_y_width(y_width),
244	m_proc_id(proc_id),
245	m_max_frozen_cycles(max_frozen_cycles),
246	m_paddr_nbits(vci_param::N),
247	m_debug_start_cycle(debug_start_cycle),
248	m_debug_ok(debug_ok),
249	m_dcache_paddr_ext_reset(0),
250	m_icache_paddr_ext_reset(0),
251
252	r_mmu_ptpr("r_mmu_ptpr"),
253	r_mmu_mode("r_mmu_mode"),
254	r_mmu_word_lo("r_mmu_word_lo"),
255	r_mmu_word_hi("r_mmu_word_hi"),
256	r_mmu_ibvar("r_mmu_ibvar"),
257	r_mmu_dbvar("r_mmu_dbvar"),
258	r_mmu_ietr("r_mmu_ietr"),
259	r_mmu_detr("r_mmu_detr"),
260
261	r_icache_fsm("r_icache_fsm"),
262	r_icache_fsm_save("r_icache_fsm_save"),
263	r_icache_vci_paddr("r_icache_vci_paddr"),
264	r_icache_vaddr_save("r_icache_vaddr_save"),
265
266	r_icache_miss_way("r_icache_miss_way"),
267	r_icache_miss_set("r_icache_miss_set"),
268	r_icache_miss_word("r_icache_miss_word"),
269	r_icache_miss_inval("r_icache_miss_inval"),
270	r_icache_miss_clack("r_icache_miss_clack"),
271
272	r_icache_cc_way("r_icache_cc_way"),
273	r_icache_cc_set("r_icache_cc_set"),
274	r_icache_cc_word("r_icache_cc_word"),
275	r_icache_cc_need_write("r_icache_cc_need_write"),
276
277	r_icache_flush_count("r_icache_flush_count"),
278
279	r_icache_miss_req("r_icache_miss_req"),
280	r_icache_unc_req("r_icache_unc_req"),
281
282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
284
285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
287
288	r_icache_cc_send_req("r_icache_cc_send_req"),
289	r_icache_cc_send_type("r_icache_cc_send_type"),
290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
291	r_icache_cc_send_way("r_icache_cc_send_way"),
292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
293
294	r_dcache_fsm("r_dcache_fsm"),
295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
297
298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
299	r_dcache_updt_req("r_dcache_updt_req"),
300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
301	r_dcache_save_wdata("r_dcache_save_wdata"),
302	r_dcache_save_be("r_dcache_save_be"),
303	r_dcache_save_paddr("r_dcache_save_paddr"),
304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
307
308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
309	r_dcache_dirty_way("r_dcache_dirty_way"),
310	r_dcache_dirty_set("r_dcache_dirty_set"),
311
312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
324
325	r_dcache_xtn_way("r_dcache_xtn_way"),
326	r_dcache_xtn_set("r_dcache_xtn_set"),
327
328	r_dcache_miss_type("r_dcache_miss_type"),
329	r_dcache_miss_word("r_dcache_miss_word"),
330	r_dcache_miss_way("r_dcache_miss_way"),
331	r_dcache_miss_set("r_dcache_miss_set"),
332	r_dcache_miss_inval("r_dcache_miss_inval"),
333	r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
334	r_dcache_miss_wdt("r_dcache_miss_wdt"),
335
336	r_dcache_cc_way("r_dcache_cc_way"),
337	r_dcache_cc_set("r_dcache_cc_set"),
338	r_dcache_cc_word("r_dcache_cc_word"),
339	r_dcache_cc_need_write("r_dcache_cc_need_write"),
340
341	r_dcache_flush_count("r_dcache_flush_count"),
342
343	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
344
345	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
346	r_dcache_tlb_ins("r_dcache_tlb_ins"),
347	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
348	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
349	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
350	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
351	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
352	r_dcache_tlb_way("r_dcache_tlb_way"),
353	r_dcache_tlb_set("r_dcache_tlb_set"),
354
355	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
356	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
357
358	r_dcache_xtn_req("r_dcache_xtn_req"),
359	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
360
361	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
362	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
363
364	r_dcache_cc_send_req("r_dcache_cc_send_req"),
365	r_dcache_cc_send_type("r_dcache_cc_send_type"),
366	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
367	r_dcache_cc_send_way("r_dcache_cc_send_way"),
368	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
369
370	r_vci_cmd_fsm("r_vci_cmd_fsm"),
371	r_vci_cmd_min("r_vci_cmd_min"),
372	r_vci_cmd_max("r_vci_cmd_max"),
373	r_vci_cmd_cpt("r_vci_cmd_cpt"),
374	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
375
376	r_vci_rsp_fsm("r_vci_rsp_fsm"),
377	r_vci_rsp_cpt("r_vci_rsp_cpt"),
378	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
379	r_vci_rsp_data_error("r_vci_rsp_data_error"),
380	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
381	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
382
383	r_cc_send_fsm("r_cc_send_fsm"),
384	r_cc_send_last_client("r_cc_send_last_client"),
385
386	r_cc_receive_fsm("r_cc_receive_fsm"),
387	r_cc_receive_data_ins("r_cc_receive_data_ins"),
388	r_cc_receive_word_idx("r_cc_receive_word_idx"),
389	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
390	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
391	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
392
393	r_cc_receive_icache_req("r_cc_receive_icache_req"),
394	r_cc_receive_icache_type("r_cc_receive_icache_type"),
395	r_cc_receive_icache_way("r_cc_receive_icache_way"),
396	r_cc_receive_icache_set("r_cc_receive_icache_set"),
397	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
398	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
399
400	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
401	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
402	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
403	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
404	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
405	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
406
407	r_iss(this->name(), proc_id),
408	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
409	r_icache("icache", icache_ways, icache_sets, icache_words),
410	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
411	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
412	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
413	{
414	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
415
416	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
417	"Need more PLEN bits.");
418
419	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
420	"Need more TRDID bits.");
421
422	assert((icache_words == dcache_words) and
423	"icache_words and dcache_words parameters must be equal");
424
425	assert((itlb_sets == dtlb_sets) and
426	"itlb_sets and dtlb_sets parameters must be etqual");
427
428	assert((itlb_ways == dtlb_ways) and
429	"itlb_ways and dtlb_ways parameters must be etqual");
430
431	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
432	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
433	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
434	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
435	(uint32_log2(m_icache_words << 2));
436
437	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
438
439	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
440	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
441
442	SC_METHOD(transition);
443	dont_initialize();
444	sensitive << p_clk.pos();
445
446	SC_METHOD(genMoore);
447	dont_initialize();
448	sensitive << p_clk.neg();
449
450	typename iss_t::CacheInfo cache_info;
451	cache_info.has_mmu = true;
452	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
453	cache_info.icache_assoc = icache_ways;
454	cache_info.icache_n_lines = icache_sets;
455	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
456	cache_info.dcache_assoc = dcache_ways;
457	cache_info.dcache_n_lines = dcache_sets;
458	r_iss.setCacheInfo(cache_info);
459	}
460
461	/////////////////////////////////////
462	tmpl(/**/)::~VciCcVCacheWrapper()
463	/////////////////////////////////////
464	{
465	delete [] r_dcache_in_tlb;
466	delete [] r_dcache_contains_ptd;
467	}
468
469	////////////////////////
470	tmpl(void)::print_cpi()
471	////////////////////////
472	{
473	std::cout << name() << " CPI = "
474	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
475	}
476
477	////////////////////////////////////
478	tmpl(void)::print_trace(size_t mode)
479	////////////////////////////////////
480	{
481	// b0 : write buffer trace
482	// b1 : dump processor registers
483	// b2 : dcache trace
484	// b3 : icache trace
485	// b4 : dtlb trace
486	// b5 : itlb trace
487	// b6 : SR (ISS register 32)
488
489	std::cout << std::dec << "PROC " << name() << std::endl;
490
491	std::cout << " " << m_ireq << std::endl;
492	std::cout << " " << m_irsp << std::endl;
493	std::cout << " " << m_dreq << std::endl;
494	std::cout << " " << m_drsp << std::endl;
495
496	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
497	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
498	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
499	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
500	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
501	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
502	<< " \| MMU = " << r_mmu_mode.read();
503
504	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
505	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
506	std::cout << std::endl;
507
508	if (mode & 0x01)
509	{
510	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
511	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
512	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
513	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
514
515	r_wbuf.printTrace((mode >> 1) & 1);
516	}
517	if (mode & 0x02)
518	{
519	r_iss.dump();
520	}
521	if (mode & 0x04)
522	{
523	std::cout << " Data Cache" << std::endl;
524	r_dcache.printTrace();
525	}
526	if (mode & 0x08)
527	{
528	std::cout << " Instruction Cache" << std::endl;
529	r_icache.printTrace();
530	}
531	if (mode & 0x10)
532	{
533	std::cout << " Data TLB" << std::endl;
534	r_dtlb.printTrace();
535	}
536	if (mode & 0x20)
537	{
538	std::cout << " Instruction TLB" << std::endl;
539	r_itlb.printTrace();
540	}
541	if (mode & 0x40)
542	{
543	uint32_t status = r_iss.debugGetRegisterValue(32);
544	std::cout << name();
545	if (status != m_previous_status ) std::cout << " NEW ";
546	std::cout << " status = " << std::hex << status << " " << std::endl;
547	m_previous_status = status;
548	}
549	}
550
551	//////////////////////////////////////////
552	tmpl(void)::cache_monitor(paddr_t addr)
553	//////////////////////////////////////////
554	{
555	bool cache_hit;
556	size_t cache_way = 0;
557	size_t cache_set = 0;
558	size_t cache_word = 0;
559	uint32_t cache_rdata = 0;
560
561	cache_hit = r_dcache.read_neutral(addr,
562	&cache_rdata,
563	&cache_way,
564	&cache_set,
565	&cache_word);
566
567	if (cache_hit != m_debug_previous_d_hit)
568	{
569	std::cout << "Monitor PROC " << name()
570	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
571	<< " / HIT = " << cache_hit
572	<< " / PADDR = " << std::hex << addr
573	<< " / DATA = " << cache_rdata
574	<< " / WAY = " << cache_way << std::endl;
575	m_debug_previous_d_hit = cache_hit;
576	}
577
578	cache_hit = r_icache.read_neutral(addr,
579	&cache_rdata,
580	&cache_way,
581	&cache_set,
582	&cache_word);
583
584	if (cache_hit != m_debug_previous_i_hit)
585	{
586	std::cout << "Monitor PROC " << name()
587	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
588	<< " / HIT = " << cache_hit
589	<< " / PADDR = " << std::hex << addr
590	<< " / DATA = " << cache_rdata
591	<< " / WAY = " << cache_way << std::endl;
592	m_debug_previous_i_hit = cache_hit;
593	}
594	}
595
596	/*
597	////////////////////////
598	tmpl(void)::print_stats()
599	////////////////////////
600	{
601	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
602	std::cout << name() << std::endl
603	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
604	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
605	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
606	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
607	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
608	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
609	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
610	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
611	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
612	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
613	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
614	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
615	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
616	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
617	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
618	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
619	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
620	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
621	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
622	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
623	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
624	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
625	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
626	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
627	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
628	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
629	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
630	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
631	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
632	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
633	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
634	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
635	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
636	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
637	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
638	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
639	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
640	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
641	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
642	}
643
644	////////////////////////
645	tmpl(void)::clear_stats()
646	////////////////////////
647	{
648	m_cpt_dcache_data_read = 0;
649	m_cpt_dcache_data_write = 0;
650	m_cpt_dcache_dir_read = 0;
651	m_cpt_dcache_dir_write = 0;
652	m_cpt_icache_data_read = 0;
653	m_cpt_icache_data_write = 0;
654	m_cpt_icache_dir_read = 0;
655	m_cpt_icache_dir_write = 0;
656
657	m_cpt_frz_cycles = 0;
658	m_cpt_dcache_frz_cycles = 0;
659	m_cpt_total_cycles = 0;
660
661	m_cpt_read = 0;
662	m_cpt_write = 0;
663	m_cpt_data_miss = 0;
664	m_cpt_ins_miss = 0;
665	m_cpt_unc_read = 0;
666	m_cpt_write_cached = 0;
667	m_cpt_ins_read = 0;
668
669	m_cost_write_frz = 0;
670	m_cost_data_miss_frz = 0;
671	m_cost_unc_read_frz = 0;
672	m_cost_ins_miss_frz = 0;
673
674	m_cpt_imiss_transaction = 0;
675	m_cpt_dmiss_transaction = 0;
676	m_cpt_unc_transaction = 0;
677	m_cpt_write_transaction = 0;
678	m_cpt_icache_unc_transaction = 0;
679
680	m_cost_imiss_transaction = 0;
681	m_cost_dmiss_transaction = 0;
682	m_cost_unc_transaction = 0;
683	m_cost_write_transaction = 0;
684	m_cost_icache_unc_transaction = 0;
685	m_length_write_transaction = 0;
686
687	m_cpt_ins_tlb_read = 0;
688	m_cpt_ins_tlb_miss = 0;
689	m_cpt_ins_tlb_update_acc = 0;
690
691	m_cpt_data_tlb_read = 0;
692	m_cpt_data_tlb_miss = 0;
693	m_cpt_data_tlb_update_acc = 0;
694	m_cpt_data_tlb_update_dirty = 0;
695	m_cpt_ins_tlb_hit_dcache = 0;
696	m_cpt_data_tlb_hit_dcache = 0;
697	m_cpt_ins_tlb_occup_cache = 0;
698	m_cpt_data_tlb_occup_cache = 0;
699
700	m_cost_ins_tlb_miss_frz = 0;
701	m_cost_data_tlb_miss_frz = 0;
702	m_cost_ins_tlb_update_acc_frz = 0;
703	m_cost_data_tlb_update_acc_frz = 0;
704	m_cost_data_tlb_update_dirty_frz = 0;
705	m_cost_ins_tlb_occup_cache_frz = 0;
706	m_cost_data_tlb_occup_cache_frz = 0;
707
708	m_cpt_itlbmiss_transaction = 0;
709	m_cpt_itlb_ll_transaction = 0;
710	m_cpt_itlb_sc_transaction = 0;
711	m_cpt_dtlbmiss_transaction = 0;
712	m_cpt_dtlb_ll_transaction = 0;
713	m_cpt_dtlb_sc_transaction = 0;
714	m_cpt_dtlb_ll_dirty_transaction = 0;
715	m_cpt_dtlb_sc_dirty_transaction = 0;
716
717	m_cost_itlbmiss_transaction = 0;
718	m_cost_itlb_ll_transaction = 0;
719	m_cost_itlb_sc_transaction = 0;
720	m_cost_dtlbmiss_transaction = 0;
721	m_cost_dtlb_ll_transaction = 0;
722	m_cost_dtlb_sc_transaction = 0;
723	m_cost_dtlb_ll_dirty_transaction = 0;
724	m_cost_dtlb_sc_dirty_transaction = 0;
725
726	m_cpt_cc_update_data = 0;
727	m_cpt_cc_inval_ins = 0;
728	m_cpt_cc_inval_data = 0;
729	m_cpt_cc_broadcast = 0;
730
731	m_cost_updt_data_frz = 0;
732	m_cost_inval_ins_frz = 0;
733	m_cost_inval_data_frz = 0;
734	m_cost_broadcast_frz = 0;
735
736	m_cpt_cc_cleanup_data = 0;
737	m_cpt_cc_cleanup_ins = 0;
738	}
739
740	*/
741
742	/////////////////////////
743	tmpl(void)::transition()
744	/////////////////////////
745	{
746	if (not p_resetn.read())
747	{
748	r_iss.reset();
749	r_wbuf.reset();
750	r_icache.reset();
751	r_dcache.reset();
752	r_itlb.reset();
753	r_dtlb.reset();
754
755	r_dcache_fsm = DCACHE_IDLE;
756	r_icache_fsm = ICACHE_IDLE;
757	r_vci_cmd_fsm = CMD_IDLE;
758	r_vci_rsp_fsm = RSP_IDLE;
759	r_cc_receive_fsm = CC_RECEIVE_IDLE;
760	r_cc_send_fsm = CC_SEND_IDLE;
761
762	// reset data physical address extension
763	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
764
765	// reset inst physical address extension
766	r_icache_paddr_ext = m_icache_paddr_ext_reset;
767
768	// reset dcache directory extension
769	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
770	{
771	r_dcache_in_tlb[i] = false;
772	r_dcache_contains_ptd[i] = false;
773	}
774
775	// Response FIFOs and cleanup buffer
776	r_vci_rsp_fifo_icache.init();
777	r_vci_rsp_fifo_dcache.init();
778
779	// ICACHE & DCACHE activated
780	// ITLB & DTLB desactivated
781	r_mmu_mode = 0x3;
782
783	// No request from ICACHE FSM to CMD FSM
784	r_icache_miss_req = false;
785	r_icache_unc_req = false;
786
787	// No request from ICACHE_FSM to DCACHE FSM
788	r_icache_tlb_miss_req = false;
789
790	// No request from ICACHE_FSM to CC_SEND FSM
791	r_icache_cc_send_req = false;
792	r_icache_cleanup_victim_req = false;
793
794	r_icache_clack_req = false;
795
796	// No pending write in pipeline
797	r_dcache_wbuf_req = false;
798	r_dcache_updt_req = false;
799
800	// No request from DCACHE_FSM to CMD_FSM
801	r_dcache_vci_miss_req = false;
802	r_dcache_vci_unc_req = false;
803	r_dcache_vci_cas_req = false;
804	r_dcache_vci_ll_req = false;
805	r_dcache_vci_sc_req = false;
806
807	// No processor XTN request pending
808	r_dcache_xtn_req = false;
809
810	// No request from DCACHE FSM to CC_SEND FSM
811	r_dcache_cc_send_req = false;
812	r_dcache_cleanup_victim_req = false;
813
814	r_dcache_clack_req = false;
815
816	// Reset watchdog timer threshold to max value
817	r_dcache_miss_wdt_max = UINT32_MAX;
818
819	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
820	r_cc_receive_icache_req = false;
821	r_cc_receive_dcache_req = false;
822
823	// last cc_send client was dcache
824	r_cc_send_last_client = false;
825
826	// No pending cleanup after a replacement
827	r_icache_miss_clack = false;
828	r_dcache_miss_clack = false;
829
830	// No signalisation of a coherence request matching a pending miss
831	r_icache_miss_inval = false;
832	r_dcache_miss_inval = false;
833
834	r_dspin_clack_req = false;
835
836	// No signalisation of errors
837	r_vci_rsp_ins_error = false;
838	r_vci_rsp_data_error = false;
839
840	// Debug variables
841	m_debug_previous_i_hit = false;
842	m_debug_previous_d_hit = false;
843	m_debug_icache_fsm = false;
844	m_debug_dcache_fsm = false;
845	m_debug_cmd_fsm = false;
846
847	// activity counters
848	m_cpt_dcache_data_read = 0;
849	m_cpt_dcache_data_write = 0;
850	m_cpt_dcache_dir_read = 0;
851	m_cpt_dcache_dir_write = 0;
852	m_cpt_icache_data_read = 0;
853	m_cpt_icache_data_write = 0;
854	m_cpt_icache_dir_read = 0;
855	m_cpt_icache_dir_write = 0;
856
857	m_cpt_frz_cycles = 0;
858	m_cpt_total_cycles = 0;
859	m_cpt_stop_simulation = 0;
860
861	m_cpt_data_miss = 0;
862	m_cpt_ins_miss = 0;
863	m_cpt_unc_read = 0;
864	m_cpt_write_cached = 0;
865	m_cpt_ins_read = 0;
866
867	m_cost_write_frz = 0;
868	m_cost_data_miss_frz = 0;
869	m_cost_unc_read_frz = 0;
870	m_cost_ins_miss_frz = 0;
871
872	m_cpt_imiss_transaction = 0;
873	m_cpt_dmiss_transaction = 0;
874	m_cpt_unc_transaction = 0;
875	m_cpt_write_transaction = 0;
876	m_cpt_icache_unc_transaction = 0;
877
878	m_cost_imiss_transaction = 0;
879	m_cost_dmiss_transaction = 0;
880	m_cost_unc_transaction = 0;
881	m_cost_write_transaction = 0;
882	m_cost_icache_unc_transaction = 0;
883	m_length_write_transaction = 0;
884
885	m_cpt_ins_tlb_read = 0;
886	m_cpt_ins_tlb_miss = 0;
887	m_cpt_ins_tlb_update_acc = 0;
888
889	m_cpt_data_tlb_read = 0;
890	m_cpt_data_tlb_miss = 0;
891	m_cpt_data_tlb_update_acc = 0;
892	m_cpt_data_tlb_update_dirty = 0;
893	m_cpt_ins_tlb_hit_dcache = 0;
894	m_cpt_data_tlb_hit_dcache = 0;
895	m_cpt_ins_tlb_occup_cache = 0;
896	m_cpt_data_tlb_occup_cache = 0;
897
898	m_cost_ins_tlb_miss_frz = 0;
899	m_cost_data_tlb_miss_frz = 0;
900	m_cost_ins_tlb_update_acc_frz = 0;
901	m_cost_data_tlb_update_acc_frz = 0;
902	m_cost_data_tlb_update_dirty_frz = 0;
903	m_cost_ins_tlb_occup_cache_frz = 0;
904	m_cost_data_tlb_occup_cache_frz = 0;
905
906	m_cpt_ins_tlb_inval = 0;
907	m_cpt_data_tlb_inval = 0;
908	m_cost_ins_tlb_inval_frz = 0;
909	m_cost_data_tlb_inval_frz = 0;
910
911	m_cpt_cc_broadcast = 0;
912
913	m_cost_updt_data_frz = 0;
914	m_cost_inval_ins_frz = 0;
915	m_cost_inval_data_frz = 0;
916	m_cost_broadcast_frz = 0;
917
918	m_cpt_cc_cleanup_data = 0;
919	m_cpt_cc_cleanup_ins = 0;
920
921	m_cpt_itlbmiss_transaction = 0;
922	m_cpt_itlb_ll_transaction = 0;
923	m_cpt_itlb_sc_transaction = 0;
924	m_cpt_dtlbmiss_transaction = 0;
925	m_cpt_dtlb_ll_transaction = 0;
926	m_cpt_dtlb_sc_transaction = 0;
927	m_cpt_dtlb_ll_dirty_transaction = 0;
928	m_cpt_dtlb_sc_dirty_transaction = 0;
929
930	m_cost_itlbmiss_transaction = 0;
931	m_cost_itlb_ll_transaction = 0;
932	m_cost_itlb_sc_transaction = 0;
933	m_cost_dtlbmiss_transaction = 0;
934	m_cost_dtlb_ll_transaction = 0;
935	m_cost_dtlb_sc_transaction = 0;
936	m_cost_dtlb_ll_dirty_transaction = 0;
937	m_cost_dtlb_sc_dirty_transaction = 0;
938	/*
939	m_cpt_dcache_frz_cycles = 0;
940	m_cpt_read = 0;
941	m_cpt_write = 0;
942	m_cpt_cc_update_data = 0;
943	m_cpt_cc_inval_ins = 0;
944	m_cpt_cc_inval_data = 0;
945	*/
946
947	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
948	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
949	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
950	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
951
952	// init the llsc reservation buffer
953	r_dcache_llsc_valid = false;
954	m_monitor_ok = false;
955
956	return;
957	}
958
959	// Response FIFOs default values
960	bool vci_rsp_fifo_icache_get = false;
961	bool vci_rsp_fifo_icache_put = false;
962	uint32_t vci_rsp_fifo_icache_data = 0;
963
964	bool vci_rsp_fifo_dcache_get = false;
965	bool vci_rsp_fifo_dcache_put = false;
966	uint32_t vci_rsp_fifo_dcache_data = 0;
967
968	// updt fifo
969	bool cc_receive_updt_fifo_get = false;
970	bool cc_receive_updt_fifo_put = false;
971	uint32_t cc_receive_updt_fifo_be = 0;
972	uint32_t cc_receive_updt_fifo_data = 0;
973	bool cc_receive_updt_fifo_eop = false;
974
975	#ifdef INSTRUMENTATION
976	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
977	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
978	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
979	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
980	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
981	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
982	#endif
983
984	m_cpt_total_cycles++;
985
986	m_debug_icache_fsm = m_debug_icache_fsm \|\|
987	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
988	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
989	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
990	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
991	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
992
993	/////////////////////////////////////////////////////////////////////
994	// Get data and instruction requests from processor
995	///////////////////////////////////////////////////////////////////////
996
997	r_iss.getRequests(m_ireq, m_dreq);
998
999	////////////////////////////////////////////////////////////////////////////////////
1000	// ICACHE_FSM
1001	//
1002	// 1/ Coherence operations
1003	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1004	// - There is a coherence request when r_tgt_icache_req is set.
1005	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1006	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1007	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1008	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1009	// - For both types of requests, actions associated to the pre-empted state
1010	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1011	// or CC_CLACK) to execute the requested coherence operation, and returns
1012	// to the pre-empted state.
1013	//
1014	// 2/ Processor requests
1015	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1016	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1017	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1018	// flip-flops are reset when the transaction starts.
1019	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1020	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1021	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1022	// The availability of the missing cache line is signaled by the response fifo,
1023	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1024	// and ICACHE_MISS_DIR_UPDT states.
1025	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1026	// to wait the response from the RSP FSM, through the response fifo.
1027	// The missing instruction is directly returned to processor in this state.
1028	//
1029	// 3/ TLB miss
1030	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1031	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1032	// register, and goes to the ICACHE_TLB_WAIT state.
1033	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1034	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1035	// to signal the completion.
1036	//
1037	// 4/ XTN requests
1038	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1039	// using the r_dcache_xtn_req flip-flop.
1040	// The request opcode and the address to be invalidated are transmitted
1041	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1042	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1043	// is completed.
1044	//
1045	// 5/ Error Handling
1046	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1047	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1048	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1049	////////////////////////////////////////////////////////////////////////////////////////
1050
1051	// default value for m_irsp
1052	m_irsp.valid = false;
1053	m_irsp.error = false;
1054	m_irsp.instruction = 0;
1055
1056	switch (r_icache_fsm.read())
1057	{
1058	/////////////////
1059	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1060	// and coherence requests with a fixed priority:
1061	// 1/ Coherence requests => ICACHE_CC_CHECK
1062	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1063	// 3/ tlb miss => ICACHE_TLB_WAIT
1064	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1065	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1066	{
1067	// coherence clack interrupt
1068	if (r_icache_clack_req.read())
1069	{
1070	r_icache_fsm = ICACHE_CC_CHECK;
1071	r_icache_fsm_save = r_icache_fsm.read();
1072	break;
1073	}
1074
1075	// coherence interrupt
1076	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1077	{
1078	r_icache_fsm = ICACHE_CC_CHECK;
1079	r_icache_fsm_save = r_icache_fsm.read();
1080	break;
1081	}
1082
1083	// XTN requests sent by DCACHE FSM
1084	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1085	// because they require access to icache or itlb, that are already accessed
1086	if (r_dcache_xtn_req.read())
1087	{
1088	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1089	{
1090	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1091	}
1092	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1093	{
1094	r_icache_flush_count = 0;
1095	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1096	}
1097	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1098	{
1099	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1100	}
1101	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1102	{
1103	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1104	}
1105	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1106	{
1107	if (sizeof(paddr_t) <= 32)
1108	{
1109	assert(r_mmu_word_hi.read() == 0 &&
1110	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1111	r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
1112	}
1113	else
1114	{
1115	r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
1116	(paddr_t) r_mmu_word_lo.read();
1117	}
1118	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1119	}
1120	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1121	{
1122	r_icache_paddr_ext = r_dcache_save_wdata.read();
1123	r_dcache_xtn_req = false;
1124	}
1125	else
1126	{
1127	assert(false and
1128	"undefined XTN request received by ICACHE FSM");
1129	}
1130	break;
1131	} // end if xtn_req
1132
1133	// processor request
1134	if (m_ireq.valid )
1135	{
1136	bool cacheable;
1137	paddr_t paddr;
1138	bool tlb_hit = false;
1139	pte_info_t tlb_flags;
1140	size_t tlb_way;
1141	size_t tlb_set;
1142	paddr_t tlb_nline;
1143	uint32_t cache_inst = 0;
1144	size_t cache_way;
1145	size_t cache_set;
1146	size_t cache_word;
1147	int cache_state = CACHE_SLOT_STATE_EMPTY;
1148
1149	// We register processor request
1150	r_icache_vaddr_save = m_ireq.addr;
1151	paddr = (paddr_t) m_ireq.addr;
1152
1153	// sytematic itlb access (if activated)
1154	if (r_mmu_mode.read() & INS_TLB_MASK)
1155	{
1156
1157	#ifdef INSTRUMENTATION
1158	m_cpt_itlb_read++;
1159	#endif
1160	tlb_hit = r_itlb.translate(m_ireq.addr,
1161	&paddr,
1162	&tlb_flags,
1163	&tlb_nline, // unused
1164	&tlb_way, // unused
1165	&tlb_set); // unused
1166	}
1167	else if (vci_param::N > 32)
1168	{
1169	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1170	}
1171
1172	// systematic icache access (if activated)
1173	if (r_mmu_mode.read() & INS_CACHE_MASK)
1174	{
1175
1176
1177	#ifdef INSTRUMENTATION
1178	m_cpt_icache_data_read++;
1179	m_cpt_icache_dir_read++;
1180	#endif
1181	r_icache.read(paddr,
1182	&cache_inst,
1183	&cache_way,
1184	&cache_set,
1185	&cache_word,
1186	&cache_state);
1187	}
1188
1189	// We compute cacheability and check access rights:
1190	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1191	// and the access rights are defined by the U and X bits in the PTE.
1192	// - If MMU not activated : cacheability is defined by the segment table,
1193	// and there is no access rights checking
1194
1195	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1196	{
1197	// cacheability
1198	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1199	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1200	}
1201	else // itlb activated
1202	{
1203	if (tlb_hit) // ITLB hit
1204	{
1205	// cacheability
1206	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1207	else cacheable = tlb_flags.c;
1208
1209	// access rights checking
1210	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1211	{
1212
1213	#if DEBUG_ICACHE
1214	if ( m_debug_icache_fsm )
1215	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1216	<< " : PADDR = " << std::hex << paddr << std::endl;
1217	#endif
1218	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1219	r_mmu_ibvar = m_ireq.addr;
1220	m_irsp.valid = true;
1221	m_irsp.error = true;
1222	m_irsp.instruction = 0;
1223	break;
1224	}
1225	else if (not tlb_flags.x)
1226	{
1227
1228	#if DEBUG_ICACHE
1229	if ( m_debug_icache_fsm )
1230	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1231	<< " : PADDR = " << std::hex << paddr << std::endl;
1232	#endif
1233	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1234	r_mmu_ibvar = m_ireq.addr;
1235	m_irsp.valid = true;
1236	m_irsp.error = true;
1237	m_irsp.instruction = 0;
1238	break;
1239	}
1240	}
1241	else // ITLB miss
1242	{
1243
1244	#ifdef INSTRUMENTATION
1245	m_cpt_itlb_miss++;
1246	#endif
1247	r_icache_fsm = ICACHE_TLB_WAIT;
1248	r_icache_tlb_miss_req = true;
1249	break;
1250	}
1251	} // end if itlb activated
1252
1253	// physical address registration
1254	r_icache_vci_paddr = paddr;
1255
1256	// Finally, we send the response to processor, and compute next state
1257	if (cacheable)
1258	{
1259	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1260	{
1261
1262	#ifdef INSTRUMENTATION
1263	m_cpt_icache_miss++;
1264	#endif
1265	// we request a VCI transaction
1266	r_icache_fsm = ICACHE_MISS_SELECT;
1267	#if DEBUG_ICACHE
1268	if (m_debug_icache_fsm)
1269	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1270	<< " : PADDR = " << std::hex << paddr << std::endl;
1271	#endif
1272	r_icache_miss_req = true;
1273	}
1274	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1275	{
1276	// stalled until cleanup is acknowledged
1277	r_icache_fsm = ICACHE_IDLE;
1278	}
1279	else // cache hit
1280	{
1281
1282	#ifdef INSTRUMENTATION
1283	m_cpt_ins_read++;
1284	#endif
1285	// return instruction to processor
1286	m_irsp.valid = true;
1287	m_irsp.instruction = cache_inst;
1288	r_icache_fsm = ICACHE_IDLE;
1289	#if DEBUG_ICACHE
1290	if (m_debug_icache_fsm)
1291	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1292	<< " : PADDR = " << std::hex << paddr
1293	<< " / INST = " << cache_inst << std::endl;
1294	#endif
1295	}
1296	}
1297	else // non cacheable read
1298	{
1299	r_icache_unc_req = true;
1300	r_icache_fsm = ICACHE_UNC_WAIT;
1301
1302	#if DEBUG_ICACHE
1303	if (m_debug_icache_fsm)
1304	{
1305	std::cout << " <PROC " << name()
1306	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1307	<< " : PADDR = " << std::hex << paddr << std::endl;
1308	}
1309	#endif
1310	}
1311	} // end if m_ireq.valid
1312	break;
1313	}
1314	/////////////////////
1315	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1316	// the itlb is udated by the DCACHE FSM, as well as the
1317	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1318	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1319	// reset the r_icache_tlb_miss_req flip-flop
1320	// external coherence request are accepted in this state.
1321	{
1322	// coherence clack interrupt
1323	if (r_icache_clack_req.read())
1324	{
1325	r_icache_fsm = ICACHE_CC_CHECK;
1326	r_icache_fsm_save = r_icache_fsm.read();
1327	break;
1328	}
1329
1330	// coherence interrupt
1331	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1332	{
1333	r_icache_fsm = ICACHE_CC_CHECK;
1334	r_icache_fsm_save = r_icache_fsm.read();
1335	break;
1336	}
1337
1338	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1339
1340	// DCACHE FSM signals response by reseting the request flip-flop
1341	if (not r_icache_tlb_miss_req.read())
1342	{
1343	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1344	{
1345	r_icache_tlb_rsp_error = false;
1346	m_irsp.error = true;
1347	m_irsp.valid = true;
1348	r_icache_fsm = ICACHE_IDLE;
1349	}
1350	else // tlb updated : return to IDLE state
1351	{
1352	r_icache_fsm = ICACHE_IDLE;
1353	}
1354	}
1355	break;
1356	}
1357	//////////////////////////
1358	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1359	{
1360	r_itlb.flush();
1361	r_dcache_xtn_req = false;
1362	r_icache_fsm = ICACHE_IDLE;
1363	break;
1364	}
1365	////////////////////////////
1366	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1367	// r_icache_flush_count as a slot counter,
1368	// looping in this state until all slots are visited.
1369	// It can require two cycles per slot:
1370	// We test here the slot state, and make the actual inval
1371	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1372	// A cleanup request is generated for each valid line
1373	{
1374	// coherence clack interrupt
1375	if (r_icache_clack_req.read())
1376	{
1377	r_icache_fsm = ICACHE_CC_CHECK;
1378	r_icache_fsm_save = r_icache_fsm.read();
1379	break;
1380	}
1381
1382	// coherence request (from CC_RECEIVE FSM)
1383	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1384	{
1385	r_icache_fsm = ICACHE_CC_CHECK;
1386	r_icache_fsm_save = r_icache_fsm.read();
1387	break;
1388	}
1389
1390	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1391	{
1392	int state;
1393	paddr_t tag;
1394	size_t way = r_icache_flush_count.read() / m_icache_sets;
1395	size_t set = r_icache_flush_count.read() % m_icache_sets;
1396
1397	#ifdef INSTRUMENTATION
1398	m_cpt_icache_dir_read++;
1399	#endif
1400	r_icache.read_dir(way,
1401	set,
1402	&tag,
1403	&state);
1404
1405	if (state == CACHE_SLOT_STATE_VALID) // inval required
1406	{
1407	// request cleanup
1408	r_icache_cc_send_req = true;
1409	r_icache_cc_send_nline = tag * m_icache_sets + set;
1410	r_icache_cc_send_way = way;
1411	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1412
1413	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1414	r_icache_miss_way = way;
1415	r_icache_miss_set = set;
1416	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1417	}
1418	else if (r_icache_flush_count.read() ==
1419	(m_icache_sets*m_icache_ways - 1)) // last slot
1420	{
1421	r_dcache_xtn_req = false;
1422	m_drsp.valid = true;
1423	r_icache_fsm = ICACHE_IDLE;
1424	}
1425
1426	// saturation counter, to have the same last slot condition
1427	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1428	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1429	{
1430	r_icache_flush_count = r_icache_flush_count.read() + 1;
1431	}
1432	}
1433	break;
1434	}
1435	///////////////////////////////
1436	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1437	{
1438	size_t way = r_icache_miss_way.read();
1439	size_t set = r_icache_miss_set.read();
1440
1441	#ifdef INSTRUMENTATION
1442	m_cpt_icache_dir_write++;
1443	#endif
1444
1445	r_icache.write_dir(way,
1446	set,
1447	CACHE_SLOT_STATE_ZOMBI);
1448
1449	if (r_icache_flush_count.read() ==
1450	(m_icache_sets*m_icache_ways - 1)) // last slot
1451	{
1452	r_dcache_xtn_req = false;
1453	m_drsp.valid = true;
1454	r_icache_fsm = ICACHE_IDLE;
1455	}
1456	else
1457	{
1458	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1459	}
1460	break;
1461	}
1462
1463	//////////////////////////
1464	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1465	// stored in the r_dcache_save_wdata register
1466	{
1467	r_itlb.inval(r_dcache_save_wdata.read());
1468	r_dcache_xtn_req = false;
1469	r_icache_fsm = ICACHE_IDLE;
1470	break;
1471	}
1472	///////////////////////////////
1473	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1474	// requires 3 cycles (in case of hit on itlb and icache).
1475	// In this state, access TLB to translate virtual address
1476	// stored in the r_dcache_save_wdata register.
1477	{
1478	paddr_t paddr;
1479	bool hit;
1480
1481	// read physical address in TLB when MMU activated
1482	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1483	{
1484
1485	#ifdef INSTRUMENTATION
1486	m_cpt_itlb_read++;
1487	#endif
1488	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1489	}
1490	else // itlb not activated
1491	{
1492	paddr = (paddr_t) r_dcache_save_wdata.read();
1493	hit = true;
1494	}
1495
1496	if (hit) // continue the selective inval process
1497	{
1498	r_icache_vci_paddr = paddr;
1499	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1500	}
1501	else // miss : send a request to DCACHE FSM
1502	{
1503
1504	#ifdef INSTRUMENTATION
1505	m_cpt_itlb_miss++;
1506	#endif
1507	r_icache_tlb_miss_req = true;
1508	r_icache_vaddr_save = r_dcache_save_wdata.read();
1509	r_icache_fsm = ICACHE_TLB_WAIT;
1510	}
1511	break;
1512	}
1513	///////////////////////////////
1514	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1515	// require 2 cycles. In this state, we read directory
1516	// with address stored in r_icache_vci_paddr register.
1517	{
1518	int state;
1519	size_t way;
1520	size_t set;
1521	size_t word;
1522
1523	#ifdef INSTRUMENTATION
1524	m_cpt_icache_dir_read++;
1525	#endif
1526	r_icache.read_dir(r_icache_vci_paddr.read(),
1527	&state,
1528	&way,
1529	&set,
1530	&word);
1531
1532	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1533	{
1534	r_icache_miss_way = way;
1535	r_icache_miss_set = set;
1536	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1537	}
1538	else // miss : acknowlege the XTN request and return
1539	{
1540	r_dcache_xtn_req = false;
1541	r_icache_fsm = ICACHE_IDLE;
1542	}
1543	break;
1544	}
1545	///////////////////////////////
1546	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1547	{
1548	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1549	{
1550
1551	#ifdef INSTRUMENTATION
1552	m_cpt_icache_dir_write++;
1553	#endif
1554	r_icache.write_dir(r_icache_miss_way.read(),
1555	r_icache_miss_set.read(),
1556	CACHE_SLOT_STATE_ZOMBI);
1557
1558	// request cleanup
1559	r_icache_cc_send_req = true;
1560	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1561	r_icache_cc_send_way = r_icache_miss_way.read();
1562	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1563
1564	// acknowledge the XTN request and return
1565	r_dcache_xtn_req = false;
1566	r_icache_fsm = ICACHE_IDLE;
1567	}
1568	break;
1569	}
1570	////////////////////////
1571	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1572	// Waiting in this state if no slot available.
1573	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1574	// we send the cleanup request in this state.
1575	// If not, a r_icache_cleanup_victim_req flip-flop is
1576	// utilized for saving this cleanup request, and it will be sent later
1577	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1578	// The r_icache_miss_clack flip-flop is set
1579	// when a cleanup is required
1580	{
1581	if (m_ireq.valid) m_cost_ins_miss_frz++;
1582
1583	// coherence clack interrupt
1584	if (r_icache_clack_req.read())
1585	{
1586	r_icache_fsm = ICACHE_CC_CHECK;
1587	r_icache_fsm_save = r_icache_fsm.read();
1588	break;
1589	}
1590
1591	// coherence interrupt
1592	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1593	{
1594	r_icache_fsm = ICACHE_CC_CHECK;
1595	r_icache_fsm_save = r_icache_fsm.read();
1596	break;
1597	}
1598
1599
1600	bool found;
1601	bool cleanup;
1602	size_t way;
1603	size_t set;
1604	paddr_t victim;
1605
1606	#ifdef INSTRUMENTATION
1607	m_cpt_icache_dir_read++;
1608	#endif
1609	r_icache.read_select(r_icache_vci_paddr.read(),
1610	&victim,
1611	&way,
1612	&set,
1613	&found,
1614	&cleanup);
1615	if (not found)
1616	{
1617	break;
1618	}
1619	else
1620	{
1621	r_icache_miss_way = way;
1622	r_icache_miss_set = set;
1623
1624	if (cleanup)
1625	{
1626	if (not r_icache_cc_send_req.read())
1627	{
1628	r_icache_cc_send_req = true;
1629	r_icache_cc_send_nline = victim;
1630	r_icache_cc_send_way = way;
1631	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1632	}
1633	else
1634	{
1635	r_icache_cleanup_victim_req = true;
1636	r_icache_cleanup_victim_nline = victim;
1637	}
1638
1639	r_icache_miss_clack = true;
1640	r_icache_fsm = ICACHE_MISS_CLEAN;
1641	}
1642	else
1643	{
1644	r_icache_fsm = ICACHE_MISS_WAIT;
1645	}
1646
1647	#if DEBUG_ICACHE
1648	if (m_debug_icache_fsm)
1649	{
1650	std::cout << " <PROC " << name()
1651	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1652	<< " / WAY = " << way
1653	<< " / SET = " << set;
1654	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1655	else std::cout << std::endl;
1656	}
1657	#endif
1658	}
1659	break;
1660	}
1661	///////////////////////
1662	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1663	{
1664	if (m_ireq.valid) m_cost_ins_miss_frz++;
1665
1666	#ifdef INSTRUMENTATION
1667	m_cpt_icache_dir_write++;
1668	#endif
1669	r_icache.write_dir(r_icache_miss_way.read(),
1670	r_icache_miss_set.read(),
1671	CACHE_SLOT_STATE_ZOMBI);
1672	#if DEBUG_ICACHE
1673	if (m_debug_icache_fsm)
1674	{
1675	std::cout << " <PROC " << name()
1676	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1677	<< " / WAY = " << r_icache_miss_way.read()
1678	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1679	}
1680	#endif
1681
1682	r_icache_fsm = ICACHE_MISS_WAIT;
1683	break;
1684	}
1685	//////////////////////
1686	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1687	{
1688	if (m_ireq.valid) m_cost_ins_miss_frz++;
1689
1690	// send cleanup victim request
1691	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1692	{
1693	r_icache_cc_send_req = true;
1694	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1695	r_icache_cc_send_way = r_icache_miss_way;
1696	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1697	r_icache_cleanup_victim_req = false;
1698	}
1699
1700	// coherence clack interrupt
1701	if (r_icache_clack_req.read())
1702	{
1703	r_icache_fsm = ICACHE_CC_CHECK;
1704	r_icache_fsm_save = r_icache_fsm.read();
1705	break;
1706	}
1707
1708	// coherence interrupt
1709	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1710	{
1711	r_icache_fsm = ICACHE_CC_CHECK;
1712	r_icache_fsm_save = r_icache_fsm.read();
1713	break;
1714	}
1715
1716	if (r_vci_rsp_ins_error.read()) // bus error
1717	{
1718	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1719	r_mmu_ibvar = r_icache_vaddr_save.read();
1720	m_irsp.valid = true;
1721	m_irsp.error = true;
1722	r_vci_rsp_ins_error = false;
1723	r_icache_fsm = ICACHE_IDLE;
1724	}
1725	else if (r_vci_rsp_fifo_icache.rok()) // response available
1726	{
1727	r_icache_miss_word = 0;
1728	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1729	}
1730	break;
1731	}
1732	///////////////////////////
1733	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1734	{
1735	if (m_ireq.valid) m_cost_ins_miss_frz++;
1736
1737	if (r_vci_rsp_fifo_icache.rok()) // response available
1738	{
1739
1740	#ifdef INSTRUMENTATION
1741	m_cpt_icache_data_write++;
1742	#endif
1743	r_icache.write(r_icache_miss_way.read(),
1744	r_icache_miss_set.read(),
1745	r_icache_miss_word.read(),
1746	r_vci_rsp_fifo_icache.read());
1747	#if DEBUG_ICACHE
1748	if (m_debug_icache_fsm)
1749	{
1750	std::cout << " <PROC " << name()
1751	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1752	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1753	<< " WAY = " << r_icache_miss_way.read()
1754	<< " SET = " << r_icache_miss_set.read()
1755	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1756	}
1757	#endif
1758	vci_rsp_fifo_icache_get = true;
1759	r_icache_miss_word = r_icache_miss_word.read() + 1;
1760
1761	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1762	{
1763	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1764	}
1765	}
1766	break;
1767	}
1768	//////////////////////////
1769	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1770	// and the cleanup ack has not been received,
1771	// as indicated by r_icache_miss_clack.
1772	// - If no matching coherence request (r_icache_miss_inval)
1773	// switch directory slot to VALID state.
1774	// - If matching coherence request, switch directory slot
1775	// to ZOMBI state, and send a cleanup request.
1776	{
1777	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1778
1779	// send cleanup victim request
1780	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1781	{
1782	r_icache_cc_send_req = true;
1783	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1784	r_icache_cc_send_way = r_icache_miss_way;
1785	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1786	r_icache_cleanup_victim_req = false;
1787	}
1788
1789	// coherence clack interrupt
1790	if (r_icache_clack_req.read())
1791	{
1792	r_icache_fsm = ICACHE_CC_CHECK;
1793	r_icache_fsm_save = r_icache_fsm.read();
1794	break;
1795	}
1796
1797	// coherence interrupt
1798	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1799	{
1800	r_icache_fsm = ICACHE_CC_CHECK;
1801	r_icache_fsm_save = r_icache_fsm.read();
1802	break;
1803	}
1804
1805	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1806	{
1807	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1808	{
1809	if (not r_icache_cc_send_req.read())
1810	{
1811	r_icache_miss_inval = false;
1812	// request cleanup
1813	r_icache_cc_send_req = true;
1814	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1815	r_icache_cc_send_way = r_icache_miss_way.read();
1816	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1817
1818	#ifdef INSTRUMENTATION
1819	m_cpt_icache_dir_write++;
1820	#endif
1821	r_icache.write_dir(r_icache_vci_paddr.read(),
1822	r_icache_miss_way.read(),
1823	r_icache_miss_set.read(),
1824	CACHE_SLOT_STATE_ZOMBI);
1825	#if DEBUG_ICACHE
1826	if (m_debug_icache_fsm)
1827	{
1828	std::cout << " <PROC " << name()
1829	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1830	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1831	<< " WAY = " << std::dec << r_icache_miss_way.read()
1832	<< " SET = " << r_icache_miss_set.read() << std::endl;
1833	}
1834	#endif
1835	}
1836	else
1837	break;
1838	}
1839	else // Switch slot to VALID state
1840	{
1841
1842	#ifdef INSTRUMENTATION
1843	m_cpt_icache_dir_write++;
1844	#endif
1845	r_icache.write_dir(r_icache_vci_paddr.read(),
1846	r_icache_miss_way.read(),
1847	r_icache_miss_set.read(),
1848	CACHE_SLOT_STATE_VALID);
1849	#if DEBUG_ICACHE
1850	if (m_debug_icache_fsm)
1851	{
1852	std::cout << " <PROC " << name()
1853	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1854	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1855	<< " WAY = " << std::dec << r_icache_miss_way.read()
1856	<< " SET = " << r_icache_miss_set.read() << std::endl;
1857	}
1858	#endif
1859	}
1860
1861	r_icache_fsm = ICACHE_IDLE;
1862	}
1863	break;
1864	}
1865	////////////////////
1866	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1867	{
1868	// coherence clack interrupt
1869	if (r_icache_clack_req.read())
1870	{
1871	r_icache_fsm = ICACHE_CC_CHECK;
1872	r_icache_fsm_save = r_icache_fsm.read();
1873	break;
1874	}
1875
1876	// coherence interrupt
1877	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1878	{
1879	r_icache_fsm = ICACHE_CC_CHECK;
1880	r_icache_fsm_save = r_icache_fsm.read();
1881	break;
1882	}
1883
1884	if (r_vci_rsp_ins_error.read()) // bus error
1885	{
1886	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1887	r_mmu_ibvar = m_ireq.addr;
1888	r_vci_rsp_ins_error = false;
1889	m_irsp.valid = true;
1890	m_irsp.error = true;
1891	r_icache_fsm = ICACHE_IDLE;
1892	}
1893	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1894	{
1895	vci_rsp_fifo_icache_get = true;
1896	r_icache_fsm = ICACHE_IDLE;
1897	if (m_ireq.valid and
1898	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1899	{
1900	m_irsp.valid = true;
1901	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1902	}
1903	}
1904	break;
1905	}
1906	/////////////////////
1907	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1908	// handling coherence requests.
1909	// if there is a matching pending miss, it is
1910	// signaled in the r_icache_miss_inval flip-flop.
1911	// The return state is defined in r_icache_fsm_save.
1912	{
1913	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1914	paddr_t mask = ~((m_icache_words << 2) - 1);
1915
1916	// CLACK handler
1917	// We switch the directory slot to EMPTY state
1918	// and reset r_icache_miss_clack if the cleanup ack
1919	// is matching a pending miss.
1920	if (r_icache_clack_req.read())
1921	{
1922
1923	if (m_ireq.valid) m_cost_ins_miss_frz++;
1924
1925	#ifdef INSTRUMENTATION
1926	m_cpt_icache_dir_write++;
1927	#endif
1928	r_icache.write_dir(0,
1929	r_icache_clack_way.read(),
1930	r_icache_clack_set.read(),
1931	CACHE_SLOT_STATE_EMPTY);
1932
1933	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1934	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1935	{
1936	r_icache_miss_clack = false;
1937	}
1938
1939	r_icache_clack_req = false;
1940
1941	// return to cc_save state
1942	r_icache_fsm = r_icache_fsm_save.read();
1943
1944	#if DEBUG_ICACHE
1945	if (m_debug_icache_fsm)
1946	{
1947	std::cout << " <PROC " << name()
1948	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1949	<< " set = " << r_icache_clack_set.read()
1950	<< " / way = " << r_icache_clack_way.read() << std::endl;
1951	}
1952	#endif
1953
1954	break;
1955	}
1956
1957	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1958
1959	// Match between MISS address and CC address
1960	if (r_cc_receive_icache_req.read() and
1961	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1962	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1963	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1964	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1965	{
1966	// signaling the matching
1967	r_icache_miss_inval = true;
1968
1969	// in case of update, go to CC_UPDT
1970	// JUST TO POP THE FIFO
1971	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1972	{
1973	r_icache_fsm = ICACHE_CC_UPDT;
1974	r_icache_cc_word = r_cc_receive_word_idx.read();
1975
1976	// just pop the fifo , don't write in icache
1977	r_icache_cc_need_write = false;
1978	}
1979	// the request is dealt with
1980	else
1981	{
1982	r_cc_receive_icache_req = false;
1983	r_icache_fsm = r_icache_fsm_save.read();
1984	}
1985	#if DEBUG_ICACHE
1986	if (m_debug_icache_fsm)
1987	{
1988	std::cout << " <PROC " << name()
1989	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1990	<< " PADDR = " << std::hex << paddr << std::endl;
1991	}
1992	#endif
1993	}
1994
1995	// CC request handler
1996
1997	int state = 0;
1998	size_t way = 0;
1999	size_t set = 0;
2000	size_t word = 0;
2001
2002	#ifdef INSTRUMENTATION
2003	m_cpt_icache_dir_read++;
2004	#endif
2005	r_icache.read_dir(paddr,
2006	&state,
2007	&way,
2008	&set,
2009	&word);
2010
2011	r_icache_cc_way = way;
2012	r_icache_cc_set = set;
2013
2014	if (state == CACHE_SLOT_STATE_VALID) // hit
2015	{
2016	// need to update the cache state
2017	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2018	{
2019	r_icache_cc_need_write = true;
2020	r_icache_fsm = ICACHE_CC_UPDT;
2021	r_icache_cc_word = r_cc_receive_word_idx.read();
2022	}
2023	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2024	{
2025	r_icache_fsm = ICACHE_CC_INVAL;
2026	}
2027	}
2028	else // miss
2029	{
2030	// multicast acknowledgement required in case of update
2031	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2032	{
2033	r_icache_fsm = ICACHE_CC_UPDT;
2034	r_icache_cc_word = r_cc_receive_word_idx.read();
2035
2036	// just pop the fifo , don't write in icache
2037	r_icache_cc_need_write = false;
2038	}
2039	else // No response needed
2040	{
2041	r_cc_receive_icache_req = false;
2042	r_icache_fsm = r_icache_fsm_save.read();
2043	}
2044	}
2045	break;
2046	}
2047	/////////////////////
2048	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2049	{
2050	assert (not r_icache_cc_send_req.read() &&
2051	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2052	"must not be set");
2053
2054	#ifdef INSTRUMENTATION
2055	m_cpt_icache_dir_read++;
2056	#endif
2057
2058	// Switch slot state to ZOMBI and send CLEANUP command
2059	r_icache.write_dir(r_icache_cc_way.read(),
2060	r_icache_cc_set.read(),
2061	CACHE_SLOT_STATE_ZOMBI);
2062
2063	// coherence request completed
2064	r_icache_cc_send_req = true;
2065	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2066	r_icache_cc_send_way = r_icache_cc_way.read();
2067	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2068
2069	r_icache_fsm = r_icache_fsm_save.read();
2070
2071	#if DEBUG_ICACHE
2072	if (m_debug_icache_fsm)
2073	{
2074	std::cout << " <PROC " << name()
2075	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2076	<< " set = " << r_icache_cc_set.read()
2077	<< " / way = " << r_icache_cc_way.read() << std::endl;
2078	}
2079	#endif
2080
2081	break;
2082	}
2083	////////////////////
2084	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2085	{
2086	assert (not r_icache_cc_send_req.read() &&
2087	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2088	"must not be set");
2089
2090	if (not r_cc_receive_updt_fifo_be.rok()) break;
2091
2092
2093	size_t word = r_icache_cc_word.read();
2094	size_t way = r_icache_cc_way.read();
2095	size_t set = r_icache_cc_set.read();
2096
2097	if (r_icache_cc_need_write.read())
2098	{
2099	r_icache.write(way,
2100	set,
2101	word,
2102	r_cc_receive_updt_fifo_data.read(),
2103	r_cc_receive_updt_fifo_be.read());
2104
2105	r_icache_cc_word = word + 1;
2106
2107	#ifdef INSTRUMENTATION
2108	m_cpt_icache_data_write++;
2109	#endif
2110
2111	#if DEBUG_ICACHE
2112	if (m_debug_icache_fsm)
2113	{
2114	std::cout << " <PROC " << name()
2115	<< " ICACHE_CC_UPDT> Write one word "
2116	<< " set = " << r_icache_cc_set.read()
2117	<< " / way = " << r_icache_cc_way.read()
2118	<< " / word = " << r_icache_cc_word.read() << std::endl;
2119	}
2120	#endif
2121	}
2122
2123	if (r_cc_receive_updt_fifo_eop.read()) // last word
2124	{
2125	// no need to write in the cache anymore
2126	r_icache_cc_need_write = false;
2127
2128	// coherence request completed
2129	r_cc_receive_icache_req = false;
2130
2131	// request multicast acknowledgement
2132	r_icache_cc_send_req = true;
2133	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2134	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2135	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2136
2137	r_icache_fsm = r_icache_fsm_save.read();
2138	}
2139	//consume fifo if not eop
2140	cc_receive_updt_fifo_get = true;
2141
2142	break;
2143	}
2144
2145	} // end switch r_icache_fsm
2146
2147	////////////////////////////////////////////////////////////////////////////////////
2148	// DCACHE FSM
2149	//
2150	// 1/ Coherence operations
2151	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2152	// - There is a coherence request when r_tgt_dcache_req is set.
2153	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2154	// and SC_WAIT states.
2155	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2156	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2157	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2158	// - For both types of requests, actions associated to the pre-empted state
2159	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2160	// or CC_CLACK) to execute the requested coherence operation, and returns
2161	// to the pre-empted state.
2162	//
2163	// 2/ TLB miss
2164	// The page tables are generally cacheable.
2165	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2166	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2167	// this sub-fsm implement the table-walk...
2168	//
2169	// 3/ processor requests
2170	// Processor requests are taken in IDLE state only.
2171	// The IDLE state implements a two stages pipe-line to handle write bursts:
2172	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2173	// - The registration in wbuf and the dcache update is done in stage P1
2174	// (if the processor request is a write).
2175	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2176	// the operations that must be done in P1 stage, and the access type
2177	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2178	// READ requests are delayed if a cache update is requested.
2179	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2180	// that is done (before handling the processor request) by a dedicated sub-fsm.
2181	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2182	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2183	//
2184	// 4/ Atomic instructions LL/SC
2185	// The LL/SC address are non cacheable (systematic access to memory).
2186	// The llsc buffer contains a registration for an active LL/SC operation
2187	// (with an address, a registration key, an aging counter and a valid bit).
2188	// - LL requests from the processor are transmitted as a one flit VCI command
2189	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2190	// be 8 as the response is 2 flits long (data and registration key)
2191	// - SC requests from the processor are systematically transmitted to the
2192	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2193	// as PKTID value). The first flit contains the registration key, the second
2194	// flit contains the data to write in case of success.
2195	// The cache is not updated, as this is done in case of success by the
2196	// coherence transaction.
2197	//
2198	// 5/ Non cacheable access:
2199	// This component implement a strong order between non cacheable access
2200	// (read or write) : A new non cacheable VCI transaction starts only when
2201	// the previous non cacheable transaction is completed. After send the VCI
2202	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2203	// So the processor is blocked until the respone arrives in CACHE L1.
2204	//
2205	// 6/ Error handling:
2206	// When the MMU is not activated, Read Bus Errors are synchronous events,
2207	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2208	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2209	// (processor is not frozen).
2210	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2211	// r_vci_rsp_data_error flip-flop, without writing any data in the
2212	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2213	// by the DCACHE FSM.
2214	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2215	// the asynchronous error using the setWriteBerr() method.
2216	// When the MMU is activated bus error are rare events, as the MMU
2217	// checks the physical address before the VCI transaction starts.
2218	////////////////////////////////////////////////////////////////////////////////////////
2219
2220	// default value for m_drsp
2221	m_drsp.valid = false;
2222	m_drsp.error = false;
2223	m_drsp.rdata = 0;
2224
2225	switch (r_dcache_fsm.read())
2226	{
2227	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2228	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2229	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2230	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2231	// 4) XTN request (processor) => DCACHE_XTN_*
2232	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2233	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2234	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2235	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2236	// 9) LL access (processor) => DCACHE_LL_WAIT
2237	// 10) SC access (processor) => DCACHE_SC_WAIT
2238	//
2239	// There is a fixed priority to handle requests to DCACHE:
2240	// 1/ the ITLB/DTLB invalidate requests
2241	// 2/ the coherence requests,
2242	// 3/ the processor requests (including DTLB miss),
2243	// 4/ the ITLB miss requests,
2244	// The address space processor request are handled as follows:
2245	// - WRITE request is blocked if the Dirty bit mus be set.
2246	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2247	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2248	// - READ request generate a simultaneouss access to DCACHE.DATA
2249	// and DCACHE.DIR, but is delayed if DCACHE update required.
2250	//
2251	// There is 4 configurations defining the access type to
2252	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2253	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2254	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2255	// 0 / 0 / NOP / NOP / NOP /
2256	// 0 / 1 / NOP / NOP / WRITE /
2257	// 1 / 0 / READ / READ / NOP /
2258	// 1 / 1 / READ / READ / WRITE /
2259	// Those two registers are set at each cycle from the 3 signals
2260	// updt_request, wbuf_request, wbuf_write_miss.
2261	{
2262	paddr_t paddr;
2263	pte_info_t tlb_flags;
2264	size_t tlb_way;
2265	size_t tlb_set;
2266	paddr_t tlb_nline = 0;
2267	size_t cache_way;
2268	size_t cache_set;
2269	size_t cache_word;
2270	uint32_t cache_rdata = 0;
2271	bool tlb_hit = false;
2272	int cache_state = CACHE_SLOT_STATE_EMPTY;
2273
2274	bool tlb_inval_required = false; // request TLB inval after cache update
2275	bool wbuf_write_miss = false; // miss a WBUF write request
2276	bool updt_request = false; // request DCACHE update in P1 stage
2277	bool wbuf_request = false; // request WBUF write in P1 stage
2278
2279	// physical address computation : systematic DTLB access if activated
2280	paddr = (paddr_t) m_dreq.addr;
2281	if (m_dreq.valid)
2282	{
2283	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2284	{
2285	tlb_hit = r_dtlb.translate(m_dreq.addr,
2286	&paddr,
2287	&tlb_flags,
2288	&tlb_nline,
2289	&tlb_way,
2290	&tlb_set);
2291	#ifdef INSTRUMENTATION
2292	m_cpt_dtlb_read++;
2293	#endif
2294	}
2295	else // identity mapping
2296	{
2297	// we take into account the paddr extension
2298	if (vci_param::N > 32)
2299	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2300	}
2301	} // end physical address computation
2302
2303	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2304	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2305	{
2306
2307	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2308	{
2309	r_dcache.read_dir(paddr,
2310	&cache_state,
2311	&cache_way,
2312	&cache_set,
2313	&cache_word);
2314
2315	r_dcache.write(r_dcache_save_cache_way.read(),
2316	r_dcache_save_cache_set.read(),
2317	r_dcache_save_cache_word.read(),
2318	r_dcache_save_wdata.read(),
2319	r_dcache_save_be.read());
2320	#ifdef INSTRUMENTATION
2321	m_cpt_dcache_dir_read++;
2322	m_cpt_dcache_data_write++;
2323	#endif
2324	}
2325	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2326	{
2327	r_dcache.read(paddr,
2328	&cache_rdata,
2329	&cache_way,
2330	&cache_set,
2331	&cache_word,
2332	&cache_state);
2333
2334	#ifdef INSTRUMENTATION
2335	m_cpt_dcache_dir_read++;
2336	m_cpt_dcache_data_read++;
2337	#endif
2338	}
2339	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2340	{
2341	r_dcache.write(r_dcache_save_cache_way.read(),
2342	r_dcache_save_cache_set.read(),
2343	r_dcache_save_cache_word.read(),
2344	r_dcache_save_wdata.read(),
2345	r_dcache_save_be.read());
2346	#ifdef INSTRUMENTATION
2347	m_cpt_dcache_data_write++;
2348	#endif
2349	}
2350	} // end dcache access
2351
2352	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2353	if (r_dcache_updt_req.read())
2354	{
2355	size_t way = r_dcache_save_cache_way.read();
2356	size_t set = r_dcache_save_cache_set.read();
2357
2358	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2359	{
2360	tlb_inval_required = true;
2361	r_dcache_tlb_inval_set = 0;
2362	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2363	(uint32_log2(m_dcache_words << 2));
2364	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2365	}
2366	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2367	{
2368	r_itlb.reset();
2369	r_dtlb.reset();
2370	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2371	}
2372
2373	#if DEBUG_DCACHE
2374	if (m_debug_dcache_fsm)
2375	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2376	<< " Cache update in P1 stage" << std::dec
2377	<< " / WAY = " << r_dcache_save_cache_way.read()
2378	<< " / SET = " << r_dcache_save_cache_set.read()
2379	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2380	<< " / WDATA = " << r_dcache_save_wdata.read()
2381	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2382	#endif
2383	} // end test TLB inval
2384
2385	// Try WBUF update in P1 stage
2386	// Miss if the write request is non cacheable, and there is a pending
2387	// non cacheable write, or if the write buffer is full.
2388	if (r_dcache_wbuf_req.read())
2389	{
2390	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2391	r_dcache_save_be.read(),
2392	r_dcache_save_wdata.read(),
2393	true);
2394	#ifdef INSTRUMENTATION
2395	m_cpt_wbuf_write++;
2396	#endif
2397	if (not wok ) // miss if write buffer full
2398	{
2399	wbuf_write_miss = true;
2400	}
2401	} // end WBUF update
2402
2403	// Computing the response to processor,
2404	// and the next value for r_dcache_fsm
2405
2406	// itlb/dtlb invalidation self-request
2407	if (tlb_inval_required)
2408	{
2409	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2410	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2411	}
2412
2413	// coherence clack request (from DSPIN CLACK)
2414	else if (r_dcache_clack_req.read())
2415	{
2416	r_dcache_fsm = DCACHE_CC_CHECK;
2417	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2418	}
2419	// coherence request (from CC_RECEIVE FSM)
2420	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2421	{
2422	r_dcache_fsm = DCACHE_CC_CHECK;
2423	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2424	}
2425
2426	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2427	// we don't take the processor request, and registers
2428	// are frozen in case of wbuf_write_miss
2429	else if (m_dreq.valid and not wbuf_write_miss)
2430	{
2431	// register processor request and DCACHE response
2432	r_dcache_save_vaddr = m_dreq.addr;
2433	r_dcache_save_be = m_dreq.be;
2434	r_dcache_save_wdata = m_dreq.wdata;
2435	r_dcache_save_paddr = paddr;
2436	r_dcache_save_cache_way = cache_way;
2437	r_dcache_save_cache_set = cache_set;
2438	r_dcache_save_cache_word = cache_word;
2439
2440	// READ XTN requests from processor
2441	// They are executed in this DCACHE_IDLE state.
2442	// The processor must not be in user mode
2443	if (m_dreq.type == iss_t::XTN_READ)
2444	{
2445	int xtn_opcode = (int) m_dreq.addr / 4;
2446
2447	// checking processor mode:
2448	if (m_dreq.mode == iss_t::MODE_USER)
2449	{
2450	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2451	r_mmu_dbvar = m_dreq.addr;
2452	m_drsp.valid = true;
2453	m_drsp.error = true;
2454	m_drsp.rdata = 0;
2455	r_dcache_fsm = DCACHE_IDLE;
2456	}
2457	else
2458	{
2459	switch (xtn_opcode)
2460	{
2461	case iss_t::XTN_INS_ERROR_TYPE:
2462	m_drsp.rdata = r_mmu_ietr.read();
2463	m_drsp.valid = true;
2464	m_drsp.error = false;
2465	break;
2466
2467	case iss_t::XTN_DATA_ERROR_TYPE:
2468	m_drsp.rdata = r_mmu_detr.read();
2469	m_drsp.valid = true;
2470	m_drsp.error = false;
2471	break;
2472
2473	case iss_t::XTN_INS_BAD_VADDR:
2474	m_drsp.rdata = r_mmu_ibvar.read();
2475	m_drsp.valid = true;
2476	m_drsp.error = false;
2477	break;
2478
2479	case iss_t::XTN_DATA_BAD_VADDR:
2480	m_drsp.rdata = r_mmu_dbvar.read();
2481	m_drsp.valid = true;
2482	m_drsp.error = false;
2483	break;
2484
2485	case iss_t::XTN_PTPR:
2486	m_drsp.rdata = r_mmu_ptpr.read();
2487	m_drsp.valid = true;
2488	m_drsp.error = false;
2489	break;
2490
2491	case iss_t::XTN_TLB_MODE:
2492	m_drsp.rdata = r_mmu_mode.read();
2493	m_drsp.valid = true;
2494	m_drsp.error = false;
2495	break;
2496
2497	case iss_t::XTN_MMU_PARAMS:
2498	m_drsp.rdata = r_mmu_params;
2499	m_drsp.valid = true;
2500	m_drsp.error = false;
2501	break;
2502
2503	case iss_t::XTN_MMU_RELEASE:
2504	m_drsp.rdata = r_mmu_release;
2505	m_drsp.valid = true;
2506	m_drsp.error = false;
2507	break;
2508
2509	case iss_t::XTN_MMU_WORD_LO:
2510	m_drsp.rdata = r_mmu_word_lo.read();
2511	m_drsp.valid = true;
2512	m_drsp.error = false;
2513	break;
2514
2515	case iss_t::XTN_MMU_WORD_HI:
2516	m_drsp.rdata = r_mmu_word_hi.read();
2517	m_drsp.valid = true;
2518	m_drsp.error = false;
2519	break;
2520
2521	case iss_t::XTN_DATA_PADDR_EXT:
2522	m_drsp.rdata = r_dcache_paddr_ext.read();
2523	m_drsp.valid = true;
2524	m_drsp.error = false;
2525	break;
2526
2527	case iss_t::XTN_INST_PADDR_EXT:
2528	m_drsp.rdata = r_icache_paddr_ext.read();
2529	m_drsp.valid = true;
2530	m_drsp.error = false;
2531	break;
2532
2533	default:
2534	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2535	r_mmu_dbvar = m_dreq.addr;
2536	m_drsp.valid = true;
2537	m_drsp.error = true;
2538	m_drsp.rdata = 0;
2539	break;
2540	} // end switch xtn_opcode
2541	} // end else
2542	} // end if XTN_READ
2543
2544	// Handling WRITE XTN requests from processor.
2545	// They are not executed in this DCACHE_IDLE state
2546	// if they require access to the caches or the TLBs
2547	// that are already accessed.
2548	// Caches can be invalidated or flushed in user mode,
2549	// and the sync instruction can be executed in user mode
2550	else if (m_dreq.type == iss_t::XTN_WRITE)
2551	{
2552	int xtn_opcode = (int)m_dreq.addr / 4;
2553	r_dcache_xtn_opcode = xtn_opcode;
2554
2555	// checking processor mode:
2556	if ((m_dreq.mode == iss_t::MODE_USER) &&
2557	(xtn_opcode != iss_t::XTN_SYNC) &&
2558	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2559	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2560	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2561	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2562	{
2563	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2564	r_mmu_dbvar = m_dreq.addr;
2565	m_drsp.valid = true;
2566	m_drsp.error = true;
2567	m_drsp.rdata = 0;
2568	r_dcache_fsm = DCACHE_IDLE;
2569	}
2570	else
2571	{
2572	switch (xtn_opcode)
2573	{
2574	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2575	r_dcache_xtn_req = true;
2576	r_dcache_fsm = DCACHE_XTN_SWITCH;
2577	break;
2578
2579	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2580	r_mmu_mode = m_dreq.wdata;
2581	m_drsp.valid = true;
2582	r_dcache_fsm = DCACHE_IDLE;
2583	break;
2584
2585	case iss_t::XTN_DTLB_INVAL: // dtlb access
2586	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2587	break;
2588
2589	case iss_t::XTN_ITLB_INVAL: // itlb access
2590	r_dcache_xtn_req = true;
2591	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2592	break;
2593
2594	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2595	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2596	break;
2597
2598	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2599	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2600	if (sizeof(paddr_t) <= 32)
2601	{
2602	assert(r_mmu_word_hi.read() == 0 &&
2603	"high bits should be 0 for 32bit paddr");
2604	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2605	}
2606	else
2607	{
2608	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2609	(paddr_t)r_mmu_word_lo.read();
2610	}
2611	break;
2612
2613	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2614	r_dcache_flush_count = 0;
2615	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2616	break;
2617
2618	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2619	r_dcache_xtn_req = true;
2620	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2621	break;
2622
2623	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2624	r_dcache_xtn_req = true;
2625	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2626	break;
2627
2628	case iss_t::XTN_ICACHE_FLUSH: // icache access
2629	r_dcache_xtn_req = true;
2630	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2631	break;
2632
2633	case iss_t::XTN_SYNC: // wait until write buffer empty
2634	r_dcache_fsm = DCACHE_XTN_SYNC;
2635	break;
2636
2637	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2638	r_mmu_word_lo = m_dreq.wdata;
2639	m_drsp.valid = true;
2640	r_dcache_fsm = DCACHE_IDLE;
2641	break;
2642
2643	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2644	r_mmu_word_hi = m_dreq.wdata;
2645	m_drsp.valid = true;
2646	r_dcache_fsm = DCACHE_IDLE;
2647	break;
2648
2649	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2650	r_dcache_llsc_valid = false;
2651	m_drsp.valid = true;
2652	r_dcache_fsm = DCACHE_IDLE;
2653	break;
2654
2655	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2656	r_dcache_paddr_ext = m_dreq.wdata;
2657	m_drsp.valid = true;
2658	r_dcache_fsm = DCACHE_IDLE;
2659	break;
2660
2661	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2662	r_dcache_xtn_req = true;
2663	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2664	break;
2665
2666	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2667	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2668	m_drsp.valid = true;
2669	r_dcache_fsm = DCACHE_IDLE;
2670	break;
2671
2672	case iss_t::XTN_DEBUG_MASK: // debug mask
2673	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2674	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2675	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2676	m_drsp.valid = true;
2677	r_dcache_fsm = DCACHE_IDLE;
2678	break;
2679
2680	default:
2681	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2682	r_mmu_dbvar = m_dreq.addr;
2683	m_drsp.valid = true;
2684	m_drsp.error = true;
2685	r_dcache_fsm = DCACHE_IDLE;
2686	break;
2687	} // end switch xtn_opcode
2688	} // end else
2689	} // end if XTN_WRITE
2690
2691	// Handling processor requests to address space (READ/WRITE/LL/SC)
2692	// The dtlb and dcache can be activated or not.
2693	// We compute the cacheability, and check processor request validity:
2694	// - If DTLB not activated : cacheability is defined by the segment table,
2695	// and there is no access rights checking.
2696	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2697	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2698	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2699	else
2700	{
2701	bool valid_req;
2702	bool cacheable;
2703
2704	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2705	{
2706	valid_req = true;
2707
2708	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2709	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2710	}
2711	else // dtlb activated
2712	{
2713	if (tlb_hit) // tlb hit
2714	{
2715	// cacheability
2716	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2717	else cacheable = tlb_flags.c;
2718
2719	// access rights checking
2720	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2721	{
2722	if ((m_dreq.type == iss_t::DATA_READ) or
2723	(m_dreq.type == iss_t::DATA_LL))
2724	{
2725	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2726	}
2727	else
2728	{
2729	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2730	}
2731	valid_req = false;
2732	r_mmu_dbvar = m_dreq.addr;
2733	m_drsp.valid = true;
2734	m_drsp.error = true;
2735	m_drsp.rdata = 0;
2736	#if DEBUG_DCACHE
2737	if (m_debug_dcache_fsm)
2738	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2739	<< " HIT in dtlb, but privilege violation" << std::endl;
2740	#endif
2741	}
2742	else if (not tlb_flags.w and
2743	((m_dreq.type == iss_t::DATA_WRITE) or
2744	(m_dreq.type == iss_t::DATA_SC)))
2745	{
2746	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2747	valid_req = false;
2748	r_mmu_dbvar = m_dreq.addr;
2749	m_drsp.valid = true;
2750	m_drsp.error = true;
2751	m_drsp.rdata = 0;
2752	#if DEBUG_DCACHE
2753	if (m_debug_dcache_fsm)
2754	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2755	<< " HIT in dtlb, but writable violation" << std::endl;
2756	#endif
2757	}
2758	else
2759	{
2760	valid_req = true;
2761	}
2762	}
2763	else // tlb miss
2764	{
2765	valid_req = false;
2766	r_dcache_tlb_vaddr = m_dreq.addr;
2767	r_dcache_tlb_ins = false;
2768	r_dcache_fsm = DCACHE_TLB_MISS;
2769	}
2770	} // end DTLB activated
2771
2772	if (valid_req) // processor request is valid (after MMU check)
2773	{
2774	// READ request
2775	// The read requests are taken only if there is no cache update.
2776	// We request a VCI transaction to CMD FSM if miss or uncachable
2777
2778	if (((m_dreq.type == iss_t::DATA_READ))
2779	and not r_dcache_updt_req.read())
2780	{
2781	if (cacheable) // cacheable read
2782	{
2783	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2784	{
2785	#ifdef INSTRUMENTATION
2786	m_cpt_dcache_miss++;
2787	#endif
2788	// request a VCI DMISS transaction
2789	r_dcache_vci_paddr = paddr;
2790	r_dcache_vci_miss_req = true;
2791	r_dcache_miss_type = PROC_MISS;
2792	r_dcache_fsm = DCACHE_MISS_SELECT;
2793	#if DEBUG_DCACHE
2794	if (m_debug_dcache_fsm)
2795	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2796	<< " READ MISS in dcache"
2797	<< " / PADDR = " << std::hex << paddr << std::endl;
2798	#endif
2799	}
2800	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2801	{
2802	// stalled until cleanup is acknowledged
2803	r_dcache_fsm = DCACHE_IDLE;
2804	#if DEBUG_DCACHE
2805	if (m_debug_dcache_fsm)
2806	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2807	<< " Pending cleanup, stalled until cleanup acknowledge"
2808	<< " / PADDR = " << std::hex << paddr << std::endl;
2809	#endif
2810	}
2811	else // cache hit
2812	{
2813	#ifdef INSTRUMENTATION
2814	m_cpt_data_read++;
2815	#endif
2816	// returns data to processor
2817	m_drsp.valid = true;
2818	m_drsp.error = false;
2819	m_drsp.rdata = cache_rdata;
2820	#if DEBUG_DCACHE
2821	if (m_debug_dcache_fsm)
2822	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2823	<< " READ HIT in dcache"
2824	<< " : PADDR = " << std::hex << paddr
2825	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2826	#endif
2827	}
2828	}
2829	else // uncacheable read
2830	{
2831	r_dcache_vci_paddr = paddr;
2832	r_dcache_vci_unc_be = m_dreq.be;
2833	r_dcache_vci_unc_write = false;
2834	r_dcache_vci_unc_req = true;
2835	r_dcache_fsm = DCACHE_UNC_WAIT;
2836	#if DEBUG_DCACHE
2837	if (m_debug_dcache_fsm)
2838	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2839	<< " READ UNCACHEABLE in dcache"
2840	<< " / PADDR = " << std::hex << paddr << std::endl;
2841	#endif
2842	}
2843	} // end READ
2844
2845	// LL request (non cachable)
2846	// We request a VCI LL transaction to CMD FSM and register
2847	// the LL/SC operation in llsc buffer.
2848	else if (m_dreq.type == iss_t::DATA_LL)
2849	{
2850	// register paddr in LLSC buffer
2851	r_dcache_llsc_paddr = paddr;
2852	r_dcache_llsc_count = LLSC_TIMEOUT;
2853	r_dcache_llsc_valid = true;
2854
2855	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2856	r_dcache_vci_ll_req = true;
2857	r_dcache_vci_paddr = paddr;
2858	r_dcache_ll_rsp_count = 0;
2859	r_dcache_fsm = DCACHE_LL_WAIT;
2860
2861	}// end LL
2862
2863	// WRITE request:
2864	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2865	// the processor and set the Dirty bit before handling the write request,
2866	// going to the DCACHE_DIRTY_GT_PTE state.
2867	// If we don't need to set the Dirty bit, we can acknowledge
2868	// the processor request, as the write arguments (including the
2869	// physical address) are registered in r_dcache_save registers,
2870	// and the write will be done in the P1 pipeline stage.
2871	else if (m_dreq.type == iss_t::DATA_WRITE)
2872	{
2873	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2874	and not tlb_flags.d) // Dirty bit must be set
2875	{
2876	// The PTE physical address is obtained from the nline value (dtlb),
2877	// and from the virtual address (word index)
2878	if (tlb_flags.b ) // PTE1
2879	{
2880	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2881	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2882	}
2883	else // PTE2
2884	{
2885	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2886	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2887	}
2888	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2889	}
2890	else // Write request accepted
2891	{
2892	#ifdef INSTRUMENTATION
2893	m_cpt_data_write++;
2894	#endif
2895	// cleaning llsc buffer if address matching
2896	if (paddr == r_dcache_llsc_paddr.read())
2897	r_dcache_llsc_valid = false;
2898
2899	if (not cacheable) // uncacheable write
2900	{
2901	r_dcache_vci_paddr = paddr;
2902	r_dcache_vci_wdata = m_dreq.wdata;
2903	r_dcache_vci_unc_write = true;
2904	r_dcache_vci_unc_be = m_dreq.be;
2905	r_dcache_vci_unc_req = true;
2906	r_dcache_fsm = DCACHE_UNC_WAIT;
2907	}
2908	else
2909	{
2910	// response to processor
2911	m_drsp.valid = true;
2912	// activating P1 stage
2913	wbuf_request = true;
2914	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2915	}
2916	}
2917	} // end WRITE
2918
2919	// SC request:
2920	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2921	// the processor and set the Dirty bit before handling the write request,
2922	// going to the DCACHE_DIRTY_GT_PTE state.
2923	// If we don't need to set the Dirty bit, we test the llsc buffer:
2924	// If failure, we send a negative response to processor.
2925	// If success, we request a SC transaction to CMD FSM and go
2926	// to DCACHE_SC_WAIT state.
2927	// We don't check a possible write hit in dcache, as the cache update
2928	// is done by the coherence transaction induced by the SC...
2929	else if (m_dreq.type == iss_t::DATA_SC)
2930	{
2931	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2932	and not tlb_flags.d) // Dirty bit must be set
2933	{
2934	// The PTE physical address is obtained from the nline value (dtlb),
2935	// and the word index (virtual address)
2936	if (tlb_flags.b) // PTE1
2937	{
2938	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2939	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2940	}
2941	else // PTE2
2942	{
2943	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2944	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2945	}
2946	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2947	m_drsp.valid = false;
2948	m_drsp.error = false;
2949	m_drsp.rdata = 0;
2950	}
2951	else // SC request accepted
2952	{
2953	#ifdef INSTRUMENTATION
2954	m_cpt_data_sc++;
2955	#endif
2956	// checking local success
2957	if (r_dcache_llsc_valid.read() and
2958	(r_dcache_llsc_paddr.read() == paddr)) // local success
2959	{
2960	// request an SC CMD and go to DCACHE_SC_WAIT state
2961	r_dcache_vci_paddr = paddr;
2962	r_dcache_vci_sc_req = true;
2963	r_dcache_vci_sc_data = m_dreq.wdata;
2964	r_dcache_fsm = DCACHE_SC_WAIT;
2965	}
2966	else // local fail
2967	{
2968	m_drsp.valid = true;
2969	m_drsp.error = false;
2970	m_drsp.rdata = 0x1;
2971	}
2972	}
2973	} // end SC
2974	} // end valid_req
2975	} // end if read/write/ll/sc request
2976	} // end processor request
2977
2978	// itlb miss request
2979	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
2980	{
2981	r_dcache_tlb_ins = true;
2982	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2983	r_dcache_fsm = DCACHE_TLB_MISS;
2984	}
2985
2986	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2987	r_dcache_updt_req = updt_request;
2988	r_dcache_wbuf_req = wbuf_request or
2989	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2990	break;
2991	}
2992	/////////////////////
2993	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2994	// Input arguments are:
2995	// - r_dcache_tlb_vaddr
2996	// - r_dcache_tlb_ins (true when itlb miss)
2997	// The sub-fsm access the dcache to find the missing TLB entry,
2998	// and activates the cache miss procedure in case of miss.
2999	// It bypass the first level page table access if possible.
3000	// It uses atomic access to update the R/L access bits
3001	// in the page table if required.
3002	// It directly updates the itlb or dtlb, and writes into the
3003	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3004	{
3005	uint32_t ptba = 0;
3006	bool bypass;
3007	paddr_t pte_paddr;
3008
3009	// evaluate bypass in order to skip first level page table access
3010	if (r_dcache_tlb_ins.read()) // itlb miss
3011	{
3012	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3013	}
3014	else // dtlb miss
3015	{
3016	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3017	}
3018
3019	if (not bypass) // Try to read PTE1/PTD1 in dcache
3020	{
3021	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3022	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3023	r_dcache_tlb_paddr = pte_paddr;
3024	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3025	}
3026	else // Try to read PTE2 in dcache
3027	{
3028	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3029	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3030	r_dcache_tlb_paddr = pte_paddr;
3031	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3032	}
3033
3034	#if DEBUG_DCACHE
3035	if (m_debug_dcache_fsm)
3036	{
3037	if (r_dcache_tlb_ins.read())
3038	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3039	else
3040	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3041	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3042	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3043	<< " / BYPASS = " << bypass
3044	<< " / PTE_ADR = " << pte_paddr << std::endl;
3045	}
3046	#endif
3047
3048	break;
3049	}
3050	/////////////////////////
3051	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3052	{
3053	// coherence clack request (from DSPIN CLACK)
3054	if (r_dcache_clack_req.read())
3055	{
3056	r_dcache_fsm = DCACHE_CC_CHECK;
3057	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3058	break;
3059	}
3060
3061	// coherence request (from CC_RECEIVE FSM)
3062	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3063	{
3064	r_dcache_fsm = DCACHE_CC_CHECK;
3065	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3066	break;
3067	}
3068
3069	uint32_t entry;
3070	size_t way;
3071	size_t set;
3072	size_t word;
3073	int cache_state;
3074	r_dcache.read(r_dcache_tlb_paddr.read(),
3075	&entry,
3076	&way,
3077	&set,
3078	&word,
3079	&cache_state);
3080	#ifdef INSTRUMENTATION
3081	m_cpt_dcache_data_read++;
3082	m_cpt_dcache_dir_read++;
3083	#endif
3084	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3085	{
3086	if (not (entry & PTE_V_MASK)) // unmapped
3087	{
3088	if (r_dcache_tlb_ins.read())
3089	{
3090	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3091	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3092	r_icache_tlb_miss_req = false;
3093	r_icache_tlb_rsp_error = true;
3094	}
3095	else
3096	{
3097	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3098	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3099	m_drsp.valid = true;
3100	m_drsp.error = true;
3101	}
3102	r_dcache_fsm = DCACHE_IDLE;
3103
3104	#if DEBUG_DCACHE
3105	if (m_debug_dcache_fsm)
3106	{
3107	std::cout << " <PROC " << name()
3108	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3109	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3110	<< std::dec << " / way = " << way
3111	<< std::dec << " / set = " << set
3112	<< std::dec << " / word = " << word
3113	<< std::hex << " / PTE1 = " << entry << std::endl;
3114	}
3115	#endif
3116
3117	}
3118	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3119	{
3120	// mark the cache line ac containing a PTD
3121	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3122
3123	// register bypass
3124	if (r_dcache_tlb_ins.read()) // itlb
3125	{
3126	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3127	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3128	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3129	}
3130	else // dtlb
3131	{
3132	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3133	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3134	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3135	}
3136	r_dcache_tlb_paddr =
3137	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3138	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3139	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3140
3141	#if DEBUG_DCACHE
3142	if (m_debug_dcache_fsm)
3143	{
3144	std::cout << " <PROC " << name()
3145	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3146	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3147	<< std::dec << " / way = " << way
3148	<< std::dec << " / set = " << set
3149	<< std::dec << " / word = " << word
3150	<< std::hex << " / PTD = " << entry << std::endl;
3151	}
3152	#endif
3153	}
3154	else // PTE1 : we must update the TLB
3155	{
3156	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3157	r_dcache_tlb_pte_flags = entry;
3158	r_dcache_tlb_cache_way = way;
3159	r_dcache_tlb_cache_set = set;
3160	r_dcache_tlb_cache_word = word;
3161	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3162
3163	#if DEBUG_DCACHE
3164	if (m_debug_dcache_fsm)
3165	{
3166	std::cout << " <PROC " << name()
3167	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3168	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3169	<< std::dec << " / way = " << way
3170	<< std::dec << " / set = " << set
3171	<< std::dec << " / word = " << word
3172	<< std::hex << " / PTE1 = " << entry << std::endl;
3173	}
3174	#endif
3175	}
3176	}
3177	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3178	{
3179	// stalled until cleanup is acknowledged
3180	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3181	}
3182	else // we must load the missing cache line in dcache
3183	{
3184	r_dcache_vci_miss_req = true;
3185	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3186	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3187	r_dcache_miss_type = PTE1_MISS;
3188	r_dcache_fsm = DCACHE_MISS_SELECT;
3189
3190	#if DEBUG_DCACHE
3191	if (m_debug_dcache_fsm)
3192	{
3193	std::cout << " <PROC " << name()
3194	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3195	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3196	}
3197	#endif
3198	}
3199	break;
3200	}
3201	////////////////////////////
3202	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3203	{
3204	size_t way;
3205	size_t set;
3206
3207	if (r_dcache_tlb_ins.read())
3208	{
3209	r_itlb.select(r_dcache_tlb_vaddr.read(),
3210	true, // PTE1
3211	&way,
3212	&set);
3213	#ifdef INSTRUMENTATION
3214	m_cpt_itlb_read++;
3215	#endif
3216	}
3217	else
3218	{
3219	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3220	true, // PTE1
3221	&way,
3222	&set);
3223	#ifdef INSTRUMENTATION
3224	m_cpt_dtlb_read++;
3225	#endif
3226	}
3227	r_dcache_tlb_way = way;
3228	r_dcache_tlb_set = set;
3229	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3230
3231	#if DEBUG_DCACHE
3232	if (m_debug_dcache_fsm)
3233	{
3234	if (r_dcache_tlb_ins.read())
3235	std::cout << " <PROC " << name()
3236	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3237	else
3238	std::cout << " <PROC " << name()
3239	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3240	std::cout << " way = " << std::dec << way
3241	<< " / set = " << set << std::endl;
3242	}
3243	#endif
3244	break;
3245	}
3246	//////////////////////////
3247	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3248	// - if L/R bit already set, exit the sub-fsm.
3249	// - if not, we update the page table but we dont write
3250	// neither in DCACHE, nor in TLB, as this will be done by
3251	// the coherence mechanism.
3252	{
3253	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3254	uint32_t pte = r_dcache_tlb_pte_flags.read();
3255	bool pt_updt = false;
3256	bool local = true;
3257
3258	// We should compute the access locality:
3259	// The PPN MSB bits define the destination cluster index.
3260	// The m_srcid MSB bits define the source cluster index.
3261	// The number of bits to compare depends on the number of clusters,
3262	// and can be obtained in the mapping table.
3263	// As long as this computation is not done, all access are local.
3264
3265	if (local) // local access
3266	{
3267	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3268	{
3269	pt_updt = true;
3270	r_dcache_vci_cas_old = pte;
3271	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3272	pte = pte \| PTE_L_MASK;
3273	r_dcache_tlb_pte_flags = pte;
3274	}
3275	}
3276	else // remote access
3277	{
3278	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3279	{
3280	pt_updt = true;
3281	r_dcache_vci_cas_old = pte;
3282	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3283	pte = pte \| PTE_R_MASK;
3284	r_dcache_tlb_pte_flags = pte;
3285	}
3286	}
3287
3288	if (not pt_updt) // update TLB and return
3289	{
3290	if (r_dcache_tlb_ins.read())
3291	{
3292	r_itlb.write(true, // 2M page
3293	pte,
3294	0, // argument unused for a PTE1
3295	r_dcache_tlb_vaddr.read(),
3296	r_dcache_tlb_way.read(),
3297	r_dcache_tlb_set.read(),
3298	nline);
3299	#ifdef INSTRUMENTATION
3300	m_cpt_itlb_write++;
3301	#endif
3302
3303	#if DEBUG_DCACHE
3304	if (m_debug_dcache_fsm)
3305	{
3306	std::cout << " <PROC " << name()
3307	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3308	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3309	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3310	r_itlb.printTrace();
3311	}
3312	#endif
3313	}
3314	else
3315	{
3316	r_dtlb.write(true, // 2M page
3317	pte,
3318	0, // argument unused for a PTE1
3319	r_dcache_tlb_vaddr.read(),
3320	r_dcache_tlb_way.read(),
3321	r_dcache_tlb_set.read(),
3322	nline);
3323	#ifdef INSTRUMENTATION
3324	m_cpt_dtlb_write++;
3325	#endif
3326
3327	#if DEBUG_DCACHE
3328	if (m_debug_dcache_fsm)
3329	{
3330	std::cout << " <PROC " << name()
3331	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3332	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3333	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3334	r_dtlb.printTrace();
3335	}
3336	#endif
3337	}
3338	r_dcache_fsm = DCACHE_TLB_RETURN;
3339	}
3340	else // update page table but not TLB
3341	{
3342	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3343
3344	#if DEBUG_DCACHE
3345	if (m_debug_dcache_fsm)
3346	{
3347	std::cout << " <PROC " << name()
3348	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3349	<< std::endl;
3350	}
3351	#endif
3352	}
3353	break;
3354	}
3355	/////////////////////////
3356	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3357	{
3358	// coherence clack request (from DSPIN CLACK)
3359	if (r_dcache_clack_req.read())
3360	{
3361	r_dcache_fsm = DCACHE_CC_CHECK;
3362	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3363	break;
3364	}
3365
3366	// coherence request (from CC_RECEIVE FSM)
3367	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3368	{
3369	r_dcache_fsm = DCACHE_CC_CHECK;
3370	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3371	break;
3372	}
3373
3374	uint32_t pte_flags;
3375	uint32_t pte_ppn;
3376	size_t way;
3377	size_t set;
3378	size_t word;
3379	int cache_state;
3380
3381	r_dcache.read(r_dcache_tlb_paddr.read(),
3382	&pte_flags,
3383	&pte_ppn,
3384	&way,
3385	&set,
3386	&word,
3387	&cache_state);
3388	#ifdef INSTRUMENTATION
3389	m_cpt_dcache_data_read++;
3390	m_cpt_dcache_dir_read++;
3391	#endif
3392	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3393	{
3394	if (not (pte_flags & PTE_V_MASK)) // unmapped
3395	{
3396	if (r_dcache_tlb_ins.read())
3397	{
3398	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3399	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3400	r_icache_tlb_miss_req = false;
3401	r_icache_tlb_rsp_error = true;
3402	}
3403	else
3404	{
3405	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3406	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3407	m_drsp.valid = true;
3408	m_drsp.error = true;
3409	}
3410	r_dcache_fsm = DCACHE_IDLE;
3411
3412	#if DEBUG_DCACHE
3413	if (m_debug_dcache_fsm)
3414	{
3415	std::cout << " <PROC " << name()
3416	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3417	<< " PTE_FLAGS = " << std::hex << pte_flags
3418	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3419	}
3420	#endif
3421	}
3422	else // mapped : we must update the TLB
3423	{
3424	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3425	r_dcache_tlb_pte_flags = pte_flags;
3426	r_dcache_tlb_pte_ppn = pte_ppn;
3427	r_dcache_tlb_cache_way = way;
3428	r_dcache_tlb_cache_set = set;
3429	r_dcache_tlb_cache_word = word;
3430	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3431
3432	#if DEBUG_DCACHE
3433	if (m_debug_dcache_fsm)
3434	{
3435	std::cout << " <PROC " << name()
3436	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3437	<< " PTE_FLAGS = " << std::hex << pte_flags
3438	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3439	}
3440	#endif
3441	}
3442	}
3443	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3444	{
3445	// stalled until cleanup is acknowledged
3446	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3447
3448	#if DEBUG_DCACHE
3449	if (m_debug_dcache_fsm)
3450	{
3451	std::cout << " <PROC " << name()
3452	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3453	<< std::endl;
3454	}
3455	#endif
3456	}
3457	else // we must load the missing cache line in dcache
3458	{
3459	r_dcache_fsm = DCACHE_MISS_SELECT;
3460	r_dcache_vci_miss_req = true;
3461	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3462	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3463	r_dcache_miss_type = PTE2_MISS;
3464
3465	#if DEBUG_DCACHE
3466	if (m_debug_dcache_fsm)
3467	{
3468	std::cout << " <PROC " << name()
3469	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3470	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3471	}
3472	#endif
3473	}
3474	break;
3475	}
3476	////////////////////////////
3477	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3478	{
3479	size_t way;
3480	size_t set;
3481
3482	if (r_dcache_tlb_ins.read())
3483	{
3484	r_itlb.select(r_dcache_tlb_vaddr.read(),
3485	false, // PTE2
3486	&way,
3487	&set);
3488	#ifdef INSTRUMENTATION
3489	m_cpt_itlb_read++;
3490	#endif
3491	}
3492	else
3493	{
3494	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3495	false, // PTE2
3496	&way,
3497	&set);
3498	#ifdef INSTRUMENTATION
3499	m_cpt_dtlb_read++;
3500	#endif
3501	}
3502
3503	#if DEBUG_DCACHE
3504	if (m_debug_dcache_fsm)
3505	{
3506	if (r_dcache_tlb_ins.read())
3507	std::cout << " <PROC " << name()
3508	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3509	else
3510	std::cout << " <PROC " << name()
3511	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3512	std::cout << " way = " << std::dec << way
3513	<< " / set = " << set << std::endl;
3514	}
3515	#endif
3516	r_dcache_tlb_way = way;
3517	r_dcache_tlb_set = set;
3518	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3519	break;
3520	}
3521	//////////////////////////
3522	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3523	// - if L/R bit already set, exit the sub-fsm.
3524	// - if not, we update the page table but we dont write
3525	// neither in DCACHE, nor in TLB, as this will be done by
3526	// the coherence mechanism.
3527	{
3528	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3529	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3530	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3531	bool pt_updt = false;
3532	bool local = true;
3533
3534	// We should compute the access locality:
3535	// The PPN MSB bits define the destination cluster index.
3536	// The m_srcid MSB bits define the source cluster index.
3537	// The number of bits to compare depends on the number of clusters,
3538	// and can be obtained in the mapping table.
3539	// As long as this computation is not done, all access are local.
3540
3541	if (local) // local access
3542	{
3543	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3544	{
3545	pt_updt = true;
3546	r_dcache_vci_cas_old = pte_flags;
3547	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3548	pte_flags = pte_flags \| PTE_L_MASK;
3549	r_dcache_tlb_pte_flags = pte_flags;
3550	}
3551	}
3552	else // remote access
3553	{
3554	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3555	{
3556	pt_updt = true;
3557	r_dcache_vci_cas_old = pte_flags;
3558	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3559	pte_flags = pte_flags \| PTE_R_MASK;
3560	r_dcache_tlb_pte_flags = pte_flags;
3561	}
3562	}
3563
3564	if (not pt_updt) // update TLB
3565	{
3566	if (r_dcache_tlb_ins.read())
3567	{
3568	r_itlb.write( false, // 4K page
3569	pte_flags,
3570	pte_ppn,
3571	r_dcache_tlb_vaddr.read(),
3572	r_dcache_tlb_way.read(),
3573	r_dcache_tlb_set.read(),
3574	nline );
3575	#ifdef INSTRUMENTATION
3576	m_cpt_itlb_write++;
3577	#endif
3578
3579	#if DEBUG_DCACHE
3580	if (m_debug_dcache_fsm)
3581	{
3582	std::cout << " <PROC " << name()
3583	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3584	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3585	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3586	r_itlb.printTrace();
3587	}
3588	#endif
3589	}
3590	else
3591	{
3592	r_dtlb.write(false, // 4K page
3593	pte_flags,
3594	pte_ppn,
3595	r_dcache_tlb_vaddr.read(),
3596	r_dcache_tlb_way.read(),
3597	r_dcache_tlb_set.read(),
3598	nline);
3599	#ifdef INSTRUMENTATION
3600	m_cpt_dtlb_write++;
3601	#endif
3602
3603	#if DEBUG_DCACHE
3604	if (m_debug_dcache_fsm)
3605	{
3606	std::cout << " <PROC " << name()
3607	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3608	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3609	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3610	r_dtlb.printTrace();
3611	}
3612	#endif
3613
3614	}
3615	r_dcache_fsm = DCACHE_TLB_RETURN;
3616	}
3617	else // update page table but not TLB
3618	{
3619	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3620
3621	#if DEBUG_DCACHE
3622	if (m_debug_dcache_fsm)
3623	{
3624	std::cout << " <PROC " << name()
3625	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3626	}
3627	#endif
3628	}
3629	break;
3630	}
3631	////////////////////////
3632	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3633	{
3634	#if DEBUG_DCACHE
3635	if (m_debug_dcache_fsm)
3636	{
3637	std::cout << " <PROC " << name()
3638	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3639	}
3640	#endif
3641	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3642	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3643
3644	// checking llsc reservation buffer
3645	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3646	r_dcache_llsc_valid = false;
3647
3648	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3649	r_dcache_vci_cas_req = true;
3650	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3651	break;
3652	}
3653	////////////////////////
3654	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3655	// We consume the response in rsp FIFO,
3656	// and exit the sub-fsm, but we don't
3657	// analyse the response, because we don't
3658	// care if the L/R bit update is not done.
3659	// We must take the coherence requests because
3660	// there is a risk of dead-lock
3661
3662	{
3663	// coherence clack request (from DSPIN CLACK)
3664	if (r_dcache_clack_req.read())
3665	{
3666	r_dcache_fsm = DCACHE_CC_CHECK;
3667	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3668	break;
3669	}
3670
3671	// coherence request (from CC_RECEIVE FSM)
3672	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3673	{
3674	r_dcache_fsm = DCACHE_CC_CHECK;
3675	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3676	break;
3677	}
3678
3679	if (r_vci_rsp_data_error.read()) // bus error
3680	{
3681	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3682	std::cout << "This should not happen in this state" << std::endl;
3683	exit(0);
3684	}
3685	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3686	{
3687	#if DEBUG_DCACHE
3688	if (m_debug_dcache_fsm)
3689	{
3690	std::cout << " <PROC " << name()
3691	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3692	}
3693	#endif
3694	vci_rsp_fifo_dcache_get = true;
3695	r_dcache_fsm = DCACHE_TLB_RETURN;
3696	}
3697	break;
3698	}
3699	///////////////////////
3700	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3701	{
3702	#if DEBUG_DCACHE
3703	if (m_debug_dcache_fsm)
3704	{
3705	std::cout << " <PROC " << name()
3706	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3707	}
3708	#endif
3709	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3710	r_dcache_fsm = DCACHE_IDLE;
3711	break;
3712	}
3713	///////////////////////
3714	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3715	// and both itlb and dtlb must be flushed.
3716	// Caution : the itlb miss requests must be taken
3717	// to avoid dead-lock in case of simultaneous ITLB miss
3718	// Caution : the clack and cc requests must be taken
3719	// to avoid dead-lock
3720	{
3721	// coherence clack request (from DSPIN CLACK)
3722	if (r_dcache_clack_req.read())
3723	{
3724	r_dcache_fsm = DCACHE_CC_CHECK;
3725	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3726	break;
3727	}
3728
3729	// coherence request (from CC_RECEIVE FSM)
3730	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3731	{
3732	r_dcache_fsm = DCACHE_CC_CHECK;
3733	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3734	break;
3735	}
3736
3737	// itlb miss request
3738	if (r_icache_tlb_miss_req.read())
3739	{
3740	r_dcache_tlb_ins = true;
3741	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3742	r_dcache_fsm = DCACHE_TLB_MISS;
3743	break;
3744	}
3745
3746	if (not r_dcache_xtn_req.read())
3747	{
3748	r_dtlb.flush();
3749	r_mmu_ptpr = m_dreq.wdata;
3750	r_dcache_fsm = DCACHE_IDLE;
3751	m_drsp.valid = true;
3752	}
3753	break;
3754	}
3755	/////////////////////
3756	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3757	// The coherence request must be taken
3758	// as there is a risk of dead-lock
3759	{
3760	// coherence clack request (from DSPIN CLACK)
3761	if (r_dcache_clack_req.read())
3762	{
3763	r_dcache_fsm = DCACHE_CC_CHECK;
3764	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3765	break;
3766	}
3767
3768	// coherence request (from CC_RECEIVE FSM)
3769	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3770	{
3771	r_dcache_fsm = DCACHE_CC_CHECK;
3772	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3773	break;
3774	}
3775
3776	if (r_wbuf.empty())
3777	{
3778	m_drsp.valid = true;
3779	r_dcache_fsm = DCACHE_IDLE;
3780	}
3781	break;
3782	}
3783	////////////////////////
3784	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3785	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3786	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3787	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3788	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3789
3790	{
3791	// coherence clack request (from DSPIN CLACK)
3792	if (r_dcache_clack_req.read())
3793	{
3794	r_dcache_fsm = DCACHE_CC_CHECK;
3795	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3796	break;
3797	}
3798
3799	// coherence request (from CC_RECEIVE FSM)
3800	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3801	{
3802	r_dcache_fsm = DCACHE_CC_CHECK;
3803	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3804	break;
3805	}
3806
3807	// itlb miss request
3808	if (r_icache_tlb_miss_req.read())
3809	{
3810	r_dcache_tlb_ins = true;
3811	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3812	r_dcache_fsm = DCACHE_TLB_MISS;
3813	break;
3814	}
3815
3816	// test if XTN request to icache completed
3817	if (not r_dcache_xtn_req.read())
3818	{
3819	r_dcache_fsm = DCACHE_IDLE;
3820	m_drsp.valid = true;
3821	}
3822	break;
3823	}
3824	/////////////////////////
3825	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3826	// r_dcache_flush_count as a slot counter,
3827	// looping in this state until all slots have been visited.
3828	// It can require two cycles per slot:
3829	// We test here the slot state, and make the actual inval
3830	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3831	// A cleanup request is generated for each valid line.
3832	// returns to IDLE and flush TLBs when last slot
3833	{
3834	// coherence clack request (from DSPIN CLACK)
3835	if (r_dcache_clack_req.read())
3836	{
3837	r_dcache_fsm = DCACHE_CC_CHECK;
3838	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3839	break;
3840	}
3841
3842	// coherence request (from CC_RECEIVE FSM)
3843	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3844	{
3845	r_dcache_fsm = DCACHE_CC_CHECK;
3846	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3847	break;
3848	}
3849
3850	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3851	{
3852	int state;
3853	paddr_t tag;
3854	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3855	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3856
3857	#ifdef INSTRUMENTATION
3858	m_cpt_dcache_dir_read++;
3859	#endif
3860	r_dcache.read_dir(way,
3861	set,
3862	&tag,
3863	&state);
3864
3865	if (state == CACHE_SLOT_STATE_VALID) // inval required
3866	{
3867	// request cleanup
3868	r_dcache_cc_send_req = true;
3869	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3870	r_dcache_cc_send_way = way;
3871	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3872
3873	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3874	r_dcache_miss_way = way;
3875	r_dcache_miss_set = set;
3876	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3877	}
3878	else if (r_dcache_flush_count.read() ==
3879	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3880	{
3881	r_dtlb.reset();
3882	r_itlb.reset();
3883	r_dcache_fsm = DCACHE_IDLE;
3884	m_drsp.valid = true;
3885	}
3886
3887	// saturation counter
3888	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3889	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3890	}
3891	break;
3892	}
3893	////////////////////////////
3894	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3895	// and reset directory extension.
3896	// returns to IDLE and flush TLBs when last slot
3897	{
3898	size_t way = r_dcache_miss_way.read();
3899	size_t set = r_dcache_miss_set.read();
3900
3901	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3902	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3903
3904	#ifdef INSTRUMENTATION
3905	m_cpt_dcache_dir_write++;
3906	#endif
3907	r_dcache.write_dir(way,
3908	set,
3909	CACHE_SLOT_STATE_ZOMBI);
3910
3911	if (r_dcache_flush_count.read() ==
3912	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3913	{
3914	r_dtlb.reset();
3915	r_itlb.reset();
3916	r_dcache_fsm = DCACHE_IDLE;
3917	m_drsp.valid = true;
3918	}
3919	else
3920	{
3921	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3922	}
3923	break;
3924	}
3925	/////////////////////////
3926	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3927	{
3928	r_dtlb.inval(r_dcache_save_wdata.read());
3929	r_dcache_fsm = DCACHE_IDLE;
3930	m_drsp.valid = true;
3931	break;
3932	}
3933	////////////////////////////
3934	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3935	// requires 3 cycles: access tlb, read cache, inval cache
3936	// we compute the physical address in this state
3937	{
3938	paddr_t paddr;
3939	bool hit;
3940
3941	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
3942	{
3943
3944	#ifdef INSTRUMENTATION
3945	m_cpt_dtlb_read++;
3946	#endif
3947	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
3948	&paddr);
3949	}
3950	else // dtlb not activated
3951	{
3952	paddr = (paddr_t)r_dcache_save_wdata.read();
3953	if (vci_param::N > 32)
3954	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3955	hit = true;
3956	}
3957
3958	if (hit) // tlb hit
3959	{
3960	r_dcache_save_paddr = paddr;
3961	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3962	}
3963	else // tlb miss
3964	{
3965
3966	#ifdef INSTRUMENTATION
3967	m_cpt_dtlb_miss++;
3968	#endif
3969	r_dcache_tlb_ins = false; // dtlb
3970	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3971	r_dcache_fsm = DCACHE_TLB_MISS;
3972	}
3973
3974	#if DEBUG_DCACHE
3975	if (m_debug_dcache_fsm)
3976	{
3977	std::cout << " <PROC " << name()
3978	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3979	<< " / VADDR = " << r_dcache_save_wdata.read()
3980	<< " / PADDR = " << paddr << std::endl;
3981	}
3982	#endif
3983
3984	break;
3985	}
3986	////////////////////////////
3987	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3988	// requires 2 cycles: read cache / inval cache
3989	// In this state we read dcache.
3990	{
3991	size_t way;
3992	size_t set;
3993	size_t word;
3994	int state;
3995
3996	#ifdef INSTRUMENTATION
3997	m_cpt_dcache_dir_read++;
3998	#endif
3999	r_dcache.read_dir(r_dcache_save_paddr.read(),
4000	&state,
4001	&way,
4002	&set,
4003	&word);
4004
4005	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4006	{
4007	r_dcache_xtn_way = way;
4008	r_dcache_xtn_set = set;
4009	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4010	}
4011	else // miss : nothing to do
4012	{
4013	r_dcache_fsm = DCACHE_IDLE;
4014	m_drsp.valid = true;
4015	}
4016
4017	#if DEBUG_DCACHE
4018	if (m_debug_dcache_fsm)
4019	{
4020	std::cout << " <PROC " << name()
4021	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4022	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4023	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4024	<< " / SET = " << set
4025	<< " / WAY = " << way << std::endl;
4026	}
4027	#endif
4028	break;
4029	}
4030	////////////////////////////
4031	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4032	// Blocked if previous cleanup not completed
4033	// Test if itlb or dtlb inval is required
4034	{
4035	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4036	{
4037	size_t way = r_dcache_xtn_way.read();
4038	size_t set = r_dcache_xtn_set.read();
4039	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4040
4041	#ifdef INSTRUMENTATION
4042	m_cpt_dcache_dir_write++;
4043	#endif
4044	r_dcache.write_dir(way,
4045	set,
4046	CACHE_SLOT_STATE_ZOMBI);
4047
4048	// request cleanup
4049	r_dcache_cc_send_req = true;
4050	r_dcache_cc_send_nline = nline;
4051	r_dcache_cc_send_way = way;
4052	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4053
4054	// possible itlb & dtlb invalidate
4055	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4056	{
4057	r_dcache_tlb_inval_line = nline;
4058	r_dcache_tlb_inval_set = 0;
4059	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4060	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4061	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4062	}
4063	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4064	{
4065	r_itlb.reset();
4066	r_dtlb.reset();
4067	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4068	r_dcache_fsm = DCACHE_IDLE;
4069	m_drsp.valid = true;
4070	}
4071	else
4072	{
4073	r_dcache_fsm = DCACHE_IDLE;
4074	m_drsp.valid = true;
4075	}
4076
4077	#if DEBUG_DCACHE
4078	if (m_debug_dcache_fsm)
4079	{
4080	std::cout << " <PROC " << name()
4081	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4082	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4083	}
4084	#endif
4085	}
4086	break;
4087	}
4088	//////////////////////////////
4089	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4090	{
4091	r_dcache_fsm = DCACHE_IDLE;
4092	m_drsp.valid = true;
4093	break;
4094	}
4095	////////////////////////
4096	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4097	// Waiting in this state if no slot available.
4098	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4099	// we send the cleanup request in this state.
4100	// If not, a r_icache_cleanup_victim_req flip-flop is
4101	// utilized for saving this cleanup request, and it will be sent later
4102	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4103	// The r_icache_miss_clack flip-flop is set
4104	// when a cleanup is required
4105	{
4106	if (m_dreq.valid) m_cost_data_miss_frz++;
4107
4108	// coherence clack request (from DSPIN CLACK)
4109	if (r_dcache_clack_req.read())
4110	{
4111	r_dcache_fsm = DCACHE_CC_CHECK;
4112	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4113	break;
4114	}
4115
4116	// coherence request (from CC_RECEIVE FSM)
4117	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4118	{
4119	r_dcache_fsm = DCACHE_CC_CHECK;
4120	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4121	break;
4122	}
4123
4124	bool found = false;
4125	bool cleanup = false;
4126	size_t way = 0;
4127	size_t set = 0;
4128	paddr_t victim = 0;
4129
4130	#ifdef INSTRUMENTATION
4131	m_cpt_dcache_dir_read++;
4132	#endif
4133	r_dcache.read_select(r_dcache_save_paddr.read(),
4134	&victim,
4135	&way,
4136	&set,
4137	&found,
4138	&cleanup);
4139
4140	if (not found)
4141	{
4142	break;
4143	}
4144	else
4145	{
4146	r_dcache_miss_way = way;
4147	r_dcache_miss_set = set;
4148
4149	// reset to 0 the miss watchdog timer
4150	r_dcache_miss_wdt = 0;
4151
4152	if (cleanup)
4153	{
4154	if (not r_dcache_cc_send_req.read())
4155	{
4156	r_dcache_cc_send_req = true;
4157	r_dcache_cc_send_nline = victim;
4158	r_dcache_cc_send_way = way;
4159	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4160
4161	}
4162	else
4163	{
4164	r_dcache_cleanup_victim_req = true;
4165	r_dcache_cleanup_victim_nline = victim;
4166	}
4167
4168	r_dcache_miss_clack = true;
4169	r_dcache_fsm = DCACHE_MISS_CLEAN;
4170	}
4171	else
4172	{
4173	r_dcache_fsm = DCACHE_MISS_WAIT;
4174	}
4175
4176	#if DEBUG_DCACHE
4177	if (m_debug_dcache_fsm)
4178	{
4179	std::cout << " <PROC " << name()
4180	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4181	<< " / WAY = " << way
4182	<< " / SET = " << set
4183	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4184	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4185	else std::cout << std::endl;
4186	}
4187	#endif
4188	} // end found
4189	break;
4190	}
4191	///////////////////////
4192	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4193	// and possibly request itlb or dtlb invalidate
4194	{
4195	if (m_dreq.valid) m_cost_data_miss_frz++;
4196
4197	size_t way = r_dcache_miss_way.read();
4198	size_t set = r_dcache_miss_set.read();
4199
4200	#ifdef INSTRUMENTATION
4201	m_cpt_dcache_dir_read++;
4202	#endif
4203	r_dcache.write_dir(way,
4204	set,
4205	CACHE_SLOT_STATE_ZOMBI);
4206	#if DEBUG_DCACHE
4207	if (m_debug_dcache_fsm)
4208	{
4209	std::cout << " <PROC " << name()
4210	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4211	<< " / way = " << way
4212	<< " / set = " << set << std::endl;
4213	}
4214	#endif
4215	// if selective itlb & dtlb invalidate are required
4216	// the miss response is not handled before invalidate completed
4217	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4218	{
4219	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4220
4221	if (not r_dcache_cleanup_victim_req.read())
4222	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4223	else
4224	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4225
4226	r_dcache_tlb_inval_set = 0;
4227	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4228	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4229	}
4230	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4231	{
4232	r_itlb.reset();
4233	r_dtlb.reset();
4234	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4235	r_dcache_fsm = DCACHE_MISS_WAIT;
4236	}
4237	else
4238	{
4239	r_dcache_fsm = DCACHE_MISS_WAIT;
4240	}
4241	break;
4242	}
4243	//////////////////////
4244	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4245	// This state is in charge of error signaling
4246	// There is 5 types of error depending on the requester
4247	{
4248	if (m_dreq.valid) m_cost_data_miss_frz++;
4249
4250	// send cleanup victim request
4251	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4252	{
4253	r_dcache_cc_send_req = true;
4254	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4255	r_dcache_cc_send_way = r_dcache_miss_way;
4256	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4257	r_dcache_cleanup_victim_req = false;
4258	}
4259
4260	// coherence clack request (from DSPIN CLACK)
4261	if (r_dcache_clack_req.read())
4262	{
4263	r_dcache_fsm = DCACHE_CC_CHECK;
4264	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4265	break;
4266	}
4267
4268	// coherence request (from CC_RECEIVE FSM)
4269	if (r_cc_receive_dcache_req.read() and
4270	not r_dcache_cc_send_req.read() and
4271	not r_dcache_cleanup_victim_req.read())
4272	{
4273	r_dcache_fsm = DCACHE_CC_CHECK;
4274	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4275	break;
4276	}
4277
4278	// increment MISS watchdog timer for black-hole detection
4279	r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1;
4280	if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) {
4281	r_mmu_detr = MMU_READ_DATA_TIMEOUT;
4282	r_mmu_dbvar = r_dcache_save_vaddr.read();
4283	m_drsp.valid = true;
4284	m_drsp.error = true;
4285	r_dcache_fsm = DCACHE_IDLE;
4286	break;
4287	}
4288
4289	if (r_vci_rsp_data_error.read()) // bus error
4290	{
4291	switch (r_dcache_miss_type.read())
4292	{
4293	case PROC_MISS:
4294	{
4295	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4296	r_mmu_dbvar = r_dcache_save_vaddr.read();
4297	m_drsp.valid = true;
4298	m_drsp.error = true;
4299	r_dcache_fsm = DCACHE_IDLE;
4300	break;
4301	}
4302	case PTE1_MISS:
4303	{
4304	if (r_dcache_tlb_ins.read())
4305	{
4306	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4307	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4308	r_icache_tlb_miss_req = false;
4309	r_icache_tlb_rsp_error = true;
4310	}
4311	else
4312	{
4313	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4314	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4315	m_drsp.valid = true;
4316	m_drsp.error = true;
4317	}
4318	r_dcache_fsm = DCACHE_IDLE;
4319	break;
4320	}
4321	case PTE2_MISS:
4322	{
4323	if (r_dcache_tlb_ins.read())
4324	{
4325	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4326	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4327	r_icache_tlb_miss_req = false;
4328	r_icache_tlb_rsp_error = true;
4329	}
4330	else
4331	{
4332	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4333	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4334	m_drsp.valid = true;
4335	m_drsp.error = true;
4336	}
4337	r_dcache_fsm = DCACHE_IDLE;
4338	break;
4339	}
4340	} // end switch type
4341	r_vci_rsp_data_error = false;
4342	}
4343	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4344	{
4345	r_dcache_miss_word = 0;
4346	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4347	}
4348	break;
4349	}
4350	//////////////////////////
4351	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4352	{
4353	if (m_dreq.valid) m_cost_data_miss_frz++;
4354
4355	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4356	{
4357	#ifdef INSTRUMENTATION
4358	m_cpt_dcache_data_write++;
4359	#endif
4360	r_dcache.write(r_dcache_miss_way.read(),
4361	r_dcache_miss_set.read(),
4362	r_dcache_miss_word.read(),
4363	r_vci_rsp_fifo_dcache.read());
4364	#if DEBUG_DCACHE
4365	if (m_debug_dcache_fsm)
4366	{
4367	std::cout << " <PROC " << name()
4368	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4369	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4370	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4371	<< " / SET = " << r_dcache_miss_set.read()
4372	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4373	}
4374	#endif
4375	vci_rsp_fifo_dcache_get = true;
4376	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4377
4378	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4379	{
4380	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4381	}
4382	}
4383	break;
4384	}
4385	//////////////////////////
4386	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4387	// and the cleanup ack has not been received,
4388	// as indicated by the r_dcache_miss clack.
4389	// - If no matching coherence request (r_dcache_inval_miss)
4390	// switch directory slot to VALID state.
4391	// - If matching coherence request, switch directory slot
4392	// to ZOMBI state, and send a cleanup request.
4393	{
4394	if (m_dreq.valid) m_cost_data_miss_frz++;
4395
4396	// send cleanup victim request
4397	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4398	{
4399	r_dcache_cc_send_req = true;
4400	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4401	r_dcache_cc_send_way = r_dcache_miss_way;
4402	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4403	r_dcache_cleanup_victim_req = false;
4404	}
4405
4406	// coherence clack request (from DSPIN CLACK)
4407	if (r_dcache_clack_req.read())
4408	{
4409	r_dcache_fsm = DCACHE_CC_CHECK;
4410	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4411	break;
4412	}
4413
4414	// coherence request (from CC_RECEIVE FSM)
4415	if (r_cc_receive_dcache_req.read() and
4416	not r_dcache_cc_send_req.read() and
4417	not r_dcache_cleanup_victim_req.read())
4418	{
4419	r_dcache_fsm = DCACHE_CC_CHECK;
4420	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4421	break;
4422	}
4423
4424	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4425	{
4426	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4427	{
4428	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4429	{
4430	r_dcache_miss_inval = false;
4431	// request cleanup
4432	r_dcache_cc_send_req = true;
4433	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4434	r_dcache_cc_send_way = r_dcache_miss_way.read();
4435	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4436
4437	#ifdef INSTRUMENTATION
4438	m_cpt_dcache_dir_write++;
4439	#endif
4440	r_dcache.write_dir( r_dcache_save_paddr.read(),
4441	r_dcache_miss_way.read(),
4442	r_dcache_miss_set.read(),
4443	CACHE_SLOT_STATE_ZOMBI );
4444	#if DEBUG_DCACHE
4445	if (m_debug_dcache_fsm)
4446	std::cout << " <PROC " << name()
4447	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4448	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4449	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4450	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4451	#endif
4452	}
4453	else
4454	break;
4455	}
4456	else // switch slot to VALID state
4457	{
4458
4459	#ifdef INSTRUMENTATION
4460	m_cpt_dcache_dir_write++;
4461	#endif
4462	r_dcache.write_dir(r_dcache_save_paddr.read(),
4463	r_dcache_miss_way.read(),
4464	r_dcache_miss_set.read(),
4465	CACHE_SLOT_STATE_VALID);
4466
4467	#if DEBUG_DCACHE
4468	if (m_debug_dcache_fsm)
4469	std::cout << " <PROC " << name()
4470	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4471	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4472	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4473	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4474	#endif
4475	// reset directory extension
4476	size_t way = r_dcache_miss_way.read();
4477	size_t set = r_dcache_miss_set.read();
4478	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4479	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4480	}
4481	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4482	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4483	else r_dcache_fsm = DCACHE_IDLE;
4484	}
4485	break;
4486	}
4487	/////////////////////
4488	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4489	{
4490	// coherence clack request (from DSPIN CLACK)
4491	if (r_dcache_clack_req.read())
4492	{
4493	r_dcache_fsm = DCACHE_CC_CHECK;
4494	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4495	break;
4496	}
4497
4498	// coherence request (from CC_RECEIVE FSM)
4499	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4500	{
4501	r_dcache_fsm = DCACHE_CC_CHECK;
4502	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4503	break;
4504	}
4505
4506	if (r_vci_rsp_data_error.read()) // bus error
4507	{
4508	if (r_dcache_vci_unc_write.read())
4509	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4510	else
4511	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4512
4513	r_mmu_dbvar = m_dreq.addr;
4514	r_vci_rsp_data_error = false;
4515	m_drsp.error = true;
4516	m_drsp.valid = true;
4517	r_dcache_fsm = DCACHE_IDLE;
4518	break;
4519	}
4520	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4521	{
4522	// consume data
4523	vci_rsp_fifo_dcache_get = true;
4524	r_dcache_fsm = DCACHE_IDLE;
4525
4526	// acknowledge the processor request if it has not been modified
4527	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4528	{
4529	m_drsp.valid = true;
4530	m_drsp.error = false;
4531	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4532	}
4533	}
4534	break;
4535	}
4536	/////////////////////
4537	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4538	{
4539	// coherence clack request (from DSPIN CLACK)
4540	if (r_dcache_clack_req.read())
4541	{
4542	r_dcache_fsm = DCACHE_CC_CHECK;
4543	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4544	break;
4545	}
4546
4547	// coherence request (from CC_RECEIVE FSM)
4548	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4549	{
4550	r_dcache_fsm = DCACHE_CC_CHECK;
4551	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4552	break;
4553	}
4554
4555	if (r_vci_rsp_data_error.read()) // bus error
4556	{
4557	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4558	r_mmu_dbvar = m_dreq.addr;
4559	r_vci_rsp_data_error = false;
4560	m_drsp.error = true;
4561	m_drsp.valid = true;
4562	r_dcache_fsm = DCACHE_IDLE;
4563	break;
4564	}
4565	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4566	{
4567	// consume data
4568	vci_rsp_fifo_dcache_get = true;
4569
4570	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4571	{
4572	// set key value in llsc reservation buffer
4573	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4574	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4575	}
4576	else // last flit
4577	{
4578	// acknowledge the processor request if it has not been modified
4579	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4580	{
4581	m_drsp.valid = true;
4582	m_drsp.error = false;
4583	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4584	}
4585	r_dcache_fsm = DCACHE_IDLE;
4586	}
4587	}
4588	break;
4589	}
4590	////////////////////
4591	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4592	{
4593	// coherence clack request (from DSPIN CLACK)
4594	if (r_dcache_clack_req.read())
4595	{
4596	r_dcache_fsm = DCACHE_CC_CHECK;
4597	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4598	break;
4599	}
4600
4601	// coherence request (from CC_RECEIVE FSM)
4602	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4603	{
4604	r_dcache_fsm = DCACHE_CC_CHECK;
4605	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4606	break;
4607	}
4608
4609	if (r_vci_rsp_data_error.read()) // bus error
4610	{
4611	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4612	r_mmu_dbvar = m_dreq.addr;
4613	r_vci_rsp_data_error = false;
4614	m_drsp.error = true;
4615	m_drsp.valid = true;
4616	r_dcache_fsm = DCACHE_IDLE;
4617	break;
4618	}
4619	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4620	{
4621	// consume response
4622	vci_rsp_fifo_dcache_get = true;
4623	m_drsp.valid = true;
4624	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4625	r_dcache_fsm = DCACHE_IDLE;
4626	}
4627	break;
4628	}
4629	//////////////////////////
4630	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4631	// before handling a processor WRITE or SC request
4632	// Input argument is r_dcache_dirty_paddr
4633	// In this first state, we get PTE value in dcache
4634	// and post a CAS request to CMD FSM
4635	{
4636	// get PTE in dcache
4637	uint32_t pte;
4638	size_t way;
4639	size_t set;
4640	size_t word; // unused
4641	int state;
4642
4643	#ifdef INSTRUMENTATION
4644	m_cpt_dcache_data_read++;
4645	m_cpt_dcache_dir_read++;
4646	#endif
4647	r_dcache.read(r_dcache_dirty_paddr.read(),
4648	&pte,
4649	&way,
4650	&set,
4651	&word,
4652	&state);
4653
4654	assert( (state == CACHE_SLOT_STATE_VALID) and
4655	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4656
4657	// request CAS transaction to CMD_FSM
4658	r_dcache_dirty_way = way;
4659	r_dcache_dirty_set = set;
4660
4661	// check llsc reservation buffer
4662	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4663	r_dcache_llsc_valid = false;
4664
4665	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4666	r_dcache_vci_cas_req = true;
4667	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4668	r_dcache_vci_cas_old = pte;
4669	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4670	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4671
4672	#if DEBUG_DCACHE
4673	if (m_debug_dcache_fsm)
4674	{
4675	std::cout << " <PROC " << name()
4676	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4677	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4678	<< " / PTE_VALUE = " << pte << std::dec
4679	<< " / SET = " << set
4680	<< " / WAY = " << way << std::endl;
4681	}
4682	#endif
4683	break;
4684	}
4685	///////////////////////
4686	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4687	// and return to IDLE state when response is received.
4688	// we don't care if the CAS is a failure:
4689	// - if the CAS is a success, the coherence mechanism
4690	// updates the local copy.
4691	// - if the CAS is a failure, we just retry the write.
4692	{
4693	// coherence clack request (from DSPIN CLACK)
4694	if (r_dcache_clack_req.read())
4695	{
4696	r_dcache_fsm = DCACHE_CC_CHECK;
4697	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4698	break;
4699	}
4700
4701	// coherence request (from CC_RECEIVE FSM)
4702	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4703	{
4704	r_dcache_fsm = DCACHE_CC_CHECK;
4705	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4706	break;
4707	}
4708
4709	if (r_vci_rsp_data_error.read()) // bus error
4710	{
4711	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4712	std::cout << "This should not happen in this state" << std::endl;
4713	exit(0);
4714	}
4715	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4716	{
4717	vci_rsp_fifo_dcache_get = true;
4718	r_dcache_fsm = DCACHE_IDLE;
4719
4720	#if DEBUG_DCACHE
4721	if (m_debug_dcache_fsm)
4722	{
4723	std::cout << " <PROC " << name()
4724	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4725	}
4726	#endif
4727	}
4728	break;
4729	}
4730	/////////////////////
4731	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4732	// handling coherence requests for DCACHE.
4733	// If there is a matching pending miss on the modified cache
4734	// line this is signaled in the r_dcache_miss inval flip-flop.
4735	// If the updated (or invalidated) cache line has copies in TLBs
4736	// these TLB copies are invalidated.
4737	// The return state is defined in r_dcache_fsm_cc_save
4738	{
4739	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4740	paddr_t mask = ~((m_dcache_words << 2) - 1);
4741
4742	// CLACK handler
4743	// We switch the directory slot to EMPTY state and reset
4744	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4745	if (r_dcache_clack_req.read())
4746	{
4747	if (m_dreq.valid ) m_cost_data_miss_frz++;
4748
4749	#ifdef INSTRUMENTATION
4750	m_cpt_dcache_dir_write++;
4751	#endif
4752	r_dcache.write_dir(0,
4753	r_dcache_clack_way.read(),
4754	r_dcache_clack_set.read(),
4755	CACHE_SLOT_STATE_EMPTY);
4756
4757	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4758	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4759	{
4760	r_dcache_miss_clack = false;
4761	}
4762
4763	r_dcache_clack_req = false;
4764
4765	// return to cc_save state
4766	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4767
4768	#if DEBUG_DCACHE
4769	if (m_debug_dcache_fsm)
4770	{
4771	std::cout << " <PROC " << name()
4772	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4773	<< " Switch slot to EMPTY state : "
4774	<< " set = " << r_dcache_clack_set.read()
4775	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4776	}
4777	#endif
4778	break;
4779	}
4780
4781	assert(not r_dcache_cc_send_req.read() and
4782	"CC_SEND must be available in DCACHE_CC_CHECK");
4783
4784	// Match between MISS address and CC address
4785	if (r_cc_receive_dcache_req.read() and
4786	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4787	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4788	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4789	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4790	{
4791	// signaling matching
4792	r_dcache_miss_inval = true;
4793
4794	// in case of update, go to CC_UPDT
4795	// JUST TO POP THE FIFO
4796	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4797	{
4798	r_dcache_fsm = DCACHE_CC_UPDT;
4799	r_dcache_cc_word = r_cc_receive_word_idx.read();
4800
4801	// just pop the fifo , don't write in icache
4802	r_dcache_cc_need_write = false;
4803	}
4804	// the request is dealt with
4805	else
4806	{
4807	r_cc_receive_dcache_req = false;
4808	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4809	}
4810
4811	#if DEBUG_DCACHE
4812	if (m_debug_dcache_fsm)
4813	{
4814	std::cout << " <PROC " << name()
4815	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4816	<< " PADDR = " << std::hex << paddr << std::endl;
4817	}
4818	#endif
4819	}
4820
4821	// CC request handler
4822
4823	int state = 0;
4824	size_t way = 0;
4825	size_t set = 0;
4826	size_t word = 0;
4827
4828	#ifdef INSTRUMENTATION
4829	m_cpt_dcache_dir_read++;
4830	#endif
4831	r_dcache.read_dir(paddr,
4832	&state,
4833	&way,
4834	&set,
4835	&word); // unused
4836
4837	r_dcache_cc_way = way;
4838	r_dcache_cc_set = set;
4839
4840	if (state == CACHE_SLOT_STATE_VALID) // hit
4841	{
4842	// need to update the cache state
4843	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4844	{
4845	r_dcache_cc_need_write = true;
4846	r_dcache_fsm = DCACHE_CC_UPDT;
4847	r_dcache_cc_word = r_cc_receive_word_idx.read();
4848	}
4849	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4850	{
4851	r_dcache_fsm = DCACHE_CC_INVAL;
4852	}
4853	}
4854	else // miss
4855	{
4856	// multicast acknowledgement required in case of update
4857	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4858	{
4859	r_dcache_fsm = DCACHE_CC_UPDT;
4860	r_dcache_cc_word = r_cc_receive_word_idx.read();
4861
4862	// just pop the fifo , don't write in icache
4863	r_dcache_cc_need_write = false;
4864	}
4865	else // No response needed
4866	{
4867	r_cc_receive_dcache_req = false;
4868	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4869	}
4870	}
4871
4872	#if DEBUG_DCACHE
4873	if (m_debug_dcache_fsm)
4874	{
4875	std::cout << " <PROC " << name()
4876	<< " DCACHE_CC_CHECK> Coherence request received:"
4877	<< " PADDR = " << std::hex << paddr
4878	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4879	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4880	}
4881	#endif
4882
4883	break;
4884	}
4885	/////////////////////
4886	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4887	// CLEANUP after possible invalidation of copies in
4888	// TLBs
4889	{
4890	size_t way = r_dcache_cc_way.read();
4891	size_t set = r_dcache_cc_set.read();
4892
4893	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4894	{
4895	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4896	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4897	r_dcache_tlb_inval_set = 0;
4898	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4899	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4900	break;
4901	}
4902
4903	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4904	{
4905	r_itlb.reset();
4906	r_dtlb.reset();
4907	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4908
4909	#if DEBUG_DCACHE
4910	if (m_debug_dcache_fsm)
4911	{
4912	std::cout << " <PROC " << name()
4913	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4914	}
4915	#endif
4916	}
4917
4918	assert(not r_dcache_cc_send_req.read() &&
4919	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4920	"must not be set");
4921
4922	// Switch slot state to ZOMBI and send CLEANUP command
4923	r_dcache.write_dir(way,
4924	set,
4925	CACHE_SLOT_STATE_ZOMBI);
4926
4927	// coherence request completed
4928	r_cc_receive_dcache_req = false;
4929	r_dcache_cc_send_req = true;
4930	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4931	r_dcache_cc_send_way = r_dcache_cc_way.read();
4932	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4933	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4934
4935	#if DEBUG_DCACHE
4936	if (m_debug_dcache_fsm)
4937	{
4938	std::cout << " <PROC " << name()
4939	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4940	<< " / WAY = " << way
4941	<< " / SET = " << set << std::endl;
4942	}
4943	#endif
4944	break;
4945	}
4946	///////////////////
4947	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4948	// after possible invalidation of copies in TLBs
4949	{
4950	size_t word = r_dcache_cc_word.read();
4951	size_t way = r_dcache_cc_way.read();
4952	size_t set = r_dcache_cc_set.read();
4953
4954	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4955	{
4956	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4957	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4958	r_dcache_tlb_inval_set = 0;
4959	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4960	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4961
4962	break;
4963	}
4964
4965	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4966	{
4967	r_itlb.reset();
4968	r_dtlb.reset();
4969	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4970
4971	#if DEBUG_DCACHE
4972	if (m_debug_dcache_fsm)
4973	{
4974	std::cout << " <PROC " << name()
4975	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4976	}
4977	#endif
4978	}
4979
4980	assert (not r_dcache_cc_send_req.read() &&
4981	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4982	"must not be set");
4983
4984	if (not r_cc_receive_updt_fifo_be.rok()) break;
4985
4986	if (r_dcache_cc_need_write.read())
4987	{
4988
4989	#ifdef INSTRUMENTATION
4990	m_cpt_dcache_data_write++;
4991	#endif
4992	r_dcache.write(way,
4993	set,
4994	word,
4995	r_cc_receive_updt_fifo_data.read(),
4996	r_cc_receive_updt_fifo_be.read());
4997
4998	r_dcache_cc_word = word + 1;
4999
5000	#if DEBUG_DCACHE
5001	if (m_debug_dcache_fsm)
5002	{
5003	std::cout << " <PROC " << name()
5004	<< " DCACHE_CC_UPDT> Write one word" << std::dec
5005	<< " / WAY = " << way
5006	<< " / SET = " << set
5007	<< " / WORD = " << word
5008	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
5009	}
5010	#endif
5011	}
5012
5013	if (r_cc_receive_updt_fifo_eop.read()) // last word
5014	{
5015	// no need to write in the cache anymore
5016	r_dcache_cc_need_write = false;
5017
5018	// coherence request completed
5019	r_cc_receive_dcache_req = false;
5020
5021	// request multicast acknowledgement
5022	r_dcache_cc_send_req = true;
5023	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5024	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5025	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5026	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5027	}
5028
5029	//consume fifo if not eop
5030	cc_receive_updt_fifo_get = true;
5031
5032	break;
5033	}
5034	///////////////////////////
5035	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5036	// It makes assumption: m_itlb_sets == m_dtlb_sets
5037	// All ways are handled in parallel.
5038	// We enter this state when a DCACHE line is modified,
5039	// and there is a copy in itlb or dtlb.
5040	// It can be caused by:
5041	// - a coherence inval or updt transaction,
5042	// - a line inval caused by a cache miss
5043	// - a processor XTN inval request,
5044	// - a WRITE hit,
5045	// - a Dirty bit update
5046	// Input arguments are:
5047	// - r_dcache_tlb_inval_line
5048	// - r_dcache_tlb_inval_set
5049	// - r_dcache_fsm_scan_save
5050	{
5051	paddr_t line = r_dcache_tlb_inval_line.read();
5052	size_t set = r_dcache_tlb_inval_set.read();
5053	size_t way;
5054	bool ok;
5055
5056	for (way = 0; way < m_itlb_ways; way++)
5057	{
5058	ok = r_itlb.inval(line, way, set);
5059
5060	#if DEBUG_DCACHE
5061	if (m_debug_dcache_fsm and ok)
5062	{
5063	std::cout << " <PROC " << name()
5064	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5065	<< " line = " << line << std::dec
5066	<< " / set = " << set
5067	<< " / way = " << way << std::endl;
5068	}
5069	#endif
5070	}
5071
5072	for (way = 0; way < m_dtlb_ways; way++)
5073	{
5074	ok = r_dtlb.inval( line, way, set);
5075
5076	#if DEBUG_DCACHE
5077	if (m_debug_dcache_fsm and ok)
5078	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5079	<< " Invalidate DTLB entry" << std::hex
5080	<< " / line = " << line << std::dec
5081	<< " / set = " << set
5082	<< " / way = " << way << std::endl;
5083	#endif
5084	}
5085
5086	// return to the calling state when TLB inval completed
5087	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5088	{
5089	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5090	}
5091	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5092	break;
5093	}
5094	} // end switch r_dcache_fsm
5095
5096	///////////////// wbuf update ///////////////////////////////////////////////////////
5097	r_wbuf.update();
5098
5099	///////////////// llsc update ///////////////////////////////////////////////////////
5100	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5101	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5102
5103	//////////////// test processor frozen //////////////////////////////////////////////
5104	// The simulation exit if the number of consecutive frozen cycles
5105	// is larger than the m_max_frozen_cycles (constructor parameter)
5106	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5107	{
5108	m_cpt_frz_cycles++; // used for instrumentation
5109	m_cpt_stop_simulation++; // used for debug
5110	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5111	{
5112	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5113	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5114	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5115	<< std::endl;
5116	r_iss.dump();
5117	exit(1);
5118	}
5119	}
5120	else
5121	{
5122	m_cpt_stop_simulation = 0;
5123	}
5124
5125	/////////// execute one iss cycle /////////////////////////////////
5126	{
5127	uint32_t it = 0;
5128	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5129	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5130	}
5131
5132	////////////////////////////////////////////////////////////////////////////
5133	// The VCI_CMD FSM controls the following ressources:
5134	// - r_vci_cmd_fsm
5135	// - r_vci_cmd_min
5136	// - r_vci_cmd_max
5137	// - r_vci_cmd_cpt
5138	// - r_vci_cmd_imiss_prio
5139	// - wbuf (reset)
5140	// - r_icache_miss_req (reset)
5141	// - r_icache_unc_req (reset)
5142	// - r_dcache_vci_miss_req (reset)
5143	// - r_dcache_vci_unc_req (reset)
5144	// - r_dcache_vci_ll_req (reset)
5145	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5146	// - r_dcache_vci_cas_req (reset)
5147	//
5148	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5149	// There are 8 request types, with the following priorities :
5150	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5151	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5152	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5153	// 4 - Instruction Uncachable : r_icache_unc_req
5154	// 5 - Data Write : r_wbuf.rok()
5155	// 6 - Data Linked Load : r_dcache_vci_ll_req
5156	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5157	// 8 - Compare And Swap : r_dcache_vci_cas_req
5158	//
5159	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5160	// and the VCI_RSP_FSM are fully desynchronized.
5161	//
5162	// VCI formats:
5163	// According to the VCI advanced specification, all read requests packets
5164	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5165	// are one word packets.
5166	// For write burst packets, all words are in the same cache line,
5167	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5168	// The sc command packet implements actually a compare-and-swap mechanism
5169	// and the packet contains two flits.
5170	////////////////////////////////////////////////////////////////////////////////////
5171
5172
5173	switch (r_vci_cmd_fsm.read())
5174	{
5175	//////////////
5176	case CMD_IDLE:
5177	{
5178	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5179	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5180	// to check a possible pending write on the same cache line.
5181	// As there is only one possible access per cycle to write buffer, we implement
5182	// a round-robin priority between DCACHE and ICACHE for this access,
5183	// using the r_vci_cmd_imiss_prio flip-flop.
5184
5185	size_t wbuf_min;
5186	size_t wbuf_max;
5187
5188	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5189	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5190
5191	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5192	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5193
5194	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5195	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5196
5197	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5198	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5199
5200	bool icache_miss_req = r_icache_miss_req.read() and
5201	(not (r_dcache_vci_miss_req.read() or
5202	r_dcache_vci_ll_req.read() or
5203	r_dcache_vci_cas_req.read() or
5204	r_dcache_vci_sc_req.read()) or
5205	r_vci_cmd_imiss_prio.read());
5206
5207	// 1 - Data unc write
5208	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5209	{
5210	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5211	r_dcache_vci_unc_req = false;
5212	}
5213	// 2 data read miss
5214	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5215	{
5216	r_vci_cmd_fsm = CMD_DATA_MISS;
5217	r_dcache_vci_miss_req = false;
5218	r_vci_cmd_imiss_prio = true;
5219	}
5220	// 3 - Data Read Uncachable
5221	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5222	{
5223	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5224	r_dcache_vci_unc_req = false;
5225	}
5226	// 4 - Data Linked Load
5227	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5228	{
5229	r_vci_cmd_fsm = CMD_DATA_LL;
5230	r_dcache_vci_ll_req = false;
5231	r_vci_cmd_imiss_prio = true;
5232	}
5233	// 5 - Instruction Miss
5234	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5235	{
5236	r_vci_cmd_fsm = CMD_INS_MISS;
5237	r_icache_miss_req = false;
5238	r_vci_cmd_imiss_prio = false;
5239	}
5240	// 6 - Instruction Uncachable
5241	else if (r_icache_unc_req.read())
5242	{
5243	r_vci_cmd_fsm = CMD_INS_UNC;
5244	r_icache_unc_req = false;
5245	}
5246	// 7 - Data Write
5247	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5248	{
5249	r_vci_cmd_fsm = CMD_DATA_WRITE;
5250	r_vci_cmd_cpt = wbuf_min;
5251	r_vci_cmd_min = wbuf_min;
5252	r_vci_cmd_max = wbuf_max;
5253	}
5254	// 8 - Data Store Conditionnal
5255	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5256	{
5257	r_vci_cmd_fsm = CMD_DATA_SC;
5258	r_dcache_vci_sc_req = false;
5259	r_vci_cmd_imiss_prio = true;
5260	r_vci_cmd_cpt = 0;
5261	}
5262	// 9 - Compare And Swap
5263	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5264	{
5265	r_vci_cmd_fsm = CMD_DATA_CAS;
5266	r_dcache_vci_cas_req = false;
5267	r_vci_cmd_imiss_prio = true;
5268	r_vci_cmd_cpt = 0;
5269	}
5270
5271	#if DEBUG_CMD
5272	if (m_debug_cmd_fsm )
5273	{
5274	std::cout << " <PROC " << name() << " CMD_IDLE>"
5275	<< " / dmiss_req = " << dcache_miss_req
5276	<< " / imiss_req = " << icache_miss_req
5277	<< std::endl;
5278	}
5279	#endif
5280	break;
5281	}
5282	////////////////////
5283	case CMD_DATA_WRITE:
5284	{
5285	if (p_vci.cmdack.read())
5286	{
5287	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5288	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5289	{
5290	r_vci_cmd_fsm = CMD_IDLE;
5291	r_wbuf.sent();
5292	}
5293	}
5294	break;
5295	}
5296	/////////////////
5297	case CMD_DATA_SC:
5298	case CMD_DATA_CAS:
5299	{
5300	// The CAS and SC VCI commands contain two flits
5301	if (p_vci.cmdack.read())
5302	{
5303	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5304	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5305	}
5306	break;
5307	}
5308	//////////////////
5309	case CMD_INS_MISS:
5310	case CMD_INS_UNC:
5311	case CMD_DATA_MISS:
5312	case CMD_DATA_UNC_READ:
5313	case CMD_DATA_UNC_WRITE:
5314	case CMD_DATA_LL:
5315	{
5316	// all read VCI commands contain one single flit
5317	if (p_vci.cmdack.read()) {
5318	r_vci_cmd_fsm = CMD_IDLE;
5319	}
5320	break;
5321	}
5322
5323	} // end switch r_vci_cmd_fsm
5324
5325	//////////////////////////////////////////////////////////////////////////
5326	// The VCI_RSP FSM controls the following ressources:
5327	// - r_vci_rsp_fsm:
5328	// - r_vci_rsp_fifo_icache (push)
5329	// - r_vci_rsp_fifo_dcache (push)
5330	// - r_vci_rsp_data_error (set)
5331	// - r_vci_rsp_ins_error (set)
5332	// - r_vci_rsp_cpt
5333	// - r_dcache_vci_sc_req (reset when SC response recieved)
5334	//
5335	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5336	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5337	// to identify the transactions.
5338	//
5339	// VCI vormat:
5340	// This component checks the response packet length and accepts only
5341	// single word packets for write response packets.
5342	//
5343	// Error handling:
5344	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5345	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5346	// flip_flop and the error is signaled by the DCACHE FSM.
5347	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5348	// flip_flop and the error is signaled by the ICACHE FSM.
5349	// In case of Cleanup Error, the simulation stops with an error message...
5350	//////////////////////////////////////////////////////////////////////////
5351
5352	switch (r_vci_rsp_fsm.read())
5353	{
5354	//////////////
5355	case RSP_IDLE:
5356	{
5357	if (p_vci.rspval.read())
5358	{
5359	r_vci_rsp_cpt = 0;
5360
5361	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5362	{
5363	r_vci_rsp_fsm = RSP_DATA_UNC;
5364	}
5365	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5366	{
5367	r_vci_rsp_fsm = RSP_DATA_MISS;
5368	}
5369	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5370	{
5371	r_vci_rsp_fsm = RSP_INS_UNC;
5372	}
5373	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5374	{
5375	r_vci_rsp_fsm = RSP_INS_MISS;
5376	}
5377	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5378	{
5379	r_vci_rsp_fsm = RSP_DATA_WRITE;
5380	}
5381	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5382	{
5383	r_vci_rsp_fsm = RSP_DATA_UNC;
5384	}
5385	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5386	{
5387	r_vci_rsp_fsm = RSP_DATA_LL;
5388	}
5389	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5390	{
5391	r_vci_rsp_fsm = RSP_DATA_UNC;
5392	}
5393	else
5394	{
5395	assert(false and "Unexpected VCI response");
5396	}
5397	}
5398	break;
5399	}
5400	//////////////////
5401	case RSP_INS_MISS:
5402	{
5403	if (p_vci.rspval.read())
5404	{
5405	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5406	{
5407	r_vci_rsp_ins_error = true;
5408	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5409	}
5410	else // no error reported
5411	{
5412	if (r_vci_rsp_fifo_icache.wok())
5413	{
5414	if (r_vci_rsp_cpt.read() >= m_icache_words)
5415	{
5416	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5417	<< " VCI response packet too long "
5418	<< " for instruction miss" << std::endl;
5419	exit(0);
5420	}
5421	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5422	vci_rsp_fifo_icache_put = true,
5423	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5424	if (p_vci.reop.read())
5425	{
5426	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5427	{
5428	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5429	<< " VCI response packet too short"
5430	<< " for instruction miss" << std::endl;
5431	exit(0);
5432	}
5433	r_vci_rsp_fsm = RSP_IDLE;
5434	}
5435	}
5436	}
5437	}
5438	break;
5439	}
5440	/////////////////
5441	case RSP_INS_UNC:
5442	{
5443	if (p_vci.rspval.read())
5444	{
5445	assert(p_vci.reop.read() and
5446	"illegal VCI response packet for uncachable instruction");
5447
5448	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5449	{
5450	r_vci_rsp_ins_error = true;
5451	r_vci_rsp_fsm = RSP_IDLE;
5452	}
5453	else // no error reported
5454	{
5455	if (r_vci_rsp_fifo_icache.wok())
5456	{
5457	vci_rsp_fifo_icache_put = true;
5458	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5459	r_vci_rsp_fsm = RSP_IDLE;
5460	}
5461	}
5462	}
5463	break;
5464	}
5465	///////////////////
5466	case RSP_DATA_MISS:
5467	{
5468	if (p_vci.rspval.read())
5469	{
5470	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5471	{
5472	r_vci_rsp_data_error = true;
5473	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5474	}
5475	else // no error reported
5476	{
5477	if (r_vci_rsp_fifo_dcache.wok())
5478	{
5479	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5480	"The VCI response packet for data miss is too long");
5481
5482	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5483	vci_rsp_fifo_dcache_put = true,
5484	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5485	if (p_vci.reop.read())
5486	{
5487	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5488	"The VCI response packet for data miss is too short");
5489
5490	r_vci_rsp_fsm = RSP_IDLE;
5491	}
5492	}
5493	}
5494	}
5495	break;
5496	}
5497	//////////////////
5498	case RSP_DATA_UNC:
5499	{
5500	if (p_vci.rspval.read())
5501	{
5502	assert(p_vci.reop.read() and
5503	"illegal VCI response packet for uncachable read data");
5504
5505	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5506	{
5507	r_vci_rsp_data_error = true;
5508	r_vci_rsp_fsm = RSP_IDLE;
5509	}
5510	else // no error reported
5511	{
5512	if (r_vci_rsp_fifo_dcache.wok())
5513	{
5514	vci_rsp_fifo_dcache_put = true;
5515	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5516	r_vci_rsp_fsm = RSP_IDLE;
5517	}
5518	}
5519	}
5520	break;
5521	}
5522	/////////////////
5523	case RSP_DATA_LL:
5524	{
5525	if (p_vci.rspval.read())
5526	{
5527	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5528	{
5529	r_vci_rsp_data_error = true;
5530	r_vci_rsp_fsm = RSP_IDLE;
5531	break;
5532	}
5533	if (r_vci_rsp_cpt.read() == 0) //first flit
5534	{
5535	if (r_vci_rsp_fifo_dcache.wok())
5536	{
5537	assert(!p_vci.reop.read() &&
5538	"illegal VCI response packet for LL");
5539	vci_rsp_fifo_dcache_put = true;
5540	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5541	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5542	}
5543	break;
5544	}
5545	else // last flit
5546	{
5547	if (r_vci_rsp_fifo_dcache.wok())
5548	{
5549	assert(p_vci.reop.read() &&
5550	"illegal VCI response packet for LL");
5551	vci_rsp_fifo_dcache_put = true;
5552	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5553	r_vci_rsp_fsm = RSP_IDLE;
5554	}
5555	break;
5556	}
5557	}
5558	break;
5559	}
5560	////////////////////
5561	case RSP_DATA_WRITE:
5562	{
5563	if (p_vci.rspval.read())
5564	{
5565	assert(p_vci.reop.read() and
5566	"a VCI response packet must contain one flit for a write transaction");
5567
5568	r_vci_rsp_fsm = RSP_IDLE;
5569	uint32_t wbuf_index = p_vci.rtrdid.read();
5570	r_wbuf.completed(wbuf_index);
5571	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5572	}
5573	break;
5574	}
5575	} // end switch r_vci_rsp_fsm
5576
5577	/////////////////////////////////////////////////////////////////////////////////////
5578	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5579	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5580	// and ICACHE FSM) that are served with a round-robin priority.
5581	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5582	// soon as the request has been sent.
5583	/////////////////////////////////////////////////////////////////////////////////////
5584	switch (r_cc_send_fsm.read())
5585	{
5586	///////////////////////////
5587	case CC_SEND_IDLE:
5588	{
5589	///////////////////////////////////////////////////////
5590	// handling round robin between icache and dcache : //
5591	// we first check for the last client and listen for //
5592	// a request of the other, then update the client //
5593	// r_cc_send_last_client : 0 dcache / 1 icache
5594	///////////////////////////////////////////////////////
5595	bool update_last_client = r_cc_send_last_client.read();
5596	if (r_cc_send_last_client.read() == 0) // last client was dcache
5597	{
5598	if (r_icache_cc_send_req.read()) // request from icache
5599	update_last_client = 1; // update last client to icache
5600	}
5601	else // last client was icache
5602	{
5603	if (r_dcache_cc_send_req.read()) // request from dcache
5604	update_last_client = 0; // update last client to dcache
5605	}
5606	r_cc_send_last_client = update_last_client;
5607
5608	// if there is an actual request
5609	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5610	{
5611	// the new client is dcache and has a cleanup request
5612	if ((update_last_client == 0) and
5613	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5614	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5615	// the new client is dcache and has a multi acknowledgement request
5616	else if ((update_last_client == 0) and
5617	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5618	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5619	// the new client is icache and has a cleanup request
5620	else if ((update_last_client == 1) and
5621	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5622	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5623	// the new client is icache and has a multi acknowledgement request
5624	else if ((update_last_client == 1) and
5625	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5626	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5627	}
5628	break;
5629	}
5630	///////////////////////////
5631	case CC_SEND_CLEANUP_1:
5632	{
5633	// wait for the first flit to be consumed
5634	if (p_dspin_p2m.read.read())
5635	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5636
5637	break;
5638	}
5639	///////////////////////////
5640	case CC_SEND_CLEANUP_2:
5641	{
5642	// wait for the second flit to be consumed
5643	if (p_dspin_p2m.read.read())
5644	{
5645	if (r_cc_send_last_client.read() == 0) // dcache active request
5646	r_dcache_cc_send_req = false; // reset dcache request
5647	else // icache active request
5648	r_icache_cc_send_req = false; // reset icache request
5649
5650	// go back to idle state
5651	r_cc_send_fsm = CC_SEND_IDLE;
5652	}
5653	break;
5654	}
5655	///////////////////////////
5656	case CC_SEND_MULTI_ACK:
5657	{
5658	// wait for the flit to be consumed
5659	if (p_dspin_p2m.read.read())
5660	{
5661	if (r_cc_send_last_client.read() == 0) // dcache active request
5662	r_dcache_cc_send_req = false; // reset dcache request
5663	else // icache active request
5664	r_icache_cc_send_req = false; // reset icache request
5665	// go back to idle state
5666	r_cc_send_fsm = CC_SEND_IDLE;
5667	}
5668	break;
5669	}
5670	} // end switch CC_SEND FSM
5671
5672	///////////////////////////////////////////////////////////////////////////////
5673	// CC_RECEIVE FSM
5674	// This FSM receive all coherence packets on a DSPIN40 port.
5675	// There is 5 packet types:
5676	// - CC_DATA_INVAL : DCACHE invalidate request
5677	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5678	// - CC_INST_INVAL : ICACHE invalidate request
5679	// - CC_INST_UPDT : ICACHE update request (multi-words)
5680	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5681	//////////////////////////////////////////////////////////////////////////////
5682	switch (r_cc_receive_fsm.read())
5683	{
5684	/////////////////////
5685	case CC_RECEIVE_IDLE:
5686	{
5687	// a coherence request has arrived
5688	if (p_dspin_m2p.write.read())
5689	{
5690	// initialize dspin received data
5691	uint64_t receive_data = p_dspin_m2p.data.read();
5692	// initialize coherence packet type
5693	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5694	DspinDhccpParam::M2P_TYPE);
5695	// test for a broadcast
5696	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5697	{
5698	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5699	}
5700	// test for a multi updt
5701	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5702	{
5703	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5704	}
5705	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5706	{
5707	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5708	}
5709	// test for a multi inval
5710	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5711	{
5712	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5713	}
5714	else
5715	{
5716	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5717	}
5718	}
5719	break;
5720	}
5721	///////////////////////////////
5722	case CC_RECEIVE_BRDCAST_HEADER:
5723	{
5724	// no actual data in the HEADER, just skip to second flit
5725	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5726	break;
5727	}
5728	//////////////////////////////
5729	case CC_RECEIVE_BRDCAST_NLINE:
5730	{
5731	// initialize dspin received data
5732	uint64_t receive_data = p_dspin_m2p.data.read();
5733	// wait for both dcache and icache to take the request
5734	// TODO maybe we need to wait for both only to leave the state, but
5735	// not to actually post a request to an available cache => need a
5736	// flip_flop to check that ?
5737	if (not (r_cc_receive_icache_req.read()) and
5738	not (r_cc_receive_dcache_req.read()) and
5739	(p_dspin_m2p.write.read()))
5740	{
5741	// request dcache to handle the BROADCAST
5742	r_cc_receive_dcache_req = true;
5743	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5744	DspinDhccpParam::BROADCAST_NLINE);
5745	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5746	// request icache to handle the BROADCAST
5747	r_cc_receive_icache_req = true;
5748	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5749	DspinDhccpParam::BROADCAST_NLINE);
5750	r_cc_receive_icache_type = CC_TYPE_INVAL;
5751	// get back to idle state
5752	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5753	break;
5754	}
5755	// keep waiting for the caches to accept the request
5756	break;
5757	}
5758	/////////////////////////////
5759	case CC_RECEIVE_DATA_INVAL_HEADER:
5760	{
5761	// sample updt tab index in the HEADER, then skip to second flit
5762	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5763	break;
5764	}
5765	/////////////////////////////
5766	case CC_RECEIVE_INS_INVAL_HEADER:
5767	{
5768	// sample updt tab index in the HEADER, then skip to second flit
5769	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5770	break;
5771	}
5772	////////////////////////////
5773	case CC_RECEIVE_DATA_INVAL_NLINE:
5774	{
5775	// sample nline in the second flit
5776	uint64_t receive_data = p_dspin_m2p.data.read();
5777	// for data INVAL, wait for dcache to take the request
5778	if (p_dspin_m2p.write.read() and
5779	not r_cc_receive_dcache_req.read())
5780	{
5781	// request dcache to handle the INVAL
5782	r_cc_receive_dcache_req = true;
5783	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5784	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5785	// get back to idle state
5786	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5787	break;
5788	}
5789	break;
5790	}
5791	//////////////////////////////
5792	case CC_RECEIVE_INS_INVAL_NLINE:
5793	{
5794	// sample nline in the second flit
5795	uint64_t receive_data = p_dspin_m2p.data.read();
5796	// for ins INVAL, wait for icache to take the request
5797	if (p_dspin_m2p.write.read() and
5798	not r_cc_receive_icache_req.read())
5799	{
5800	// request icache to handle the INVAL
5801	r_cc_receive_icache_req = true;
5802	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5803	r_cc_receive_icache_type = CC_TYPE_INVAL;
5804	// get back to idle state
5805	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5806	break;
5807	}
5808	break;
5809	}
5810	////////////////////////////
5811	case CC_RECEIVE_DATA_UPDT_HEADER:
5812	{
5813	// sample updt tab index in the HEADER, than skip to second flit
5814	uint64_t receive_data = p_dspin_m2p.data.read();
5815	// for data INVAL, wait for dcache to take the request and fifo to
5816	// be empty
5817	if (not r_cc_receive_dcache_req.read())
5818	{
5819	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5820	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5821	break;
5822	}
5823	break;
5824	}
5825	////////////////////////////
5826	case CC_RECEIVE_INS_UPDT_HEADER:
5827	{
5828	// sample updt tab index in the HEADER, than skip to second flit
5829	uint64_t receive_data = p_dspin_m2p.data.read();
5830	// for ins INVAL, wait for icache to take the request and fifo to be
5831	// empty
5832	if (not r_cc_receive_icache_req.read())
5833	{
5834	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5835	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5836	break;
5837	}
5838	// keep waiting for the correct cache to accept the request
5839	break;
5840	}
5841	///////////////////////////
5842	case CC_RECEIVE_DATA_UPDT_NLINE:
5843	{
5844	// sample nline and word index in the second flit
5845	uint64_t receive_data = p_dspin_m2p.data.read();
5846	// for data INVAL, wait for dcache to take the request and fifo to
5847	// be empty
5848	if (r_cc_receive_updt_fifo_be.empty() and
5849	p_dspin_m2p.write.read())
5850	{
5851	r_cc_receive_dcache_req = true;
5852	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5853	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5854	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5855	// get back to idle state
5856	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5857	break;
5858	}
5859	break;
5860	}
5861	////////////////////////////
5862	case CC_RECEIVE_INS_UPDT_NLINE:
5863	{
5864	// sample nline and word index in the second flit
5865	uint64_t receive_data = p_dspin_m2p.data.read();
5866	// for ins INVAL, wait for icache to take the request and fifo to be
5867	// empty
5868	if (r_cc_receive_updt_fifo_be.empty() and
5869	p_dspin_m2p.write.read())
5870	{
5871	r_cc_receive_icache_req = true;
5872	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5873	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5874	r_cc_receive_icache_type = CC_TYPE_UPDT;
5875	// get back to idle state
5876	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5877	break;
5878	}
5879	break;
5880	}
5881	//////////////////////////
5882	case CC_RECEIVE_DATA_UPDT_DATA:
5883	{
5884	// wait for the fifo
5885	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5886	{
5887	uint64_t receive_data = p_dspin_m2p.data.read();
5888	bool receive_eop = p_dspin_m2p.eop.read();
5889	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5890	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5891	cc_receive_updt_fifo_eop = receive_eop;
5892	cc_receive_updt_fifo_put = true;
5893	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5894	}
5895	break;
5896	}
5897	//////////////////////////
5898	case CC_RECEIVE_INS_UPDT_DATA:
5899	{
5900	// wait for the fifo
5901	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5902	{
5903	uint64_t receive_data = p_dspin_m2p.data.read();
5904	bool receive_eop = p_dspin_m2p.eop.read();
5905	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5906	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5907	cc_receive_updt_fifo_eop = receive_eop;
5908	cc_receive_updt_fifo_put = true;
5909	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5910	}
5911	break;
5912	}
5913
5914	} // end switch CC_RECEIVE FSM
5915
5916	///////////////// DSPIN CLACK interface ///////////////
5917
5918	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5919	DspinDhccpParam::CLACK_TYPE);
5920
5921	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5922	DspinDhccpParam::CLACK_WAY);
5923
5924	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5925	DspinDhccpParam::CLACK_SET);
5926
5927	bool dspin_clack_get = false;
5928	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5929	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5930
5931	if (r_dspin_clack_req.read())
5932	{
5933	// CLACK DATA: Send request to DCACHE FSM
5934	if (dcache_clack_request and not r_dcache_clack_req.read())
5935	{
5936	r_dcache_clack_req = true;
5937	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
5938	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
5939	dspin_clack_get = true;
5940	}
5941
5942	// CLACK INST: Send request to ICACHE FSM
5943	else if (icache_clack_request and not r_icache_clack_req.read())
5944	{
5945	r_icache_clack_req = true;
5946	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5947	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5948	dspin_clack_get = true;
5949	}
5950	}
5951	else
5952	{
5953	dspin_clack_get = true;
5954	}
5955
5956	if (dspin_clack_get)
5957	{
5958	r_dspin_clack_req = p_dspin_clack.write.read();
5959	r_dspin_clack_flit = p_dspin_clack.data.read();
5960	}
5961
5962	///////////////// Response FIFOs update //////////////////////
5963	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5964	vci_rsp_fifo_icache_put,
5965	vci_rsp_fifo_icache_data);
5966
5967	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5968	vci_rsp_fifo_dcache_put,
5969	vci_rsp_fifo_dcache_data);
5970
5971	///////////////// updt FIFO update //////////////////////
5972	//TODO check this
5973	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5974	cc_receive_updt_fifo_put,
5975	cc_receive_updt_fifo_be);
5976	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5977	cc_receive_updt_fifo_put,
5978	cc_receive_updt_fifo_data);
5979	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5980	cc_receive_updt_fifo_put,
5981	cc_receive_updt_fifo_eop);
5982
5983	} // end transition()
5984
5985	///////////////////////
5986	tmpl(void)::genMoore()
5987	///////////////////////
5988	{
5989
5990	// VCI initiator command on the direct network
5991	// it depends on the CMD FSM state
5992
5993	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5994	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
5995
5996	p_vci.pktid = 0;
5997	p_vci.srcid = m_srcid;
5998	p_vci.cons = is_sc_or_cas;
5999	p_vci.contig = not is_sc_or_cas;
6000	p_vci.wrap = false;
6001	p_vci.clen = 0;
6002	p_vci.cfixed = false;
6003
6004	if (m_monitor_ok) {
6005	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
6006	if (((p_vci.address.read()) >= m_monitor_base) and
6007	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
6008	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6009	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6010	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6011	<< " : address = " << p_vci.address.read()
6012	<< " / be = " << p_vci.be.read();
6013	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6014	std::cout << " / data = " << p_vci.wdata.read();
6015	}
6016	std::cout << std::dec << std::endl;
6017	}
6018	}
6019	}
6020
6021	switch (r_vci_cmd_fsm.read()) {
6022
6023	case CMD_IDLE:
6024	p_vci.cmdval = false;
6025	p_vci.address = 0;
6026	p_vci.wdata = 0;
6027	p_vci.be = 0;
6028	p_vci.trdid = 0;
6029	p_vci.pktid = 0;
6030	p_vci.plen = 0;
6031	p_vci.cmd = vci_param::CMD_NOP;
6032	p_vci.eop = false;
6033	break;
6034
6035	case CMD_INS_MISS:
6036	p_vci.cmdval = true;
6037	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6038	p_vci.wdata = 0;
6039	p_vci.be = 0xF;
6040	p_vci.trdid = 0;
6041	p_vci.pktid = TYPE_READ_INS_MISS;
6042	p_vci.plen = m_icache_words << 2;
6043	p_vci.cmd = vci_param::CMD_READ;
6044	p_vci.eop = true;
6045	break;
6046
6047	case CMD_INS_UNC:
6048	p_vci.cmdval = true;
6049	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6050	p_vci.wdata = 0;
6051	p_vci.be = 0xF;
6052	p_vci.trdid = 0;
6053	p_vci.pktid = TYPE_READ_INS_UNC;
6054	p_vci.plen = 4;
6055	p_vci.cmd = vci_param::CMD_READ;
6056	p_vci.eop = true;
6057	break;
6058
6059	case CMD_DATA_MISS:
6060	p_vci.cmdval = true;
6061	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6062	p_vci.wdata = 0;
6063	p_vci.be = 0xF;
6064	p_vci.trdid = 0;
6065	p_vci.pktid = TYPE_READ_DATA_MISS;
6066	p_vci.plen = m_dcache_words << 2;
6067	p_vci.cmd = vci_param::CMD_READ;
6068	p_vci.eop = true;
6069	break;
6070
6071	case CMD_DATA_UNC_READ:
6072	p_vci.cmdval = true;
6073	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6074	p_vci.wdata = 0;
6075	p_vci.be = r_dcache_vci_unc_be.read();
6076	p_vci.trdid = 0;
6077	p_vci.pktid = TYPE_DATA_UNC;
6078	p_vci.plen = 4;
6079	p_vci.cmd = vci_param::CMD_READ;
6080	p_vci.eop = true;
6081	break;
6082
6083	case CMD_DATA_UNC_WRITE:
6084	p_vci.cmdval = true;
6085	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6086	p_vci.wdata = r_dcache_vci_wdata.read();
6087	p_vci.be = r_dcache_vci_unc_be.read();
6088	p_vci.trdid = 0;
6089	p_vci.pktid = TYPE_DATA_UNC;
6090	p_vci.plen = 4;
6091	p_vci.cmd = vci_param::CMD_WRITE;
6092	p_vci.eop = true;
6093	break;
6094
6095	case CMD_DATA_WRITE:
6096	p_vci.cmdval = true;
6097	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6098	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6099	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6100	p_vci.trdid = r_wbuf.getIndex();
6101	p_vci.pktid = TYPE_WRITE;
6102	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6103	p_vci.cmd = vci_param::CMD_WRITE;
6104	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6105	break;
6106
6107	case CMD_DATA_LL:
6108	p_vci.cmdval = true;
6109	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6110	p_vci.wdata = 0;
6111	p_vci.be = 0xF;
6112	p_vci.trdid = 0;
6113	p_vci.pktid = TYPE_LL;
6114	p_vci.plen = 8;
6115	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6116	p_vci.eop = true;
6117	break;
6118
6119	case CMD_DATA_SC:
6120	p_vci.cmdval = true;
6121	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6122	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6123	else p_vci.wdata = r_dcache_vci_sc_data.read();
6124	p_vci.be = 0xF;
6125	p_vci.trdid = 0;
6126	p_vci.pktid = TYPE_SC;
6127	p_vci.plen = 8;
6128	p_vci.cmd = vci_param::CMD_NOP;
6129	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6130	break;
6131
6132	case CMD_DATA_CAS:
6133	p_vci.cmdval = true;
6134	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6135	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6136	else p_vci.wdata = r_dcache_vci_cas_new.read();
6137	p_vci.be = 0xF;
6138	p_vci.trdid = 0;
6139	p_vci.pktid = TYPE_CAS;
6140	p_vci.plen = 8;
6141	p_vci.cmd = vci_param::CMD_NOP;
6142	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6143	break;
6144	} // end switch r_vci_cmd_fsm
6145
6146	// VCI initiator response on the direct network
6147	// it depends on the VCI_RSP FSM
6148
6149	switch (r_vci_rsp_fsm.read())
6150	{
6151	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6152	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6153	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6154	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6155	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6156	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6157	case RSP_IDLE : p_vci.rspack = false; break;
6158	} // end switch r_vci_rsp_fsm
6159
6160
6161	// Send coherence packets on DSPIN P2M
6162	// it depends on the CC_SEND FSM
6163
6164	uint64_t dspin_send_data = 0;
6165	switch (r_cc_send_fsm.read())
6166	{
6167	//////////////////
6168	case CC_SEND_IDLE:
6169	{
6170	p_dspin_p2m.write = false;
6171	break;
6172	}
6173	///////////////////////
6174	case CC_SEND_CLEANUP_1:
6175	{
6176	// initialize dspin send data
6177	DspinDhccpParam::dspin_set(dspin_send_data,
6178	m_cc_global_id,
6179	DspinDhccpParam::CLEANUP_SRCID);
6180	DspinDhccpParam::dspin_set(dspin_send_data,
6181	0,
6182	DspinDhccpParam::P2M_BC);
6183
6184	if (r_cc_send_last_client.read() == 0) // dcache active request
6185	{
6186	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6187	>> (m_nline_width - m_x_width - m_y_width)
6188	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6189
6190	DspinDhccpParam::dspin_set(dspin_send_data,
6191	dest,
6192	DspinDhccpParam::CLEANUP_DEST);
6193
6194	DspinDhccpParam::dspin_set(dspin_send_data,
6195	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6196	DspinDhccpParam::CLEANUP_NLINE_MSB);
6197
6198	DspinDhccpParam::dspin_set(dspin_send_data,
6199	r_dcache_cc_send_way.read(),
6200	DspinDhccpParam::CLEANUP_WAY_INDEX);
6201
6202	DspinDhccpParam::dspin_set(dspin_send_data,
6203	DspinDhccpParam::TYPE_CLEANUP_DATA,
6204	DspinDhccpParam::P2M_TYPE);
6205	}
6206	else // icache active request
6207	{
6208	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6209	>> (m_nline_width - m_x_width - m_y_width)
6210	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6211
6212	DspinDhccpParam::dspin_set(dspin_send_data,
6213	dest,
6214	DspinDhccpParam::CLEANUP_DEST);
6215
6216	DspinDhccpParam::dspin_set(dspin_send_data,
6217	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
6218	DspinDhccpParam::CLEANUP_NLINE_MSB);
6219
6220	DspinDhccpParam::dspin_set(dspin_send_data,
6221	r_icache_cc_send_way.read(),
6222	DspinDhccpParam::CLEANUP_WAY_INDEX);
6223
6224	DspinDhccpParam::dspin_set(dspin_send_data,
6225	DspinDhccpParam::TYPE_CLEANUP_INST,
6226	DspinDhccpParam::P2M_TYPE);
6227	}
6228	// send flit
6229	p_dspin_p2m.data = dspin_send_data;
6230	p_dspin_p2m.write = true;
6231	p_dspin_p2m.eop = false;
6232	break;
6233	}
6234	///////////////////////
6235	case CC_SEND_CLEANUP_2:
6236	{
6237	// initialize dspin send data
6238
6239	if (r_cc_send_last_client.read() == 0) // dcache active request
6240	{
6241	DspinDhccpParam::dspin_set(dspin_send_data,
6242	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6243	DspinDhccpParam::CLEANUP_NLINE_LSB);
6244	}
6245	else // icache active request
6246	{
6247	DspinDhccpParam::dspin_set(dspin_send_data,
6248	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6249	DspinDhccpParam::CLEANUP_NLINE_LSB);
6250	}
6251	// send flit
6252	p_dspin_p2m.data = dspin_send_data;
6253	p_dspin_p2m.write = true;
6254	p_dspin_p2m.eop = true;
6255	break;
6256	}
6257	///////////////////////
6258	case CC_SEND_MULTI_ACK:
6259	{
6260	// initialize dspin send data
6261	DspinDhccpParam::dspin_set(dspin_send_data,
6262	0,
6263	DspinDhccpParam::P2M_BC);
6264	DspinDhccpParam::dspin_set(dspin_send_data,
6265	DspinDhccpParam::TYPE_MULTI_ACK,
6266	DspinDhccpParam::P2M_TYPE);
6267
6268	if (r_cc_send_last_client.read() == 0) // dcache active request
6269	{
6270	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6271	>> (m_nline_width - m_x_width - m_y_width)
6272	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6273
6274	DspinDhccpParam::dspin_set(dspin_send_data,
6275	dest,
6276	DspinDhccpParam::MULTI_ACK_DEST);
6277
6278	DspinDhccpParam::dspin_set(dspin_send_data,
6279	r_dcache_cc_send_updt_tab_idx.read(),
6280	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6281	}
6282	else // icache active request
6283	{
6284	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6285	>> (m_nline_width - m_x_width - m_y_width)
6286	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6287
6288
6289	DspinDhccpParam::dspin_set(dspin_send_data,
6290	dest,
6291	DspinDhccpParam::MULTI_ACK_DEST);
6292
6293	DspinDhccpParam::dspin_set(dspin_send_data,
6294	r_icache_cc_send_updt_tab_idx.read(),
6295	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6296	}
6297	// send flit
6298	p_dspin_p2m.data = dspin_send_data;
6299	p_dspin_p2m.write = true;
6300	p_dspin_p2m.eop = true;
6301
6302	break;
6303	}
6304	} // end switch CC_SEND FSM
6305
6306	// Receive coherence packets
6307	// It depends on the CC_RECEIVE FSM
6308	switch (r_cc_receive_fsm.read())
6309	{
6310	/////////////////////
6311	case CC_RECEIVE_IDLE:
6312	{
6313	p_dspin_m2p.read = false;
6314	break;
6315	}
6316	///////////////////////////////
6317	case CC_RECEIVE_BRDCAST_HEADER:
6318	{
6319	p_dspin_m2p.read = true;
6320	break;
6321	}
6322	//////////////////////////////
6323	case CC_RECEIVE_BRDCAST_NLINE:
6324	{
6325	// TODO maybe we need to wait for both only to leave the state, but
6326	// not to actually post a request to an available cache => need a
6327	// flip_flop to check that ?
6328	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6329	p_dspin_m2p.read = true;
6330	else
6331	p_dspin_m2p.read = false;
6332	break;
6333	}
6334	/////////////////////////////
6335	case CC_RECEIVE_DATA_INVAL_HEADER:
6336	case CC_RECEIVE_INS_INVAL_HEADER:
6337	{
6338	p_dspin_m2p.read = true;
6339	break;
6340	}
6341	////////////////////////////
6342	case CC_RECEIVE_DATA_INVAL_NLINE:
6343	{
6344	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6345	break;
6346	}
6347	case CC_RECEIVE_INS_INVAL_NLINE:
6348	{
6349	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6350	break;
6351	}
6352	///////////////////////////
6353	case CC_RECEIVE_DATA_UPDT_HEADER:
6354	{
6355	if (not r_cc_receive_dcache_req.read())
6356	p_dspin_m2p.read = true;
6357	else
6358	p_dspin_m2p.read = false;
6359	break;
6360	}
6361	////////////////////////////
6362	case CC_RECEIVE_INS_UPDT_HEADER:
6363	{
6364	if (not r_cc_receive_icache_req.read())
6365	p_dspin_m2p.read = true;
6366	else
6367	p_dspin_m2p.read = false;
6368	break;
6369	}
6370	///////////////////////////
6371	case CC_RECEIVE_DATA_UPDT_NLINE:
6372	case CC_RECEIVE_INS_UPDT_NLINE:
6373	{
6374	if (r_cc_receive_updt_fifo_be.empty())
6375	p_dspin_m2p.read = true;
6376	else
6377	p_dspin_m2p.read = false;
6378	break;
6379	}
6380	///////////////////////////
6381	case CC_RECEIVE_DATA_UPDT_DATA:
6382	case CC_RECEIVE_INS_UPDT_DATA:
6383	{
6384	if (r_cc_receive_updt_fifo_be.wok())
6385	p_dspin_m2p.read = true;
6386	else
6387	p_dspin_m2p.read = false;
6388	break;
6389	}
6390	} // end switch CC_RECEIVE FSM
6391
6392
6393	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6394	DspinDhccpParam::CLACK_TYPE);
6395
6396	bool dspin_clack_get = false;
6397	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6398	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6399
6400	if (r_dspin_clack_req.read())
6401	{
6402	// CLACK DATA: wait if pending request to DCACHE FSM
6403	if (dcache_clack_request and not r_dcache_clack_req.read())
6404	{
6405	dspin_clack_get = true;
6406	}
6407
6408	// CLACK INST: wait if pending request to ICACHE FSM
6409	else if (icache_clack_request and not r_icache_clack_req.read())
6410	{
6411	dspin_clack_get = true;
6412	}
6413	}
6414	else
6415	{
6416	dspin_clack_get = true;
6417	}
6418
6419	p_dspin_clack.read = dspin_clack_get;
6420	} // end genMoore
6421
6422	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6423	// This version of monitor print both Read and Write request
6424	{
6425	m_monitor_ok = true;
6426	m_monitor_base = base;
6427	m_monitor_length = length;
6428	}
6429
6430	tmpl(void)::stop_monitor()
6431	{
6432	m_monitor_ok = false;
6433	}
6434
6435	}}
6436
6437	// Local Variables:
6438	// tab-width: 4
6439	// c-basic-offset: 4
6440	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6441	// indent-tabs-mode: nil
6442	// End:
6443
6444	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0