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vci_mem_cache.h @ 1011

Last change on this file since 1011 was 1011, checked in by cfuguet, 9 years ago

reconf: introduce a scratchpad mode in the memory cache.

Initialize the memory cache directory with all slots valid. The cache lines correspond to the lowest local memory segment (i.e. the first 256 Kbytes).

If there is a read or write miss while in scratchpad mode, the request is dropped (black-hole behavior).

In scratchpad mode, when a broadcast invalidate is triggered by a write, the line is not invalidated. The Read FSM needs to check in the IVT if there is a pending invalidate during a read. The same for the Cleanup FSM. This additional IVT check is only performed when in scratchpad mode.

TODO: Support of the scratchpad mode on the CAS FSM. But probably not needed because the distributed bootloader initializes the Local, Remote and Dirty flags to 1 before enabling the MMU.

File size: 44.6 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory.h"
50	#include "xram_transaction.h"
51	#include "update_tab.h"
52	#include "dspin_interface.h"
53	#include "dspin_dhccp_param.h"
54
55	#define TRT_ENTRIES 4 // Number of entries in TRT
56	#define UPT_ENTRIES 4 // Number of entries in UPT
57	#define IVT_ENTRIES 4 // Number of entries in IVT
58	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
59
60	namespace soclib { namespace caba {
61
62	using namespace sc_core;
63
64	template<typename vci_param_int,
65	typename vci_param_ext,
66	size_t memc_dspin_in_width,
67	size_t memc_dspin_out_width>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef typename vci_param_int::fast_addr_t addr_t;
72	typedef typename sc_dt::sc_uint<64> wide_data_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e
80	{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_CONFIG,
86	TGT_CMD_ERROR
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e
91	{
92	TGT_RSP_READ_IDLE,
93	TGT_RSP_WRITE_IDLE,
94	TGT_RSP_CAS_IDLE,
95	TGT_RSP_XRAM_IDLE,
96	TGT_RSP_MULTI_ACK_IDLE,
97	TGT_RSP_CLEANUP_IDLE,
98	TGT_RSP_TGT_CMD_IDLE,
99	TGT_RSP_CONFIG_IDLE,
100	TGT_RSP_READ,
101	TGT_RSP_WRITE,
102	TGT_RSP_CAS,
103	TGT_RSP_XRAM,
104	TGT_RSP_MULTI_ACK,
105	TGT_RSP_CLEANUP,
106	TGT_RSP_TGT_CMD,
107	TGT_RSP_CONFIG
108	};
109
110	/* States of the CC_TEST fsm */
111	enum cc_test_fsm_state_e
112	{
113	CC_TEST_IDLE,
114	CC_TEST_SEND,
115	CC_TEST_WAIT
116	};
117
118	/* States of the DSPIN_TGT fsm */
119	enum cc_receive_fsm_state_e
120	{
121	CC_RECEIVE_IDLE,
122	CC_RECEIVE_CLEANUP,
123	CC_RECEIVE_CLEANUP_EOP,
124	CC_RECEIVE_MULTI_ACK,
125	CC_RECEIVE_TEST,
126	CC_RECEIVE_TEST_EOP
127	};
128
129	/* States of the CC_SEND fsm */
130	enum cc_send_fsm_state_e
131	{
132	CC_SEND_XRAM_RSP_IDLE,
133	CC_SEND_WRITE_IDLE,
134	CC_SEND_CAS_IDLE,
135	CC_SEND_CONFIG_IDLE,
136	CC_SEND_TEST_IDLE,
137	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
138	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
139	CC_SEND_XRAM_RSP_INVAL_HEADER,
140	CC_SEND_XRAM_RSP_INVAL_NLINE,
141	CC_SEND_WRITE_BRDCAST_HEADER,
142	CC_SEND_WRITE_BRDCAST_NLINE,
143	CC_SEND_WRITE_UPDT_HEADER,
144	CC_SEND_WRITE_UPDT_NLINE,
145	CC_SEND_WRITE_UPDT_DATA,
146	CC_SEND_CAS_BRDCAST_HEADER,
147	CC_SEND_CAS_BRDCAST_NLINE,
148	CC_SEND_CAS_UPDT_HEADER,
149	CC_SEND_CAS_UPDT_NLINE,
150	CC_SEND_CAS_UPDT_DATA,
151	CC_SEND_CAS_UPDT_DATA_HIGH,
152	CC_SEND_CONFIG_INVAL_HEADER,
153	CC_SEND_CONFIG_INVAL_NLINE,
154	CC_SEND_CONFIG_BRDCAST_HEADER,
155	CC_SEND_CONFIG_BRDCAST_NLINE,
156	CC_SEND_TEST_HEADER,
157	CC_SEND_TEST_SIGNATURE
158	};
159
160	/* States of the MULTI_ACK fsm */
161	enum multi_ack_fsm_state_e
162	{
163	MULTI_ACK_IDLE,
164	MULTI_ACK_UPT_LOCK,
165	MULTI_ACK_UPT_CLEAR,
166	MULTI_ACK_WRITE_RSP
167	};
168
169	/* States of the CONFIG fsm */
170	enum config_fsm_state_e
171	{
172	CONFIG_IDLE,
173	CONFIG_LOOP,
174	CONFIG_WAIT,
175	CONFIG_RSP,
176	CONFIG_DIR_REQ,
177	CONFIG_DIR_ACCESS,
178	CONFIG_IVT_LOCK,
179	CONFIG_BC_SEND,
180	CONFIG_INVAL_SEND,
181	CONFIG_HEAP_REQ,
182	CONFIG_HEAP_SCAN,
183	CONFIG_HEAP_LAST,
184	CONFIG_TRT_LOCK,
185	CONFIG_TRT_SET,
186	CONFIG_PUT_REQ
187	};
188
189	/* States of the READ fsm */
190	enum read_fsm_state_e
191	{
192	READ_IDLE,
193	READ_DIR_REQ,
194	READ_DIR_LOCK,
195	READ_DIR_HIT,
196	READ_HEAP_REQ,
197	READ_HEAP_LOCK,
198	READ_HEAP_WRITE,
199	READ_HEAP_ERASE,
200	READ_HEAP_LAST,
201	READ_RSP,
202	READ_TRT_LOCK,
203	READ_TRT_SET,
204	READ_TRT_REQ,
205	READ_IVT_LOCK
206	};
207
208	/* States of the WRITE fsm */
209	enum write_fsm_state_e
210	{
211	WRITE_IDLE,
212	WRITE_NEXT,
213	WRITE_DIR_REQ,
214	WRITE_DIR_LOCK,
215	WRITE_DIR_HIT,
216	WRITE_UPT_LOCK,
217	WRITE_UPT_HEAP_LOCK,
218	WRITE_UPT_REQ,
219	WRITE_UPT_NEXT,
220	WRITE_UPT_DEC,
221	WRITE_RSP,
222	WRITE_MISS_TRT_LOCK,
223	WRITE_MISS_TRT_DATA,
224	WRITE_MISS_TRT_SET,
225	WRITE_MISS_XRAM_REQ,
226	WRITE_BC_DIR_READ,
227	WRITE_BC_TRT_LOCK,
228	WRITE_BC_IVT_LOCK,
229	WRITE_BC_DIR_INVAL,
230	WRITE_BC_CC_SEND,
231	WRITE_BC_XRAM_REQ,
232	WRITE_WAIT
233	};
234
235	/* States of the IXR_RSP fsm */
236	enum ixr_rsp_fsm_state_e
237	{
238	IXR_RSP_IDLE,
239	IXR_RSP_TRT_ERASE,
240	IXR_RSP_TRT_READ
241	};
242
243	/* States of the XRAM_RSP fsm */
244	enum xram_rsp_fsm_state_e
245	{
246	XRAM_RSP_IDLE,
247	XRAM_RSP_TRT_COPY,
248	XRAM_RSP_TRT_DIRTY,
249	XRAM_RSP_DIR_LOCK,
250	XRAM_RSP_DIR_UPDT,
251	XRAM_RSP_DIR_RSP,
252	XRAM_RSP_IVT_LOCK,
253	XRAM_RSP_INVAL_WAIT,
254	XRAM_RSP_INVAL,
255	XRAM_RSP_WRITE_DIRTY,
256	XRAM_RSP_HEAP_REQ,
257	XRAM_RSP_HEAP_ERASE,
258	XRAM_RSP_HEAP_LAST,
259	XRAM_RSP_ERROR_ERASE,
260	XRAM_RSP_ERROR_RSP
261	};
262
263	/* States of the IXR_CMD fsm */
264	enum ixr_cmd_fsm_state_e
265	{
266	IXR_CMD_READ_IDLE,
267	IXR_CMD_WRITE_IDLE,
268	IXR_CMD_CAS_IDLE,
269	IXR_CMD_XRAM_IDLE,
270	IXR_CMD_CONFIG_IDLE,
271	IXR_CMD_READ_TRT,
272	IXR_CMD_WRITE_TRT,
273	IXR_CMD_CAS_TRT,
274	IXR_CMD_XRAM_TRT,
275	IXR_CMD_CONFIG_TRT,
276	IXR_CMD_READ_SEND,
277	IXR_CMD_WRITE_SEND,
278	IXR_CMD_CAS_SEND,
279	IXR_CMD_XRAM_SEND,
280	IXR_CMD_CONFIG_SEND
281	};
282
283	/* States of the CAS fsm */
284	enum cas_fsm_state_e
285	{
286	CAS_IDLE,
287	CAS_DIR_REQ,
288	CAS_DIR_LOCK,
289	CAS_DIR_HIT_READ,
290	CAS_DIR_HIT_COMPARE,
291	CAS_DIR_HIT_WRITE,
292	CAS_UPT_LOCK,
293	CAS_UPT_HEAP_LOCK,
294	CAS_UPT_REQ,
295	CAS_UPT_NEXT,
296	CAS_BC_TRT_LOCK,
297	CAS_BC_IVT_LOCK,
298	CAS_BC_DIR_INVAL,
299	CAS_BC_CC_SEND,
300	CAS_BC_XRAM_REQ,
301	CAS_RSP_FAIL,
302	CAS_RSP_SUCCESS,
303	CAS_MISS_TRT_LOCK,
304	CAS_MISS_TRT_SET,
305	CAS_MISS_XRAM_REQ,
306	CAS_WAIT
307	};
308
309	/* States of the CLEANUP fsm */
310	enum cleanup_fsm_state_e
311	{
312	CLEANUP_IDLE,
313	CLEANUP_GET_NLINE,
314	CLEANUP_DIR_REQ,
315	CLEANUP_DIR_LOCK,
316	CLEANUP_DIR_WRITE,
317	CLEANUP_HEAP_REQ,
318	CLEANUP_HEAP_LOCK,
319	CLEANUP_HEAP_SEARCH,
320	CLEANUP_HEAP_CLEAN,
321	CLEANUP_HEAP_FREE,
322	CLEANUP_IVT_LOCK,
323	CLEANUP_IVT_DECREMENT,
324	CLEANUP_IVT_CLEAR,
325	CLEANUP_WRITE_RSP,
326	CLEANUP_SEND_CLACK,
327	CLEANUP_TEST_HEADER,
328	CLEANUP_TEST_SIGNATURE
329	};
330
331	/* States of the ALLOC_DIR fsm */
332	enum alloc_dir_fsm_state_e
333	{
334	ALLOC_DIR_RESET,
335	ALLOC_DIR_READ,
336	ALLOC_DIR_WRITE,
337	ALLOC_DIR_CAS,
338	ALLOC_DIR_CLEANUP,
339	ALLOC_DIR_XRAM_RSP,
340	ALLOC_DIR_CONFIG
341	};
342
343	/* States of the ALLOC_TRT fsm */
344	enum alloc_trt_fsm_state_e
345	{
346	ALLOC_TRT_READ,
347	ALLOC_TRT_WRITE,
348	ALLOC_TRT_CAS,
349	ALLOC_TRT_XRAM_RSP,
350	ALLOC_TRT_IXR_RSP,
351	ALLOC_TRT_IXR_CMD,
352	ALLOC_TRT_CONFIG
353	};
354
355	/* States of the ALLOC_UPT fsm */
356	enum alloc_upt_fsm_state_e
357	{
358	ALLOC_UPT_WRITE,
359	ALLOC_UPT_CAS,
360	ALLOC_UPT_MULTI_ACK
361	};
362
363	/* States of the ALLOC_IVT fsm */
364	enum alloc_ivt_fsm_state_e
365	{
366	ALLOC_IVT_WRITE,
367	ALLOC_IVT_XRAM_RSP,
368	ALLOC_IVT_CLEANUP,
369	ALLOC_IVT_CAS,
370	ALLOC_IVT_CONFIG,
371	ALLOC_IVT_READ
372	};
373
374	/* States of the ALLOC_HEAP fsm */
375	enum alloc_heap_fsm_state_e
376	{
377	ALLOC_HEAP_RESET,
378	ALLOC_HEAP_READ,
379	ALLOC_HEAP_WRITE,
380	ALLOC_HEAP_CAS,
381	ALLOC_HEAP_CLEANUP,
382	ALLOC_HEAP_XRAM_RSP,
383	ALLOC_HEAP_CONFIG
384	};
385
386	/* transaction type, pktid field */
387	enum transaction_type_e
388	{
389	// b3 unused
390	// b2 READ / NOT READ
391	// Si READ
392	// b1 DATA / INS
393	// b0 UNC / MISS
394	// Si NOT READ
395	// b1 accÃšs table llsc type SW / other
396	// b2 WRITE/CAS/LL/SC
397	TYPE_READ_DATA_UNC = 0x0,
398	TYPE_READ_DATA_MISS = 0x1,
399	TYPE_READ_INS_UNC = 0x2,
400	TYPE_READ_INS_MISS = 0x3,
401	TYPE_WRITE = 0x4,
402	TYPE_CAS = 0x5,
403	TYPE_LL = 0x6,
404	TYPE_SC = 0x7
405	};
406
407	/* SC return values */
408	enum sc_status_type_e
409	{
410	SC_SUCCESS = 0x00000000,
411	SC_FAIL = 0x00000001
412	};
413
414	// debug variables
415	bool m_debug;
416	bool m_debug_previous_valid;
417	size_t m_debug_previous_count;
418	bool m_debug_previous_dirty;
419	data_t * m_debug_previous_data;
420	data_t * m_debug_data;
421
422	// instrumentation counters
423	uint64_t m_cpt_cycles; // Counter of cycles
424	uint64_t m_cpt_reset_count; // Cycle at which the counters were last reset
425
426	// Counters accessible in software (not yet but eventually)
427	uint32_t m_cpt_read_local; // Number of local READ transactions
428	uint32_t m_cpt_read_remote; // number of remote READ transactions
429	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
430
431	uint32_t m_cpt_write_local; // Number of local WRITE transactions
432	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
433	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
434	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
435	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
436
437	uint32_t m_cpt_ll_local; // Number of local LL transactions
438	uint32_t m_cpt_ll_remote; // number of remote LL transactions
439	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
440
441	uint32_t m_cpt_sc_local; // Number of local SC transactions
442	uint32_t m_cpt_sc_remote; // number of remote SC transactions
443	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
444
445	uint32_t m_cpt_cas_local; // Number of local SC transactions
446	uint32_t m_cpt_cas_remote; // number of remote SC transactions
447	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
448
449	uint32_t m_cpt_update; // Number of requests causing an UPDATE
450	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
451	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
452	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
453
454	uint32_t m_cpt_minval; // Number of requests causing M_INV
455	uint32_t m_cpt_minval_local; // Number of local M_INV transactions
456	uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions
457	uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV
458
459	uint32_t m_cpt_binval; // Number of BROADCAST INVAL
460
461	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions
462	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
463	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
464
465	// Counters not accessible by software
466	uint32_t m_cpt_read_miss; // Number of MISS READ
467	uint32_t m_cpt_write_miss; // Number of MISS WRITE
468	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
469	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because of writes
470
471	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
472	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
473
474	uint32_t m_cpt_get;
475	uint32_t m_cpt_put;
476
477	size_t m_prev_count;
478
479	protected:
480
481	SC_HAS_PROCESS(VciMemCache);
482
483	public:
484	sc_in<bool> p_clk;
485	sc_in<bool> p_resetn;
486	sc_out<bool> p_irq;
487	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
488	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
489	soclib::caba::DspinInput<memc_dspin_in_width> p_dspin_p2m;
490	soclib::caba::DspinOutput<memc_dspin_out_width> p_dspin_m2p;
491	soclib::caba::DspinOutput<memc_dspin_out_width> p_dspin_clack;
492
493	#if MONITOR_MEMCACHE_FSM == 1
494	sc_out<int> p_read_fsm;
495	sc_out<int> p_write_fsm;
496	sc_out<int> p_xram_rsp_fsm;
497	sc_out<int> p_cas_fsm;
498	sc_out<int> p_cleanup_fsm;
499	sc_out<int> p_config_fsm;
500	sc_out<int> p_alloc_heap_fsm;
501	sc_out<int> p_alloc_dir_fsm;
502	sc_out<int> p_alloc_trt_fsm;
503	sc_out<int> p_alloc_upt_fsm;
504	sc_out<int> p_alloc_ivt_fsm;
505	sc_out<int> p_tgt_cmd_fsm;
506	sc_out<int> p_tgt_rsp_fsm;
507	sc_out<int> p_ixr_cmd_fsm;
508	sc_out<int> p_ixr_rsp_fsm;
509	sc_out<int> p_cc_send_fsm;
510	sc_out<int> p_cc_receive_fsm;
511	sc_out<int> p_multi_ack_fsm;
512	#endif
513
514	VciMemCache(
515	sc_module_name name, // Instance Name
516	const soclib::common::MappingTable &mtp, // Mapping table INT network
517	const soclib::common::MappingTable &mtx, // Mapping table RAM network
518	const soclib::common::IntTab &srcid_x, // global index RAM network
519	const soclib::common::IntTab &tgtid_d, // global index INT network
520	const size_t x_width, // X width in platform
521	const size_t y_width, // Y width in platform
522	const size_t nways, // Number of ways per set
523	const size_t nsets, // Number of sets
524	const size_t nwords, // Number of words per line
525	const size_t max_copies, // max number of copies
526	const size_t heap_size=HEAP_ENTRIES,
527	const size_t trt_lines=TRT_ENTRIES,
528	const size_t upt_lines=UPT_ENTRIES,
529	const size_t ivt_lines=IVT_ENTRIES,
530	const size_t debug_start_cycle=0,
531	const bool debug_ok=false );
532
533	~VciMemCache();
534
535	void reset_counters();
536	void print_stats(bool activity_counters = true, bool stats = true);
537	void print_trace( size_t detailed = 0 );
538	void cache_monitor(addr_t addr, bool single_word = false);
539	void start_monitor(addr_t addr, addr_t length);
540	void stop_monitor();
541
542	private:
543
544	void scratchpad_reset();
545	void transition();
546	void genMoore();
547	void check_monitor(addr_t addr, data_t data, bool read);
548
549	uint32_t req_distance(uint32_t req_srcid);
550	bool is_local_req(uint32_t req_srcid);
551	int read_instrumentation(uint32_t regr, uint32_t & rdata);
552
553	// Component attributes
554	size_t m_nseg; // number of segments
555	const size_t m_srcid_x; // global index on RAM network
556	const size_t m_initiators; // Number of initiators
557	const size_t m_heap_size; // Size of the heap
558	const size_t m_ways; // Number of ways in a set
559	const size_t m_sets; // Number of cache sets
560	const size_t m_words; // Number of words in a line
561	size_t m_x_self; // X self coordinate
562	size_t m_y_self; // Y self coordinate
563	const size_t m_x_width; // number of x bits in platform
564	const size_t m_y_width; // number of y bits in platform
565	size_t m_debug_start_cycle;
566	bool m_debug_ok;
567	uint32_t m_trt_lines;
568	TransactionTab m_trt; // xram transaction table
569	uint32_t m_upt_lines;
570	UpdateTab m_upt; // pending update
571	UpdateTab m_ivt; // pending invalidate
572	CacheDirectory m_cache_directory; // data cache directory
573	CacheData m_cache_data; // data array[set][way][word]
574	HeapDirectory m_heap; // heap for copies
575	size_t m_max_copies; // max number of copies in heap
576	GenericLLSCGlobalTable
577	< 32 , // number of slots
578	4096, // number of processors in the system
579	8000, // registration life (# of LL operations)
580	addr_t > m_llsc_table; // ll/sc registration table
581
582	// adress masks
583	const soclib::common::AddressMaskingTable<addr_t> m_x;
584	const soclib::common::AddressMaskingTable<addr_t> m_y;
585	const soclib::common::AddressMaskingTable<addr_t> m_z;
586	const soclib::common::AddressMaskingTable<addr_t> m_nline;
587
588	// broadcast address
589	uint32_t m_broadcast_boundaries;
590
591	// configuration interface constants
592	soclib::common::Segment* m_config_seg;
593	const uint32_t m_config_addr_mask;
594	const uint32_t m_config_regr_width;
595	const uint32_t m_config_func_width;
596	const uint32_t m_config_regr_idx_mask;
597	const uint32_t m_config_func_idx_mask;
598
599	// Fifo between TGT_CMD fsm and READ fsm
600	GenericFifo<addr_t> m_cmd_read_addr_fifo;
601	GenericFifo<size_t> m_cmd_read_length_fifo;
602	GenericFifo<size_t> m_cmd_read_srcid_fifo;
603	GenericFifo<size_t> m_cmd_read_trdid_fifo;
604	GenericFifo<size_t> m_cmd_read_pktid_fifo;
605
606	// Fifo between TGT_CMD fsm and WRITE fsm
607	GenericFifo<addr_t> m_cmd_write_addr_fifo;
608	GenericFifo<bool> m_cmd_write_eop_fifo;
609	GenericFifo<size_t> m_cmd_write_srcid_fifo;
610	GenericFifo<size_t> m_cmd_write_trdid_fifo;
611	GenericFifo<size_t> m_cmd_write_pktid_fifo;
612	GenericFifo<data_t> m_cmd_write_data_fifo;
613	GenericFifo<be_t> m_cmd_write_be_fifo;
614
615	// Fifo between TGT_CMD fsm and CAS fsm
616	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
617	GenericFifo<bool> m_cmd_cas_eop_fifo;
618	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
619	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
620	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
621	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
622
623	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
624	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
625
626	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
627	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
628
629	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
630	GenericFifo<uint64_t> m_cc_receive_to_cc_test_fifo;
631
632	// Buffer between TGT_CMD fsm and TGT_RSP fsm
633	// (segmentation violation response request)
634	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
635
636	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
637	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
638	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
639	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
640	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
641
642	sc_signal<addr_t> r_tgt_cmd_config_addr;
643	sc_signal<size_t> r_tgt_cmd_config_cmd;
644
645	//////////////////////////////////////////////////
646	// Registers controlled by the TGT_CMD fsm
647	//////////////////////////////////////////////////
648
649	sc_signal<int> r_tgt_cmd_fsm;
650
651	///////////////////////////////////////////////////////
652	// Registers controlled by the CONFIG fsm
653	///////////////////////////////////////////////////////
654
655	sc_signal<int> r_config_fsm; // FSM state
656	sc_signal<int> r_config_cmd; // config request type
657	sc_signal<addr_t> r_config_address; // target buffer physical address
658	sc_signal<size_t> r_config_srcid; // config request srcid
659	sc_signal<size_t> r_config_trdid; // config request trdid
660	sc_signal<size_t> r_config_pktid; // config request pktid
661	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
662	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
663	sc_signal<size_t> r_config_dir_way; // DIR: selected way
664	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
665	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
666	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
667	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
668	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
669	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
670	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
671	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
672	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
673	sc_signal<bool> r_config_scratchpad; // enable scratchpad mode
674
675	// Buffer between CONFIG fsm and IXR_CMD fsm
676	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
677	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
678
679	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
680	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
681	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
682	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
683	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
684	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
685
686	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
687	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
688	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
689	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
690	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
691	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
692	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
693
694	///////////////////////////////////////////////////////
695	// Registers controlled by the READ fsm
696	///////////////////////////////////////////////////////
697
698	sc_signal<int> r_read_fsm; // FSM state
699	sc_signal<size_t> r_read_copy; // Srcid of the first copy
700	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
701	sc_signal<bool> r_read_copy_inst; // Type of the first copy
702	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
703	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
704	sc_signal<bool> r_read_lock; // lock bit (in directory)
705	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
706	sc_signal<size_t> r_read_count; // number of copies
707	sc_signal<size_t> r_read_ptr; // pointer to the heap
708	sc_signal<data_t> * r_read_data; // data (one cache line)
709	sc_signal<size_t> r_read_way; // associative way (in cache)
710	sc_signal<size_t> r_read_trt_index; // Transaction Table index
711	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
712	sc_signal<bool> r_read_last_free; // Last free entry
713	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
714
715	// Buffer between READ fsm and IXR_CMD fsm
716	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
717	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
718
719	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
720	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
721	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
722	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
723	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
724	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
725	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
726	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
727	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
728
729	///////////////////////////////////////////////////////////////
730	// Registers controlled by the WRITE fsm
731	///////////////////////////////////////////////////////////////
732
733	sc_signal<int> r_write_fsm; // FSM state
734	sc_signal<addr_t> r_write_address; // first word address
735	sc_signal<size_t> r_write_word_index; // first word index in line
736	sc_signal<size_t> r_write_word_count; // number of words in line
737	sc_signal<size_t> r_write_srcid; // transaction srcid
738	sc_signal<size_t> r_write_trdid; // transaction trdid
739	sc_signal<size_t> r_write_pktid; // transaction pktid
740	sc_signal<data_t> * r_write_data; // data (one cache line)
741	sc_signal<be_t> * r_write_be; // one byte enable per word
742	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
743	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
744	sc_signal<bool> r_write_lock; // lock bit (in directory)
745	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
746	sc_signal<size_t> r_write_copy; // first owner of the line
747	sc_signal<size_t> r_write_copy_cache; // first owner of the line
748	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
749	sc_signal<size_t> r_write_count; // number of copies
750	sc_signal<size_t> r_write_ptr; // pointer to the heap
751	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
752	sc_signal<bool> r_write_to_dec; // need to decrement update counter
753	sc_signal<size_t> r_write_way; // way of the line
754	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
755	sc_signal<size_t> r_write_upt_index; // index in Update Table
756	sc_signal<bool> r_write_sc_fail; // sc command failed
757	sc_signal<data_t> r_write_sc_key; // sc command key
758	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
759
760	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
761	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
762	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
763	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
764	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
765	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
766
767	// Buffer between WRITE fsm and IXR_CMD fsm
768	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
769	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
770
771	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
772	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
773	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
774	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
775	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
776	sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line)
777	sc_signal<be_t> * r_write_to_cc_send_be; // word enable
778	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
779	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
780	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
781	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
782
783	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
784	sc_signal<bool> r_write_to_multi_ack_req; // valid request
785	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
786
787	/////////////////////////////////////////////////////////
788	// Registers controlled by MULTI_ACK fsm
789	//////////////////////////////////////////////////////////
790
791	sc_signal<int> r_multi_ack_fsm; // FSM state
792	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
793	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
794	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
795	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
796	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
797
798	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
799	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
800	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
801	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
802	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
803
804	///////////////////////////////////////////////////////
805	// Registers controlled by CLEANUP fsm
806	///////////////////////////////////////////////////////
807
808	sc_signal<int> r_cleanup_fsm; // FSM state
809	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
810	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
811	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
812	sc_signal<addr_t> r_cleanup_nline; // cache line index
813
814
815	sc_signal<copy_t> r_cleanup_copy; // first copy
816	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
817	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
818	sc_signal<copy_t> r_cleanup_count; // number of copies
819	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
820	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
821	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
822	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
823	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
824	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
825	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
826	sc_signal<bool> r_cleanup_valid; // valid bit (in directory)
827	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
828	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
829	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
830	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
831
832	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp
833	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
834	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
835
836	sc_signal<bool> r_cleanup_need_rsp; // write response required
837	sc_signal<bool> r_cleanup_need_ack; // config acknowledge required
838
839	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
840
841	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
842	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
843	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
844	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
845	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
846
847	///////////////////////////////////////////////////////
848	// Registers controlled by CAS fsm
849	///////////////////////////////////////////////////////
850
851	sc_signal<int> r_cas_fsm; // FSM state
852	sc_signal<data_t> r_cas_wdata; // write data word
853	sc_signal<data_t> * r_cas_rdata; // read data word
854	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
855	sc_signal<size_t> r_cas_cpt; // size of command
856	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
857	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
858	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
859	sc_signal<size_t> r_cas_count; // number of copies
860	sc_signal<size_t> r_cas_ptr; // pointer to the heap
861	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
862	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
863	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
864	sc_signal<size_t> r_cas_way; // way in directory
865	sc_signal<size_t> r_cas_set; // set in directory
866	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
867	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
868	sc_signal<size_t> r_cas_upt_index; // Update Table index
869	sc_signal<data_t> * r_cas_data; // cache line data
870
871	// Buffer between CAS fsm and IXR_CMD fsm
872	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
873	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
874
875	// Buffer between CAS fsm and TGT_RSP fsm
876	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
877	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
878	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
879	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
880	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
881
882	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
883	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
884	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
885	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
886	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
887	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
888	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
889	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
890	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
891	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
892	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
893
894	////////////////////////////////////////////////////
895	// Registers controlled by the IXR_RSP fsm
896	////////////////////////////////////////////////////
897
898	sc_signal<int> r_ixr_rsp_fsm; // FSM state
899	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
900	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
901
902	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
903	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
904
905	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
906	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
907
908	////////////////////////////////////////////////////
909	// Registers controlled by the XRAM_RSP fsm
910	////////////////////////////////////////////////////
911
912	sc_signal<int> r_xram_rsp_fsm; // FSM state
913	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
914	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
915	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
916	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
917	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
918	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
919	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
920	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
921	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
922	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
923	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
924	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
925	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
926	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
927	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
928	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
929	sc_signal<bool> r_xram_rsp_rerror_irq; // WRITE MISS rerror irq
930	sc_signal<bool> r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
931	sc_signal<addr_t> r_xram_rsp_rerror_address; // WRITE MISS rerror address
932	sc_signal<size_t> r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid
933
934	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
935	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
936	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
937	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
938	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
939	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
940	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
941	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
942	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
943	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
944
945	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
946	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
947	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
948	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
949	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
950	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
951	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
952
953	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
954	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
955	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
956
957	////////////////////////////////////////////////////
958	// Registers controlled by the IXR_CMD fsm
959	////////////////////////////////////////////////////
960
961	sc_signal<int> r_ixr_cmd_fsm;
962	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
963	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
964	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
965	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
966	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
967
968	////////////////////////////////////////////////////
969	// Registers controlled by TGT_RSP fsm
970	////////////////////////////////////////////////////
971
972	sc_signal<int> r_tgt_rsp_fsm;
973	sc_signal<size_t> r_tgt_rsp_cpt;
974	sc_signal<bool> r_tgt_rsp_key_sent;
975
976	////////////////////////////////////////////////////
977	// Registers controlled by CC_SEND fsm
978	////////////////////////////////////////////////////
979
980	sc_signal<int> r_cc_send_fsm;
981	sc_signal<size_t> r_cc_send_cpt;
982	sc_signal<bool> r_cc_send_inst;
983
984	////////////////////////////////////////////////////
985	// Registers controlled by CC_RECEIVE fsm
986	////////////////////////////////////////////////////
987
988	sc_signal<int> r_cc_receive_fsm;
989
990	////////////////////////////////////////////////////
991	// Registers controlled by CC_TEST fsm
992	////////////////////////////////////////////////////
993
994	sc_signal<int> r_cc_test_fsm;
995	sc_signal<size_t> r_cc_test_srcid;
996
997	// Buffer between CC_TEST fsm and CC_SEND fsm
998	sc_signal<bool> r_cc_test_to_cc_send_req;
999
1000	// Buffer between CC_TEST fsm and CLEANUP fsm
1001	sc_signal<bool> r_cc_test_to_cleanup_req;
1002
1003	////////////////////////////////////////////////////
1004	// Registers controlled by ALLOC_DIR fsm
1005	////////////////////////////////////////////////////
1006
1007	sc_signal<int> r_alloc_dir_fsm;
1008	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1009
1010	////////////////////////////////////////////////////
1011	// Registers controlled by ALLOC_TRT fsm
1012	////////////////////////////////////////////////////
1013
1014	sc_signal<int> r_alloc_trt_fsm;
1015
1016	////////////////////////////////////////////////////
1017	// Registers controlled by ALLOC_UPT fsm
1018	////////////////////////////////////////////////////
1019
1020	sc_signal<int> r_alloc_upt_fsm;
1021
1022	////////////////////////////////////////////////////
1023	// Registers controlled by ALLOC_IVT fsm
1024	////////////////////////////////////////////////////
1025
1026	sc_signal<int> r_alloc_ivt_fsm;
1027
1028	////////////////////////////////////////////////////
1029	// Registers controlled by ALLOC_HEAP fsm
1030	////////////////////////////////////////////////////
1031
1032	sc_signal<int> r_alloc_heap_fsm;
1033	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1034	}; // end class VciMemCache
1035
1036	}}
1037
1038	#endif
1039
1040	// Local Variables:
1041	// tab-width: 2
1042	// c-basic-offset: 2
1043	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1044	// indent-tabs-mode: nil
1045	// End:
1046
1047	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1048

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source: branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 1011

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