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tsar_iob_cluster.h @ 1001

Last change on this file since 1001 was 1001, checked in by cfuguet, 9 years ago

reconf: introducing a hardware barrier in the global-local interface of
the local interconnects.

This barrier is controlled by a port (barrier enable) in the dspin and vci local interconnects.

The barrier enable port is connected to a configuration register of the XICU component to allow the software to control this barrier. The barrier is enabled when the barrier enable port value is different of 0xFFFFFFFF. As the configuration register of the XICU component are reset to 0, this barrier is enabled by default.

This barrier allows to isolate the cluster from the rest of the architecture and only if it self-diagnoses as functional, it release the barrier to communicate with the others.

The same barrier enable signal is connected to the five local interconnects. Therefore, either all are released or all are disabled.

If a local initiator or an external initiator sends a packet out or into the cluster respectively, and the barrier is enabled, the packet is dropped.

File size: 11.9 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.h
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8
9	#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
10	#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
11
12	#include <systemc>
13	#include <sys/time.h>
14	#include <iostream>
15	#include <sstream>
16	#include <cstdlib>
17	#include <cstdarg>
18
19	#include "gdbserver.h"
20	#include "mapping_table.h"
21	#include "mips32.h"
22	#include "vci_simple_ram.h"
23	#include "vci_xicu.h"
24	#include "vci_local_crossbar.h"
25	#include "dspin_local_crossbar.h"
26	#include "vci_dspin_initiator_wrapper.h"
27	#include "vci_dspin_target_wrapper.h"
28	#include "dspin_router.h"
29	#include "vci_multi_dma.h"
30	#include "vci_mem_cache.h"
31	#include "vci_cc_vcache_wrapper.h"
32	#include "vci_io_bridge.h"
33	#include "vci_simple_rom.h"
34
35	namespace soclib { namespace caba {
36
37	///////////////////////////////////////////////////////////////////////////
38	template<typename vci_param_int,
39	typename vci_param_ext,
40	size_t dspin_int_cmd_width,
41	size_t dspin_int_rsp_width,
42	size_t dspin_ram_cmd_width,
43	size_t dspin_ram_rsp_width>
44	class TsarIobCluster
45	///////////////////////////////////////////////////////////////////////////
46	: public soclib::caba::BaseModule
47	{
48
49	public:
50
51	// Ports
52	sc_in<bool> p_clk;
53	sc_in<bool> p_resetn;
54
55	sc_in<bool> p_false;
56
57	// Thes two ports are used to connect IOB to IOX nework in top cell
58	soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini;
59	soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt;
60
61	// These arrays of ports are used to connect the INT & RAM networks in top cell
62	soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out;
63	soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in;
64	soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out;
65	soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in;
66
67	soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out;
68	soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in;
69	soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out;
70	soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in;
71
72	// interrupt signals
73	sc_signal<bool> signal_proc_it[16];
74	sc_signal<bool> signal_irq_mdma[8];
75	sc_signal<bool> signal_irq_memc;
76	sc_signal<uint32_t> signal_cfg_router_cmd[3];
77	sc_signal<uint32_t> signal_cfg_router_rsp[2];
78	sc_signal<uint32_t> signal_cfg_xbar_barrier;
79
80	// INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars
81	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d;
82	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d;
83	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c;
84	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c;
85	DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c;
86	DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c;
87	DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;
88	DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;
89	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c;
90	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c;
91
92	// INT network VCI signals between VCI components and VCI local crossbar
93	VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
94	VciSignals<vci_param_int> signal_int_vci_ini_mdma;
95	VciSignals<vci_param_int> signal_int_vci_ini_iobx;
96
97	VciSignals<vci_param_int> signal_int_vci_tgt_memc;
98	VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
99	VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
100	VciSignals<vci_param_int> signal_int_vci_tgt_drom;
101	VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
102
103	VciSignals<vci_param_int> signal_int_vci_l2g;
104	VciSignals<vci_param_int> signal_int_vci_g2l;
105
106	// Coherence DSPIN signals between DSPIN local crossbars and CC components
107	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc;
108	DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
109	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
110	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
111	DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
112	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
113
114	// RAM network VCI signals between VCI components and VCI/DSPIN wrappers
115	VciSignals<vci_param_ext> signal_ram_vci_ini_memc;
116	VciSignals<vci_param_ext> signal_ram_vci_ini_iobx;
117	VciSignals<vci_param_ext> signal_ram_vci_tgt_xram;
118
119	// RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar
120	// and routers
121	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
122	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
123	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
124	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
125	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i;
126	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i;
127	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar;
128	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar;
129	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false;
130	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false;
131
132	//////////////////////////////////////
133	// Hardwate Components (pointers)
134	//////////////////////////////////////
135	VciCcVCacheWrapper<vci_param_int,
136	dspin_int_cmd_width,
137	dspin_int_rsp_width,
138	GdbServer<Mips32ElIss> >* proc[8];
139
140	VciMemCache<vci_param_int,
141	vci_param_ext,
142	dspin_int_rsp_width,
143	dspin_int_cmd_width>* memc;
144
145	VciDspinInitiatorWrapper<vci_param_ext,
146	dspin_ram_cmd_width,
147	dspin_ram_rsp_width>* memc_ram_wi;
148
149	VciXicu<vci_param_int>* xicu;
150
151	VciMultiDma<vci_param_int>* mdma;
152
153	VciSimpleRom<vci_param_int>* drom;
154
155	VciLocalCrossbar<vci_param_int>* int_xbar_d;
156
157	VciDspinInitiatorWrapper<vci_param_int,
158	dspin_int_cmd_width,
159	dspin_int_rsp_width>* int_wi_gate_d;
160
161	VciDspinTargetWrapper<vci_param_int,
162	dspin_int_cmd_width,
163	dspin_int_rsp_width>* int_wt_gate_d;
164
165	DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c;
166	DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c;
167	DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c;
168
169	DspinRouter<dspin_int_cmd_width>** int_router_cmd;
170	DspinRouter<dspin_int_rsp_width>** int_router_rsp;
171
172	VciSimpleRam<vci_param_ext>* xram;
173
174	VciDspinTargetWrapper<vci_param_ext,
175	dspin_ram_cmd_width,
176	dspin_ram_rsp_width>* xram_ram_wt;
177
178	DspinRouter<dspin_ram_cmd_width>* ram_router_cmd;
179	DspinRouter<dspin_ram_rsp_width>* ram_router_rsp;
180
181	DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;
182	DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;
183
184
185	// IO Network Components (not instanciated in all clusters)
186
187	VciIoBridge<vci_param_int,
188	vci_param_ext>* iob;
189
190	VciDspinInitiatorWrapper<vci_param_ext,
191	dspin_ram_cmd_width,
192	dspin_ram_rsp_width>* iob_ram_wi;
193
194	// cluster constructor
195	TsarIobCluster( sc_module_name insname,
196	size_t nb_procs,
197	size_t nb_dmas,
198	size_t x, // x coordinate
199	size_t y, // y coordinate
200	size_t x_size,
201	size_t y_size,
202
203	size_t p_width, // pid field bits
204
205	const soclib::common::MappingTable &mt_int,
206	const soclib::common::MappingTable &mt_ext,
207	const soclib::common::MappingTable &mt_iox,
208
209	size_t x_width, // x field bits
210	size_t y_width, // y field bits
211	size_t l_width, // l field bits
212
213	size_t int_memc_tgt_id,
214	size_t int_xicu_tgt_id,
215	size_t int_mdma_tgt_id,
216	size_t int_drom_tgt_id,
217	size_t int_iobx_tgt_id,
218	size_t int_proc_ini_id,
219	size_t int_mdma_ini_id,
220	size_t int_iobx_ini_id,
221
222	size_t ram_xram_tgt_id,
223	size_t ram_memc_ini_id,
224	size_t ram_iobx_ini_id,
225
226	bool is_io,
227	size_t iox_iobx_tgt_id,
228	size_t iox_iobx_ini_id,
229
230	size_t memc_ways,
231	size_t memc_sets,
232	size_t l1_i_ways,
233	size_t l1_i_sets,
234	size_t l1_d_ways,
235	size_t l1_d_sets,
236	size_t xram_latency,
237	size_t xcu_nb_hwi,
238	size_t xcu_nb_pti,
239	size_t xcu_nb_wti,
240	size_t xcu_nb_out,
241	size_t irq_per_proc,
242
243	bool distboot,
244
245	const Loader &loader, // loader for XRAM
246
247	uint32_t frozen_cycles,
248	uint32_t start_debug_cycle,
249	bool memc_debug_ok,
250	bool proc_debug_ok,
251	bool iob0_debug_ok );
252
253	~TsarIobCluster();
254
255	protected:
256
257	SC_HAS_PROCESS(TsarIobCluster);
258
259	void init();
260
261
262	};
263
264	}}
265
266	#endif
267
268	// Local Variables:
269	// tab-width: 3
270	// c-basic-offset: 3
271	// c-file-offsets:((innamespace . 0)(inline-open . 0))
272	// indent-tabs-mode: nil
273	// End:
274
275	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
276	//

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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h @ 1001

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