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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 1000

Last change on this file since 1000 was 1000, checked in by cfuguet, 9 years ago
reconf: update simulation scripts and fix some minor bugs in the platform topcell.
File size: 34.4 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79	size_t irq_per_proc,
80
81	bool distboot,
82
83	const Loader &loader,
84
85	uint32_t frozen_cycles,
86	uint32_t debug_start_cycle,
87	bool memc_debug_ok,
88	bool proc_debug_ok,
89	bool iob_debug_ok ) :
90
91	// constructor initialization list
92
93	soclib::caba::BaseModule(insname),
94	p_clk("clk"),
95	p_resetn("resetn")
96	{
97
98	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
99
100	size_t cluster_id = (x_id << y_width) \| y_id;
101
102	// Vectors of DSPIN ports for inter-cluster communications
103	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
104	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
105	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
106	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
107
108	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
109	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
110	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
111	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
112
113	// VCI ports from IOB to IOX network (only in IO clusters)
114	if (is_io)
115	{
116	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
117	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
118	}
119
120	/////////////////////////////////////////////////////////////////////////////
121	// Hardware components
122	/////////////////////////////////////////////////////////////////////////////
123
124	//////////// PROCS
125	for (size_t p = 0; p < nb_procs; p++)
126	{
127	std::ostringstream s_proc;
128	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
129	proc[p] = new VciCcVCacheWrapper<vci_param_int,
130	dspin_int_cmd_width,
131	dspin_int_rsp_width,
132	GdbServer<Mips32ElIss> >(
133	s_proc.str().c_str(),
134	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
135	mt_int, // Mapping Table INT network
136	IntTab(cluster_id,p), // SRCID
137	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
138	8, // ITLB ways
139	8, // ITLB sets
140	8, // DTLB ways
141	8, // DTLB sets
142	l1_i_ways, l1_i_sets, 16, // ICACHE size
143	l1_d_ways, l1_d_sets, 16, // DCACHE size
144	4, // WBUF nlines
145	4, // WBUF nwords
146	x_width, // number of bits for x coordinate
147	y_width, // number of bits for y coordinate
148	frozen_cycles, // max frozen cycles
149	debug_start_cycle,
150	proc_debug_ok);
151
152	// initialize physical address extension with cluster ID when using
153	// distributed boot
154	if (distboot)
155	{
156	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
157	proc[p]->set_icache_paddr_ext_reset(cluster_id);
158	}
159	}
160
161	/////////// MEMC
162	std::ostringstream s_memc;
163	s_memc << "memc_" << x_id << "_" << y_id;
164	memc = new VciMemCache<vci_param_int,
165	vci_param_ext,
166	dspin_int_rsp_width,
167	dspin_int_cmd_width>(
168	s_memc.str().c_str(),
169	mt_int, // Mapping Table INT network
170	mt_ram, // Mapping Table RAM network
171	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
172	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
173	x_width, // number of bits for x coordinate
174	y_width, // number of bits for y coordinate
175	memc_ways, memc_sets, 16, // CACHE SIZE
176	3, // MAX NUMBER OF COPIES
177	4096, // HEAP SIZE
178	8, // TRANSACTION TABLE DEPTH
179	8, // UPDATE TABLE DEPTH
180	8, // INVALIDATE TABLE DEPTH
181	debug_start_cycle,
182	memc_debug_ok );
183
184	std::ostringstream s_wi_memc;
185	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
186	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
187	dspin_ram_cmd_width,
188	dspin_ram_rsp_width>(
189	s_wi_memc.str().c_str(),
190	x_width + y_width + l_width);
191
192	/////////// XICU
193	std::ostringstream s_xicu;
194	s_xicu << "xicu_" << x_id << "_" << y_id;
195	xicu = new VciXicu<vci_param_int>(
196	s_xicu.str().c_str(),
197	mt_int, // mapping table INT network
198	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
199	xcu_nb_pti, // number of timer IRQs
200	xcu_nb_hwi, // number of hard IRQs
201	xcu_nb_wti, // number of soft IRQs
202	xcu_nb_out, // number of output IRQs
203	5); // number of config regs
204
205	//////////// MDMA
206	std::ostringstream s_mdma;
207	s_mdma << "mdma_" << x_id << "_" << y_id;
208	mdma = new VciMultiDma<vci_param_int>(
209	s_mdma.str().c_str(),
210	mt_int,
211	IntTab(cluster_id, nb_procs), // SRCID
212	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
213	64, // burst size
214	nb_dmas); // number of IRQs
215
216	/////////// DISTRIBUTED ROM
217	std::ostringstream s_drom;
218	s_drom << "drom_" << x_id << "_" << y_id;
219	drom = new VciSimpleRom<vci_param_int>(
220	s_drom.str().c_str(),
221	IntTab(cluster_id, int_drom_tgt_id),
222	mt_int,
223	loader,
224	x_width + y_width); // msb drop bits
225
226	/////////// Direct LOCAL_XBAR(S)
227	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
228	size_t nb_direct_targets = is_io ? 5 : 4;
229
230	std::ostringstream s_int_xbar_d;
231	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
232	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
233	s_int_xbar_d.str().c_str(),
234	mt_int, // mapping table
235	cluster_id, // cluster id
236	nb_direct_initiators, // number of local initiators
237	nb_direct_targets, // number of local targets
238	0 ); // default target
239
240	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
241	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
242	<< x_id << "_" << y_id;
243	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
244	dspin_int_cmd_width,
245	dspin_int_rsp_width>(
246	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
247	x_width + y_width + l_width);
248
249	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
250	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
251	<< x_id << "_" << y_id;
252	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
253	dspin_int_cmd_width,
254	dspin_int_rsp_width>(
255	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
256	x_width + y_width + l_width);
257
258	//////////// Coherence LOCAL_XBAR(S)
259	std::ostringstream s_int_xbar_m2p_c;
260	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
261	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
262	s_int_xbar_m2p_c.str().c_str(),
263	mt_int, // mapping table
264	x_id, y_id, // cluster coordinates
265	x_width, y_width, l_width, // several dests
266	1, // number of local sources
267	nb_procs, // number of local dests
268	2, 2, // fifo depths
269	true, // pseudo CMD
270	false, // no routing table
271	true ); // broacast
272
273	std::ostringstream s_int_xbar_p2m_c;
274	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
275	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
276	s_int_xbar_p2m_c.str().c_str(),
277	mt_int, // mapping table
278	x_id, y_id, // cluster coordinates
279	x_width, y_width, 0, // only one dest
280	nb_procs, // number of local sources
281	1, // number of local dests
282	2, 2, // fifo depths
283	false, // pseudo RSP
284	false, // no routing table
285	false ); // no broacast
286
287	std::ostringstream s_int_xbar_clack_c;
288	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
289	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
290	s_int_xbar_clack_c.str().c_str(),
291	mt_int, // mapping table
292	x_id, y_id, // cluster coordinates
293	x_width, y_width, l_width,
294	1, // number of local sources
295	nb_procs, // number of local targets
296	1, 1, // fifo depths
297	true, // CMD
298	false, // no routing table
299	false); // broadcast
300
301	const bool ROUTER_CONFIG_SUPPORTED = true;
302
303	////////////// INT ROUTER(S)
304	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
305	for (int k = 0; k < 3; k++)
306	{
307	std::ostringstream s_int_router_cmd;
308	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
309	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
310	s_int_router_cmd.str().c_str(),
311	x_id, y_id,
312	x_width, y_width,
313	4, 4,
314	(k == 1),
315	ROUTER_CONFIG_SUPPORTED);
316	}
317
318	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
319	for (int k = 0; k < 2; k++)
320	{
321	std::ostringstream s_int_router_rsp;
322	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
323	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
324	s_int_router_rsp.str().c_str(),
325	x_id, y_id,
326	x_width, y_width,
327	4, 4,
328	false,
329	ROUTER_CONFIG_SUPPORTED);
330	}
331
332	////////////// XRAM
333	std::ostringstream s_xram;
334	s_xram << "xram_" << x_id << "_" << y_id;
335	xram = new VciSimpleRam<vci_param_ext>(
336	s_xram.str().c_str(),
337	IntTab(cluster_id, ram_xram_tgt_id),
338	mt_ram,
339	loader,
340	xram_latency);
341
342	std::ostringstream s_wt_xram;
343	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
344	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
345	dspin_ram_cmd_width,
346	dspin_ram_rsp_width>(
347	s_wt_xram.str().c_str(),
348	x_width + y_width + l_width);
349
350	///////////// RAM ROUTER(S)
351	std::ostringstream s_ram_router_cmd;
352	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
353	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
354	s_ram_router_cmd.str().c_str(),
355	x_id, y_id, // router coordinates in mesh
356	x_width, // x field width in first flit
357	y_width, // y field width in first flit
358	4, 4); // input & output fifo depths
359
360	std::ostringstream s_ram_router_rsp;
361	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
362	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
363	s_ram_router_rsp.str().c_str(),
364	x_id, y_id, // coordinates in mesh
365	x_width, // x field width in first flit
366	y_width, // y field width in first flit
367	4, 4); // input & output fifo depths
368
369
370	////////////////////// I/O CLUSTER ONLY ///////////////////////
371	if ( is_io )
372	{
373	/////////// IO_BRIDGE
374	std::ostringstream s_iob;
375	s_iob << "iob_" << x_id << "_" << y_id;
376	iob = new VciIoBridge<vci_param_int,
377	vci_param_ext>(
378	s_iob.str().c_str(),
379	mt_ram, // EXT network maptab
380	mt_int, // INT network maptab
381	mt_iox, // IOX network maptab
382	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
383	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
384	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
385	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
386	16, // cache line words
387	8, // IOTLB ways
388	8, // IOTLB sets
389	debug_start_cycle,
390	iob_debug_ok );
391
392	std::ostringstream s_iob_ram_wi;
393	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
394	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
395	dspin_ram_cmd_width,
396	dspin_ram_rsp_width>(
397	s_iob_ram_wi.str().c_str(),
398	vci_param_int::S);
399
400	std::ostringstream s_ram_xbar_cmd;
401	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
402	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
403	s_ram_xbar_cmd.str().c_str(), // name
404	mt_ram, // mapping table
405	x_id, y_id, // x, y
406	x_width, y_width, l_width, // x_width, y_width, l_width
407	2, 0, // local inputs, local outputs
408	2, 2, // in fifo, out fifo depths
409	true, // is cmd ?
410	false, // use routing table ?
411	false); // support broadcast ?
412
413	std::ostringstream s_ram_xbar_rsp;
414	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
415	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
416	s_ram_xbar_rsp.str().c_str(), // name
417	mt_ram, // mapping table
418	x_id, y_id, // x, y
419	x_width, y_width, l_width, // x_width, y_width, l_width
420	0, 2, // local inputs, local outputs
421	2, 2, // in fifo, out fifo depths
422	false, // is cmd ?
423	true, // use routing table ?
424	false); // support broadcast ?
425	} // end if IO
426
427	////////////////////////////////////
428	// Connections are defined here
429	////////////////////////////////////
430
431	// on coherence network : local srcid[proc] in [0...nb_procs-1]
432	// : local srcid[memc] = nb_procs
433
434	//////////////////////// internal CMD & RSP routers
435	for(int k = 0; k < 3; k++)
436	{
437	int_router_cmd[k]->p_clk (this->p_clk);
438	int_router_cmd[k]->p_resetn (this->p_resetn);
439	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
440	for (int i = 0; i < 4; i++)
441	{
442	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
443	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
444	}
445	}
446
447	for(int k = 0; k < 2; k++)
448	{
449	int_router_rsp[k]->p_clk (this->p_clk);
450	int_router_rsp[k]->p_resetn (this->p_resetn);
451	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
452	for (int i = 0; i < 4; i++)
453	{
454	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
455	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
456	}
457	}
458
459	// local ports
460	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
461	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
462	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
463	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
464	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
465	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
466
467	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
468	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
469	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
470	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
471
472	///////////////////// CMD DSPIN local crossbar direct
473	int_xbar_d->p_clk (this->p_clk);
474	int_xbar_d->p_resetn (this->p_resetn);
475	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
476	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
477
478	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
479	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
480	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
481	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
482	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
483	for (size_t p = 0; p < nb_procs; p++)
484	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
485
486	if ( is_io )
487	{
488	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
489	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
490	}
491
492	int_wi_gate_d->p_clk (this->p_clk);
493	int_wi_gate_d->p_resetn (this->p_resetn);
494	int_wi_gate_d->p_vci (signal_int_vci_l2g);
495	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
496	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
497
498	int_wt_gate_d->p_clk (this->p_clk);
499	int_wt_gate_d->p_resetn (this->p_resetn);
500	int_wt_gate_d->p_vci (signal_int_vci_g2l);
501	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
502	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
503
504	////////////////////// M2P DSPIN local crossbar coherence
505	int_xbar_m2p_c->p_clk (this->p_clk);
506	int_xbar_m2p_c->p_resetn (this->p_resetn);
507	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
508	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
509	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
510	for (size_t p = 0; p < nb_procs; p++)
511	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
512
513	////////////////////////// P2M DSPIN local crossbar coherence
514	int_xbar_p2m_c->p_clk (this->p_clk);
515	int_xbar_p2m_c->p_resetn (this->p_resetn);
516	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
517	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
518	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
519	for (size_t p = 0; p < nb_procs; p++)
520	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
521
522	////////////////////// CLACK DSPIN local crossbar coherence
523	int_xbar_clack_c->p_clk (this->p_clk);
524	int_xbar_clack_c->p_resetn (this->p_resetn);
525	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
526	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
527	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
528	for (size_t p = 0; p < nb_procs; p++)
529	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
530
531	//////////////////////////////////// Processors
532	for (size_t p = 0; p < nb_procs; p++)
533	{
534	proc[p]->p_clk (this->p_clk);
535	proc[p]->p_resetn (this->p_resetn);
536	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
537	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
538	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
539	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
540
541	for ( size_t j = 0 ; j < 6 ; j++)
542	{
543	if ( j < irq_per_proc )
544	{
545	proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]);
546	}
547	else
548	{
549	proc[p]->p_irq[j] (signal_false);
550	}
551	}
552	}
553
554	///////////////////////////////////// XICU
555	xicu->p_clk (this->p_clk);
556	xicu->p_resetn (this->p_resetn);
557	xicu->p_vci (signal_int_vci_tgt_xicu);
558	for ( size_t i=0 ; i < xcu_nb_out ; i++)
559	{
560	xicu->p_irq[i] (signal_proc_it[i]);
561	}
562	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
563	{
564	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
565	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
566	else xicu->p_hwi[i] (signal_false);
567	}
568	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
569	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
570	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
571	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
572	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
573
574	///////////////////////////////////// MEMC
575	memc->p_clk (this->p_clk);
576	memc->p_resetn (this->p_resetn);
577	memc->p_vci_ixr (signal_ram_vci_ini_memc);
578	memc->p_vci_tgt (signal_int_vci_tgt_memc);
579	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
580	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
581	memc->p_dspin_clack (signal_int_dspin_clack_memc);
582	memc->p_irq (signal_irq_memc);
583
584	// wrapper to RAM network
585	memc_ram_wi->p_clk (this->p_clk);
586	memc_ram_wi->p_resetn (this->p_resetn);
587	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
588	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
589	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
590
591	//////////////////////////////////// XRAM
592	xram->p_clk (this->p_clk);
593	xram->p_resetn (this->p_resetn);
594	xram->p_vci (signal_ram_vci_tgt_xram);
595
596	// wrapper to RAM network
597	xram_ram_wt->p_clk (this->p_clk);
598	xram_ram_wt->p_resetn (this->p_resetn);
599	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
600	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
601	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
602
603	/////////////////////////////////// MDMA
604	mdma->p_clk (this->p_clk);
605	mdma->p_resetn (this->p_resetn);
606	mdma->p_vci_target (signal_int_vci_tgt_mdma);
607	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
608	for (size_t i=0 ; i<nb_dmas ; i++)
609	mdma->p_irq[i] (signal_irq_mdma[i]);
610
611	/////////////////////////////////// DROM
612	drom->p_clk (this->p_clk);
613	drom->p_resetn (this->p_resetn);
614	drom->p_vci (signal_int_vci_tgt_drom);
615
616	//////////////////////////// RAM network CMD & RSP routers
617	ram_router_cmd->p_clk (this->p_clk);
618	ram_router_cmd->p_resetn (this->p_resetn);
619	ram_router_rsp->p_clk (this->p_clk);
620	ram_router_rsp->p_resetn (this->p_resetn);
621	for( size_t n=0 ; n<4 ; n++)
622	{
623	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
624	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
625	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
626	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
627	}
628
629	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
630	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
631
632	if ( is_io )
633	{
634	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
635	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
636	}
637	else
638	{
639	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
640	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
641	}
642
643	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
644	if ( is_io )
645	{
646	// IO bridge
647	iob->p_clk (this->p_clk);
648	iob->p_resetn (this->p_resetn);
649	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
650	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
651	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
652	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
653	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
654
655	// initiator wrapper to RAM network
656	iob_ram_wi->p_clk (this->p_clk);
657	iob_ram_wi->p_resetn (this->p_resetn);
658	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
659	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
660	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
661
662	// crossbar between MEMC and IOB to RAM network
663	ram_xbar_cmd->p_clk (this->p_clk);
664	ram_xbar_cmd->p_resetn (this->p_resetn);
665	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
666	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
667	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
668	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
669
670	ram_xbar_rsp->p_clk (this->p_clk);
671	ram_xbar_rsp->p_resetn (this->p_resetn);
672	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
673	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
674	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
675	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
676	}
677
678	SC_METHOD(init);
679
680	} // end constructor
681
682	tmpl(void)::init()
683	{
684	signal_ram_dspin_cmd_false.write = false;
685	signal_ram_dspin_rsp_false.read = true;
686	} // end init
687
688	tmpl(/**/)::~TsarIobCluster()
689	{
690	for (int k = 0; k < 3; k++)
691	{
692	delete int_router_cmd[k];
693	}
694	delete [] int_router_cmd;
695
696	for (int k = 0; k < 2; k++)
697	{
698	delete int_router_rsp[k];
699	}
700	delete [] int_router_rsp;
701	}
702
703	}}
704
705
706	// Local Variables:
707	// tab-width: 4
708	// c-basic-offset: 4
709	// c-file-offsets:((innamespace . 0)(inline-open . 0))
710	// indent-tabs-mode: nil
711	// End:
712
713	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
714

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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