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tsar_iob_cluster.cpp @ 931

Last change on this file since 931 was 931, checked in by cfuguet, 9 years ago

reconf: introducing the segment recovery mechanism in the dspin_router

The p_recovery_cfg port, connected through a signal to a config register in the XICU, is formatted in two fields: the 4 LSb contain the blackhole relative position and the 4 bits after contain the recovery direction.

A request with the blackhole cluster as destination is rerouted through the defined recovery direction.

Remove the reconfiguration parameter of the constructor. The p_recovery_cfg port is instantiated when the bind_recovery_port is called. This port is also connected during this function to the signal that is passed as an argument.

File size: 34.0 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_inputs,
76
77	bool distboot,
78
79	const Loader &loader,
80
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok,
85	bool iob_debug_ok ) :
86
87	// constructor initialization list
88
89	soclib::caba::BaseModule(insname),
90	p_clk("clk"),
91	p_resetn("resetn")
92	{
93
94	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
95
96	size_t cluster_id = (x_id << x_width) \| y_id;
97
98	// Vectors of DSPIN ports for inter-cluster communications
99	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
100	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
101	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
102	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
103
104	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
105	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
106	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
107	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
108
109	// VCI ports from IOB to IOX network (only in IO clusters)
110	if (is_io)
111	{
112	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
113	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
114	}
115
116	/////////////////////////////////////////////////////////////////////////////
117	// Hardware components
118	/////////////////////////////////////////////////////////////////////////////
119
120	//////////// PROCS
121	for (size_t p = 0; p < nb_procs; p++)
122	{
123	std::ostringstream s_proc;
124	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
125	proc[p] = new VciCcVCacheWrapper<vci_param_int,
126	dspin_int_cmd_width,
127	dspin_int_rsp_width,
128	GdbServer<Mips32ElIss> >(
129	s_proc.str().c_str(),
130	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
131	mt_int, // Mapping Table INT network
132	IntTab(cluster_id,p), // SRCID
133	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
134	8, // ITLB ways
135	8, // ITLB sets
136	8, // DTLB ways
137	8, // DTLB sets
138	l1_i_ways, l1_i_sets, 16, // ICACHE size
139	l1_d_ways, l1_d_sets, 16, // DCACHE size
140	4, // WBUF nlines
141	4, // WBUF nwords
142	x_width, // number of bits for x coordinate
143	y_width, // number of bits for y coordinate
144	frozen_cycles, // max frozen cycles
145	debug_start_cycle,
146	proc_debug_ok);
147
148	// initialize physical address extension with cluster ID when using
149	// distributed boot
150	if (distboot)
151	{
152	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
153	proc[p]->set_icache_paddr_ext_reset(cluster_id);
154	}
155	}
156
157	/////////// MEMC
158	std::ostringstream s_memc;
159	s_memc << "memc_" << x_id << "_" << y_id;
160	memc = new VciMemCache<vci_param_int,
161	vci_param_ext,
162	dspin_int_rsp_width,
163	dspin_int_cmd_width>(
164	s_memc.str().c_str(),
165	mt_int, // Mapping Table INT network
166	mt_ram, // Mapping Table RAM network
167	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
168	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
169	x_width, // number of bits for x coordinate
170	y_width, // number of bits for y coordinate
171	memc_ways, memc_sets, 16, // CACHE SIZE
172	3, // MAX NUMBER OF COPIES
173	4096, // HEAP SIZE
174	8, // TRANSACTION TABLE DEPTH
175	8, // UPDATE TABLE DEPTH
176	8, // INVALIDATE TABLE DEPTH
177	debug_start_cycle,
178	memc_debug_ok );
179
180	std::ostringstream s_wi_memc;
181	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
182	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
183	dspin_ram_cmd_width,
184	dspin_ram_rsp_width>(
185	s_wi_memc.str().c_str(),
186	x_width + y_width + l_width);
187
188	/////////// XICU
189	std::ostringstream s_xicu;
190	s_xicu << "xicu_" << x_id << "_" << y_id;
191	xicu = new VciXicu<vci_param_int>(
192	s_xicu.str().c_str(),
193	mt_int, // mapping table INT network
194	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
195	xcu_nb_inputs, // number of timer IRQs
196	xcu_nb_inputs, // number of hard IRQs
197	xcu_nb_inputs, // number of soft IRQs
198	16, // number of output IRQs
199	5); // number of config regs
200
201	//////////// MDMA
202	std::ostringstream s_mdma;
203	s_mdma << "mdma_" << x_id << "_" << y_id;
204	mdma = new VciMultiDma<vci_param_int>(
205	s_mdma.str().c_str(),
206	mt_int,
207	IntTab(cluster_id, nb_procs), // SRCID
208	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
209	64, // burst size
210	nb_dmas); // number of IRQs
211
212	/////////// DISTRIBUTED ROM
213	std::ostringstream s_drom;
214	s_drom << "drom_" << x_id << "_" << y_id;
215	drom = new VciSimpleRom<vci_param_int>(
216	s_drom.str().c_str(),
217	IntTab(cluster_id, int_drom_tgt_id),
218	mt_int,
219	loader,
220	x_width + y_width); // msb drop bits
221
222	/////////// Direct LOCAL_XBAR(S)
223	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
224	size_t nb_direct_targets = is_io ? 5 : 4;
225
226	std::ostringstream s_int_xbar_d;
227	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
228	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
229	s_int_xbar_d.str().c_str(),
230	mt_int, // mapping table
231	cluster_id, // cluster id
232	nb_direct_initiators, // number of local initiators
233	nb_direct_targets, // number of local targets
234	0 ); // default target
235
236	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
237	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
238	<< x_id << "_" << y_id;
239	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
240	dspin_int_cmd_width,
241	dspin_int_rsp_width>(
242	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
243	x_width + y_width + l_width);
244
245	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
246	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
247	<< x_id << "_" << y_id;
248	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
249	dspin_int_cmd_width,
250	dspin_int_rsp_width>(
251	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
252	x_width + y_width + l_width);
253
254	//////////// Coherence LOCAL_XBAR(S)
255	std::ostringstream s_int_xbar_m2p_c;
256	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
257	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
258	s_int_xbar_m2p_c.str().c_str(),
259	mt_int, // mapping table
260	x_id, y_id, // cluster coordinates
261	x_width, y_width, l_width, // several dests
262	1, // number of local sources
263	nb_procs, // number of local dests
264	2, 2, // fifo depths
265	true, // pseudo CMD
266	false, // no routing table
267	true ); // broacast
268
269	std::ostringstream s_int_xbar_p2m_c;
270	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
271	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
272	s_int_xbar_p2m_c.str().c_str(),
273	mt_int, // mapping table
274	x_id, y_id, // cluster coordinates
275	x_width, y_width, 0, // only one dest
276	nb_procs, // number of local sources
277	1, // number of local dests
278	2, 2, // fifo depths
279	false, // pseudo RSP
280	false, // no routing table
281	false ); // no broacast
282
283	std::ostringstream s_int_xbar_clack_c;
284	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
285	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
286	s_int_xbar_clack_c.str().c_str(),
287	mt_int, // mapping table
288	x_id, y_id, // cluster coordinates
289	x_width, y_width, l_width,
290	1, // number of local sources
291	nb_procs, // number of local targets
292	1, 1, // fifo depths
293	true, // CMD
294	false, // no routing table
295	false); // broadcast
296
297	////////////// INT ROUTER(S)
298	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
299	for (int k = 0; k < 3; k++)
300	{
301	std::ostringstream s_int_router_cmd;
302	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
303	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
304	s_int_router_cmd.str().c_str(),
305	x_id, y_id,
306	x_width, y_width,
307	4, 4,
308	(k == 1));
309	}
310
311	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
312	for (int k = 0; k < 2; k++)
313	{
314	std::ostringstream s_int_router_rsp;
315	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
316	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
317	s_int_router_rsp.str().c_str(),
318	x_id, y_id,
319	x_width, y_width,
320	4, 4,
321	false);
322	}
323
324	////////////// XRAM
325	std::ostringstream s_xram;
326	s_xram << "xram_" << x_id << "_" << y_id;
327	xram = new VciSimpleRam<vci_param_ext>(
328	s_xram.str().c_str(),
329	IntTab(cluster_id, ram_xram_tgt_id),
330	mt_ram,
331	loader,
332	xram_latency);
333
334	std::ostringstream s_wt_xram;
335	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
336	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
337	dspin_ram_cmd_width,
338	dspin_ram_rsp_width>(
339	s_wt_xram.str().c_str(),
340	x_width + y_width + l_width);
341
342	///////////// RAM ROUTER(S)
343	std::ostringstream s_ram_router_cmd;
344	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
345	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
346	s_ram_router_cmd.str().c_str(),
347	x_id, y_id, // router coordinates in mesh
348	x_width, // x field width in first flit
349	y_width, // y field width in first flit
350	4, 4); // input & output fifo depths
351
352	std::ostringstream s_ram_router_rsp;
353	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
354	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
355	s_ram_router_rsp.str().c_str(),
356	x_id, y_id, // coordinates in mesh
357	x_width, // x field width in first flit
358	y_width, // y field width in first flit
359	4, 4); // input & output fifo depths
360
361
362	////////////////////// I/O CLUSTER ONLY ///////////////////////
363	if ( is_io )
364	{
365	/////////// IO_BRIDGE
366	std::ostringstream s_iob;
367	s_iob << "iob_" << x_id << "_" << y_id;
368	iob = new VciIoBridge<vci_param_int,
369	vci_param_ext>(
370	s_iob.str().c_str(),
371	mt_ram, // EXT network maptab
372	mt_int, // INT network maptab
373	mt_iox, // IOX network maptab
374	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
375	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
376	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
377	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
378	16, // cache line words
379	8, // IOTLB ways
380	8, // IOTLB sets
381	debug_start_cycle,
382	iob_debug_ok );
383
384	std::ostringstream s_iob_ram_wi;
385	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
386	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
387	dspin_ram_cmd_width,
388	dspin_ram_rsp_width>(
389	s_iob_ram_wi.str().c_str(),
390	vci_param_int::S);
391
392	std::ostringstream s_ram_xbar_cmd;
393	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
394	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
395	s_ram_xbar_cmd.str().c_str(), // name
396	mt_ram, // mapping table
397	x_id, y_id, // x, y
398	x_width, y_width, l_width, // x_width, y_width, l_width
399	2, 0, // local inputs, local outputs
400	2, 2, // in fifo, out fifo depths
401	true, // is cmd ?
402	false, // use routing table ?
403	false); // support broadcast ?
404
405	std::ostringstream s_ram_xbar_rsp;
406	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
407	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
408	s_ram_xbar_rsp.str().c_str(), // name
409	mt_ram, // mapping table
410	x_id, y_id, // x, y
411	x_width, y_width, l_width, // x_width, y_width, l_width
412	0, 2, // local inputs, local outputs
413	2, 2, // in fifo, out fifo depths
414	false, // is cmd ?
415	true, // use routing table ?
416	false); // support broadcast ?
417	} // end if IO
418
419	////////////////////////////////////
420	// Connections are defined here
421	////////////////////////////////////
422
423	// on coherence network : local srcid[proc] in [0...nb_procs-1]
424	// : local srcid[memc] = nb_procs
425
426	//////////////////////// internal CMD & RSP routers
427	for(int k = 0; k < 3; k++)
428	{
429	int_router_cmd[k]->p_clk (this->p_clk);
430	int_router_cmd[k]->p_resetn (this->p_resetn);
431	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
432	for (int i = 0; i < 4; i++)
433	{
434	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
435	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
436	}
437	}
438
439	for(int k = 0; k < 2; k++)
440	{
441	int_router_rsp[k]->p_clk (this->p_clk);
442	int_router_rsp[k]->p_resetn (this->p_resetn);
443	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
444	for (int i = 0; i < 4; i++)
445	{
446	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
447	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
448	}
449	}
450
451	// local ports
452	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
453	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
454	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
455	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
456	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
457	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
458
459	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
460	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
461	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
462	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
463
464	///////////////////// CMD DSPIN local crossbar direct
465	int_xbar_d->p_clk (this->p_clk);
466	int_xbar_d->p_resetn (this->p_resetn);
467	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
468	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
469
470	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
471	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
472	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
473	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
474	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
475	for (size_t p = 0; p < nb_procs; p++)
476	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
477
478	if ( is_io )
479	{
480	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
481	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
482	}
483
484	int_wi_gate_d->p_clk (this->p_clk);
485	int_wi_gate_d->p_resetn (this->p_resetn);
486	int_wi_gate_d->p_vci (signal_int_vci_l2g);
487	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
488	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
489
490	int_wt_gate_d->p_clk (this->p_clk);
491	int_wt_gate_d->p_resetn (this->p_resetn);
492	int_wt_gate_d->p_vci (signal_int_vci_g2l);
493	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
494	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
495
496	////////////////////// M2P DSPIN local crossbar coherence
497	int_xbar_m2p_c->p_clk (this->p_clk);
498	int_xbar_m2p_c->p_resetn (this->p_resetn);
499	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
500	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
501	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
502	for (size_t p = 0; p < nb_procs; p++)
503	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
504
505	////////////////////////// P2M DSPIN local crossbar coherence
506	int_xbar_p2m_c->p_clk (this->p_clk);
507	int_xbar_p2m_c->p_resetn (this->p_resetn);
508	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
509	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
510	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
511	for (size_t p = 0; p < nb_procs; p++)
512	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
513
514	////////////////////// CLACK DSPIN local crossbar coherence
515	int_xbar_clack_c->p_clk (this->p_clk);
516	int_xbar_clack_c->p_resetn (this->p_resetn);
517	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
518	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
519	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
520	for (size_t p = 0; p < nb_procs; p++)
521	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
522
523	//////////////////////////////////// Processors
524	for (size_t p = 0; p < nb_procs; p++)
525	{
526	proc[p]->p_clk (this->p_clk);
527	proc[p]->p_resetn (this->p_resetn);
528	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
529	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
530	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
531	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
532
533	for ( size_t j = 0 ; j < 6 ; j++)
534	{
535	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
536	else proc[p]->p_irq[j] (signal_false);
537	}
538	}
539
540	///////////////////////////////////// XICU
541	xicu->p_clk (this->p_clk);
542	xicu->p_resetn (this->p_resetn);
543	xicu->p_vci (signal_int_vci_tgt_xicu);
544	for ( size_t i=0 ; i < 16 ; i++)
545	{
546	xicu->p_irq[i] (signal_proc_it[i]);
547	}
548	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
549	{
550	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
551	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
552	else xicu->p_hwi[i] (signal_false);
553	}
554	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
555	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
556	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
557	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
558	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
559
560	///////////////////////////////////// MEMC
561	memc->p_clk (this->p_clk);
562	memc->p_resetn (this->p_resetn);
563	memc->p_vci_ixr (signal_ram_vci_ini_memc);
564	memc->p_vci_tgt (signal_int_vci_tgt_memc);
565	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
566	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
567	memc->p_dspin_clack (signal_int_dspin_clack_memc);
568	memc->p_irq (signal_irq_memc);
569
570	// wrapper to RAM network
571	memc_ram_wi->p_clk (this->p_clk);
572	memc_ram_wi->p_resetn (this->p_resetn);
573	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
574	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
575	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
576
577	//////////////////////////////////// XRAM
578	xram->p_clk (this->p_clk);
579	xram->p_resetn (this->p_resetn);
580	xram->p_vci (signal_ram_vci_tgt_xram);
581
582	// wrapper to RAM network
583	xram_ram_wt->p_clk (this->p_clk);
584	xram_ram_wt->p_resetn (this->p_resetn);
585	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
586	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
587	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
588
589	/////////////////////////////////// MDMA
590	mdma->p_clk (this->p_clk);
591	mdma->p_resetn (this->p_resetn);
592	mdma->p_vci_target (signal_int_vci_tgt_mdma);
593	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
594	for (size_t i=0 ; i<nb_dmas ; i++)
595	mdma->p_irq[i] (signal_irq_mdma[i]);
596
597	/////////////////////////////////// DROM
598	drom->p_clk (this->p_clk);
599	drom->p_resetn (this->p_resetn);
600	drom->p_vci (signal_int_vci_tgt_drom);
601
602	//////////////////////////// RAM network CMD & RSP routers
603	ram_router_cmd->p_clk (this->p_clk);
604	ram_router_cmd->p_resetn (this->p_resetn);
605	ram_router_rsp->p_clk (this->p_clk);
606	ram_router_rsp->p_resetn (this->p_resetn);
607	for( size_t n=0 ; n<4 ; n++)
608	{
609	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
610	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
611	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
612	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
613	}
614
615	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
616	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
617
618	if ( is_io )
619	{
620	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
621	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
622	}
623	else
624	{
625	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
626	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
627	}
628
629	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
630	if ( is_io )
631	{
632	// IO bridge
633	iob->p_clk (this->p_clk);
634	iob->p_resetn (this->p_resetn);
635	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
636	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
637	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
638	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
639	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
640
641	// initiator wrapper to RAM network
642	iob_ram_wi->p_clk (this->p_clk);
643	iob_ram_wi->p_resetn (this->p_resetn);
644	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
645	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
646	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
647
648	// crossbar between MEMC and IOB to RAM network
649	ram_xbar_cmd->p_clk (this->p_clk);
650	ram_xbar_cmd->p_resetn (this->p_resetn);
651	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
652	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
653	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
654	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
655
656	ram_xbar_rsp->p_clk (this->p_clk);
657	ram_xbar_rsp->p_resetn (this->p_resetn);
658	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
659	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
660	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
661	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
662	}
663
664	SC_METHOD(init);
665
666	} // end constructor
667
668	tmpl(void)::init()
669	{
670	signal_ram_dspin_cmd_false.write = false;
671	signal_ram_dspin_rsp_false.read = true;
672	} // end init
673
674	tmpl(/**/)::~TsarIobCluster()
675	{
676	for (int k = 0; k < 3; k++)
677	{
678	delete int_router_cmd[k];
679	}
680	delete [] int_router_cmd;
681
682	for (int k = 0; k < 2; k++)
683	{
684	delete int_router_rsp[k];
685	}
686	delete [] int_router_rsp;
687	}
688
689	}}
690
691
692	// Local Variables:
693	// tab-width: 4
694	// c-basic-offset: 4
695	// c-file-offsets:((innamespace . 0)(inline-open . 0))
696	// indent-tabs-mode: nil
697	// End:
698
699	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
700

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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 931

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