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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 961

Last change on this file since 961 was 961, checked in by cfuguet, 9 years ago

reconf: merge commit 959 concerning parameters of the XICU

All four parameters (HWI, PTI, WTI and IRQ) has their own width constant in the hard_config.h.

File size: 34.1 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79
80	bool distboot,
81
82	const Loader &loader,
83
84	uint32_t frozen_cycles,
85	uint32_t debug_start_cycle,
86	bool memc_debug_ok,
87	bool proc_debug_ok,
88	bool iob_debug_ok ) :
89
90	// constructor initialization list
91
92	soclib::caba::BaseModule(insname),
93	p_clk("clk"),
94	p_resetn("resetn")
95	{
96
97	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
98
99	size_t cluster_id = (x_id << x_width) \| y_id;
100
101	// Vectors of DSPIN ports for inter-cluster communications
102	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
103	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
104	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
105	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
106
107	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
108	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
109	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
110	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
111
112	// VCI ports from IOB to IOX network (only in IO clusters)
113	if (is_io)
114	{
115	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
116	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
117	}
118
119	/////////////////////////////////////////////////////////////////////////////
120	// Hardware components
121	/////////////////////////////////////////////////////////////////////////////
122
123	//////////// PROCS
124	for (size_t p = 0; p < nb_procs; p++)
125	{
126	std::ostringstream s_proc;
127	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
128	proc[p] = new VciCcVCacheWrapper<vci_param_int,
129	dspin_int_cmd_width,
130	dspin_int_rsp_width,
131	GdbServer<Mips32ElIss> >(
132	s_proc.str().c_str(),
133	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
134	mt_int, // Mapping Table INT network
135	IntTab(cluster_id,p), // SRCID
136	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
137	8, // ITLB ways
138	8, // ITLB sets
139	8, // DTLB ways
140	8, // DTLB sets
141	l1_i_ways, l1_i_sets, 16, // ICACHE size
142	l1_d_ways, l1_d_sets, 16, // DCACHE size
143	4, // WBUF nlines
144	4, // WBUF nwords
145	x_width, // number of bits for x coordinate
146	y_width, // number of bits for y coordinate
147	frozen_cycles, // max frozen cycles
148	debug_start_cycle,
149	proc_debug_ok);
150
151	// initialize physical address extension with cluster ID when using
152	// distributed boot
153	if (distboot)
154	{
155	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
156	proc[p]->set_icache_paddr_ext_reset(cluster_id);
157	}
158	}
159
160	/////////// MEMC
161	std::ostringstream s_memc;
162	s_memc << "memc_" << x_id << "_" << y_id;
163	memc = new VciMemCache<vci_param_int,
164	vci_param_ext,
165	dspin_int_rsp_width,
166	dspin_int_cmd_width>(
167	s_memc.str().c_str(),
168	mt_int, // Mapping Table INT network
169	mt_ram, // Mapping Table RAM network
170	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
171	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
172	x_width, // number of bits for x coordinate
173	y_width, // number of bits for y coordinate
174	memc_ways, memc_sets, 16, // CACHE SIZE
175	3, // MAX NUMBER OF COPIES
176	4096, // HEAP SIZE
177	8, // TRANSACTION TABLE DEPTH
178	8, // UPDATE TABLE DEPTH
179	8, // INVALIDATE TABLE DEPTH
180	debug_start_cycle,
181	memc_debug_ok );
182
183	std::ostringstream s_wi_memc;
184	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
185	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
186	dspin_ram_cmd_width,
187	dspin_ram_rsp_width>(
188	s_wi_memc.str().c_str(),
189	x_width + y_width + l_width);
190
191	/////////// XICU
192	std::ostringstream s_xicu;
193	s_xicu << "xicu_" << x_id << "_" << y_id;
194	xicu = new VciXicu<vci_param_int>(
195	s_xicu.str().c_str(),
196	mt_int, // mapping table INT network
197	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
198	xcu_nb_pti, // number of timer IRQs
199	xcu_nb_hwi, // number of hard IRQs
200	xcu_nb_wti, // number of soft IRQs
201	xcu_nb_out, // number of output IRQs
202	5); // number of config regs
203
204	//////////// MDMA
205	std::ostringstream s_mdma;
206	s_mdma << "mdma_" << x_id << "_" << y_id;
207	mdma = new VciMultiDma<vci_param_int>(
208	s_mdma.str().c_str(),
209	mt_int,
210	IntTab(cluster_id, nb_procs), // SRCID
211	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
212	64, // burst size
213	nb_dmas); // number of IRQs
214
215	/////////// DISTRIBUTED ROM
216	std::ostringstream s_drom;
217	s_drom << "drom_" << x_id << "_" << y_id;
218	drom = new VciSimpleRom<vci_param_int>(
219	s_drom.str().c_str(),
220	IntTab(cluster_id, int_drom_tgt_id),
221	mt_int,
222	loader,
223	x_width + y_width); // msb drop bits
224
225	/////////// Direct LOCAL_XBAR(S)
226	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
227	size_t nb_direct_targets = is_io ? 5 : 4;
228
229	std::ostringstream s_int_xbar_d;
230	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
231	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
232	s_int_xbar_d.str().c_str(),
233	mt_int, // mapping table
234	cluster_id, // cluster id
235	nb_direct_initiators, // number of local initiators
236	nb_direct_targets, // number of local targets
237	0 ); // default target
238
239	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
240	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
241	<< x_id << "_" << y_id;
242	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
243	dspin_int_cmd_width,
244	dspin_int_rsp_width>(
245	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
246	x_width + y_width + l_width);
247
248	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
249	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
250	<< x_id << "_" << y_id;
251	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
252	dspin_int_cmd_width,
253	dspin_int_rsp_width>(
254	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
255	x_width + y_width + l_width);
256
257	//////////// Coherence LOCAL_XBAR(S)
258	std::ostringstream s_int_xbar_m2p_c;
259	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
260	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
261	s_int_xbar_m2p_c.str().c_str(),
262	mt_int, // mapping table
263	x_id, y_id, // cluster coordinates
264	x_width, y_width, l_width, // several dests
265	1, // number of local sources
266	nb_procs, // number of local dests
267	2, 2, // fifo depths
268	true, // pseudo CMD
269	false, // no routing table
270	true ); // broacast
271
272	std::ostringstream s_int_xbar_p2m_c;
273	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
274	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
275	s_int_xbar_p2m_c.str().c_str(),
276	mt_int, // mapping table
277	x_id, y_id, // cluster coordinates
278	x_width, y_width, 0, // only one dest
279	nb_procs, // number of local sources
280	1, // number of local dests
281	2, 2, // fifo depths
282	false, // pseudo RSP
283	false, // no routing table
284	false ); // no broacast
285
286	std::ostringstream s_int_xbar_clack_c;
287	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
288	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
289	s_int_xbar_clack_c.str().c_str(),
290	mt_int, // mapping table
291	x_id, y_id, // cluster coordinates
292	x_width, y_width, l_width,
293	1, // number of local sources
294	nb_procs, // number of local targets
295	1, 1, // fifo depths
296	true, // CMD
297	false, // no routing table
298	false); // broadcast
299
300	////////////// INT ROUTER(S)
301	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
302	for (int k = 0; k < 3; k++)
303	{
304	std::ostringstream s_int_router_cmd;
305	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
306	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
307	s_int_router_cmd.str().c_str(),
308	x_id, y_id,
309	x_width, y_width,
310	4, 4,
311	(k == 1));
312	}
313
314	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
315	for (int k = 0; k < 2; k++)
316	{
317	std::ostringstream s_int_router_rsp;
318	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
319	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
320	s_int_router_rsp.str().c_str(),
321	x_id, y_id,
322	x_width, y_width,
323	4, 4,
324	false);
325	}
326
327	////////////// XRAM
328	std::ostringstream s_xram;
329	s_xram << "xram_" << x_id << "_" << y_id;
330	xram = new VciSimpleRam<vci_param_ext>(
331	s_xram.str().c_str(),
332	IntTab(cluster_id, ram_xram_tgt_id),
333	mt_ram,
334	loader,
335	xram_latency);
336
337	std::ostringstream s_wt_xram;
338	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
339	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
340	dspin_ram_cmd_width,
341	dspin_ram_rsp_width>(
342	s_wt_xram.str().c_str(),
343	x_width + y_width + l_width);
344
345	///////////// RAM ROUTER(S)
346	std::ostringstream s_ram_router_cmd;
347	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
348	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
349	s_ram_router_cmd.str().c_str(),
350	x_id, y_id, // router coordinates in mesh
351	x_width, // x field width in first flit
352	y_width, // y field width in first flit
353	4, 4); // input & output fifo depths
354
355	std::ostringstream s_ram_router_rsp;
356	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
357	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
358	s_ram_router_rsp.str().c_str(),
359	x_id, y_id, // coordinates in mesh
360	x_width, // x field width in first flit
361	y_width, // y field width in first flit
362	4, 4); // input & output fifo depths
363
364
365	////////////////////// I/O CLUSTER ONLY ///////////////////////
366	if ( is_io )
367	{
368	/////////// IO_BRIDGE
369	std::ostringstream s_iob;
370	s_iob << "iob_" << x_id << "_" << y_id;
371	iob = new VciIoBridge<vci_param_int,
372	vci_param_ext>(
373	s_iob.str().c_str(),
374	mt_ram, // EXT network maptab
375	mt_int, // INT network maptab
376	mt_iox, // IOX network maptab
377	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
378	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
379	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
380	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
381	16, // cache line words
382	8, // IOTLB ways
383	8, // IOTLB sets
384	debug_start_cycle,
385	iob_debug_ok );
386
387	std::ostringstream s_iob_ram_wi;
388	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
389	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
390	dspin_ram_cmd_width,
391	dspin_ram_rsp_width>(
392	s_iob_ram_wi.str().c_str(),
393	vci_param_int::S);
394
395	std::ostringstream s_ram_xbar_cmd;
396	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
397	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
398	s_ram_xbar_cmd.str().c_str(), // name
399	mt_ram, // mapping table
400	x_id, y_id, // x, y
401	x_width, y_width, l_width, // x_width, y_width, l_width
402	2, 0, // local inputs, local outputs
403	2, 2, // in fifo, out fifo depths
404	true, // is cmd ?
405	false, // use routing table ?
406	false); // support broadcast ?
407
408	std::ostringstream s_ram_xbar_rsp;
409	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
410	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
411	s_ram_xbar_rsp.str().c_str(), // name
412	mt_ram, // mapping table
413	x_id, y_id, // x, y
414	x_width, y_width, l_width, // x_width, y_width, l_width
415	0, 2, // local inputs, local outputs
416	2, 2, // in fifo, out fifo depths
417	false, // is cmd ?
418	true, // use routing table ?
419	false); // support broadcast ?
420	} // end if IO
421
422	////////////////////////////////////
423	// Connections are defined here
424	////////////////////////////////////
425
426	// on coherence network : local srcid[proc] in [0...nb_procs-1]
427	// : local srcid[memc] = nb_procs
428
429	//////////////////////// internal CMD & RSP routers
430	for(int k = 0; k < 3; k++)
431	{
432	int_router_cmd[k]->p_clk (this->p_clk);
433	int_router_cmd[k]->p_resetn (this->p_resetn);
434	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
435	for (int i = 0; i < 4; i++)
436	{
437	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
438	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
439	}
440	}
441
442	for(int k = 0; k < 2; k++)
443	{
444	int_router_rsp[k]->p_clk (this->p_clk);
445	int_router_rsp[k]->p_resetn (this->p_resetn);
446	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
447	for (int i = 0; i < 4; i++)
448	{
449	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
450	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
451	}
452	}
453
454	// local ports
455	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
456	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
457	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
458	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
459	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
460	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
461
462	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
463	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
464	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
465	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
466
467	///////////////////// CMD DSPIN local crossbar direct
468	int_xbar_d->p_clk (this->p_clk);
469	int_xbar_d->p_resetn (this->p_resetn);
470	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
471	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
472
473	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
474	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
475	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
476	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
477	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
478	for (size_t p = 0; p < nb_procs; p++)
479	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
480
481	if ( is_io )
482	{
483	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
484	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
485	}
486
487	int_wi_gate_d->p_clk (this->p_clk);
488	int_wi_gate_d->p_resetn (this->p_resetn);
489	int_wi_gate_d->p_vci (signal_int_vci_l2g);
490	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
491	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
492
493	int_wt_gate_d->p_clk (this->p_clk);
494	int_wt_gate_d->p_resetn (this->p_resetn);
495	int_wt_gate_d->p_vci (signal_int_vci_g2l);
496	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
497	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
498
499	////////////////////// M2P DSPIN local crossbar coherence
500	int_xbar_m2p_c->p_clk (this->p_clk);
501	int_xbar_m2p_c->p_resetn (this->p_resetn);
502	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
503	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
504	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
505	for (size_t p = 0; p < nb_procs; p++)
506	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
507
508	////////////////////////// P2M DSPIN local crossbar coherence
509	int_xbar_p2m_c->p_clk (this->p_clk);
510	int_xbar_p2m_c->p_resetn (this->p_resetn);
511	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
512	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
513	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
514	for (size_t p = 0; p < nb_procs; p++)
515	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
516
517	////////////////////// CLACK DSPIN local crossbar coherence
518	int_xbar_clack_c->p_clk (this->p_clk);
519	int_xbar_clack_c->p_resetn (this->p_resetn);
520	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
521	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
522	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
523	for (size_t p = 0; p < nb_procs; p++)
524	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
525
526	//////////////////////////////////// Processors
527	for (size_t p = 0; p < nb_procs; p++)
528	{
529	proc[p]->p_clk (this->p_clk);
530	proc[p]->p_resetn (this->p_resetn);
531	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
532	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
533	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
534	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
535
536	for ( size_t j = 0 ; j < 6 ; j++)
537	{
538	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
539	else proc[p]->p_irq[j] (signal_false);
540	}
541	}
542
543	///////////////////////////////////// XICU
544	xicu->p_clk (this->p_clk);
545	xicu->p_resetn (this->p_resetn);
546	xicu->p_vci (signal_int_vci_tgt_xicu);
547	for ( size_t i=0 ; i < xcu_nb_out ; i++)
548	{
549	xicu->p_irq[i] (signal_proc_it[i]);
550	}
551	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
552	{
553	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
554	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
555	else xicu->p_hwi[i] (signal_false);
556	}
557	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
558	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
559	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
560	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
561	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
562
563	///////////////////////////////////// MEMC
564	memc->p_clk (this->p_clk);
565	memc->p_resetn (this->p_resetn);
566	memc->p_vci_ixr (signal_ram_vci_ini_memc);
567	memc->p_vci_tgt (signal_int_vci_tgt_memc);
568	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
569	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
570	memc->p_dspin_clack (signal_int_dspin_clack_memc);
571	memc->p_irq (signal_irq_memc);
572
573	// wrapper to RAM network
574	memc_ram_wi->p_clk (this->p_clk);
575	memc_ram_wi->p_resetn (this->p_resetn);
576	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
577	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
578	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
579
580	//////////////////////////////////// XRAM
581	xram->p_clk (this->p_clk);
582	xram->p_resetn (this->p_resetn);
583	xram->p_vci (signal_ram_vci_tgt_xram);
584
585	// wrapper to RAM network
586	xram_ram_wt->p_clk (this->p_clk);
587	xram_ram_wt->p_resetn (this->p_resetn);
588	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
589	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
590	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
591
592	/////////////////////////////////// MDMA
593	mdma->p_clk (this->p_clk);
594	mdma->p_resetn (this->p_resetn);
595	mdma->p_vci_target (signal_int_vci_tgt_mdma);
596	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
597	for (size_t i=0 ; i<nb_dmas ; i++)
598	mdma->p_irq[i] (signal_irq_mdma[i]);
599
600	/////////////////////////////////// DROM
601	drom->p_clk (this->p_clk);
602	drom->p_resetn (this->p_resetn);
603	drom->p_vci (signal_int_vci_tgt_drom);
604
605	//////////////////////////// RAM network CMD & RSP routers
606	ram_router_cmd->p_clk (this->p_clk);
607	ram_router_cmd->p_resetn (this->p_resetn);
608	ram_router_rsp->p_clk (this->p_clk);
609	ram_router_rsp->p_resetn (this->p_resetn);
610	for( size_t n=0 ; n<4 ; n++)
611	{
612	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
613	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
614	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
615	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
616	}
617
618	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
619	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
620
621	if ( is_io )
622	{
623	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
624	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
625	}
626	else
627	{
628	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
629	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
630	}
631
632	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
633	if ( is_io )
634	{
635	// IO bridge
636	iob->p_clk (this->p_clk);
637	iob->p_resetn (this->p_resetn);
638	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
639	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
640	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
641	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
642	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
643
644	// initiator wrapper to RAM network
645	iob_ram_wi->p_clk (this->p_clk);
646	iob_ram_wi->p_resetn (this->p_resetn);
647	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
648	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
649	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
650
651	// crossbar between MEMC and IOB to RAM network
652	ram_xbar_cmd->p_clk (this->p_clk);
653	ram_xbar_cmd->p_resetn (this->p_resetn);
654	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
655	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
656	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
657	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
658
659	ram_xbar_rsp->p_clk (this->p_clk);
660	ram_xbar_rsp->p_resetn (this->p_resetn);
661	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
662	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
663	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
664	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
665	}
666
667	SC_METHOD(init);
668
669	} // end constructor
670
671	tmpl(void)::init()
672	{
673	signal_ram_dspin_cmd_false.write = false;
674	signal_ram_dspin_rsp_false.read = true;
675	} // end init
676
677	tmpl(/**/)::~TsarIobCluster()
678	{
679	for (int k = 0; k < 3; k++)
680	{
681	delete int_router_cmd[k];
682	}
683	delete [] int_router_cmd;
684
685	for (int k = 0; k < 2; k++)
686	{
687	delete int_router_rsp[k];
688	}
689	delete [] int_router_rsp;
690	}
691
692	}}
693
694
695	// Local Variables:
696	// tab-width: 4
697	// c-basic-offset: 4
698	// c-file-offsets:((innamespace . 0)(inline-open . 0))
699	// indent-tabs-mode: nil
700	// End:
701
702	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
703

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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