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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 963

Last change on this file since 963 was 963, checked in by cfuguet, 9 years ago
reconf: consider the IRQ_PER_PROCESSOR constant when connecting XICU irqs.
File size: 34.3 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79	size_t irq_per_proc,
80
81	bool distboot,
82
83	const Loader &loader,
84
85	uint32_t frozen_cycles,
86	uint32_t debug_start_cycle,
87	bool memc_debug_ok,
88	bool proc_debug_ok,
89	bool iob_debug_ok ) :
90
91	// constructor initialization list
92
93	soclib::caba::BaseModule(insname),
94	p_clk("clk"),
95	p_resetn("resetn")
96	{
97
98	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
99
100	size_t cluster_id = (x_id << x_width) \| y_id;
101
102	// Vectors of DSPIN ports for inter-cluster communications
103	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
104	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
105	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
106	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
107
108	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
109	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
110	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
111	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
112
113	// VCI ports from IOB to IOX network (only in IO clusters)
114	if (is_io)
115	{
116	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
117	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
118	}
119
120	/////////////////////////////////////////////////////////////////////////////
121	// Hardware components
122	/////////////////////////////////////////////////////////////////////////////
123
124	//////////// PROCS
125	for (size_t p = 0; p < nb_procs; p++)
126	{
127	std::ostringstream s_proc;
128	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
129	proc[p] = new VciCcVCacheWrapper<vci_param_int,
130	dspin_int_cmd_width,
131	dspin_int_rsp_width,
132	GdbServer<Mips32ElIss> >(
133	s_proc.str().c_str(),
134	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
135	mt_int, // Mapping Table INT network
136	IntTab(cluster_id,p), // SRCID
137	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
138	8, // ITLB ways
139	8, // ITLB sets
140	8, // DTLB ways
141	8, // DTLB sets
142	l1_i_ways, l1_i_sets, 16, // ICACHE size
143	l1_d_ways, l1_d_sets, 16, // DCACHE size
144	4, // WBUF nlines
145	4, // WBUF nwords
146	x_width, // number of bits for x coordinate
147	y_width, // number of bits for y coordinate
148	frozen_cycles, // max frozen cycles
149	debug_start_cycle,
150	proc_debug_ok);
151
152	// initialize physical address extension with cluster ID when using
153	// distributed boot
154	if (distboot)
155	{
156	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
157	proc[p]->set_icache_paddr_ext_reset(cluster_id);
158	}
159	}
160
161	/////////// MEMC
162	std::ostringstream s_memc;
163	s_memc << "memc_" << x_id << "_" << y_id;
164	memc = new VciMemCache<vci_param_int,
165	vci_param_ext,
166	dspin_int_rsp_width,
167	dspin_int_cmd_width>(
168	s_memc.str().c_str(),
169	mt_int, // Mapping Table INT network
170	mt_ram, // Mapping Table RAM network
171	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
172	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
173	x_width, // number of bits for x coordinate
174	y_width, // number of bits for y coordinate
175	memc_ways, memc_sets, 16, // CACHE SIZE
176	3, // MAX NUMBER OF COPIES
177	4096, // HEAP SIZE
178	8, // TRANSACTION TABLE DEPTH
179	8, // UPDATE TABLE DEPTH
180	8, // INVALIDATE TABLE DEPTH
181	debug_start_cycle,
182	memc_debug_ok );
183
184	std::ostringstream s_wi_memc;
185	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
186	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
187	dspin_ram_cmd_width,
188	dspin_ram_rsp_width>(
189	s_wi_memc.str().c_str(),
190	x_width + y_width + l_width);
191
192	/////////// XICU
193	std::ostringstream s_xicu;
194	s_xicu << "xicu_" << x_id << "_" << y_id;
195	xicu = new VciXicu<vci_param_int>(
196	s_xicu.str().c_str(),
197	mt_int, // mapping table INT network
198	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
199	xcu_nb_pti, // number of timer IRQs
200	xcu_nb_hwi, // number of hard IRQs
201	xcu_nb_wti, // number of soft IRQs
202	xcu_nb_out, // number of output IRQs
203	5); // number of config regs
204
205	//////////// MDMA
206	std::ostringstream s_mdma;
207	s_mdma << "mdma_" << x_id << "_" << y_id;
208	mdma = new VciMultiDma<vci_param_int>(
209	s_mdma.str().c_str(),
210	mt_int,
211	IntTab(cluster_id, nb_procs), // SRCID
212	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
213	64, // burst size
214	nb_dmas); // number of IRQs
215
216	/////////// DISTRIBUTED ROM
217	std::ostringstream s_drom;
218	s_drom << "drom_" << x_id << "_" << y_id;
219	drom = new VciSimpleRom<vci_param_int>(
220	s_drom.str().c_str(),
221	IntTab(cluster_id, int_drom_tgt_id),
222	mt_int,
223	loader,
224	x_width + y_width); // msb drop bits
225
226	/////////// Direct LOCAL_XBAR(S)
227	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
228	size_t nb_direct_targets = is_io ? 5 : 4;
229
230	std::ostringstream s_int_xbar_d;
231	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
232	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
233	s_int_xbar_d.str().c_str(),
234	mt_int, // mapping table
235	cluster_id, // cluster id
236	nb_direct_initiators, // number of local initiators
237	nb_direct_targets, // number of local targets
238	0 ); // default target
239
240	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
241	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
242	<< x_id << "_" << y_id;
243	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
244	dspin_int_cmd_width,
245	dspin_int_rsp_width>(
246	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
247	x_width + y_width + l_width);
248
249	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
250	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
251	<< x_id << "_" << y_id;
252	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
253	dspin_int_cmd_width,
254	dspin_int_rsp_width>(
255	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
256	x_width + y_width + l_width);
257
258	//////////// Coherence LOCAL_XBAR(S)
259	std::ostringstream s_int_xbar_m2p_c;
260	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
261	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
262	s_int_xbar_m2p_c.str().c_str(),
263	mt_int, // mapping table
264	x_id, y_id, // cluster coordinates
265	x_width, y_width, l_width, // several dests
266	1, // number of local sources
267	nb_procs, // number of local dests
268	2, 2, // fifo depths
269	true, // pseudo CMD
270	false, // no routing table
271	true ); // broacast
272
273	std::ostringstream s_int_xbar_p2m_c;
274	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
275	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
276	s_int_xbar_p2m_c.str().c_str(),
277	mt_int, // mapping table
278	x_id, y_id, // cluster coordinates
279	x_width, y_width, 0, // only one dest
280	nb_procs, // number of local sources
281	1, // number of local dests
282	2, 2, // fifo depths
283	false, // pseudo RSP
284	false, // no routing table
285	false ); // no broacast
286
287	std::ostringstream s_int_xbar_clack_c;
288	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
289	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
290	s_int_xbar_clack_c.str().c_str(),
291	mt_int, // mapping table
292	x_id, y_id, // cluster coordinates
293	x_width, y_width, l_width,
294	1, // number of local sources
295	nb_procs, // number of local targets
296	1, 1, // fifo depths
297	true, // CMD
298	false, // no routing table
299	false); // broadcast
300
301	////////////// INT ROUTER(S)
302	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
303	for (int k = 0; k < 3; k++)
304	{
305	std::ostringstream s_int_router_cmd;
306	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
307	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
308	s_int_router_cmd.str().c_str(),
309	x_id, y_id,
310	x_width, y_width,
311	4, 4,
312	(k == 1));
313	}
314
315	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
316	for (int k = 0; k < 2; k++)
317	{
318	std::ostringstream s_int_router_rsp;
319	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
320	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
321	s_int_router_rsp.str().c_str(),
322	x_id, y_id,
323	x_width, y_width,
324	4, 4,
325	false);
326	}
327
328	////////////// XRAM
329	std::ostringstream s_xram;
330	s_xram << "xram_" << x_id << "_" << y_id;
331	xram = new VciSimpleRam<vci_param_ext>(
332	s_xram.str().c_str(),
333	IntTab(cluster_id, ram_xram_tgt_id),
334	mt_ram,
335	loader,
336	xram_latency);
337
338	std::ostringstream s_wt_xram;
339	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
340	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
341	dspin_ram_cmd_width,
342	dspin_ram_rsp_width>(
343	s_wt_xram.str().c_str(),
344	x_width + y_width + l_width);
345
346	///////////// RAM ROUTER(S)
347	std::ostringstream s_ram_router_cmd;
348	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
349	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
350	s_ram_router_cmd.str().c_str(),
351	x_id, y_id, // router coordinates in mesh
352	x_width, // x field width in first flit
353	y_width, // y field width in first flit
354	4, 4); // input & output fifo depths
355
356	std::ostringstream s_ram_router_rsp;
357	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
358	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
359	s_ram_router_rsp.str().c_str(),
360	x_id, y_id, // coordinates in mesh
361	x_width, // x field width in first flit
362	y_width, // y field width in first flit
363	4, 4); // input & output fifo depths
364
365
366	////////////////////// I/O CLUSTER ONLY ///////////////////////
367	if ( is_io )
368	{
369	/////////// IO_BRIDGE
370	std::ostringstream s_iob;
371	s_iob << "iob_" << x_id << "_" << y_id;
372	iob = new VciIoBridge<vci_param_int,
373	vci_param_ext>(
374	s_iob.str().c_str(),
375	mt_ram, // EXT network maptab
376	mt_int, // INT network maptab
377	mt_iox, // IOX network maptab
378	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
379	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
380	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
381	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
382	16, // cache line words
383	8, // IOTLB ways
384	8, // IOTLB sets
385	debug_start_cycle,
386	iob_debug_ok );
387
388	std::ostringstream s_iob_ram_wi;
389	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
390	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
391	dspin_ram_cmd_width,
392	dspin_ram_rsp_width>(
393	s_iob_ram_wi.str().c_str(),
394	vci_param_int::S);
395
396	std::ostringstream s_ram_xbar_cmd;
397	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
398	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
399	s_ram_xbar_cmd.str().c_str(), // name
400	mt_ram, // mapping table
401	x_id, y_id, // x, y
402	x_width, y_width, l_width, // x_width, y_width, l_width
403	2, 0, // local inputs, local outputs
404	2, 2, // in fifo, out fifo depths
405	true, // is cmd ?
406	false, // use routing table ?
407	false); // support broadcast ?
408
409	std::ostringstream s_ram_xbar_rsp;
410	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
411	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
412	s_ram_xbar_rsp.str().c_str(), // name
413	mt_ram, // mapping table
414	x_id, y_id, // x, y
415	x_width, y_width, l_width, // x_width, y_width, l_width
416	0, 2, // local inputs, local outputs
417	2, 2, // in fifo, out fifo depths
418	false, // is cmd ?
419	true, // use routing table ?
420	false); // support broadcast ?
421	} // end if IO
422
423	////////////////////////////////////
424	// Connections are defined here
425	////////////////////////////////////
426
427	// on coherence network : local srcid[proc] in [0...nb_procs-1]
428	// : local srcid[memc] = nb_procs
429
430	//////////////////////// internal CMD & RSP routers
431	for(int k = 0; k < 3; k++)
432	{
433	int_router_cmd[k]->p_clk (this->p_clk);
434	int_router_cmd[k]->p_resetn (this->p_resetn);
435	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
436	for (int i = 0; i < 4; i++)
437	{
438	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
439	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
440	}
441	}
442
443	for(int k = 0; k < 2; k++)
444	{
445	int_router_rsp[k]->p_clk (this->p_clk);
446	int_router_rsp[k]->p_resetn (this->p_resetn);
447	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
448	for (int i = 0; i < 4; i++)
449	{
450	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
451	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
452	}
453	}
454
455	// local ports
456	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
457	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
458	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
459	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
460	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
461	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
462
463	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
464	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
465	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
466	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
467
468	///////////////////// CMD DSPIN local crossbar direct
469	int_xbar_d->p_clk (this->p_clk);
470	int_xbar_d->p_resetn (this->p_resetn);
471	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
472	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
473
474	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
475	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
476	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
477	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
478	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
479	for (size_t p = 0; p < nb_procs; p++)
480	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
481
482	if ( is_io )
483	{
484	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
485	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
486	}
487
488	int_wi_gate_d->p_clk (this->p_clk);
489	int_wi_gate_d->p_resetn (this->p_resetn);
490	int_wi_gate_d->p_vci (signal_int_vci_l2g);
491	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
492	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
493
494	int_wt_gate_d->p_clk (this->p_clk);
495	int_wt_gate_d->p_resetn (this->p_resetn);
496	int_wt_gate_d->p_vci (signal_int_vci_g2l);
497	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
498	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
499
500	////////////////////// M2P DSPIN local crossbar coherence
501	int_xbar_m2p_c->p_clk (this->p_clk);
502	int_xbar_m2p_c->p_resetn (this->p_resetn);
503	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
504	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
505	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
506	for (size_t p = 0; p < nb_procs; p++)
507	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
508
509	////////////////////////// P2M DSPIN local crossbar coherence
510	int_xbar_p2m_c->p_clk (this->p_clk);
511	int_xbar_p2m_c->p_resetn (this->p_resetn);
512	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
513	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
514	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
515	for (size_t p = 0; p < nb_procs; p++)
516	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
517
518	////////////////////// CLACK DSPIN local crossbar coherence
519	int_xbar_clack_c->p_clk (this->p_clk);
520	int_xbar_clack_c->p_resetn (this->p_resetn);
521	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
522	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
523	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
524	for (size_t p = 0; p < nb_procs; p++)
525	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
526
527	//////////////////////////////////// Processors
528	for (size_t p = 0; p < nb_procs; p++)
529	{
530	proc[p]->p_clk (this->p_clk);
531	proc[p]->p_resetn (this->p_resetn);
532	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
533	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
534	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
535	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
536
537	for ( size_t j = 0 ; j < 6 ; j++)
538	{
539	if ( j < irq_per_proc )
540	{
541	proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]);
542	}
543	else
544	{
545	proc[p]->p_irq[j] (signal_false);
546	}
547	}
548	}
549
550	///////////////////////////////////// XICU
551	xicu->p_clk (this->p_clk);
552	xicu->p_resetn (this->p_resetn);
553	xicu->p_vci (signal_int_vci_tgt_xicu);
554	for ( size_t i=0 ; i < xcu_nb_out ; i++)
555	{
556	xicu->p_irq[i] (signal_proc_it[i]);
557	}
558	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
559	{
560	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
561	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
562	else xicu->p_hwi[i] (signal_false);
563	}
564	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
565	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
566	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
567	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
568	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
569
570	///////////////////////////////////// MEMC
571	memc->p_clk (this->p_clk);
572	memc->p_resetn (this->p_resetn);
573	memc->p_vci_ixr (signal_ram_vci_ini_memc);
574	memc->p_vci_tgt (signal_int_vci_tgt_memc);
575	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
576	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
577	memc->p_dspin_clack (signal_int_dspin_clack_memc);
578	memc->p_irq (signal_irq_memc);
579
580	// wrapper to RAM network
581	memc_ram_wi->p_clk (this->p_clk);
582	memc_ram_wi->p_resetn (this->p_resetn);
583	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
584	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
585	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
586
587	//////////////////////////////////// XRAM
588	xram->p_clk (this->p_clk);
589	xram->p_resetn (this->p_resetn);
590	xram->p_vci (signal_ram_vci_tgt_xram);
591
592	// wrapper to RAM network
593	xram_ram_wt->p_clk (this->p_clk);
594	xram_ram_wt->p_resetn (this->p_resetn);
595	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
596	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
597	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
598
599	/////////////////////////////////// MDMA
600	mdma->p_clk (this->p_clk);
601	mdma->p_resetn (this->p_resetn);
602	mdma->p_vci_target (signal_int_vci_tgt_mdma);
603	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
604	for (size_t i=0 ; i<nb_dmas ; i++)
605	mdma->p_irq[i] (signal_irq_mdma[i]);
606
607	/////////////////////////////////// DROM
608	drom->p_clk (this->p_clk);
609	drom->p_resetn (this->p_resetn);
610	drom->p_vci (signal_int_vci_tgt_drom);
611
612	//////////////////////////// RAM network CMD & RSP routers
613	ram_router_cmd->p_clk (this->p_clk);
614	ram_router_cmd->p_resetn (this->p_resetn);
615	ram_router_rsp->p_clk (this->p_clk);
616	ram_router_rsp->p_resetn (this->p_resetn);
617	for( size_t n=0 ; n<4 ; n++)
618	{
619	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
620	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
621	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
622	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
623	}
624
625	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
626	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
627
628	if ( is_io )
629	{
630	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
631	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
632	}
633	else
634	{
635	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
636	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
637	}
638
639	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
640	if ( is_io )
641	{
642	// IO bridge
643	iob->p_clk (this->p_clk);
644	iob->p_resetn (this->p_resetn);
645	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
646	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
647	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
648	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
649	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
650
651	// initiator wrapper to RAM network
652	iob_ram_wi->p_clk (this->p_clk);
653	iob_ram_wi->p_resetn (this->p_resetn);
654	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
655	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
656	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
657
658	// crossbar between MEMC and IOB to RAM network
659	ram_xbar_cmd->p_clk (this->p_clk);
660	ram_xbar_cmd->p_resetn (this->p_resetn);
661	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
662	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
663	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
664	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
665
666	ram_xbar_rsp->p_clk (this->p_clk);
667	ram_xbar_rsp->p_resetn (this->p_resetn);
668	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
669	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
670	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
671	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
672	}
673
674	SC_METHOD(init);
675
676	} // end constructor
677
678	tmpl(void)::init()
679	{
680	signal_ram_dspin_cmd_false.write = false;
681	signal_ram_dspin_rsp_false.read = true;
682	} // end init
683
684	tmpl(/**/)::~TsarIobCluster()
685	{
686	for (int k = 0; k < 3; k++)
687	{
688	delete int_router_cmd[k];
689	}
690	delete [] int_router_cmd;
691
692	for (int k = 0; k < 2; k++)
693	{
694	delete int_router_rsp[k];
695	}
696	delete [] int_router_rsp;
697	}
698
699	}}
700
701
702	// Local Variables:
703	// tab-width: 4
704	// c-basic-offset: 4
705	// c-file-offsets:((innamespace . 0)(inline-open . 0))
706	// indent-tabs-mode: nil
707	// End:
708
709	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
710

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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