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source: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 446

Last change on this file since 446 was 446, checked in by cfuguet, 11 years ago

Modifications in vci_cc_vcache_wrapper:

Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.

Adding third port for the clack coherence network.

Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

File size: 234.6 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CMD 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_UPDT",
65	"ICACHE_CC_INVAL",
66	"ICACHE_CC_SEND_WAIT",
67	};
68
69	const char *dcache_fsm_state_str[] = {
70	"DCACHE_IDLE",
71
72	"DCACHE_TLB_MISS",
73	"DCACHE_TLB_PTE1_GET",
74	"DCACHE_TLB_PTE1_SELECT",
75	"DCACHE_TLB_PTE1_UPDT",
76	"DCACHE_TLB_PTE2_GET",
77	"DCACHE_TLB_PTE2_SELECT",
78	"DCACHE_TLB_PTE2_UPDT",
79	"DCACHE_TLB_LR_UPDT",
80	"DCACHE_TLB_LR_WAIT",
81	"DCACHE_TLB_RETURN",
82
83	"DCACHE_XTN_SWITCH",
84	"DCACHE_XTN_SYNC",
85	"DCACHE_XTN_IC_INVAL_VA",
86	"DCACHE_XTN_IC_FLUSH",
87	"DCACHE_XTN_IC_INVAL_PA",
88	"DCACHE_XTN_IT_INVAL",
89	"DCACHE_XTN_DC_FLUSH",
90	"DCACHE_XTN_DC_FLUSH_GO",
91	"DCACHE_XTN_DC_INVAL_VA",
92	"DCACHE_XTN_DC_INVAL_PA",
93	"DCACHE_XTN_DC_INVAL_END",
94	"DCACHE_XTN_DC_INVAL_GO",
95	"DCACHE_XTN_DT_INVAL",
96
97	"DCACHE_DIRTY_GET_PTE",
98	"DCACHE_DIRTY_WAIT",
99
100	"DCACHE_MISS_SELECT",
101	"DCACHE_MISS_CLEAN",
102	"DCACHE_MISS_WAIT",
103	"DCACHE_MISS_DATA_UPDT",
104	"DCACHE_MISS_DIR_UPDT",
105
106	"DCACHE_UNC_WAIT",
107	"DCACHE_LL_WAIT",
108	"DCACHE_SC_WAIT",
109
110	"DCACHE_CC_CHECK",
111	"DCACHE_CC_UPDT",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_SEND_WAIT",
114
115	"DCACHE_INVAL_TLB_SCAN",
116	};
117
118	const char *cmd_fsm_state_str[] = {
119	"CMD_IDLE",
120	"CMD_INS_MISS",
121	"CMD_INS_UNC",
122	"CMD_DATA_MISS",
123	"CMD_DATA_UNC",
124	"CMD_DATA_WRITE",
125	"CMD_DATA_LL",
126	"CMD_DATA_SC",
127	"CMD_DATA_CAS",
128	};
129
130	const char *vci_pktid_type_str[] = {
131	"TYPE_READ_DATA_UNC",
132	"TYPE_READ_DATA_MISS",
133	"TYPE_READ_INS_UNC",
134	"TYPE_READ_INS_MISS",
135	"TYPE_WRITE",
136	"TYPE_CAS",
137	"TYPE_LL",
138	"TYPE_SC",
139	};
140
141	const char *vci_cmd_type_str[] = {
142	"NOP or STORE_COND",
143	"READ",
144	"WRITE",
145	"LOCKED_READ"
146	};
147
148	const char *rsp_fsm_state_str[] = {
149	"RSP_IDLE",
150	"RSP_INS_MISS",
151	"RSP_INS_UNC",
152	"RSP_DATA_MISS",
153	"RSP_DATA_UNC",
154	"RSP_DATA_LL",
155	"RSP_DATA_WRITE",
156	};
157
158	const char *cc_receive_fsm_state_str[] = {
159	"CC_RECEIVE_IDLE",
160	"CC_RECEIVE_CLACK",
161	"CC_RECEIVE_BRDCAST_HEADER",
162	"CC_RECEIVE_BRDCAST_NLINE",
163	"CC_RECEIVE_INVAL_HEADER",
164	"CC_RECEIVE_INVAL_NLINE",
165	"CC_RECEIVE_UPDT_HEADER",
166	"CC_RECEIVE_UPDT_NLINE",
167	"CC_RECEIVE_UPDT_DATA",
168	};
169
170	const char *cc_send_fsm_state_str[] = {
171	"CC_SEND_IDLE",
172	"CC_SEND_CLEANUP_1",
173	"CC_SEND_CLEANUP_2",
174	"CC_SEND_MULTI_ACK",
175	};
176	}
177
178	#define tmpl(...) \
179	template<typename vci_param, \
180	size_t dspin_in_width, \
181	size_t dspin_out_width, \
182	typename iss_t> __VA_ARGS__ \
183	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
184
185	using namespace soclib::common;
186
187	/////////////////////////////////
188	tmpl(/**/)::VciCcVCacheWrapper(
189	sc_module_name name,
190	const int proc_id,
191	const MappingTable &mtd,
192	const IntTab &srcid,
193	const size_t cc_global_id,
194	const size_t itlb_ways,
195	const size_t itlb_sets,
196	const size_t dtlb_ways,
197	const size_t dtlb_sets,
198	const size_t icache_ways,
199	const size_t icache_sets,
200	const size_t icache_words,
201	const size_t dcache_ways,
202	const size_t dcache_sets,
203	const size_t dcache_words,
204	const size_t wbuf_nlines,
205	const size_t wbuf_nwords,
206	const size_t x_width,
207	const size_t y_width,
208	const uint32_t max_frozen_cycles,
209	const uint32_t debug_start_cycle,
210	const bool debug_ok )
211	: soclib::caba::BaseModule(name),
212
213	p_clk("p_clk"),
214	p_resetn("p_resetn"),
215	p_vci("p_vci"),
216	p_dspin_m2p("p_dspin_m2p"),
217	p_dspin_p2m("p_dspin_p2m"),
218	p_dspin_clack("p_dspin_clack"),
219
220	m_cacheability_table( mtd.getCacheabilityTable() ),
221	m_srcid( mtd.indexForId(srcid) ),
222	m_cc_global_id( cc_global_id ),
223	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
224	m_itlb_ways( itlb_ways ),
225	m_itlb_sets( itlb_sets ),
226	m_dtlb_ways( dtlb_ways ),
227	m_dtlb_sets( dtlb_sets ),
228	m_icache_ways( icache_ways ),
229	m_icache_sets( icache_sets ),
230	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
231	m_icache_words( icache_words ),
232	m_dcache_ways( dcache_ways ),
233	m_dcache_sets( dcache_sets ),
234	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
235	m_dcache_words( dcache_words ),
236	m_x_width( x_width ),
237	m_y_width( y_width ),
238	m_proc_id( proc_id ),
239	m_max_frozen_cycles( max_frozen_cycles ),
240	m_paddr_nbits( vci_param::N ),
241	m_debug_start_cycle( debug_start_cycle ),
242	m_debug_ok( debug_ok ),
243
244	r_mmu_ptpr("r_mmu_ptpr"),
245	r_mmu_mode("r_mmu_mode"),
246	r_mmu_word_lo("r_mmu_word_lo"),
247	r_mmu_word_hi("r_mmu_word_hi"),
248	r_mmu_ibvar("r_mmu_ibvar"),
249	r_mmu_dbvar("r_mmu_dbvar"),
250	r_mmu_ietr("r_mmu_ietr"),
251	r_mmu_detr("r_mmu_detr"),
252
253	r_icache_fsm("r_icache_fsm"),
254	r_icache_fsm_save("r_icache_fsm_save"),
255	r_icache_vci_paddr("r_icache_vci_paddr"),
256	r_icache_vaddr_save("r_icache_vaddr_save"),
257
258	r_icache_miss_way("r_icache_miss_way"),
259	r_icache_miss_set("r_icache_miss_set"),
260	r_icache_miss_word("r_icache_miss_word"),
261	r_icache_miss_inval("r_icache_miss_inval"),
262	r_icache_miss_clack("r_icache_miss_clack"),
263
264	r_icache_cc_way("r_icache_cc_way"),
265	r_icache_cc_set("r_icache_cc_set"),
266	r_icache_cc_word("r_icache_cc_word"),
267	r_icache_cc_need_write("r_icache_cc_need_write"),
268
269	r_icache_flush_count("r_icache_flush_count"),
270
271	r_icache_miss_req("r_icache_miss_req"),
272	r_icache_unc_req("r_icache_unc_req"),
273
274	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
275	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
276
277	r_icache_cc_send_req("r_icache_cc_send_req"),
278	r_icache_cc_send_type("r_icache_cc_send_type"),
279	r_icache_cc_send_nline("r_icache_cc_send_nline"),
280	r_icache_cc_send_way("r_icache_cc_send_way"),
281	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
282
283	r_dcache_fsm("r_dcache_fsm"),
284	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
285	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
286
287	r_dcache_wbuf_req("r_dcache_wbuf_req"),
288	r_dcache_updt_req("r_dcache_updt_req"),
289	r_dcache_save_vaddr("r_dcache_save_vaddr"),
290	r_dcache_save_wdata("r_dcache_save_wdata"),
291	r_dcache_save_be("r_dcache_save_be"),
292	r_dcache_save_paddr("r_dcache_save_paddr"),
293	r_dcache_save_cacheable("r_dcache_save_cacheable"),
294	r_dcache_save_cache_way("r_dcache_save_cache_way"),
295	r_dcache_save_cache_set("r_dcache_save_cache_set"),
296	r_dcache_save_cache_word("r_dcache_save_cache_word"),
297
298	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
299	r_dcache_dirty_way("r_dcache_dirty_way"),
300	r_dcache_dirty_set("r_dcache_dirty_set"),
301
302	r_dcache_vci_paddr("r_dcache_vci_paddr"),
303	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
304	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
305	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
306	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
307	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
308	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
309	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
310	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
311	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
312
313	r_dcache_xtn_way("r_dcache_xtn_way"),
314	r_dcache_xtn_set("r_dcache_xtn_set"),
315
316	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
317
318	r_dcache_miss_type("r_dcache_miss_type"),
319	r_dcache_miss_word("r_dcache_miss_word"),
320	r_dcache_miss_way("r_dcache_miss_way"),
321	r_dcache_miss_set("r_dcache_miss_set"),
322	r_dcache_miss_inval("r_dcache_miss_inval"),
323
324	r_dcache_cc_way("r_dcache_cc_way"),
325	r_dcache_cc_set("r_dcache_cc_set"),
326	r_dcache_cc_word("r_dcache_cc_word"),
327	r_dcache_cc_need_write("r_dcache_cc_need_write"),
328
329	r_dcache_flush_count("r_dcache_flush_count"),
330
331	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
332
333	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
334	r_dcache_tlb_ins("r_dcache_tlb_ins"),
335	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
336	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
337	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
338	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
339	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
340	r_dcache_tlb_way("r_dcache_tlb_way"),
341	r_dcache_tlb_set("r_dcache_tlb_set"),
342
343	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
344	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
345
346	r_dcache_xtn_req("r_dcache_xtn_req"),
347	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
348
349	r_dcache_cc_send_req("r_dcache_cc_send_req"),
350	r_dcache_cc_send_type("r_dcache_cc_send_type"),
351	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
352	r_dcache_cc_send_way("r_dcache_cc_send_way"),
353	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
354
355	r_vci_cmd_fsm("r_vci_cmd_fsm"),
356	r_vci_cmd_min("r_vci_cmd_min"),
357	r_vci_cmd_max("r_vci_cmd_max"),
358	r_vci_cmd_cpt("r_vci_cmd_cpt"),
359	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
360
361	r_vci_rsp_fsm("r_vci_rsp_fsm"),
362	r_vci_rsp_cpt("r_vci_rsp_cpt"),
363	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
364	r_vci_rsp_data_error("r_vci_rsp_data_error"),
365	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
366	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
367
368	r_cc_send_fsm("r_cc_send_fsm"),
369	r_cc_send_last_client("r_cc_send_last_client"),
370
371	r_cc_receive_fsm("r_cc_receive_fsm"),
372	r_cc_receive_data_ins("r_cc_receive_data_ins"),
373	r_cc_receive_word_idx("r_cc_receive_word_idx"),
374	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
375	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
376	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
377
378	r_cc_receive_icache_req("r_cc_receive_icache_req"),
379	r_cc_receive_icache_type("r_cc_receive_icache_type"),
380	r_cc_receive_icache_way("r_cc_receive_icache_way"),
381	r_cc_receive_icache_set("r_cc_receive_icache_set"),
382	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
383	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
384
385	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
386	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
387	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
388	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
389	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
390	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
391
392	r_iss(this->name(), proc_id),
393	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
394	r_icache("icache", icache_ways, icache_sets, icache_words),
395	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
396	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
397	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
398	{
399	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
400
401	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
402	"Need more PLEN bits.");
403
404	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
405	"Need more TRDID bits.");
406
407	assert( (icache_words == dcache_words) and
408	"icache_words and dcache_words parameters must be equal");
409
410	assert( (itlb_sets == dtlb_sets) and
411	"itlb_sets and dtlb_sets parameters must be etqual");
412
413	assert( (itlb_ways == dtlb_ways) and
414	"itlb_ways and dtlb_ways parameters must be etqual");
415
416	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
417	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
418	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
419	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
420	(uint32_log2(m_icache_words<<2));
421
422	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
423
424	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
425	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
426
427	SC_METHOD(transition);
428	dont_initialize();
429	sensitive << p_clk.pos();
430
431	SC_METHOD(genMoore);
432	dont_initialize();
433	sensitive << p_clk.neg();
434
435	typename iss_t::CacheInfo cache_info;
436	cache_info.has_mmu = true;
437	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
438	cache_info.icache_assoc = icache_ways;
439	cache_info.icache_n_lines = icache_sets;
440	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
441	cache_info.dcache_assoc = dcache_ways;
442	cache_info.dcache_n_lines = dcache_sets;
443	r_iss.setCacheInfo(cache_info);
444	}
445
446	/////////////////////////////////////
447	tmpl(/**/)::~VciCcVCacheWrapper()
448	/////////////////////////////////////
449	{
450	delete [] r_dcache_in_tlb;
451	delete [] r_dcache_contains_ptd;
452	}
453
454	////////////////////////
455	tmpl(void)::print_cpi()
456	////////////////////////
457	{
458	std::cout << name() << " CPI = "
459	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
460	}
461
462	////////////////////////////////////
463	tmpl(void)::print_trace(size_t mode)
464	////////////////////////////////////
465	{
466	// b0 : write buffer trace
467	// b1 : write buffer verbose
468	// b2 : dcache trace
469	// b3 : icache trace
470	// b4 : dtlb trace
471	// b5 : itlb trace
472
473	std::cout << std::dec << "PROC " << name() << std::endl;
474
475	std::cout << " " << m_ireq << std::endl;
476	std::cout << " " << m_irsp << std::endl;
477	std::cout << " " << m_dreq << std::endl;
478	std::cout << " " << m_drsp << std::endl;
479
480	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
481	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
482	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
483	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
484	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
485	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
486	<< " \| MMU = " << r_mmu_mode.read();
487	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
488	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
489	std::cout << std::endl;
490
491	if(mode & 0x01)
492	{
493	r_wbuf.printTrace((mode>>1)&1);
494	}
495	if(mode & 0x04)
496	{
497	std::cout << " Data Cache" << std::endl;
498	r_dcache.printTrace();
499	}
500	if(mode & 0x08)
501	{
502	std::cout << " Instruction Cache" << std::endl;
503	r_icache.printTrace();
504	}
505	if(mode & 0x10)
506	{
507	std::cout << " Data TLB" << std::endl;
508	r_dtlb.printTrace();
509	}
510	if(mode & 0x20)
511	{
512	std::cout << " Instruction TLB" << std::endl;
513	r_itlb.printTrace();
514	}
515	}
516
517	//////////////////////////////////////////
518	tmpl(void)::cache_monitor( paddr_t addr )
519	//////////////////////////////////////////
520	{
521	bool cache_hit;
522	size_t cache_way = 0;
523	size_t cache_set = 0;
524	size_t cache_word = 0;
525	uint32_t cache_rdata = 0;
526
527	cache_hit = r_dcache.read_neutral( addr,
528	&cache_rdata,
529	&cache_way,
530	&cache_set,
531	&cache_word );
532
533	if ( cache_hit != m_debug_previous_d_hit )
534	{
535	std::cout << "Monitor PROC " << name()
536	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
537	<< " / HIT = " << cache_hit
538	<< " / PADDR = " << std::hex << addr
539	<< " / DATA = " << cache_rdata
540	<< " / WAY = " << cache_way << std::endl;
541	m_debug_previous_d_hit = cache_hit;
542	}
543
544	cache_hit = r_icache.read_neutral( addr,
545	&cache_rdata,
546	&cache_way,
547	&cache_set,
548	&cache_word );
549
550	if ( cache_hit != m_debug_previous_i_hit )
551	{
552	std::cout << "Monitor PROC " << name()
553	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
554	<< " / HIT = " << cache_hit
555	<< " / PADDR = " << std::hex << addr
556	<< " / DATA = " << cache_rdata
557	<< " / WAY = " << cache_way << std::endl;
558	m_debug_previous_i_hit = cache_hit;
559	}
560	}
561
562	/*
563	////////////////////////
564	tmpl(void)::print_stats()
565	////////////////////////
566	{
567	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
568	std::cout << name() << std::endl
569	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
570	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
571	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
572	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
573	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
574	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
575	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
576	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
577	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
578	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
579	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
580	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
581	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
582	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
583	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
584	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
585	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
586	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
587	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
588	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
589	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
590	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
591	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
592	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
593	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
594	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
595	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
596	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
597	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
598	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
599	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
600	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
601	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
602	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
603	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
604	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
605	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
606	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
607	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
608	}
609
610	////////////////////////
611	tmpl(void)::clear_stats()
612	////////////////////////
613	{
614	m_cpt_dcache_data_read = 0;
615	m_cpt_dcache_data_write = 0;
616	m_cpt_dcache_dir_read = 0;
617	m_cpt_dcache_dir_write = 0;
618	m_cpt_icache_data_read = 0;
619	m_cpt_icache_data_write = 0;
620	m_cpt_icache_dir_read = 0;
621	m_cpt_icache_dir_write = 0;
622
623	m_cpt_frz_cycles = 0;
624	m_cpt_dcache_frz_cycles = 0;
625	m_cpt_total_cycles = 0;
626
627	m_cpt_read = 0;
628	m_cpt_write = 0;
629	m_cpt_data_miss = 0;
630	m_cpt_ins_miss = 0;
631	m_cpt_unc_read = 0;
632	m_cpt_write_cached = 0;
633	m_cpt_ins_read = 0;
634
635	m_cost_write_frz = 0;
636	m_cost_data_miss_frz = 0;
637	m_cost_unc_read_frz = 0;
638	m_cost_ins_miss_frz = 0;
639
640	m_cpt_imiss_transaction = 0;
641	m_cpt_dmiss_transaction = 0;
642	m_cpt_unc_transaction = 0;
643	m_cpt_write_transaction = 0;
644	m_cpt_icache_unc_transaction = 0;
645
646	m_cost_imiss_transaction = 0;
647	m_cost_dmiss_transaction = 0;
648	m_cost_unc_transaction = 0;
649	m_cost_write_transaction = 0;
650	m_cost_icache_unc_transaction = 0;
651	m_length_write_transaction = 0;
652
653	m_cpt_ins_tlb_read = 0;
654	m_cpt_ins_tlb_miss = 0;
655	m_cpt_ins_tlb_update_acc = 0;
656
657	m_cpt_data_tlb_read = 0;
658	m_cpt_data_tlb_miss = 0;
659	m_cpt_data_tlb_update_acc = 0;
660	m_cpt_data_tlb_update_dirty = 0;
661	m_cpt_ins_tlb_hit_dcache = 0;
662	m_cpt_data_tlb_hit_dcache = 0;
663	m_cpt_ins_tlb_occup_cache = 0;
664	m_cpt_data_tlb_occup_cache = 0;
665
666	m_cost_ins_tlb_miss_frz = 0;
667	m_cost_data_tlb_miss_frz = 0;
668	m_cost_ins_tlb_update_acc_frz = 0;
669	m_cost_data_tlb_update_acc_frz = 0;
670	m_cost_data_tlb_update_dirty_frz = 0;
671	m_cost_ins_tlb_occup_cache_frz = 0;
672	m_cost_data_tlb_occup_cache_frz = 0;
673
674	m_cpt_itlbmiss_transaction = 0;
675	m_cpt_itlb_ll_transaction = 0;
676	m_cpt_itlb_sc_transaction = 0;
677	m_cpt_dtlbmiss_transaction = 0;
678	m_cpt_dtlb_ll_transaction = 0;
679	m_cpt_dtlb_sc_transaction = 0;
680	m_cpt_dtlb_ll_dirty_transaction = 0;
681	m_cpt_dtlb_sc_dirty_transaction = 0;
682
683	m_cost_itlbmiss_transaction = 0;
684	m_cost_itlb_ll_transaction = 0;
685	m_cost_itlb_sc_transaction = 0;
686	m_cost_dtlbmiss_transaction = 0;
687	m_cost_dtlb_ll_transaction = 0;
688	m_cost_dtlb_sc_transaction = 0;
689	m_cost_dtlb_ll_dirty_transaction = 0;
690	m_cost_dtlb_sc_dirty_transaction = 0;
691
692	m_cpt_cc_update_data = 0;
693	m_cpt_cc_inval_ins = 0;
694	m_cpt_cc_inval_data = 0;
695	m_cpt_cc_broadcast = 0;
696
697	m_cost_updt_data_frz = 0;
698	m_cost_inval_ins_frz = 0;
699	m_cost_inval_data_frz = 0;
700	m_cost_broadcast_frz = 0;
701
702	m_cpt_cc_cleanup_data = 0;
703	m_cpt_cc_cleanup_ins = 0;
704	}
705
706	*/
707
708	/////////////////////////
709	tmpl(void)::transition()
710	/////////////////////////
711	{
712	if ( not p_resetn.read() )
713	{
714	r_iss.reset();
715	r_wbuf.reset();
716	r_icache.reset();
717	r_dcache.reset();
718	r_itlb.reset();
719	r_dtlb.reset();
720
721	r_dcache_fsm = DCACHE_IDLE;
722	r_icache_fsm = ICACHE_IDLE;
723	r_vci_cmd_fsm = CMD_IDLE;
724	r_vci_rsp_fsm = RSP_IDLE;
725	r_cc_receive_fsm = CC_RECEIVE_IDLE;
726	r_cc_send_fsm = CC_SEND_IDLE;
727
728	// reset data physical address extension
729	r_dcache_paddr_ext = 0;
730
731	// reset dcache directory extension
732	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
733	{
734	r_dcache_in_tlb[i] = false;
735	r_dcache_contains_ptd[i] = false;
736	}
737
738	// Response FIFOs and cleanup buffer
739	r_vci_rsp_fifo_icache.init();
740	r_vci_rsp_fifo_dcache.init();
741
742	// ICACHE & DCACHE activated
743	// ITLB & DTLB desactivated
744	r_mmu_mode = 0x3;
745
746	// No request from ICACHE FSM to CMD FSM
747	r_icache_miss_req = false;
748	r_icache_unc_req = false;
749
750	// No request from ICACHE_FSM to DCACHE FSM
751	r_icache_tlb_miss_req = false;
752
753	// No request from ICACHE_FSM to CC_SEND FSM
754	r_icache_cc_send_req = false;
755
756	r_icache_clack_req = false;
757
758	// No pending write in pipeline
759	r_dcache_wbuf_req = false;
760	r_dcache_updt_req = false;
761
762	// No request from DCACHE_FSM to CMD_FSM
763	r_dcache_vci_miss_req = false;
764	r_dcache_vci_unc_req = false;
765	r_dcache_vci_cas_req = false;
766	r_dcache_vci_ll_req = false;
767	r_dcache_vci_sc_req = false;
768
769	// No uncacheable write pending
770	r_dcache_pending_unc_write = false;
771
772	// No processor XTN request pending
773	r_dcache_xtn_req = false;
774
775	// No request from DCACHE FSM to CC_SEND FSM
776	r_dcache_cc_send_req = false;
777
778	r_dcache_clack_req = false;
779
780	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
781	r_cc_receive_icache_req = false;
782	r_cc_receive_dcache_req = false;
783
784	// last cc_send client was dcache
785	r_cc_send_last_client = false;
786
787	// No pending cleanup after a replacement
788	r_icache_miss_clack = false;
789	r_dcache_miss_clack = false;
790
791	// No signalisation of a coherence request matching a pending miss
792	r_icache_miss_inval = false;
793	r_dcache_miss_inval = false;
794
795	r_dspin_clack_req = false;
796
797	// No signalisation of errors
798	r_vci_rsp_ins_error = false;
799	r_vci_rsp_data_error = false;
800
801	// Debug variables
802	m_debug_previous_i_hit = false;
803	m_debug_previous_d_hit = false;
804	m_debug_activated = false;
805
806	// activity counters
807	m_cpt_dcache_data_read = 0;
808	m_cpt_dcache_data_write = 0;
809	m_cpt_dcache_dir_read = 0;
810	m_cpt_dcache_dir_write = 0;
811	m_cpt_icache_data_read = 0;
812	m_cpt_icache_data_write = 0;
813	m_cpt_icache_dir_read = 0;
814	m_cpt_icache_dir_write = 0;
815
816	m_cpt_frz_cycles = 0;
817	m_cpt_total_cycles = 0;
818	m_cpt_stop_simulation = 0;
819
820	m_cpt_data_miss = 0;
821	m_cpt_ins_miss = 0;
822	m_cpt_unc_read = 0;
823	m_cpt_write_cached = 0;
824	m_cpt_ins_read = 0;
825
826	m_cost_write_frz = 0;
827	m_cost_data_miss_frz = 0;
828	m_cost_unc_read_frz = 0;
829	m_cost_ins_miss_frz = 0;
830
831	m_cpt_imiss_transaction = 0;
832	m_cpt_dmiss_transaction = 0;
833	m_cpt_unc_transaction = 0;
834	m_cpt_write_transaction = 0;
835	m_cpt_icache_unc_transaction = 0;
836
837	m_cost_imiss_transaction = 0;
838	m_cost_dmiss_transaction = 0;
839	m_cost_unc_transaction = 0;
840	m_cost_write_transaction = 0;
841	m_cost_icache_unc_transaction = 0;
842	m_length_write_transaction = 0;
843
844	m_cpt_ins_tlb_read = 0;
845	m_cpt_ins_tlb_miss = 0;
846	m_cpt_ins_tlb_update_acc = 0;
847
848	m_cpt_data_tlb_read = 0;
849	m_cpt_data_tlb_miss = 0;
850	m_cpt_data_tlb_update_acc = 0;
851	m_cpt_data_tlb_update_dirty = 0;
852	m_cpt_ins_tlb_hit_dcache = 0;
853	m_cpt_data_tlb_hit_dcache = 0;
854	m_cpt_ins_tlb_occup_cache = 0;
855	m_cpt_data_tlb_occup_cache = 0;
856
857	m_cost_ins_tlb_miss_frz = 0;
858	m_cost_data_tlb_miss_frz = 0;
859	m_cost_ins_tlb_update_acc_frz = 0;
860	m_cost_data_tlb_update_acc_frz = 0;
861	m_cost_data_tlb_update_dirty_frz = 0;
862	m_cost_ins_tlb_occup_cache_frz = 0;
863	m_cost_data_tlb_occup_cache_frz = 0;
864
865	m_cpt_ins_tlb_inval = 0;
866	m_cpt_data_tlb_inval = 0;
867	m_cost_ins_tlb_inval_frz = 0;
868	m_cost_data_tlb_inval_frz = 0;
869
870	m_cpt_cc_broadcast = 0;
871
872	m_cost_updt_data_frz = 0;
873	m_cost_inval_ins_frz = 0;
874	m_cost_inval_data_frz = 0;
875	m_cost_broadcast_frz = 0;
876
877	m_cpt_cc_cleanup_data = 0;
878	m_cpt_cc_cleanup_ins = 0;
879
880	m_cpt_itlbmiss_transaction = 0;
881	m_cpt_itlb_ll_transaction = 0;
882	m_cpt_itlb_sc_transaction = 0;
883	m_cpt_dtlbmiss_transaction = 0;
884	m_cpt_dtlb_ll_transaction = 0;
885	m_cpt_dtlb_sc_transaction = 0;
886	m_cpt_dtlb_ll_dirty_transaction = 0;
887	m_cpt_dtlb_sc_dirty_transaction = 0;
888
889	m_cost_itlbmiss_transaction = 0;
890	m_cost_itlb_ll_transaction = 0;
891	m_cost_itlb_sc_transaction = 0;
892	m_cost_dtlbmiss_transaction = 0;
893	m_cost_dtlb_ll_transaction = 0;
894	m_cost_dtlb_sc_transaction = 0;
895	m_cost_dtlb_ll_dirty_transaction = 0;
896	m_cost_dtlb_sc_dirty_transaction = 0;
897	/*
898	m_cpt_dcache_frz_cycles = 0;
899	m_cpt_read = 0;
900	m_cpt_write = 0;
901	m_cpt_cc_update_data = 0;
902	m_cpt_cc_inval_ins = 0;
903	m_cpt_cc_inval_data = 0;
904	*/
905
906	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
907	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
908	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
909	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
910
911	// init the llsc reservation buffer
912	r_dcache_llsc_valid = false;
913	m_monitor_ok = false;
914
915	return;
916	}
917
918	// Response FIFOs default values
919	bool vci_rsp_fifo_icache_get = false;
920	bool vci_rsp_fifo_icache_put = false;
921	uint32_t vci_rsp_fifo_icache_data = 0;
922
923	bool vci_rsp_fifo_dcache_get = false;
924	bool vci_rsp_fifo_dcache_put = false;
925	uint32_t vci_rsp_fifo_dcache_data = 0;
926
927	// updt fifo
928	bool cc_receive_updt_fifo_get = false;
929	bool cc_receive_updt_fifo_put = false;
930	uint32_t cc_receive_updt_fifo_be = 0;
931	uint32_t cc_receive_updt_fifo_data = 0;
932	bool cc_receive_updt_fifo_eop = false;
933
934	#ifdef INSTRUMENTATION
935	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
936	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
937	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
938	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
939	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
940	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
941	#endif
942
943	m_cpt_total_cycles++;
944
945	m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
946
947	/////////////////////////////////////////////////////////////////////
948	// Get data and instruction requests from processor
949	///////////////////////////////////////////////////////////////////////
950
951	r_iss.getRequests(m_ireq, m_dreq);
952
953	////////////////////////////////////////////////////////////////////////////////////
954	// ICACHE_FSM
955	//
956	// 1/ Coherence operations
957	// They are handled as interrupts generated by the CC_RECEIVE FSM.
958	// - There is a coherence request when r_tgt_icache_req is set.
959	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
960	// - There is a cleanup ack request when r_cleanup_icache_req is set.
961	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
962	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
963	// - For both types of requests, actions associated to the pre-empted state
964	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
965	// or CC_CLACK) to execute the requested coherence operation, and returns
966	// to the pre-empted state.
967	//
968	// 2/ Processor requests
969	// They are taken in IDLE state only. In case of cache miss, or uncacheable
970	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
971	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
972	// flip-flops are reset when the transaction starts.
973	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
974	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
975	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
976	// The availability of the missing cache line is signaled by the response fifo,
977	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
978	// and ICACHE_MISS_DIR_UPDT states.
979	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
980	// to wait the response from the RSP FSM, through the response fifo.
981	// The missing instruction is directly returned to processor in this state.
982	//
983	// 3/ TLB miss
984	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
985	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
986	// register, and goes to the ICACHE_TLB_WAIT state.
987	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
988	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
989	// to signal the completion.
990	//
991	// 4/ XTN requests
992	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
993	// using the r_dcache_xtn_req flip-flop.
994	// The request opcode and the address to be invalidated are transmitted
995	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
996	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
997	// is completed.
998	//
999	// 5/ Error Handling
1000	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1001	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1002	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1003	////////////////////////////////////////////////////////////////////////////////////////
1004
1005	// default value for m_irsp
1006	m_irsp.valid = false;
1007	m_irsp.error = false;
1008	m_irsp.instruction = 0;
1009
1010	switch( r_icache_fsm.read() )
1011	{
1012	/////////////////
1013	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1014	// and coherence requests with a fixed priority:
1015	// 1/ Coherence requests => ICACHE_CC_CHECK
1016	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1017	// 3/ tlb miss => ICACHE_TLB_WAIT
1018	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1019	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1020	{
1021	// coherence clack interrupt
1022	if ( r_icache_clack_req.read() )
1023	{
1024	r_icache_fsm = ICACHE_CC_CHECK;
1025	r_icache_fsm_save = r_icache_fsm.read();
1026	break;
1027	}
1028
1029	// coherence interrupt
1030	if ( r_cc_receive_icache_req.read() )
1031	{
1032	r_icache_fsm = ICACHE_CC_CHECK;
1033	r_icache_fsm_save = r_icache_fsm.read();
1034	break;
1035	}
1036
1037	// XTN requests sent by DCACHE FSM
1038	// These request are not executed in this IDLE state, because
1039	// they require access to icache or itlb, that are already accessed
1040	if ( r_dcache_xtn_req.read() )
1041	{
1042	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1043	{
1044	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1045	}
1046	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1047	{
1048	r_icache_flush_count = 0;
1049	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1050	}
1051	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1052	{
1053	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1054	}
1055	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1056	{
1057	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1058	}
1059	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1060	{
1061	if (sizeof(paddr_t) <= 32)
1062	{
1063	assert(r_mmu_word_hi.read() == 0 &&
1064	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1065	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1066	}
1067	else
1068	{
1069	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1070	(paddr_t)r_mmu_word_lo.read();
1071	}
1072	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1073	}
1074	else
1075	{
1076	assert( false and
1077	"undefined XTN request received by ICACHE FSM");
1078	}
1079	break;
1080	} // end if xtn_req
1081
1082	// processor request
1083	if ( m_ireq.valid )
1084	{
1085	bool cacheable;
1086	paddr_t paddr;
1087	bool tlb_hit = false;
1088	pte_info_t tlb_flags;
1089	size_t tlb_way;
1090	size_t tlb_set;
1091	paddr_t tlb_nline;
1092	uint32_t cache_inst = 0;
1093	size_t cache_way;
1094	size_t cache_set;
1095	size_t cache_word;
1096	int cache_state = CACHE_SLOT_STATE_EMPTY;
1097
1098	// We register processor request
1099	r_icache_vaddr_save = m_ireq.addr;
1100
1101	// sytematic itlb access (if activated)
1102	if ( r_mmu_mode.read() & INS_TLB_MASK )
1103	{
1104
1105	#ifdef INSTRUMENTATION
1106	m_cpt_itlb_read++;
1107	#endif
1108	tlb_hit = r_itlb.translate( m_ireq.addr,
1109	&paddr,
1110	&tlb_flags,
1111	&tlb_nline, // unused
1112	&tlb_way, // unused
1113	&tlb_set ); // unused
1114	}
1115	else
1116	{
1117	paddr = (paddr_t)m_ireq.addr;
1118	}
1119
1120	// systematic icache access (if activated)
1121	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1122	{
1123
1124
1125	#ifdef INSTRUMENTATION
1126	m_cpt_icache_data_read++;
1127	m_cpt_icache_dir_read++;
1128	#endif
1129	r_icache.read( paddr,
1130	&cache_inst,
1131	&cache_way,
1132	&cache_set,
1133	&cache_word,
1134	&cache_state );
1135	}
1136
1137	// We compute cacheability and check access rights:
1138	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1139	// and the access rights are defined by the U and X bits in the PTE.
1140	// - If MMU not activated : cacheability is defined by the segment table,
1141	// and there is no access rights checking
1142
1143	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1144	{
1145	// cacheability
1146	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1147	else cacheable = m_cacheability_table[m_ireq.addr];
1148	}
1149	else // itlb activated
1150	{
1151	if ( tlb_hit ) // ITLB hit
1152	{
1153	// cacheability
1154	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1155	else cacheable = tlb_flags.c;
1156
1157	// access rights checking
1158	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1159	{
1160	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1161	r_mmu_ibvar = m_ireq.addr;
1162	m_irsp.valid = true;
1163	m_irsp.error = true;
1164	m_irsp.instruction = 0;
1165	break;
1166	}
1167	else if ( not tlb_flags.x )
1168	{
1169	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1170	r_mmu_ibvar = m_ireq.addr;
1171	m_irsp.valid = true;
1172	m_irsp.error = true;
1173	m_irsp.instruction = 0;
1174	break;
1175	}
1176	}
1177	else // ITLB miss
1178	{
1179
1180	#ifdef INSTRUMENTATION
1181	m_cpt_itlb_miss++;
1182	#endif
1183	r_icache_fsm = ICACHE_TLB_WAIT;
1184	r_icache_tlb_miss_req = true;
1185	break;
1186	}
1187	} // end if itlb activated
1188
1189	// physical address registration
1190	r_icache_vci_paddr = paddr;
1191
1192	// Finally, we send the response to processor, and compute next state
1193	if ( cacheable )
1194	{
1195	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1196	{
1197
1198	#ifdef INSTRUMENTATION
1199	m_cpt_icache_miss++;
1200	#endif
1201	// we request a VCI transaction
1202	r_icache_fsm = ICACHE_MISS_SELECT;
1203	#if DEBUG_ICACHE
1204	if ( m_debug_activated )
1205	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1206	<< " : PADDR = " << std::hex << paddr << std::endl;
1207	#endif
1208	r_icache_miss_req = true;
1209	}
1210	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1211	{
1212	// stalled until cleanup is acknowledged
1213	r_icache_fsm = ICACHE_IDLE;
1214	}
1215	else // cache hit
1216	{
1217
1218	#ifdef INSTRUMENTATION
1219	m_cpt_ins_read++;
1220	#endif
1221	// return instruction to processor
1222	m_irsp.valid = true;
1223	m_irsp.instruction = cache_inst;
1224	r_icache_fsm = ICACHE_IDLE;
1225	#if DEBUG_ICACHE
1226	if ( m_debug_activated )
1227	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1228	<< " : PADDR = " << std::hex << paddr << std::endl;
1229	#endif
1230	}
1231	}
1232	else // non cacheable read
1233	{
1234	r_icache_unc_req = true;
1235	r_icache_fsm = ICACHE_UNC_WAIT;
1236
1237	#if DEBUG_ICACHE
1238	if ( m_debug_activated )
1239	{
1240	std::cout << " <PROC " << name()
1241	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1242	<< " : PADDR = " << std::hex << paddr << std::endl;
1243	}
1244	#endif
1245	}
1246	} // end if m_ireq.valid
1247	break;
1248	}
1249	/////////////////////
1250	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1251	// the itlb is udated by the DCACHE FSM, as well as the
1252	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1253	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1254	// reset the r_icache_tlb_miss_req flip-flop
1255	// external coherence request are accepted in this state.
1256	{
1257	// coherence clack interrupt
1258	if ( r_icache_clack_req.read() )
1259	{
1260	r_icache_fsm = ICACHE_CC_CHECK;
1261	r_icache_fsm_save = r_icache_fsm.read();
1262	break;
1263	}
1264
1265	// coherence interrupt
1266	if ( r_cc_receive_icache_req.read() )
1267	{
1268	r_icache_fsm = ICACHE_CC_CHECK;
1269	r_icache_fsm_save = r_icache_fsm.read();
1270	break;
1271	}
1272
1273	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1274
1275	// DCACHE FSM signals response by reseting the request flip-flop
1276	if ( not r_icache_tlb_miss_req.read() )
1277	{
1278	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1279	{
1280	r_icache_tlb_rsp_error = false;
1281	m_irsp.error = true;
1282	m_irsp.valid = true;
1283	r_icache_fsm = ICACHE_IDLE;
1284	}
1285	else // tlb updated : return to IDLE state
1286	{
1287	r_icache_fsm = ICACHE_IDLE;
1288	}
1289	}
1290	break;
1291	}
1292	//////////////////////////
1293	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1294	{
1295	r_itlb.flush();
1296	r_dcache_xtn_req = false;
1297	r_icache_fsm = ICACHE_IDLE;
1298	break;
1299	}
1300	////////////////////////////
1301	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1302	// r_icache_flush_count as a slot counter,
1303	// looping in this state until all slots are visited.
1304	// It can require two cycles per slot:
1305	// We test here the slot state, and make the actual inval
1306	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1307	// A cleanup request is generated for each valid line
1308	{
1309	// coherence clack interrupt
1310	if ( r_icache_clack_req.read() )
1311	{
1312	r_icache_fsm = ICACHE_CC_CHECK;
1313	r_icache_fsm_save = r_icache_fsm.read();
1314	break;
1315	}
1316
1317	// coherence request (from CC_RECEIVE FSM)
1318	if ( r_cc_receive_icache_req.read() )
1319	{
1320	r_icache_fsm = ICACHE_CC_CHECK;
1321	r_icache_fsm_save = r_icache_fsm.read();
1322	break;
1323	}
1324
1325	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1326	{
1327	int state;
1328	paddr_t tag;
1329	size_t way = r_icache_flush_count.read()/m_icache_sets;
1330	size_t set = r_icache_flush_count.read()%m_icache_sets;
1331
1332	#ifdef INSTRUMENTATION
1333	m_cpt_icache_dir_read++;
1334	#endif
1335	r_icache.read_dir( way,
1336	set,
1337	&tag,
1338	&state );
1339
1340	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1341	{
1342	// request cleanup
1343	r_icache_cc_send_req = true;
1344	r_icache_cc_send_nline = tag * m_icache_sets + set;
1345	r_icache_cc_send_way = way;
1346	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1347
1348	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1349	r_icache_miss_way = way;
1350	r_icache_miss_set = set;
1351	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1352	}
1353	else if ( r_icache_flush_count.read() ==
1354	(m_icache_sets*m_icache_ways - 1) ) // last slot
1355	{
1356	r_dcache_xtn_req = false;
1357	m_drsp.valid = true;
1358	r_icache_fsm = ICACHE_IDLE;
1359	}
1360
1361	// saturation counter, to have the same last slot condition
1362	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1363	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1364	{
1365	r_icache_flush_count = r_icache_flush_count.read() + 1;
1366	}
1367	}
1368	break;
1369	}
1370	///////////////////////////////
1371	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1372	{
1373	size_t way = r_icache_miss_way.read();
1374	size_t set = r_icache_miss_set.read();
1375
1376	#ifdef INSTRUMENTATION
1377	m_cpt_icache_dir_write++;
1378	#endif
1379
1380	r_icache.write_dir( way,
1381	set,
1382	CACHE_SLOT_STATE_ZOMBI );
1383
1384	if ( r_icache_flush_count.read() ==
1385	(m_icache_sets*m_icache_ways - 1) ) // last slot
1386	{
1387	r_dcache_xtn_req = false;
1388	m_drsp.valid = true;
1389	r_icache_fsm = ICACHE_IDLE;
1390	}
1391	else
1392	{
1393	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1394	}
1395	break;
1396	}
1397
1398	//////////////////////////
1399	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1400	// stored in the r_dcache_save_wdata register
1401	{
1402	r_itlb.inval(r_dcache_save_wdata.read());
1403	r_dcache_xtn_req = false;
1404	r_icache_fsm = ICACHE_IDLE;
1405	break;
1406	}
1407	///////////////////////////////
1408	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1409	// requires 3 cycles (in case of hit on itlb and icache).
1410	// In this state, access TLB to translate virtual address
1411	// stored in the r_dcache_save_wdata register.
1412	{
1413	paddr_t paddr;
1414	bool hit;
1415
1416	// read physical address in TLB when MMU activated
1417	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1418	{
1419
1420	#ifdef INSTRUMENTATION
1421	m_cpt_itlb_read++;
1422	#endif
1423	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1424	&paddr);
1425	}
1426	else // itlb not activated
1427	{
1428	paddr = (paddr_t)r_dcache_save_wdata.read();
1429	hit = true;
1430	}
1431
1432	if ( hit ) // continue the selective inval process
1433	{
1434	r_icache_vci_paddr = paddr;
1435	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1436	}
1437	else // miss : send a request to DCACHE FSM
1438	{
1439
1440	#ifdef INSTRUMENTATION
1441	m_cpt_itlb_miss++;
1442	#endif
1443	r_icache_tlb_miss_req = true;
1444	r_icache_vaddr_save = r_dcache_save_wdata.read();
1445	r_icache_fsm = ICACHE_TLB_WAIT;
1446	}
1447	break;
1448	}
1449	///////////////////////////////
1450	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1451	// require 2 cycles. In this state, we read directory
1452	// with address stored in r_icache_vci_paddr register.
1453	{
1454	int state;
1455	size_t way;
1456	size_t set;
1457	size_t word;
1458
1459	#ifdef INSTRUMENTATION
1460	m_cpt_icache_dir_read++;
1461	#endif
1462	r_icache.read_dir(r_icache_vci_paddr.read(),
1463	&state,
1464	&way,
1465	&set,
1466	&word);
1467
1468	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1469	{
1470	r_icache_miss_way = way;
1471	r_icache_miss_set = set;
1472	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1473	}
1474	else // miss : acknowlege the XTN request and return
1475	{
1476	r_dcache_xtn_req = false;
1477	r_icache_fsm = ICACHE_IDLE;
1478	}
1479	break;
1480	}
1481	///////////////////////////////
1482	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1483	{
1484	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1485	{
1486
1487	#ifdef INSTRUMENTATION
1488	m_cpt_icache_dir_write++;
1489	#endif
1490	r_icache.write_dir( r_icache_miss_way.read(),
1491	r_icache_miss_set.read(),
1492	CACHE_SLOT_STATE_ZOMBI );
1493
1494	// request cleanup
1495	r_icache_cc_send_req = true;
1496	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1497	r_icache_cc_send_way = r_icache_miss_way.read();
1498	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1499
1500	// acknowledge the XTN request and return
1501	r_dcache_xtn_req = false;
1502	r_icache_fsm = ICACHE_IDLE;
1503	}
1504	break;
1505	}
1506	////////////////////////
1507	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1508	// if previous cleanup has been sent.
1509	// Waiting in this state if no slot available.
1510	// Set the r_icache_cleanup_req flip-flop
1511	// and the r_icache_miss_clack flip-flop,
1512	// when a cleanup is required
1513	{
1514	if (m_ireq.valid) m_cost_ins_miss_frz++;
1515
1516	// coherence clack interrupt
1517	if ( r_icache_clack_req.read() )
1518	{
1519	r_icache_fsm = ICACHE_CC_CHECK;
1520	r_icache_fsm_save = r_icache_fsm.read();
1521	break;
1522	}
1523
1524	// coherence interrupt
1525	if ( r_cc_receive_icache_req.read() )
1526	{
1527	r_icache_fsm = ICACHE_CC_CHECK;
1528	r_icache_fsm_save = r_icache_fsm.read();
1529	break;
1530	}
1531
1532	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1533	{
1534	bool found;
1535	bool cleanup;
1536	size_t way;
1537	size_t set;
1538	paddr_t victim;
1539
1540	#ifdef INSTRUMENTATION
1541	m_cpt_icache_dir_read++;
1542	#endif
1543	r_icache.read_select(r_icache_vci_paddr.read(),
1544	&victim,
1545	&way,
1546	&set,
1547	&found,
1548	&cleanup );
1549	if ( found )
1550	{
1551	r_icache_miss_way = way;
1552	r_icache_miss_set = set;
1553
1554	if ( cleanup )
1555	{
1556	r_icache_fsm = ICACHE_MISS_CLEAN;
1557	r_icache_miss_clack = true;
1558	// request cleanup
1559	r_icache_cc_send_req = true;
1560	r_icache_cc_send_nline = victim;
1561	r_icache_cc_send_way = way;
1562	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1563	}
1564	else
1565	{
1566	r_icache_fsm = ICACHE_MISS_WAIT;
1567	}
1568
1569	#if DEBUG_ICACHE
1570	if ( m_debug_activated )
1571	{
1572	std::cout << " <PROC " << name()
1573	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1574	<< " / WAY = " << way
1575	<< " / SET = " << set;
1576	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1577	else std::cout << std::endl;
1578	}
1579	#endif
1580	}
1581	}
1582	break;
1583	}
1584	///////////////////////
1585	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1586	{
1587	if (m_ireq.valid) m_cost_ins_miss_frz++;
1588
1589	#ifdef INSTRUMENTATION
1590	m_cpt_icache_dir_write++;
1591	#endif
1592	r_icache.write_dir( r_icache_miss_way.read(),
1593	r_icache_miss_set.read(),
1594	CACHE_SLOT_STATE_ZOMBI);
1595	#if DEBUG_ICACHE
1596	if ( m_debug_activated )
1597	{
1598	std::cout << " <PROC " << name()
1599	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1600	<< " / WAY = " << r_icache_miss_way.read()
1601	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1602	}
1603	#endif
1604
1605	r_icache_fsm = ICACHE_MISS_WAIT;
1606	break;
1607	}
1608	//////////////////////
1609	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1610	{
1611	if (m_ireq.valid) m_cost_ins_miss_frz++;
1612
1613	// coherence clack interrupt
1614	if ( r_icache_clack_req.read() )
1615	{
1616	r_icache_fsm = ICACHE_CC_CHECK;
1617	r_icache_fsm_save = r_icache_fsm.read();
1618	break;
1619	}
1620
1621	// coherence interrupt
1622	if ( r_cc_receive_icache_req.read() )
1623	{
1624	r_icache_fsm = ICACHE_CC_CHECK;
1625	r_icache_fsm_save = r_icache_fsm.read();
1626	break;
1627	}
1628
1629	if ( r_vci_rsp_ins_error.read() ) // bus error
1630	{
1631	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1632	r_mmu_ibvar = r_icache_vaddr_save.read();
1633	m_irsp.valid = true;
1634	m_irsp.error = true;
1635	r_vci_rsp_ins_error = false;
1636	r_icache_fsm = ICACHE_IDLE;
1637	}
1638	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1639	{
1640	r_icache_miss_word = 0;
1641	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1642	}
1643	break;
1644	}
1645	///////////////////////////
1646	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1647	{
1648	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1649
1650	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1651	{
1652
1653	#ifdef INSTRUMENTATION
1654	m_cpt_icache_data_write++;
1655	#endif
1656	r_icache.write( r_icache_miss_way.read(),
1657	r_icache_miss_set.read(),
1658	r_icache_miss_word.read(),
1659	r_vci_rsp_fifo_icache.read() );
1660	#if DEBUG_ICACHE
1661	if ( m_debug_activated )
1662	{
1663	std::cout << " <PROC " << name()
1664	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1665	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1666	<< " WAY = " << r_icache_miss_way.read()
1667	<< " SET = " << r_icache_miss_set.read()
1668	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1669	}
1670	#endif
1671	vci_rsp_fifo_icache_get = true;
1672	r_icache_miss_word = r_icache_miss_word.read() + 1;
1673
1674	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1675	{
1676	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1677	}
1678	}
1679	break;
1680	}
1681	//////////////////////////
1682	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1683	// and the cleanup ack has not been received,
1684	// as indicated by r_icache_miss_clack.
1685	// - If no matching coherence request (r_icache_miss_inval)
1686	// switch directory slot to VALID state.
1687	// - If matching coherence request, switch directory slot
1688	// to ZOMBI state, and send a cleanup request.
1689	{
1690	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1691
1692	// coherence clack interrupt
1693	if ( r_icache_clack_req.read() )
1694	{
1695	r_icache_fsm = ICACHE_CC_CHECK;
1696	r_icache_fsm_save = r_icache_fsm.read();
1697	break;
1698	}
1699
1700	// coherence interrupt
1701	if ( r_cc_receive_icache_req.read() )
1702	{
1703	r_icache_fsm = ICACHE_CC_CHECK;
1704	r_icache_fsm_save = r_icache_fsm.read();
1705	break;
1706	}
1707
1708	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1709	{
1710	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1711	{
1712	if ( not r_icache_cc_send_req.read() )
1713	{
1714	r_icache_miss_inval = false;
1715	// request cleanup
1716	r_icache_cc_send_req = true;
1717	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1718	r_icache_cc_send_way = r_icache_miss_way.read();
1719	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1720
1721	#ifdef INSTRUMENTATION
1722	m_cpt_icache_dir_write++;
1723	#endif
1724	r_icache.write_dir( r_icache_vci_paddr.read(),
1725	r_icache_miss_way.read(),
1726	r_icache_miss_set.read(),
1727	CACHE_SLOT_STATE_ZOMBI );
1728	#if DEBUG_ICACHE
1729	if ( m_debug_activated )
1730	{
1731	std::cout << " <PROC " << name()
1732	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1733	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1734	<< " WAY = " << std::dec << r_icache_miss_way.read()
1735	<< " SET = " << r_icache_miss_set.read() << std::endl;
1736	}
1737	#endif
1738	}
1739	else
1740	break;
1741	}
1742	else // Switch slot to VALID state
1743	{
1744
1745	#ifdef INSTRUMENTATION
1746	m_cpt_icache_dir_write++;
1747	#endif
1748	r_icache.write_dir( r_icache_vci_paddr.read(),
1749	r_icache_miss_way.read(),
1750	r_icache_miss_set.read(),
1751	CACHE_SLOT_STATE_VALID );
1752	#if DEBUG_ICACHE
1753	if ( m_debug_activated )
1754	{
1755	std::cout << " <PROC " << name()
1756	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1757	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1758	<< " WAY = " << std::dec << r_icache_miss_way.read()
1759	<< " SET = " << r_icache_miss_set.read() << std::endl;
1760	}
1761	#endif
1762	}
1763
1764	r_icache_fsm = ICACHE_IDLE;
1765	}
1766	break;
1767	}
1768	////////////////////
1769	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1770	{
1771	// coherence clack interrupt
1772	if ( r_icache_clack_req.read() )
1773	{
1774	r_icache_fsm = ICACHE_CC_CHECK;
1775	r_icache_fsm_save = r_icache_fsm.read();
1776	break;
1777	}
1778
1779	// coherence interrupt
1780	if ( r_cc_receive_icache_req.read() )
1781	{
1782	r_icache_fsm = ICACHE_CC_CHECK;
1783	r_icache_fsm_save = r_icache_fsm.read();
1784	break;
1785	}
1786
1787	if ( r_vci_rsp_ins_error.read() ) // bus error
1788	{
1789	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1790	r_mmu_ibvar = m_ireq.addr;
1791	r_vci_rsp_ins_error = false;
1792	m_irsp.valid = true;
1793	m_irsp.error = true;
1794	r_icache_fsm = ICACHE_IDLE;
1795	}
1796	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1797	{
1798	vci_rsp_fifo_icache_get = true;
1799	r_icache_fsm = ICACHE_IDLE;
1800	if ( m_ireq.valid and
1801	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1802	{
1803	m_irsp.valid = true;
1804	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1805	}
1806	}
1807	break;
1808	}
1809	/////////////////////
1810	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1811	// handling coherence requests.
1812	// if there is a matching pending miss, it is
1813	// signaled in the r_icache_miss_inval flip-flop.
1814	// The return state is defined in r_icache_fsm_save.
1815	{
1816	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1817	paddr_t mask = ~((m_icache_words<<2)-1);
1818
1819	if (r_icache_clack_req.read())
1820	// We switch the directory slot to EMPTY state
1821	// and reset r_icache_miss_clack if the cleanup ack
1822	// is matching a pending miss
1823	{
1824
1825	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1826
1827	#ifdef INSTRUMENTATION
1828	m_cpt_icache_dir_write++;
1829	#endif
1830	r_icache.write_dir( 0,
1831	r_icache_clack_way.read(),
1832	r_icache_clack_set.read(),
1833	CACHE_SLOT_STATE_EMPTY);
1834
1835	if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
1836	(r_icache_miss_way.read() == r_icache_clack_way.read()) )
1837	r_icache_miss_clack = false;
1838
1839	r_icache_fsm = r_icache_fsm_save.read() ;
1840	r_icache_clack_req = false;
1841
1842	#if DEBUG_ICACHE
1843	if ( m_debug_activated )
1844	{
1845	std::cout << " <PROC " << name()
1846	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1847	<< " set = " << r_icache_clack_set.read()
1848	<< " / way = " << r_icache_clack_way.read() << std::endl;
1849	}
1850	#endif
1851	}
1852	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1853	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1854	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1855	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1856	{
1857	// signaling the matching
1858	r_icache_miss_inval = true;
1859
1860	// in case of update, go to CC_UPDT
1861	// JUST TO POP THE FIFO
1862	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1863	{
1864	r_icache_fsm = ICACHE_CC_UPDT;
1865	r_icache_cc_word = r_cc_receive_word_idx.read();
1866	// just pop the fifo , don't write in icache
1867	r_icache_cc_need_write = false;
1868	}
1869	// the request is dealt with
1870	else
1871	{
1872	r_cc_receive_icache_req = false;
1873	r_icache_fsm = r_icache_fsm_save.read();
1874	}
1875	#if DEBUG_ICACHE
1876	if ( m_debug_activated )
1877	{
1878	std::cout << " <PROC " << name()
1879	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1880	<< " PADDR = " << std::hex << paddr << std::endl;
1881	}
1882	#endif
1883	}
1884	else // no match
1885	{
1886	int state = 0;
1887	size_t way = 0;
1888	size_t set = 0;
1889	size_t word = 0;
1890
1891	#ifdef INSTRUMENTATION
1892	m_cpt_icache_dir_read++;
1893	#endif
1894	r_icache.read_dir(paddr,
1895	&state,
1896	&way,
1897	&set,
1898	&word);
1899
1900	r_icache_cc_way = way;
1901	r_icache_cc_set = set;
1902
1903	if (state == CACHE_SLOT_STATE_VALID) // hit
1904	{
1905	// need to update the cache state
1906	r_icache_cc_need_write = true;
1907	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1908	{
1909	r_icache_fsm = ICACHE_CC_UPDT;
1910	r_icache_cc_word = r_cc_receive_word_idx.read();
1911	}
1912	else if ((r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) \|\| // hit inval
1913	(r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST)) // hit broadcast
1914	{
1915	r_icache_fsm = ICACHE_CC_INVAL;
1916	}
1917	}
1918	else // miss
1919	{
1920	// multicast acknowledgement required in case of update
1921	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1922	{
1923	r_icache_fsm = ICACHE_CC_UPDT;
1924	r_icache_cc_word = r_cc_receive_word_idx.read();
1925	// just pop the fifo , don't write in icache
1926	r_icache_cc_need_write = false;
1927	}
1928	else // No response needed
1929	{
1930	r_cc_receive_icache_req = false;
1931	r_icache_fsm = r_icache_fsm_save.read();
1932	}
1933	}
1934	}
1935	break;
1936	}
1937	////////////////////
1938	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1939	{
1940
1941	#if DEBUG_ICACHE
1942	if ( m_debug_activated )
1943	{
1944	std::cout << " <PROC " << name()
1945	<< " ICACHE_CC_UPDT> Write one word "
1946	<< " set = " << r_icache_cc_set.read()
1947	<< " / way = " << r_icache_cc_way.read()
1948	<< " / word = " << r_icache_cc_word.read() << std::endl;
1949	}
1950	#endif
1951
1952	#ifdef INSTRUMENTATION
1953	m_cpt_icache_data_write++;
1954	#endif
1955	size_t word = r_icache_cc_word.read();
1956	size_t way = r_icache_cc_way.read();
1957	size_t set = r_icache_cc_set.read();
1958
1959	if (r_cc_receive_updt_fifo_be.rok())
1960	{
1961	if (r_icache_cc_need_write.read())
1962	{
1963	r_icache.write( way,
1964	set,
1965	word,
1966	r_cc_receive_updt_fifo_data.read(),
1967	r_cc_receive_updt_fifo_be.read() );
1968
1969	r_icache_cc_word = word+1;
1970	}
1971	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1972	{
1973	// no need to write in the cache anymore
1974	r_icache_cc_need_write = false;
1975	// wait to send a request to cc_send_fsm
1976	if(not r_icache_cc_send_req.read()) // cc_send is available
1977	{
1978	//consume last flit
1979	cc_receive_updt_fifo_get = true;
1980	// coherence request completed
1981	r_cc_receive_icache_req = false;
1982	// request multicast acknowledgement
1983	r_icache_cc_send_req = true;
1984	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1985	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1986	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1987
1988	r_icache_fsm = r_icache_fsm_save.read();
1989	}
1990	}
1991	else
1992	{
1993	//consume fifo if not eop
1994	cc_receive_updt_fifo_get = true;
1995	}
1996	}
1997	break;
1998	}
1999	/////////////////////////
2000	case ICACHE_CC_INVAL: // hit invalidate : switch slot to ZOMBI state
2001	// and request a cleanup
2002	{
2003
2004	#if DEBUG_ICACHE
2005	if ( m_debug_activated )
2006	{
2007	std::cout << " <PROC " << name()
2008	<< " ICACHE_CC_INVAL > Slot goes to zombi state "
2009	<< " set = " << r_icache_cc_set.read()
2010	<< " / way = " << r_icache_cc_way.read() << std::endl;
2011	}
2012	#endif
2013
2014	#ifdef INSTRUMENTATION
2015	m_cpt_icache_dir_write++;
2016	#endif
2017	if (r_icache_cc_need_write.read())
2018	{
2019	r_icache.write_dir( r_icache_cc_way.read(),
2020	r_icache_cc_set.read(),
2021	CACHE_SLOT_STATE_ZOMBI );
2022	// no need to write in the cache anymore
2023	r_icache_cc_need_write = false;
2024	}
2025
2026	// cleanup
2027	// send a request to cc_send_fsm
2028	if(not r_icache_cc_send_req.read()) // cc_send is available
2029	{
2030	// coherence request completed
2031	r_cc_receive_icache_req = false;
2032	// request cleanup
2033	r_icache_cc_send_req = true;
2034	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2035	r_icache_cc_send_way = r_icache_cc_way.read();
2036	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2037
2038	r_icache_fsm = r_icache_fsm_save.read();
2039	}
2040	//else wait for previous cc_send request to be sent
2041	break;
2042	}
2043	} // end switch r_icache_fsm
2044
2045	////////////////////////////////////////////////////////////////////////////////////
2046	// DCACHE FSM
2047	//
2048	// 1/ Coherence operations
2049	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2050	// - There is a coherence request when r_tgt_dcache_req is set.
2051	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2052	// and SC_WAIT states.
2053	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2054	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2055	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2056	// - For both types of requests, actions associated to the pre-empted state
2057	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2058	// or CC_CLACK) to execute the requested coherence operation, and returns
2059	// to the pre-empted state.
2060	//
2061	// 2/ TLB miss
2062	// The page tables are generally cacheable.
2063	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2064	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2065	// this sub-fsm implement the table-walk...
2066	//
2067	// 3/ processor requests
2068	// Processor requests are taken in IDLE state only.
2069	// The IDLE state implements a two stages pipe-line to handle write bursts:
2070	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2071	// - The registration in wbuf and the dcache update is done in stage P1
2072	// (if the processor request is a write).
2073	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2074	// the operations that must be done in P1 stage, and the access type
2075	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2076	// READ requests are delayed if a cache update is requested.
2077	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2078	// that is done (before handling the processor request) by a dedicated sub-fsm.
2079	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2080	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2081	//
2082	// 4/ Atomic instructions LL/SC
2083	// The LL/SC address are non cacheable (systematic access to memory).
2084	// The llsc buffer contains a registration for an active LL/SC operation
2085	// (with an address, a registration key, an aging counter and a valid bit).
2086	// - LL requests from the processor are transmitted as a one flit VCI command
2087	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2088	// be 8 as the response is 2 flits long (data and registration key)
2089	// - SC requests from the processor are systematically transmitted to the
2090	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2091	// as PKTID value). The first flit contains the registration key, the second
2092	// flit contains the data to write in case of success.
2093	// The cache is not updated, as this is done in case of success by the
2094	// coherence transaction.
2095	//
2096	// 5/ Non cacheable access:
2097	// This component implement a strong order between non cacheable access
2098	// (read or write) : A new non cacheable VCI transaction starts only when
2099	// the previous non cacheable transaction is completed. Both cacheable and
2100	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2101	// a non cacheable write transaction posted in the write buffer by setting the
2102	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2103	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2104	// pending non cacheable write transaction completes).
2105	//
2106	// 6/ Error handling:
2107	// When the MMU is not activated, Read Bus Errors are synchronous events,
2108	// but Write Bus Errors are asynchronous events (processor is not frozen).
2109	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2110	// r_vci_rsp_data_error flip-flop, without writing any data in the
2111	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2112	// by the DCACHE FSM.
2113	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2114	// the asynchronous error using the setWriteBerr() method.
2115	// When the MMU is activated bus error are rare events, as the MMU
2116	// checks the physical address before the VCI transaction starts.
2117	////////////////////////////////////////////////////////////////////////////////////////
2118
2119	// default value for m_drsp
2120	m_drsp.valid = false;
2121	m_drsp.error = false;
2122	m_drsp.rdata = 0;
2123
2124	switch ( r_dcache_fsm.read() )
2125	{
2126	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2127	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2128	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2129	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2130	// 4) XTN request (processor) => DCACHE_XTN_*
2131	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2132	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2133	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2134	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2135	// 9) LL access (processor) => DCACHE_LL_WAIT
2136	// 10) SC access (processor) => DCACHE_SC_WAIT
2137	//
2138	// There is a fixed priority to handle requests to DCACHE:
2139	// 1/ the ITLB/DTLB invalidate requests
2140	// 2/ the coherence requests,
2141	// 3/ the processor requests (including DTLB miss),
2142	// 4/ the ITLB miss requests,
2143	// The address space processor request are handled as follows:
2144	// - WRITE request is blocked if the Dirty bit mus be set.
2145	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2146	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2147	// - READ request generate a simultaneouss access to DCACHE.DATA
2148	// and DCACHE.DIR, but is delayed if DCACHE update required.
2149	//
2150	// There is 4 configurations defining the access type to
2151	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2152	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2153	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2154	// 0 / 0 / NOP / NOP / NOP /
2155	// 0 / 1 / NOP / NOP / WRITE /
2156	// 1 / 0 / READ / READ / NOP /
2157	// 1 / 1 / READ / READ / WRITE /
2158	// Those two registers are set at each cycle from the 3 signals
2159	// updt_request, wbuf_request, wbuf_write_miss.
2160	{
2161	paddr_t paddr; // physical address
2162	pte_info_t tlb_flags;
2163	size_t tlb_way;
2164	size_t tlb_set;
2165	paddr_t tlb_nline = 0;
2166	size_t cache_way;
2167	size_t cache_set;
2168	size_t cache_word;
2169	uint32_t cache_rdata = 0;
2170	bool tlb_hit = false;
2171	int cache_state = CACHE_SLOT_STATE_EMPTY;
2172
2173	bool tlb_inval_required = false; // request TLB inval after cache update
2174	bool wbuf_write_miss = false; // miss a WBUF write request
2175	bool updt_request = false; // request DCACHE update in P1 stage
2176	bool wbuf_request = false; // request WBUF write in P1 stage
2177
2178	// physical address computation : systematic DTLB access if activated)
2179	if ( m_dreq.valid )
2180	{
2181	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2182	{
2183	tlb_hit = r_dtlb.translate( m_dreq.addr,
2184	&paddr,
2185	&tlb_flags,
2186	&tlb_nline,
2187	&tlb_way,
2188	&tlb_set );
2189	#ifdef INSTRUMENTATION
2190	m_cpt_dtlb_read++;
2191	#endif
2192	}
2193	else // identity mapping
2194	{
2195	paddr = (paddr_t)m_dreq.addr;
2196	// we take into account the paddr extension
2197	if (vci_param::N > 32)
2198	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
2199	}
2200	} // end physical address computation
2201
2202	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2203	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2204	{
2205	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2206	{
2207	r_dcache.read_dir( paddr,
2208	&cache_state,
2209	&cache_way,
2210	&cache_set,
2211	&cache_word );
2212
2213	r_dcache.write( r_dcache_save_cache_way.read(),
2214	r_dcache_save_cache_set.read(),
2215	r_dcache_save_cache_word.read(),
2216	r_dcache_save_wdata.read(),
2217	r_dcache_save_be.read() );
2218	#ifdef INSTRUMENTATION
2219	m_cpt_dcache_dir_read++;
2220	m_cpt_dcache_data_write++;
2221	#endif
2222	}
2223	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2224	{
2225	r_dcache.read( paddr,
2226	&cache_rdata,
2227	&cache_way,
2228	&cache_set,
2229	&cache_word,
2230	&cache_state );
2231
2232	#ifdef INSTRUMENTATION
2233	m_cpt_dcache_dir_read++;
2234	m_cpt_dcache_data_read++;
2235	#endif
2236	}
2237	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2238	{
2239	r_dcache.write( r_dcache_save_cache_way.read(),
2240	r_dcache_save_cache_set.read(),
2241	r_dcache_save_cache_word.read(),
2242	r_dcache_save_wdata.read(),
2243	r_dcache_save_be.read() );
2244	#ifdef INSTRUMENTATION
2245	m_cpt_dcache_data_write++;
2246	#endif
2247	}
2248	} // end dcache access
2249
2250	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2251	if ( r_dcache_updt_req.read() )
2252	{
2253	size_t way = r_dcache_save_cache_way.read();
2254	size_t set = r_dcache_save_cache_set.read();
2255
2256	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2257	{
2258	tlb_inval_required = true;
2259	r_dcache_tlb_inval_set = 0;
2260	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2261	(uint32_log2(m_dcache_words<<2));
2262	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2263	}
2264	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2265	{
2266	r_itlb.reset();
2267	r_dtlb.reset();
2268	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2269	}
2270
2271	#if DEBUG_DCACHE
2272	if ( m_debug_activated )
2273	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2274	<< " Cache update in P1 stage" << std::dec
2275	<< " / WAY = " << r_dcache_save_cache_way.read()
2276	<< " / SET = " << r_dcache_save_cache_set.read()
2277	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2278	<< " / WDATA = " << r_dcache_save_wdata.read()
2279	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2280	#endif
2281	} // end test TLB inval
2282
2283	// Try WBUF update in P1 stage
2284	// Miss if the write request is non cacheable, and there is a pending
2285	// non cacheable write, or if the write buffer is full.
2286	if ( r_dcache_wbuf_req.read() )
2287	{
2288	// miss if write not cacheable, and previous non cacheable write registered
2289	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2290	{
2291	wbuf_write_miss = true;
2292	}
2293	else // try a registration into write buffer
2294	{
2295	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2296	r_dcache_save_be.read(),
2297	r_dcache_save_wdata.read(),
2298	r_dcache_save_cacheable.read() );
2299	#ifdef INSTRUMENTATION
2300	m_cpt_wbuf_write++;
2301	#endif
2302	if ( not wok ) // miss if write buffer full
2303	{
2304	wbuf_write_miss = true;
2305	}
2306	else // update the write_buffer state extension
2307	{
2308	if(not r_dcache_pending_unc_write.read())
2309	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2310	}
2311	}
2312	} // end WBUF update
2313
2314	// Computing the response to processor,
2315	// and the next value for r_dcache_fsm
2316
2317	// itlb/dtlb invalidation self-request
2318	if ( tlb_inval_required )
2319	{
2320	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2321	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2322	}
2323
2324	// coherence clack request (from DSPIN CLACK)
2325	else if ( r_dcache_clack_req.read() )
2326	{
2327	r_dcache_fsm = DCACHE_CC_CHECK;
2328	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2329	}
2330	// coherence request (from CC_RECEIVE FSM)
2331	else if ( r_cc_receive_dcache_req.read() )
2332	{
2333	r_dcache_fsm = DCACHE_CC_CHECK;
2334	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2335	}
2336
2337	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2338	// we don't take the processor request, and registers
2339	// are frozen in case of wbuf_write_miss
2340	else if ( m_dreq.valid and not wbuf_write_miss )
2341	{
2342	// register processor request and DCACHE response
2343	r_dcache_save_vaddr = m_dreq.addr;
2344	r_dcache_save_be = m_dreq.be;
2345	r_dcache_save_wdata = m_dreq.wdata;
2346	r_dcache_save_paddr = paddr;
2347	r_dcache_save_cache_way = cache_way;
2348	r_dcache_save_cache_set = cache_set;
2349	r_dcache_save_cache_word = cache_word;
2350
2351	// READ XTN requests from processor
2352	// They are executed in this DCACHE_IDLE state.
2353	// The processor must not be in user mode
2354	if (m_dreq.type == iss_t::XTN_READ)
2355	{
2356	int xtn_opcode = (int)m_dreq.addr/4;
2357
2358	// checking processor mode:
2359	if (m_dreq.mode == iss_t::MODE_USER)
2360	{
2361	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2362	r_mmu_dbvar = m_dreq.addr;
2363	m_drsp.valid = true;
2364	m_drsp.error = true;
2365	m_drsp.rdata = 0;
2366	r_dcache_fsm = DCACHE_IDLE;
2367	}
2368	else
2369	{
2370	switch( xtn_opcode )
2371	{
2372	case iss_t::XTN_INS_ERROR_TYPE:
2373	m_drsp.rdata = r_mmu_ietr.read();
2374	m_drsp.valid = true;
2375	m_drsp.error = false;
2376	break;
2377
2378	case iss_t::XTN_DATA_ERROR_TYPE:
2379	m_drsp.rdata = r_mmu_detr.read();
2380	m_drsp.valid = true;
2381	m_drsp.error = false;
2382	break;
2383
2384	case iss_t::XTN_INS_BAD_VADDR:
2385	m_drsp.rdata = r_mmu_ibvar.read();
2386	m_drsp.valid = true;
2387	m_drsp.error = false;
2388	break;
2389
2390	case iss_t::XTN_DATA_BAD_VADDR:
2391	m_drsp.rdata = r_mmu_dbvar.read();
2392	m_drsp.valid = true;
2393	m_drsp.error = false;
2394	break;
2395
2396	case iss_t::XTN_PTPR:
2397	m_drsp.rdata = r_mmu_ptpr.read();
2398	m_drsp.valid = true;
2399	m_drsp.error = false;
2400	break;
2401
2402	case iss_t::XTN_TLB_MODE:
2403	m_drsp.rdata = r_mmu_mode.read();
2404	m_drsp.valid = true;
2405	m_drsp.error = false;
2406	break;
2407
2408	case iss_t::XTN_MMU_PARAMS:
2409	m_drsp.rdata = r_mmu_params;
2410	m_drsp.valid = true;
2411	m_drsp.error = false;
2412	break;
2413
2414	case iss_t::XTN_MMU_RELEASE:
2415	m_drsp.rdata = r_mmu_release;
2416	m_drsp.valid = true;
2417	m_drsp.error = false;
2418	break;
2419
2420	case iss_t::XTN_MMU_WORD_LO:
2421	m_drsp.rdata = r_mmu_word_lo.read();
2422	m_drsp.valid = true;
2423	m_drsp.error = false;
2424	break;
2425
2426	case iss_t::XTN_MMU_WORD_HI:
2427	m_drsp.rdata = r_mmu_word_hi.read();
2428	m_drsp.valid = true;
2429	m_drsp.error = false;
2430	break;
2431
2432	case iss_t::XTN_DATA_PADDR_EXT:
2433	m_drsp.rdata = r_dcache_paddr_ext.read();
2434	m_drsp.valid = true;
2435	m_drsp.error = false;
2436	break;
2437
2438	default:
2439	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2440	r_mmu_dbvar = m_dreq.addr;
2441	m_drsp.valid = true;
2442	m_drsp.error = true;
2443	m_drsp.rdata = 0;
2444	break;
2445	} // end switch xtn_opcode
2446	} // end else
2447	} // end if XTN_READ
2448
2449	// Handling WRITE XTN requests from processor.
2450	// They are not executed in this DCACHE_IDLE state
2451	// if they require access to the caches or the TLBs
2452	// that are already accessed.
2453	// Caches can be invalidated or flushed in user mode,
2454	// and the sync instruction can be executed in user mode
2455	else if (m_dreq.type == iss_t::XTN_WRITE)
2456	{
2457	int xtn_opcode = (int)m_dreq.addr/4;
2458	r_dcache_xtn_opcode = xtn_opcode;
2459
2460	// checking processor mode:
2461	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2462	(xtn_opcode != iss_t::XTN_SYNC) &&
2463	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2464	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2465	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2466	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2467	{
2468	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2469	r_mmu_dbvar = m_dreq.addr;
2470	m_drsp.valid = true;
2471	m_drsp.error = true;
2472	m_drsp.rdata = 0;
2473	r_dcache_fsm = DCACHE_IDLE;
2474	}
2475	else
2476	{
2477	switch( xtn_opcode )
2478	{
2479	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2480	r_dcache_xtn_req = true;
2481	r_dcache_fsm = DCACHE_XTN_SWITCH;
2482	break;
2483
2484	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2485	r_mmu_mode = m_dreq.wdata;
2486	m_drsp.valid = true;
2487	r_dcache_fsm = DCACHE_IDLE;
2488	break;
2489
2490	case iss_t::XTN_DTLB_INVAL: // dtlb access
2491	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2492	break;
2493
2494	case iss_t::XTN_ITLB_INVAL: // itlb access
2495	r_dcache_xtn_req = true;
2496	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2497	break;
2498
2499	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2500	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2501	break;
2502
2503	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2504	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2505	if (sizeof(paddr_t) <= 32)
2506	{
2507	assert(r_mmu_word_hi.read() == 0 &&
2508	"high bits should be 0 for 32bit paddr");
2509	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2510	}
2511	else
2512	{
2513	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2514	(paddr_t)r_mmu_word_lo.read();
2515	}
2516	break;
2517
2518	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2519	r_dcache_flush_count = 0;
2520	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2521	break;
2522
2523	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2524	r_dcache_xtn_req = true;
2525	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2526	break;
2527
2528	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2529	r_dcache_xtn_req = true;
2530	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2531	break;
2532
2533	case iss_t::XTN_ICACHE_FLUSH: // icache access
2534	r_dcache_xtn_req = true;
2535	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2536	break;
2537
2538	case iss_t::XTN_SYNC: // wait until write buffer empty
2539	r_dcache_fsm = DCACHE_XTN_SYNC;
2540	break;
2541
2542	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2543	r_mmu_word_lo = m_dreq.wdata;
2544	m_drsp.valid = true;
2545	r_dcache_fsm = DCACHE_IDLE;
2546	break;
2547
2548	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2549	r_mmu_word_hi = m_dreq.wdata;
2550	m_drsp.valid = true;
2551	r_dcache_fsm = DCACHE_IDLE;
2552	break;
2553
2554	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2555	r_dcache_llsc_valid = false;
2556	m_drsp.valid = true;
2557	r_dcache_fsm = DCACHE_IDLE;
2558	break;
2559
2560	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2561	r_dcache_paddr_ext = m_dreq.wdata;
2562	m_drsp.valid = true;
2563	r_dcache_fsm = DCACHE_IDLE;
2564	break;
2565
2566	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2567	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2568	m_drsp.valid = true;
2569	r_dcache_fsm = DCACHE_IDLE;
2570	break;
2571
2572	default:
2573	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2574	r_mmu_dbvar = m_dreq.addr;
2575	m_drsp.valid = true;
2576	m_drsp.error = true;
2577	r_dcache_fsm = DCACHE_IDLE;
2578	break;
2579	} // end switch xtn_opcode
2580	} // end else
2581	} // end if XTN_WRITE
2582
2583	// Handling processor requests to address space (READ/WRITE/LL/SC)
2584	// The dtlb and dcache can be activated or not.
2585	// We compute the cacheability, and check processor request validity:
2586	// - If DTLB not activated : cacheability is defined by the segment table,
2587	// and there is no access rights checking.
2588	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2589	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2590	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2591	else
2592	{
2593	bool valid_req;
2594	bool cacheable;
2595
2596	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2597	{
2598	valid_req = true;
2599
2600	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2601	else cacheable = m_cacheability_table[m_dreq.addr];
2602	}
2603	else // dtlb activated
2604	{
2605	if ( tlb_hit ) // tlb hit
2606	{
2607	// cacheability
2608	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2609	else cacheable = tlb_flags.c;
2610
2611	// access rights checking
2612	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2613	{
2614	if ( (m_dreq.type == iss_t::DATA_READ) or
2615	(m_dreq.type == iss_t::DATA_LL) )
2616	{
2617	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2618	}
2619	else
2620	{
2621	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2622	}
2623	valid_req = false;
2624	r_mmu_dbvar = m_dreq.addr;
2625	m_drsp.valid = true;
2626	m_drsp.error = true;
2627	m_drsp.rdata = 0;
2628	#if DEBUG_DCACHE
2629	if ( m_debug_activated )
2630	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2631	<< " HIT in dtlb, but privilege violation" << std::endl;
2632	#endif
2633	}
2634	else if ( not tlb_flags.w and
2635	((m_dreq.type == iss_t::DATA_WRITE) or
2636	(m_dreq.type == iss_t::DATA_SC)) )
2637	{
2638	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2639	valid_req = false;
2640	r_mmu_dbvar = m_dreq.addr;
2641	m_drsp.valid = true;
2642	m_drsp.error = true;
2643	m_drsp.rdata = 0;
2644	#if DEBUG_DCACHE
2645	if ( m_debug_activated )
2646	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2647	<< " HIT in dtlb, but writable violation" << std::endl;
2648	#endif
2649	}
2650	else
2651	{
2652	valid_req = true;
2653	}
2654	}
2655	else // tlb miss
2656	{
2657	valid_req = false;
2658	r_dcache_tlb_vaddr = m_dreq.addr;
2659	r_dcache_tlb_ins = false;
2660	r_dcache_fsm = DCACHE_TLB_MISS;
2661	}
2662	} // end DTLB activated
2663
2664	if ( valid_req ) // processor request is valid (after MMU check)
2665	{
2666	r_dcache_save_cacheable = cacheable;
2667
2668	// READ request
2669	// The read requests are taken only if there is no cache update.
2670	// We request a VCI transaction to CMD FSM if miss or uncachable
2671
2672	if ( ((m_dreq.type == iss_t::DATA_READ))
2673	and not r_dcache_updt_req.read() )
2674	{
2675	if ( cacheable ) // cacheable read
2676	{
2677	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2678	{
2679	#ifdef INSTRUMENTATION
2680	m_cpt_dcache_miss++;
2681	#endif
2682	// request a VCI DMISS transaction
2683	r_dcache_vci_paddr = paddr;
2684	r_dcache_vci_miss_req = true;
2685	r_dcache_miss_type = PROC_MISS;
2686	r_dcache_fsm = DCACHE_MISS_SELECT;
2687	#if DEBUG_DCACHE
2688	if ( m_debug_activated )
2689	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2690	<< " READ MISS in dcache"
2691	<< " / PADDR = " << std::hex << paddr << std::endl;
2692	#endif
2693	}
2694	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2695	{
2696	// stalled until cleanup is acknowledged
2697	r_dcache_fsm = DCACHE_IDLE;
2698	#if DEBUG_DCACHE
2699	if ( m_debug_activated )
2700	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2701	<< " Pending cleanup, stalled until cleanup acknowledge"
2702	<< " / PADDR = " << std::hex << paddr << std::endl;
2703	#endif
2704	}
2705	else // cache hit
2706	{
2707	#ifdef INSTRUMENTATION
2708	m_cpt_data_read++;
2709	#endif
2710	// returns data to processor
2711	m_drsp.valid = true;
2712	m_drsp.error = false;
2713	m_drsp.rdata = cache_rdata;
2714	#if DEBUG_DCACHE
2715	if ( m_debug_activated )
2716	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2717	<< " READ HIT in dcache"
2718	<< " / PADDR = " << std::hex << paddr << std::endl;
2719	#endif
2720	}
2721	}
2722	else // uncacheable read
2723	{
2724	r_dcache_vci_paddr = paddr;
2725	r_dcache_vci_unc_be = m_dreq.be;
2726	r_dcache_vci_unc_req = true;
2727	r_dcache_fsm = DCACHE_UNC_WAIT;
2728	#if DEBUG_DCACHE
2729	if ( m_debug_activated )
2730	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2731	<< " READ UNCACHEABLE in dcache"
2732	<< " / PADDR = " << std::hex << paddr << std::endl;
2733	#endif
2734	}
2735	} // end READ
2736
2737	// LL request (non cachable)
2738	// We request a VCI LL transaction to CMD FSM and register
2739	// the LL/SC operation in llsc buffer.
2740	else if (m_dreq.type == iss_t::DATA_LL)
2741	{
2742	// register paddr in LLSC buffer
2743	r_dcache_llsc_paddr = paddr;
2744	r_dcache_llsc_count = LLSC_TIMEOUT;
2745	r_dcache_llsc_valid = true;
2746
2747	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2748	r_dcache_vci_ll_req = true;
2749	r_dcache_vci_paddr = paddr;
2750	r_dcache_ll_rsp_count = 0;
2751	r_dcache_fsm = DCACHE_LL_WAIT;
2752
2753	}// end LL
2754
2755	// WRITE request:
2756	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2757	// the processor and set the Dirty bit before handling the write request,
2758	// going to the DCACHE_DIRTY_GT_PTE state.
2759	// If we don't need to set the Dirty bit, we can acknowledge
2760	// the processor request, as the write arguments (including the
2761	// physical address) are registered in r_dcache_save registers,
2762	// and the write will be done in the P1 pipeline stage.
2763	else if ( m_dreq.type == iss_t::DATA_WRITE )
2764	{
2765	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2766	and not tlb_flags.d ) // Dirty bit must be set
2767	{
2768	// The PTE physical address is obtained from the nline value (dtlb),
2769	// and from the virtual address (word index)
2770	if ( tlb_flags.b ) // PTE1
2771	{
2772	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2773	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2774	}
2775	else // PTE2
2776	{
2777	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2778	(paddr_t)((m_dreq.addr>>9) & 0x38);
2779	}
2780	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2781	}
2782	else // Write request accepted
2783	{
2784	#ifdef INSTRUMENTATION
2785	m_cpt_data_write++;
2786	#endif
2787	// cleaning llsc buffer if address matching
2788	if ( paddr == r_dcache_llsc_paddr.read() )
2789	r_dcache_llsc_valid = false;
2790
2791	// response to processor
2792	m_drsp.valid = true;
2793
2794	// activating P1 stage
2795	wbuf_request = true;
2796	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2797	}
2798	} // end WRITE
2799
2800	// SC request:
2801	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2802	// the processor and set the Dirty bit before handling the write request,
2803	// going to the DCACHE_DIRTY_GT_PTE state.
2804	// If we don't need to set the Dirty bit, we test the llsc buffer:
2805	// If failure, we send a negative response to processor.
2806	// If success, we request a SC transaction to CMD FSM and go
2807	// to DCACHE_SC_WAIT state.
2808	// We don't check a possible write hit in dcache, as the cache update
2809	// is done by the coherence transaction induced by the SC...
2810	else if ( m_dreq.type == iss_t::DATA_SC )
2811	{
2812	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2813	and not tlb_flags.d ) // Dirty bit must be set
2814	{
2815	// The PTE physical address is obtained from the nline value (dtlb),
2816	// and the word index (virtual address)
2817	if ( tlb_flags.b ) // PTE1
2818	{
2819	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2820	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2821	}
2822	else // PTE2
2823	{
2824	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2825	(paddr_t)((m_dreq.addr>>9) & 0x38);
2826	}
2827	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2828	m_drsp.valid = false;
2829	m_drsp.error = false;
2830	m_drsp.rdata = 0;
2831	}
2832	else // SC request accepted
2833	{
2834	#ifdef INSTRUMENTATION
2835	m_cpt_data_sc++;
2836	#endif
2837	// checking local success
2838	if( r_dcache_llsc_valid.read() and
2839	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2840	{
2841	// request an SC CMD and go to DCACHE_SC_WAIT state
2842	r_dcache_vci_paddr = paddr;
2843	r_dcache_vci_sc_req = true;
2844	r_dcache_vci_sc_data = m_dreq.wdata;
2845	r_dcache_fsm = DCACHE_SC_WAIT;
2846	}
2847	else // local fail
2848	{
2849	m_drsp.valid = true;
2850	m_drsp.error = false;
2851	m_drsp.rdata = 0x1;
2852	}
2853	}
2854	} // end SC
2855	} // end valid_req
2856	} // end if read/write/ll/sc request
2857	} // end processor request
2858
2859	// itlb miss request
2860	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2861	{
2862	r_dcache_tlb_ins = true;
2863	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2864	r_dcache_fsm = DCACHE_TLB_MISS;
2865	}
2866
2867	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2868	r_dcache_updt_req = updt_request;
2869	r_dcache_wbuf_req = wbuf_request or
2870	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2871	break;
2872	}
2873	/////////////////////
2874	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2875	// Input arguments are:
2876	// - r_dcache_tlb_vaddr
2877	// - r_dcache_tlb_ins (true when itlb miss)
2878	// The sub-fsm access the dcache to find the missing TLB entry,
2879	// and activates the cache miss procedure in case of miss.
2880	// It bypass the first level page table access if possible.
2881	// It uses atomic access to update the R/L access bits
2882	// in the page table if required.
2883	// It directly updates the itlb or dtlb, and writes into the
2884	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2885	{
2886	uint32_t ptba = 0;
2887	bool bypass;
2888	paddr_t pte_paddr;
2889
2890	// evaluate bypass in order to skip first level page table access
2891	if ( r_dcache_tlb_ins.read() ) // itlb miss
2892	{
2893	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2894	}
2895	else // dtlb miss
2896	{
2897	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2898	}
2899
2900	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2901	{
2902	pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) \|
2903	((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
2904	r_dcache_tlb_paddr = pte_paddr;
2905	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2906	}
2907	else // Try to read PTE2 in dcache
2908	{
2909	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2910	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2911	r_dcache_tlb_paddr = pte_paddr;
2912	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2913	}
2914
2915	#if DEBUG_DCACHE
2916	if ( m_debug_activated )
2917	{
2918	if ( r_dcache_tlb_ins.read() )
2919	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
2920	else
2921	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
2922	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2923	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
2924	<< " / BYPASS = " << bypass
2925	<< " / PTE_ADR = " << pte_paddr << std::endl;
2926	}
2927	#endif
2928
2929	break;
2930	}
2931	/////////////////////////
2932	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2933	{
2934	// coherence clack request (from DSPIN CLACK)
2935	if ( r_dcache_clack_req.read() )
2936	{
2937	r_dcache_fsm = DCACHE_CC_CHECK;
2938	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2939	break;
2940	}
2941
2942	// coherence request (from CC_RECEIVE FSM)
2943	if ( r_cc_receive_dcache_req.read() )
2944	{
2945	r_dcache_fsm = DCACHE_CC_CHECK;
2946	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2947	break;
2948	}
2949
2950	uint32_t entry;
2951	size_t way;
2952	size_t set;
2953	size_t word;
2954	int cache_state;
2955	r_dcache.read( r_dcache_tlb_paddr.read(),
2956	&entry,
2957	&way,
2958	&set,
2959	&word,
2960	&cache_state );
2961	#ifdef INSTRUMENTATION
2962	m_cpt_dcache_data_read++;
2963	m_cpt_dcache_dir_read++;
2964	#endif
2965	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2966	{
2967	if ( not (entry & PTE_V_MASK) ) // unmapped
2968	{
2969	if ( r_dcache_tlb_ins.read() )
2970	{
2971	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2972	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2973	r_icache_tlb_miss_req = false;
2974	r_icache_tlb_rsp_error = true;
2975	}
2976	else
2977	{
2978	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2979	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2980	m_drsp.valid = true;
2981	m_drsp.error = true;
2982	}
2983	r_dcache_fsm = DCACHE_IDLE;
2984
2985	#if DEBUG_DCACHE
2986	if ( m_debug_activated )
2987	{
2988	std::cout << " <PROC " << name()
2989	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2990	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2991	<< std::dec << " / way = " << way
2992	<< std::dec << " / set = " << set
2993	<< std::dec << " / word = " << word
2994	<< std::hex << " / PTE1 = " << entry << std::endl;
2995	}
2996	#endif
2997
2998	}
2999	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
3000	{
3001	// mark the cache line ac containing a PTD
3002	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
3003
3004	// register bypass
3005	if ( r_dcache_tlb_ins.read() ) // itlb
3006	{
3007	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3008	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3009	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
3010	}
3011	else // dtlb
3012	{
3013	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3014	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3015	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
3016	}
3017	r_dcache_tlb_paddr =
3018	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3019	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3020	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3021
3022	#if DEBUG_DCACHE
3023	if ( m_debug_activated )
3024	{
3025	std::cout << " <PROC " << name()
3026	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3027	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3028	<< std::dec << " / way = " << way
3029	<< std::dec << " / set = " << set
3030	<< std::dec << " / word = " << word
3031	<< std::hex << " / PTD = " << entry << std::endl;
3032	}
3033	#endif
3034	}
3035	else // PTE1 : we must update the TLB
3036	{
3037	r_dcache_in_tlb[m_icache_sets*way+set] = true;
3038	r_dcache_tlb_pte_flags = entry;
3039	r_dcache_tlb_cache_way = way;
3040	r_dcache_tlb_cache_set = set;
3041	r_dcache_tlb_cache_word = word;
3042	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3043
3044	#if DEBUG_DCACHE
3045	if ( m_debug_activated )
3046	{
3047	std::cout << " <PROC " << name()
3048	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3049	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3050	<< std::dec << " / way = " << way
3051	<< std::dec << " / set = " << set
3052	<< std::dec << " / word = " << word
3053	<< std::hex << " / PTE1 = " << entry << std::endl;
3054	}
3055	#endif
3056	}
3057	}
3058	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3059	{
3060	// stalled until cleanup is acknowledged
3061	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3062	}
3063	else // we must load the missing cache line in dcache
3064	{
3065	r_dcache_vci_miss_req = true;
3066	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3067	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3068	r_dcache_miss_type = PTE1_MISS;
3069	r_dcache_fsm = DCACHE_MISS_SELECT;
3070
3071	#if DEBUG_DCACHE
3072	if ( m_debug_activated )
3073	{
3074	std::cout << " <PROC " << name()
3075	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3076	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3077	}
3078	#endif
3079	}
3080	break;
3081	}
3082	////////////////////////////
3083	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3084	{
3085	size_t way;
3086	size_t set;
3087
3088	if ( r_dcache_tlb_ins.read() )
3089	{
3090	r_itlb.select( r_dcache_tlb_vaddr.read(),
3091	true, // PTE1
3092	&way,
3093	&set );
3094	#ifdef INSTRUMENTATION
3095	m_cpt_itlb_read++;
3096	#endif
3097	}
3098	else
3099	{
3100	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3101	true, // PTE1
3102	&way,
3103	&set );
3104	#ifdef INSTRUMENTATION
3105	m_cpt_dtlb_read++;
3106	#endif
3107	}
3108	r_dcache_tlb_way = way;
3109	r_dcache_tlb_set = set;
3110	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3111
3112	#if DEBUG_DCACHE
3113	if ( m_debug_activated )
3114	{
3115	if ( r_dcache_tlb_ins.read() )
3116	std::cout << " <PROC " << name()
3117	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3118	else
3119	std::cout << " <PROC " << name()
3120	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3121	std::cout << " way = " << std::dec << way
3122	<< " / set = " << set << std::endl;
3123	}
3124	#endif
3125	break;
3126	}
3127	//////////////////////////
3128	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3129	// - if L/R bit already set, exit the sub-fsm.
3130	// - if not, we update the page table but we dont write
3131	// neither in DCACHE, nor in TLB, as this will be done by
3132	// the coherence mechanism.
3133	{
3134	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3135	uint32_t pte = r_dcache_tlb_pte_flags.read();
3136	bool pt_updt = false;
3137	bool local = true;
3138
3139	// We should compute the access locality:
3140	// The PPN MSB bits define the destination cluster index.
3141	// The m_srcid MSB bits define the source cluster index.
3142	// The number of bits to compare depends on the number of clusters,
3143	// and can be obtained in the mapping table.
3144	// As long as this computation is not done, all access are local.
3145
3146	if ( local ) // local access
3147	{
3148	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3149	{
3150	pt_updt = true;
3151	r_dcache_vci_cas_old = pte;
3152	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3153	pte = pte \| PTE_L_MASK;
3154	r_dcache_tlb_pte_flags = pte;
3155	}
3156	}
3157	else // remote access
3158	{
3159	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3160	{
3161	pt_updt = true;
3162	r_dcache_vci_cas_old = pte;
3163	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3164	pte = pte \| PTE_R_MASK;
3165	r_dcache_tlb_pte_flags = pte;
3166	}
3167	}
3168
3169	if ( not pt_updt ) // update TLB and return
3170	{
3171	if ( r_dcache_tlb_ins.read() )
3172	{
3173	r_itlb.write( true, // 2M page
3174	pte,
3175	0, // argument unused for a PTE1
3176	r_dcache_tlb_vaddr.read(),
3177	r_dcache_tlb_way.read(),
3178	r_dcache_tlb_set.read(),
3179	nline );
3180	#ifdef INSTRUMENTATION
3181	m_cpt_itlb_write++;
3182	#endif
3183
3184	#if DEBUG_DCACHE
3185	if ( m_debug_activated )
3186	{
3187	std::cout << " <PROC " << name()
3188	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3189	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3190	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3191	r_itlb.printTrace();
3192	}
3193	#endif
3194	}
3195	else
3196	{
3197	r_dtlb.write( true, // 2M page
3198	pte,
3199	0, // argument unused for a PTE1
3200	r_dcache_tlb_vaddr.read(),
3201	r_dcache_tlb_way.read(),
3202	r_dcache_tlb_set.read(),
3203	nline );
3204	#ifdef INSTRUMENTATION
3205	m_cpt_dtlb_write++;
3206	#endif
3207
3208	#if DEBUG_DCACHE
3209	if ( m_debug_activated )
3210	{
3211	std::cout << " <PROC " << name()
3212	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3213	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3214	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3215	r_dtlb.printTrace();
3216	}
3217	#endif
3218	}
3219	r_dcache_fsm = DCACHE_TLB_RETURN;
3220	}
3221	else // update page table but not TLB
3222	{
3223	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3224
3225	#if DEBUG_DCACHE
3226	if ( m_debug_activated )
3227	{
3228	std::cout << " <PROC " << name()
3229	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3230	<< std::endl;
3231	}
3232	#endif
3233	}
3234	break;
3235	}
3236	/////////////////////////
3237	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3238	{
3239	// coherence clack request (from DSPIN CLACK)
3240	if ( r_dcache_clack_req.read() )
3241	{
3242	r_dcache_fsm = DCACHE_CC_CHECK;
3243	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3244	break;
3245	}
3246
3247	// coherence request (from CC_RECEIVE FSM)
3248	if ( r_cc_receive_dcache_req.read() )
3249	{
3250	r_dcache_fsm = DCACHE_CC_CHECK;
3251	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3252	break;
3253	}
3254
3255	uint32_t pte_flags;
3256	uint32_t pte_ppn;
3257	size_t way;
3258	size_t set;
3259	size_t word;
3260	int cache_state;
3261
3262	r_dcache.read( r_dcache_tlb_paddr.read(),
3263	&pte_flags,
3264	&pte_ppn,
3265	&way,
3266	&set,
3267	&word,
3268	&cache_state );
3269	#ifdef INSTRUMENTATION
3270	m_cpt_dcache_data_read++;
3271	m_cpt_dcache_dir_read++;
3272	#endif
3273	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3274	{
3275	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3276	{
3277	if ( r_dcache_tlb_ins.read() )
3278	{
3279	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3280	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3281	r_icache_tlb_miss_req = false;
3282	r_icache_tlb_rsp_error = true;
3283	}
3284	else
3285	{
3286	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3287	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3288	m_drsp.valid = true;
3289	m_drsp.error = true;
3290	}
3291	r_dcache_fsm = DCACHE_IDLE;
3292
3293	#if DEBUG_DCACHE
3294	if ( m_debug_activated )
3295	{
3296	std::cout << " <PROC " << name()
3297	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3298	<< " PTE_FLAGS = " << std::hex << pte_flags
3299	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3300	}
3301	#endif
3302	}
3303	else // mapped : we must update the TLB
3304	{
3305	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3306	r_dcache_tlb_pte_flags = pte_flags;
3307	r_dcache_tlb_pte_ppn = pte_ppn;
3308	r_dcache_tlb_cache_way = way;
3309	r_dcache_tlb_cache_set = set;
3310	r_dcache_tlb_cache_word = word;
3311	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3312
3313	#if DEBUG_DCACHE
3314	if ( m_debug_activated )
3315	{
3316	std::cout << " <PROC " << name()
3317	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3318	<< " PTE_FLAGS = " << std::hex << pte_flags
3319	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3320	}
3321	#endif
3322	}
3323	}
3324	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3325	{
3326	// stalled until cleanup is acknowledged
3327	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3328
3329	#if DEBUG_DCACHE
3330	if ( m_debug_activated )
3331	{
3332	std::cout << " <PROC " << name()
3333	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3334	<< std::endl;
3335	}
3336	#endif
3337	}
3338	else // we must load the missing cache line in dcache
3339	{
3340	r_dcache_fsm = DCACHE_MISS_SELECT;
3341	r_dcache_vci_miss_req = true;
3342	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3343	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3344	r_dcache_miss_type = PTE2_MISS;
3345
3346	#if DEBUG_DCACHE
3347	if ( m_debug_activated )
3348	{
3349	std::cout << " <PROC " << name()
3350	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3351	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3352	}
3353	#endif
3354	}
3355	break;
3356	}
3357	////////////////////////////
3358	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3359	{
3360	size_t way;
3361	size_t set;
3362
3363	if ( r_dcache_tlb_ins.read() )
3364	{
3365	r_itlb.select( r_dcache_tlb_vaddr.read(),
3366	false, // PTE2
3367	&way,
3368	&set );
3369	#ifdef INSTRUMENTATION
3370	m_cpt_itlb_read++;
3371	#endif
3372	}
3373	else
3374	{
3375	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3376	false, // PTE2
3377	&way,
3378	&set );
3379	#ifdef INSTRUMENTATION
3380	m_cpt_dtlb_read++;
3381	#endif
3382	}
3383
3384	#if DEBUG_DCACHE
3385	if ( m_debug_activated )
3386	{
3387	if ( r_dcache_tlb_ins.read() )
3388	std::cout << " <PROC " << name()
3389	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3390	else
3391	std::cout << " <PROC " << name()
3392	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3393	std::cout << " way = " << std::dec << way
3394	<< " / set = " << set << std::endl;
3395	}
3396	#endif
3397	r_dcache_tlb_way = way;
3398	r_dcache_tlb_set = set;
3399	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3400	break;
3401	}
3402	//////////////////////////
3403	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3404	// - if L/R bit already set, exit the sub-fsm.
3405	// - if not, we update the page table but we dont write
3406	// neither in DCACHE, nor in TLB, as this will be done by
3407	// the coherence mechanism.
3408	{
3409	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3410	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3411	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3412	bool pt_updt = false;
3413	bool local = true;
3414
3415	// We should compute the access locality:
3416	// The PPN MSB bits define the destination cluster index.
3417	// The m_srcid MSB bits define the source cluster index.
3418	// The number of bits to compare depends on the number of clusters,
3419	// and can be obtained in the mapping table.
3420	// As long as this computation is not done, all access are local.
3421
3422	if ( local ) // local access
3423	{
3424	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3425	{
3426	pt_updt = true;
3427	r_dcache_vci_cas_old = pte_flags;
3428	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3429	pte_flags = pte_flags \| PTE_L_MASK;
3430	r_dcache_tlb_pte_flags = pte_flags;
3431	}
3432	}
3433	else // remote access
3434	{
3435	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3436	{
3437	pt_updt = true;
3438	r_dcache_vci_cas_old = pte_flags;
3439	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3440	pte_flags = pte_flags \| PTE_R_MASK;
3441	r_dcache_tlb_pte_flags = pte_flags;
3442	}
3443	}
3444
3445	if ( not pt_updt ) // update TLB
3446	{
3447	if ( r_dcache_tlb_ins.read() )
3448	{
3449	r_itlb.write( false, // 4K page
3450	pte_flags,
3451	pte_ppn,
3452	r_dcache_tlb_vaddr.read(),
3453	r_dcache_tlb_way.read(),
3454	r_dcache_tlb_set.read(),
3455	nline );
3456	#ifdef INSTRUMENTATION
3457	m_cpt_itlb_write++;
3458	#endif
3459
3460	#if DEBUG_DCACHE
3461	if ( m_debug_activated )
3462	{
3463	std::cout << " <PROC " << name()
3464	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3465	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3466	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3467	r_itlb.printTrace();
3468	}
3469	#endif
3470	}
3471	else
3472	{
3473	r_dtlb.write( false, // 4K page
3474	pte_flags,
3475	pte_ppn,
3476	r_dcache_tlb_vaddr.read(),
3477	r_dcache_tlb_way.read(),
3478	r_dcache_tlb_set.read(),
3479	nline );
3480	#ifdef INSTRUMENTATION
3481	m_cpt_dtlb_write++;
3482	#endif
3483
3484	#if DEBUG_DCACHE
3485	if ( m_debug_activated )
3486	{
3487	std::cout << " <PROC " << name()
3488	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3489	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3490	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3491	r_dtlb.printTrace();
3492	}
3493	#endif
3494
3495	}
3496	r_dcache_fsm = DCACHE_TLB_RETURN;
3497	}
3498	else // update page table but not TLB
3499	{
3500	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3501
3502	#if DEBUG_DCACHE
3503	if ( m_debug_activated )
3504	{
3505	std::cout << " <PROC " << name()
3506	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3507	}
3508	#endif
3509	}
3510	break;
3511	}
3512	////////////////////////
3513	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3514	{
3515	#if DEBUG_DCACHE
3516	if ( m_debug_activated )
3517	{
3518	std::cout << " <PROC " << name()
3519	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3520	}
3521	#endif
3522	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3523	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3524
3525	// checking llsc reservation buffer
3526	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3527	r_dcache_llsc_valid = false;
3528
3529	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3530	r_dcache_vci_cas_req = true;
3531	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3532	break;
3533	}
3534	////////////////////////
3535	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3536	// We consume the response in rsp FIFO,
3537	// and exit the sub-fsm, but we don't
3538	// analyse the response, because we don't
3539	// care if the L/R bit update is not done.
3540	// We must take the coherence requests because
3541	// there is a risk of dead-lock
3542
3543	{
3544	// coherence clack request (from DSPIN CLACK)
3545	if ( r_dcache_clack_req.read() )
3546	{
3547	r_dcache_fsm = DCACHE_CC_CHECK;
3548	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3549	break;
3550	}
3551
3552	// coherence request (from CC_RECEIVE FSM)
3553	if ( r_cc_receive_dcache_req.read() )
3554	{
3555	r_dcache_fsm = DCACHE_CC_CHECK;
3556	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3557	break;
3558	}
3559
3560	if ( r_vci_rsp_data_error.read() ) // bus error
3561	{
3562	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3563	std::cout << "This should not happen in this state" << std::endl;
3564	exit(0);
3565	}
3566	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3567	{
3568	#if DEBUG_DCACHE
3569	if ( m_debug_activated )
3570	{
3571	std::cout << " <PROC " << name()
3572	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3573	}
3574	#endif
3575	vci_rsp_fifo_dcache_get = true;
3576	r_dcache_fsm = DCACHE_TLB_RETURN;
3577	}
3578	break;
3579	}
3580	///////////////////////
3581	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3582	{
3583	#if DEBUG_DCACHE
3584	if ( m_debug_activated )
3585	{
3586	std::cout << " <PROC " << name()
3587	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3588	}
3589	#endif
3590	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3591	r_dcache_fsm = DCACHE_IDLE;
3592	break;
3593	}
3594	///////////////////////
3595	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3596	// and both itlb and dtlb must be flushed.
3597	// Caution : the itlb miss requests must be taken
3598	// to avoid dead-lock in case of simultaneous ITLB miss
3599	{
3600	// itlb miss request
3601	if ( r_icache_tlb_miss_req.read() )
3602	{
3603	r_dcache_tlb_ins = true;
3604	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3605	r_dcache_fsm = DCACHE_TLB_MISS;
3606	break;
3607	}
3608
3609	if ( not r_dcache_xtn_req.read() )
3610	{
3611	r_dtlb.flush();
3612	r_mmu_ptpr = m_dreq.wdata;
3613	r_dcache_fsm = DCACHE_IDLE;
3614	m_drsp.valid = true;
3615	}
3616	break;
3617	}
3618	/////////////////////
3619	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3620	// The coherence request must be taken
3621	// as there is a risk of dead-lock
3622	{
3623	// coherence clack request (from DSPIN CLACK)
3624	if ( r_dcache_clack_req.read() )
3625	{
3626	r_dcache_fsm = DCACHE_CC_CHECK;
3627	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3628	break;
3629	}
3630
3631	// coherence request (from CC_RECEIVE FSM)
3632	if ( r_cc_receive_dcache_req.read() )
3633	{
3634	r_dcache_fsm = DCACHE_CC_CHECK;
3635	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3636	break;
3637	}
3638
3639	if ( r_wbuf.empty() )
3640	{
3641	m_drsp.valid = true;
3642	r_dcache_fsm = DCACHE_IDLE;
3643	}
3644	break;
3645	}
3646	////////////////////////
3647	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3648	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3649	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3650	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3651	// and because it can exist a simultaneous ITLB miss
3652	{
3653	// coherence clack request (from DSPIN CLACK)
3654	if ( r_dcache_clack_req.read() )
3655	{
3656	r_dcache_fsm = DCACHE_CC_CHECK;
3657	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3658	break;
3659	}
3660
3661	// coherence request (from CC_RECEIVE FSM)
3662	if ( r_cc_receive_dcache_req.read() )
3663	{
3664	r_dcache_fsm = DCACHE_CC_CHECK;
3665	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3666	break;
3667	}
3668
3669	// itlb miss request
3670	if ( r_icache_tlb_miss_req.read() )
3671	{
3672	r_dcache_tlb_ins = true;
3673	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3674	r_dcache_fsm = DCACHE_TLB_MISS;
3675	break;
3676	}
3677
3678	// test if XTN request to icache completed
3679	if ( not r_dcache_xtn_req.read() )
3680	{
3681	r_dcache_fsm = DCACHE_IDLE;
3682	m_drsp.valid = true;
3683	}
3684	break;
3685	}
3686	/////////////////////////
3687	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3688	// r_dcache_flush_count as a slot counter,
3689	// looping in this state until all slots have been visited.
3690	// It can require two cycles per slot:
3691	// We test here the slot state, and make the actual inval
3692	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3693	// A cleanup request is generated for each valid line.
3694	// returns to IDLE and flush TLBs when last slot
3695	{
3696	// coherence clack request (from DSPIN CLACK)
3697	if ( r_dcache_clack_req.read() )
3698	{
3699	r_dcache_fsm = DCACHE_CC_CHECK;
3700	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3701	break;
3702	}
3703
3704	// coherence request (from CC_RECEIVE FSM)
3705	if ( r_cc_receive_dcache_req.read() )
3706	{
3707	r_dcache_fsm = DCACHE_CC_CHECK;
3708	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3709	break;
3710	}
3711
3712	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3713	{
3714	int state;
3715	paddr_t tag;
3716	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3717	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3718
3719	#ifdef INSTRUMENTATION
3720	m_cpt_dcache_dir_read++;
3721	#endif
3722	r_dcache.read_dir( way,
3723	set,
3724	&tag,
3725	&state );
3726
3727	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3728	{
3729	// request cleanup
3730	r_dcache_cc_send_req = true;
3731	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3732	r_dcache_cc_send_way = way;
3733	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3734
3735	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3736	r_dcache_miss_way = way;
3737	r_dcache_miss_set = set;
3738	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3739	}
3740	else if ( r_dcache_flush_count.read() ==
3741	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3742	{
3743	r_dtlb.reset();
3744	r_itlb.reset();
3745	r_dcache_fsm = DCACHE_IDLE;
3746	m_drsp.valid = true;
3747	}
3748
3749	// saturation counter
3750	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3751	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3752	}
3753	break;
3754	}
3755	////////////////////////////
3756	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3757	// and reset directory extension.
3758	// returns to IDLE and flush TLBs when last slot
3759	{
3760	size_t way = r_dcache_miss_way.read();
3761	size_t set = r_dcache_miss_set.read();
3762
3763	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3764	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3765
3766	#ifdef INSTRUMENTATION
3767	m_cpt_dcache_dir_write++;
3768	#endif
3769	r_dcache.write_dir( way,
3770	set,
3771	CACHE_SLOT_STATE_ZOMBI );
3772
3773	if ( r_dcache_flush_count.read() ==
3774	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3775	{
3776	r_dtlb.reset();
3777	r_itlb.reset();
3778	r_dcache_fsm = DCACHE_IDLE;
3779	m_drsp.valid = true;
3780	}
3781	else
3782	{
3783	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3784	}
3785	break;
3786	}
3787	/////////////////////////
3788	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3789	{
3790	r_dtlb.inval(r_dcache_save_wdata.read());
3791	r_dcache_fsm = DCACHE_IDLE;
3792	m_drsp.valid = true;
3793	break;
3794	}
3795	////////////////////////////
3796	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3797	// requires 3 cycles: access tlb, read cache, inval cache
3798	// we compute the physical address in this state
3799	{
3800	paddr_t paddr;
3801	bool hit;
3802
3803	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3804	{
3805
3806	#ifdef INSTRUMENTATION
3807	m_cpt_dtlb_read++;
3808	#endif
3809	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3810	&paddr );
3811	}
3812	else // dtlb not activated
3813	{
3814	paddr = (paddr_t)r_dcache_save_wdata.read();
3815	hit = true;
3816	}
3817
3818	if ( hit ) // tlb hit
3819	{
3820	r_dcache_save_paddr = paddr;
3821	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3822	}
3823	else // tlb miss
3824	{
3825
3826	#ifdef INSTRUMENTATION
3827	m_cpt_dtlb_miss++;
3828	#endif
3829	r_dcache_tlb_ins = false; // dtlb
3830	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3831	r_dcache_fsm = DCACHE_TLB_MISS;
3832	}
3833
3834	#if DEBUG_DCACHE
3835	if ( m_debug_activated )
3836	{
3837	std::cout << " <PROC " << name()
3838	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3839	<< " / VADDR = " << r_dcache_save_wdata.read()
3840	<< " / PADDR = " << paddr << std::endl;
3841	}
3842	#endif
3843
3844	break;
3845	}
3846	////////////////////////////
3847	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3848	// requires 2 cycles: read cache / inval cache
3849	// In this state we read dcache.
3850	{
3851	size_t way;
3852	size_t set;
3853	size_t word;
3854	int state;
3855
3856	#ifdef INSTRUMENTATION
3857	m_cpt_dcache_dir_read++;
3858	#endif
3859	r_dcache.read_dir( r_dcache_save_paddr.read(),
3860	&state,
3861	&way,
3862	&set,
3863	&word );
3864
3865	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3866	{
3867	r_dcache_xtn_way = way;
3868	r_dcache_xtn_set = set;
3869	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3870	}
3871	else // miss : nothing to do
3872	{
3873	r_dcache_fsm = DCACHE_IDLE;
3874	m_drsp.valid = true;
3875	}
3876
3877	#if DEBUG_DCACHE
3878	if ( m_debug_activated )
3879	{
3880	std::cout << " <PROC " << name()
3881	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3882	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3883	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3884	<< " / SET = " << set
3885	<< " / WAY = " << way << std::endl;
3886	}
3887	#endif
3888	break;
3889	}
3890	////////////////////////////
3891	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3892	// Blocked if previous cleanup not completed
3893	// Test if itlb or dtlb inval is required
3894	{
3895	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3896	{
3897	size_t way = r_dcache_xtn_way.read();
3898	size_t set = r_dcache_xtn_set.read();
3899	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3900
3901	#ifdef INSTRUMENTATION
3902	m_cpt_dcache_dir_write++;
3903	#endif
3904	r_dcache.write_dir( way,
3905	set,
3906	CACHE_SLOT_STATE_ZOMBI );
3907
3908	// request cleanup
3909	r_dcache_cc_send_req = true;
3910	r_dcache_cc_send_nline = nline;
3911	r_dcache_cc_send_way = way;
3912	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3913
3914	// possible itlb & dtlb invalidate
3915	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3916	{
3917	r_dcache_tlb_inval_line = nline;
3918	r_dcache_tlb_inval_set = 0;
3919	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3920	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3921	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3922	}
3923	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3924	{
3925	r_itlb.reset();
3926	r_dtlb.reset();
3927	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3928	r_dcache_fsm = DCACHE_IDLE;
3929	m_drsp.valid = true;
3930	}
3931	else
3932	{
3933	r_dcache_fsm = DCACHE_IDLE;
3934	m_drsp.valid = true;
3935	}
3936
3937	#if DEBUG_DCACHE
3938	if ( m_debug_activated )
3939	{
3940	std::cout << " <PROC " << name()
3941	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3942	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3943	}
3944	#endif
3945	}
3946	break;
3947	}
3948	//////////////////////////////
3949	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3950	{
3951	r_dcache_fsm = DCACHE_IDLE;
3952	m_drsp.valid = true;
3953	break;
3954	}
3955	////////////////////////
3956	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3957	// if previous cleanup has been sent.
3958	// Waiting in this state if no slot available
3959	// Set the r_dcache_cleanup_req flip-flop
3960	// and the r_dcache_miss_clack flip-flop
3961	// when a cleanup is required
3962	{
3963	if ( m_dreq.valid) m_cost_data_miss_frz++;
3964
3965	// coherence clack request (from DSPIN CLACK)
3966	if ( r_dcache_clack_req.read() )
3967	{
3968	r_dcache_fsm = DCACHE_CC_CHECK;
3969	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3970	break;
3971	}
3972
3973	// coherence request (from CC_RECEIVE FSM)
3974	if ( r_cc_receive_dcache_req.read() )
3975	{
3976	r_dcache_fsm = DCACHE_CC_CHECK;
3977	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3978	break;
3979	}
3980
3981	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3982	{
3983	bool found = false;
3984	bool cleanup = false;
3985	size_t way = 0;
3986	size_t set = 0;
3987	paddr_t victim = 0;
3988
3989	#ifdef INSTRUMENTATION
3990	m_cpt_dcache_dir_read++;
3991	#endif
3992	r_dcache.read_select( r_dcache_save_paddr.read(),
3993	&victim,
3994	&way,
3995	&set,
3996	&found,
3997	&cleanup );
3998
3999	if ( found )
4000	{
4001	r_dcache_miss_way = way;
4002	r_dcache_miss_set = set;
4003
4004	if ( cleanup )
4005	{
4006	r_dcache_miss_clack = true;
4007	r_dcache_fsm = DCACHE_MISS_CLEAN;
4008	// request cleanup
4009	r_dcache_cc_send_req = true;
4010	r_dcache_cc_send_nline = victim;
4011	r_dcache_cc_send_way = way;
4012	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4013	}
4014	else
4015	{
4016	r_dcache_fsm = DCACHE_MISS_WAIT;
4017	}
4018
4019	#if DEBUG_DCACHE
4020	if ( m_debug_activated )
4021	{
4022	std::cout << " <PROC " << name()
4023	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4024	<< " / WAY = " << way
4025	<< " / SET = " << set
4026	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4027	if(cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4028	else std::cout << std::endl;
4029	}
4030	#endif
4031	} // end found
4032	}
4033	break;
4034	}
4035	///////////////////////
4036	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4037	// and possibly request itlb or dtlb invalidate
4038	{
4039	if ( m_dreq.valid) m_cost_data_miss_frz++;
4040
4041	size_t way = r_dcache_miss_way.read();
4042	size_t set = r_dcache_miss_set.read();
4043
4044	#ifdef INSTRUMENTATION
4045	m_cpt_dcache_dir_read++;
4046	#endif
4047	r_dcache.write_dir( way,
4048	set,
4049	CACHE_SLOT_STATE_ZOMBI );
4050	#if DEBUG_DCACHE
4051	if ( m_debug_activated )
4052	{
4053	std::cout << " <PROC " << name()
4054	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4055	<< " / way = " << way
4056	<< " / set = " << set << std::endl;
4057	}
4058	#endif
4059	// if selective itlb & dtlb invalidate are required
4060	// the miss response is not handled before invalidate completed
4061	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
4062	{
4063	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4064	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
4065	r_dcache_tlb_inval_set = 0;
4066	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4067	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4068	}
4069	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
4070	{
4071	r_itlb.reset();
4072	r_dtlb.reset();
4073	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4074	r_dcache_fsm = DCACHE_MISS_WAIT;
4075	}
4076	else
4077	{
4078	r_dcache_fsm = DCACHE_MISS_WAIT;
4079	}
4080	break;
4081	}
4082	//////////////////////
4083	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4084	// This state is in charge of error signaling
4085	// There is 5 types of error depending on the requester
4086	{
4087	if ( m_dreq.valid) m_cost_data_miss_frz++;
4088
4089	// coherence clack request (from DSPIN CLACK)
4090	if ( r_dcache_clack_req.read() )
4091	{
4092	r_dcache_fsm = DCACHE_CC_CHECK;
4093	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4094	break;
4095	}
4096
4097	// coherence request (from CC_RECEIVE FSM)
4098	if ( r_cc_receive_dcache_req.read() )
4099	{
4100	r_dcache_fsm = DCACHE_CC_CHECK;
4101	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4102	break;
4103	}
4104
4105	if ( r_vci_rsp_data_error.read() ) // bus error
4106	{
4107	switch ( r_dcache_miss_type.read() )
4108	{
4109	case PROC_MISS:
4110	{
4111	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4112	r_mmu_dbvar = r_dcache_save_vaddr.read();
4113	m_drsp.valid = true;
4114	m_drsp.error = true;
4115	r_dcache_fsm = DCACHE_IDLE;
4116	break;
4117	}
4118	case PTE1_MISS:
4119	{
4120	if ( r_dcache_tlb_ins.read() )
4121	{
4122	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4123	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4124	r_icache_tlb_miss_req = false;
4125	r_icache_tlb_rsp_error = true;
4126	}
4127	else
4128	{
4129	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4130	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4131	m_drsp.valid = true;
4132	m_drsp.error = true;
4133	}
4134	r_dcache_fsm = DCACHE_IDLE;
4135	break;
4136	}
4137	case PTE2_MISS:
4138	{
4139	if ( r_dcache_tlb_ins.read() )
4140	{
4141	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4142	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4143	r_icache_tlb_miss_req = false;
4144	r_icache_tlb_rsp_error = true;
4145	}
4146	else
4147	{
4148	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4149	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4150	m_drsp.valid = true;
4151	m_drsp.error = true;
4152	}
4153	r_dcache_fsm = DCACHE_IDLE;
4154	break;
4155	}
4156	} // end switch type
4157	r_vci_rsp_data_error = false;
4158	}
4159	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4160	{
4161	r_dcache_miss_word = 0;
4162	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4163	}
4164	break;
4165	}
4166	//////////////////////////
4167	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4168	{
4169	if ( m_dreq.valid) m_cost_data_miss_frz++;
4170
4171	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4172	{
4173	#ifdef INSTRUMENTATION
4174	m_cpt_dcache_data_write++;
4175	#endif
4176	r_dcache.write( r_dcache_miss_way.read(),
4177	r_dcache_miss_set.read(),
4178	r_dcache_miss_word.read(),
4179	r_vci_rsp_fifo_dcache.read() );
4180	#if DEBUG_DCACHE
4181	if ( m_debug_activated )
4182	{
4183	std::cout << " <PROC " << name()
4184	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4185	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4186	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4187	<< " / SET = " << r_dcache_miss_set.read()
4188	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4189	}
4190	#endif
4191	vci_rsp_fifo_dcache_get = true;
4192	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4193
4194	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4195	{
4196	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4197	}
4198	}
4199	break;
4200	}
4201	//////////////////////////
4202	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4203	// and the cleanup ack has not been received,
4204	// as indicated by the r_dcache_miss clack.
4205	// - If no matching coherence request (r_dcache_inval_miss)
4206	// switch directory slot to VALID state.
4207	// - If matching coherence request, switch directory slot
4208	// to ZOMBI state, and send a cleanup request.
4209	{
4210	if ( m_dreq.valid) m_cost_data_miss_frz++;
4211
4212	// coherence clack request (from DSPIN CLACK)
4213	if ( r_dcache_clack_req.read() )
4214	{
4215	r_dcache_fsm = DCACHE_CC_CHECK;
4216	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4217	break;
4218	}
4219
4220	// coherence request (from CC_RECEIVE FSM)
4221	if ( r_cc_receive_dcache_req.read() )
4222	{
4223	r_dcache_fsm = DCACHE_CC_CHECK;
4224	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4225	break;
4226	}
4227
4228	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4229	{
4230	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4231	{
4232	if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
4233	{
4234	r_dcache_miss_inval = false;
4235	// request cleanup
4236	r_dcache_cc_send_req = true;
4237	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4238	r_dcache_cc_send_way = r_dcache_miss_way.read();
4239	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4240
4241	#ifdef INSTRUMENTATION
4242	m_cpt_dcache_dir_write++;
4243	#endif
4244	r_dcache.write_dir( r_dcache_save_paddr.read(),
4245	r_dcache_miss_way.read(),
4246	r_dcache_miss_set.read(),
4247	CACHE_SLOT_STATE_ZOMBI );
4248	#if DEBUG_DCACHE
4249	if ( m_debug_activated )
4250	std::cout << " <PROC " << name()
4251	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4252	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4253	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4254	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4255	#endif
4256	}
4257	else
4258	break;
4259	}
4260	else // switch slot to VALID state
4261	{
4262
4263	#ifdef INSTRUMENTATION
4264	m_cpt_dcache_dir_write++;
4265	#endif
4266	r_dcache.write_dir( r_dcache_save_paddr.read(),
4267	r_dcache_miss_way.read(),
4268	r_dcache_miss_set.read(),
4269	CACHE_SLOT_STATE_VALID );
4270
4271	#if DEBUG_DCACHE
4272	if ( m_debug_activated )
4273	std::cout << " <PROC " << name()
4274	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4275	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4276	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4277	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4278	#endif
4279	// reset directory extension
4280	size_t way = r_dcache_miss_way.read();
4281	size_t set = r_dcache_miss_set.read();
4282	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4283	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4284	}
4285	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4286	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4287	else r_dcache_fsm = DCACHE_IDLE;
4288	}
4289	break;
4290	}
4291	/////////////////////
4292	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4293	{
4294	// coherence clack request (from DSPIN CLACK)
4295	if ( r_dcache_clack_req.read() )
4296	{
4297	r_dcache_fsm = DCACHE_CC_CHECK;
4298	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4299	break;
4300	}
4301
4302	// coherence request (from CC_RECEIVE FSM)
4303	if ( r_cc_receive_dcache_req.read() )
4304	{
4305	r_dcache_fsm = DCACHE_CC_CHECK;
4306	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4307	break;
4308	}
4309
4310	if ( r_vci_rsp_data_error.read() ) // bus error
4311	{
4312	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4313	r_mmu_dbvar = m_dreq.addr;
4314	r_vci_rsp_data_error = false;
4315	m_drsp.error = true;
4316	m_drsp.valid = true;
4317	r_dcache_fsm = DCACHE_IDLE;
4318	break;
4319	}
4320	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4321	{
4322	// consume data
4323	vci_rsp_fifo_dcache_get = true;
4324	r_dcache_fsm = DCACHE_IDLE;
4325
4326	// acknowledge the processor request if it has not been modified
4327	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4328	{
4329	m_drsp.valid = true;
4330	m_drsp.error = false;
4331	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4332	}
4333	}
4334	break;
4335	}
4336	/////////////////////
4337	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4338	{
4339	// coherence clack request (from DSPIN CLACK)
4340	if ( r_dcache_clack_req.read() )
4341	{
4342	r_dcache_fsm = DCACHE_CC_CHECK;
4343	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4344	break;
4345	}
4346
4347	// coherence request (from CC_RECEIVE FSM)
4348	if ( r_cc_receive_dcache_req.read() )
4349	{
4350	r_dcache_fsm = DCACHE_CC_CHECK;
4351	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4352	break;
4353	}
4354
4355	if ( r_vci_rsp_data_error.read() ) // bus error
4356	{
4357	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4358	r_mmu_dbvar = m_dreq.addr;
4359	r_vci_rsp_data_error = false;
4360	m_drsp.error = true;
4361	m_drsp.valid = true;
4362	r_dcache_fsm = DCACHE_IDLE;
4363	break;
4364	}
4365	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4366	{
4367	// consume data
4368	vci_rsp_fifo_dcache_get = true;
4369
4370	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4371	{
4372	// set key value in llsc reservation buffer
4373	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4374	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4375	}
4376	else // last flit
4377	{
4378	// acknowledge the processor request if it has not been modified
4379	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4380	{
4381	m_drsp.valid = true;
4382	m_drsp.error = false;
4383	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4384	}
4385	r_dcache_fsm = DCACHE_IDLE;
4386	}
4387	}
4388	break;
4389	}
4390	////////////////////
4391	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4392	{
4393	// coherence clack request (from DSPIN CLACK)
4394	if ( r_dcache_clack_req.read() )
4395	{
4396	r_dcache_fsm = DCACHE_CC_CHECK;
4397	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4398	break;
4399	}
4400
4401	// coherence request (from CC_RECEIVE FSM)
4402	if ( r_cc_receive_dcache_req.read() )
4403	{
4404	r_dcache_fsm = DCACHE_CC_CHECK;
4405	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4406	break;
4407	}
4408
4409	if ( r_vci_rsp_data_error.read() ) // bus error
4410	{
4411	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4412	r_mmu_dbvar = m_dreq.addr;
4413	r_vci_rsp_data_error = false;
4414	m_drsp.error = true;
4415	m_drsp.valid = true;
4416	r_dcache_fsm = DCACHE_IDLE;
4417	break;
4418	}
4419	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4420	{
4421	// consume response
4422	vci_rsp_fifo_dcache_get = true;
4423	m_drsp.valid = true;
4424	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4425	r_dcache_fsm = DCACHE_IDLE;
4426	}
4427	break;
4428	}
4429	//////////////////////////
4430	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4431	// before handling a processor WRITE or SC request
4432	// Input argument is r_dcache_dirty_paddr
4433	// In this first state, we get PTE value in dcache
4434	// and post a CAS request to CMD FSM
4435	{
4436	// get PTE in dcache
4437	uint32_t pte;
4438	size_t way;
4439	size_t set;
4440	size_t word; // unused
4441	int state;
4442
4443	#ifdef INSTRUMENTATION
4444	m_cpt_dcache_data_read++;
4445	m_cpt_dcache_dir_read++;
4446	#endif
4447	r_dcache.read( r_dcache_dirty_paddr.read(),
4448	&pte,
4449	&way,
4450	&set,
4451	&word,
4452	&state );
4453
4454	assert( (state == CACHE_SLOT_STATE_VALID) and
4455	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4456
4457	// request CAS transaction to CMD_FSM
4458	r_dcache_dirty_way = way;
4459	r_dcache_dirty_set = set;
4460
4461	// check llsc reservation buffer
4462	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4463	r_dcache_llsc_valid = false;
4464
4465	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4466	r_dcache_vci_cas_req = true;
4467	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4468	r_dcache_vci_cas_old = pte;
4469	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4470	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4471
4472	#if DEBUG_DCACHE
4473	if ( m_debug_activated )
4474	{
4475	std::cout << " <PROC " << name()
4476	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4477	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4478	<< " / PTE_VALUE = " << pte << std::dec
4479	<< " / SET = " << set
4480	<< " / WAY = " << way << std::endl;
4481	}
4482	#endif
4483	break;
4484	}
4485	///////////////////////
4486	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4487	// and return to IDLE state when response is received.
4488	// we don't care if the CAS is a failure:
4489	// - if the CAS is a success, the coherence mechanism
4490	// updates the local copy.
4491	// - if the CAS is a failure, we just retry the write.
4492	{
4493	// coherence clack request (from DSPIN CLACK)
4494	if ( r_dcache_clack_req.read() )
4495	{
4496	r_dcache_fsm = DCACHE_CC_CHECK;
4497	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4498	break;
4499	}
4500
4501	// coherence request (from CC_RECEIVE FSM)
4502	if ( r_cc_receive_dcache_req.read() )
4503	{
4504	r_dcache_fsm = DCACHE_CC_CHECK;
4505	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4506	break;
4507	}
4508
4509	if ( r_vci_rsp_data_error.read() ) // bus error
4510	{
4511	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4512	std::cout << "This should not happen in this state" << std::endl;
4513	exit(0);
4514	}
4515	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4516	{
4517	vci_rsp_fifo_dcache_get = true;
4518	r_dcache_fsm = DCACHE_IDLE;
4519
4520	#if DEBUG_DCACHE
4521	if ( m_debug_activated )
4522	{
4523	std::cout << " <PROC " << name()
4524	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4525	}
4526	#endif
4527	}
4528	break;
4529	}
4530	/////////////////////
4531	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4532	// handling coherence requests for DCACHE.
4533	// If there is a matching pending miss on the modified cache
4534	// line this is signaled in the r_dcache_miss inval flip-flop.
4535	// If the updated (or invalidated) cache line has copies in TLBs
4536	// these TLB copies are invalidated.
4537	// The return state is defined in r_dcache_fsm_cc_save
4538	{
4539	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4540	paddr_t mask = ~((m_dcache_words<<2)-1);
4541
4542	#if DEBUG_DCACHE
4543	if ( m_debug_activated )
4544	{
4545	std::cout << " <PROC " << name()
4546	<< " DCACHE_CC_CHECK> paddr = " << paddr
4547	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4548	<< " mask = " << mask
4549	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = "
4550	<< (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4551	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = "
4552	<< (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4553	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = "
4554	<< ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4555	<<std::endl;
4556	}
4557	#endif
4558
4559	if (r_dcache_clack_req.read())
4560	// We switch the directory slot to EMPTY state
4561	// and reset r_icache_miss_clack if the cleanup ack
4562	// is matching a pending miss.
4563	{
4564
4565	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4566
4567	#ifdef INSTRUMENTATION
4568	m_cpt_dcache_dir_write++;
4569	#endif
4570	r_dcache.write_dir( 0,
4571	r_dcache_clack_way.read(),
4572	r_dcache_clack_set.read(),
4573	CACHE_SLOT_STATE_EMPTY);
4574
4575	if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4576	(r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
4577	r_dcache_miss_clack = false;
4578
4579	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4580	r_dcache_clack_req = false;
4581	#if DEBUG_DCACHE
4582	if ( m_debug_activated )
4583	{
4584	std::cout << " <PROC " << name()
4585	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4586	<< " set = " << r_dcache_clack_set.read()
4587	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4588	}
4589	#endif
4590	}
4591	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4592	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4593	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4594	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4595	{
4596	// signaling matching
4597	r_dcache_miss_inval = true;
4598
4599	// in case of update, go to CC_UPDT
4600	// JUST TO POP THE FIFO
4601	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4602	{
4603	r_dcache_fsm = DCACHE_CC_UPDT;
4604	r_dcache_cc_word = r_cc_receive_word_idx.read();
4605	// just pop the fifo , don't write in icache
4606	r_dcache_cc_need_write = false;
4607	}
4608	// the request is dealt with
4609	else
4610	{
4611	r_cc_receive_dcache_req = false;
4612	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4613	}
4614
4615	#if DEBUG_DCACHE
4616	if ( m_debug_activated )
4617	{
4618	std::cout << " <PROC " << name()
4619	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4620	<< " PADDR = " << std::hex << paddr << std::endl;
4621	}
4622	#endif
4623
4624	}
4625	else // no match
4626	{
4627	int state = 0;
4628	size_t way = 0;
4629	size_t set = 0;
4630	size_t word = 0;
4631
4632	#ifdef INSTRUMENTATION
4633	m_cpt_dcache_dir_read++;
4634	#endif
4635	r_dcache.read_dir( paddr,
4636	&state,
4637	&way,
4638	&set,
4639	&word ); // unused
4640
4641	r_dcache_cc_way = way;
4642	r_dcache_cc_set = set;
4643
4644	if ( state == CACHE_SLOT_STATE_VALID) // hit
4645	{
4646	// need to update the cache state
4647	r_dcache_cc_need_write = true;
4648	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4649	{
4650	r_dcache_fsm = DCACHE_CC_UPDT;
4651	r_dcache_cc_word = r_cc_receive_word_idx.read();
4652	}
4653	else if ((r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) \|\| // hit broadcast
4654	(r_cc_receive_dcache_type.read() == CC_TYPE_INVAL )) // hit inval
4655	{
4656	r_dcache_fsm = DCACHE_CC_INVAL;
4657	}
4658	}
4659	else // miss
4660	{
4661	// multicast acknowledgement required in case of update
4662	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4663	{
4664	r_dcache_fsm = DCACHE_CC_UPDT;
4665	r_dcache_cc_word = r_cc_receive_word_idx.read();
4666	// just pop the fifo , don't write in icache
4667	r_dcache_cc_need_write = false;
4668	}
4669	else // No response needed
4670	{
4671	r_cc_receive_dcache_req = false;
4672	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4673	}
4674	}
4675
4676	#if DEBUG_DCACHE
4677	if ( m_debug_activated )
4678	{
4679	std::cout << " <PROC " << name()
4680	<< " DCACHE_CC_CHECK> Coherence request received:"
4681	<< " PADDR = " << std::hex << paddr
4682	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4683	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4684	}
4685	#endif
4686	}
4687	break;
4688	}
4689	///////////////////
4690	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4691	// after possible invalidation of copies in TLBs
4692	{
4693	size_t word = r_dcache_cc_word.read();
4694	size_t way = r_dcache_cc_way.read();
4695	size_t set = r_dcache_cc_set.read();
4696
4697	if (r_cc_receive_updt_fifo_be.rok())
4698	{
4699	if (r_dcache_cc_need_write.read())
4700	{
4701	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4702	{
4703	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4704	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4705	r_dcache_tlb_inval_set = 0;
4706	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4707	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4708	break;
4709	}
4710
4711	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4712	{
4713	r_itlb.reset();
4714	r_dtlb.reset();
4715	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4716
4717	#if DEBUG_DCACHE
4718	if ( m_debug_activated )
4719	{
4720	std::cout << " <PROC " << name()
4721	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4722	}
4723	#endif
4724	}
4725
4726	#ifdef INSTRUMENTATION
4727	m_cpt_dcache_data_write++;
4728	#endif
4729	r_dcache.write( way,
4730	set,
4731	word,
4732	r_cc_receive_updt_fifo_data.read(),
4733	r_cc_receive_updt_fifo_be.read() );
4734
4735	r_dcache_cc_word = word + 1;
4736
4737	#if DEBUG_DCACHE
4738	if ( m_debug_activated )
4739	{
4740	std::cout << " <PROC " << name()
4741	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4742	<< " / WAY = " << way
4743	<< " / SET = " << set
4744	<< " / WORD = " << word
4745	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4746	}
4747	#endif
4748	}
4749
4750	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4751	{
4752	// no need to write in the cache anymore
4753	r_dcache_cc_need_write = false;
4754
4755	// wait to send a request to cc_send_fsm
4756	if(not r_dcache_cc_send_req.read())
4757	// cc_send is available
4758	{
4759	//consume last fifo flit if eop and request to cc_send possible
4760	cc_receive_updt_fifo_get = true;
4761
4762	// coherence request completed
4763	r_cc_receive_dcache_req = false;
4764
4765	// request multicast acknowledgement
4766	r_dcache_cc_send_req = true;
4767	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4768	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4769	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4770
4771	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4772	}
4773	}
4774	else
4775	{
4776	//consume fifo if not eop
4777	cc_receive_updt_fifo_get = true;
4778	}
4779	}
4780	break;
4781	}
4782	/////////////////////////
4783	case DCACHE_CC_INVAL: // hit invalidate : switch state to ZOMBI state
4784	// and request a cleanup, after possible
4785	// invalidation of copies in TLBs
4786	{
4787	size_t way = r_dcache_cc_way.read();
4788	size_t set = r_dcache_cc_set.read();
4789	paddr_t nline = r_cc_receive_dcache_nline.read();
4790
4791	if (r_dcache_cc_need_write.read())
4792	{
4793	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4794	{
4795	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4796	r_dcache_tlb_inval_line = nline;
4797	r_dcache_tlb_inval_set = 0;
4798	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4799	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4800	break;
4801	}
4802	else
4803	{
4804	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4805	{
4806	r_itlb.reset();
4807	r_dtlb.reset();
4808	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4809
4810	#if DEBUG_DCACHE
4811	if ( m_debug_activated )
4812	{
4813	std::cout << " <PROC " << name()
4814	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4815	}
4816	#endif
4817	}
4818
4819	#ifdef INSTRUMENTATION
4820	m_cpt_dcache_dir_write++;
4821	#endif
4822	r_dcache.write_dir( way,
4823	set,
4824	CACHE_SLOT_STATE_ZOMBI );
4825
4826	r_dcache_cc_need_write = false;
4827	#if DEBUG_DCACHE
4828	if ( m_debug_activated )
4829	{
4830	std::cout << " <PROC " << name()
4831	<< " DCACHE_CC_INVAL > Slot goes to ZOMBI state "
4832	<< " SET = " << set
4833	<< " / WAY = " << way << std::endl;
4834	}
4835	#endif
4836	}
4837	}
4838	// cleanup
4839	// send a request to cc_send_fsm
4840	if(not r_dcache_cc_send_req.read()) // cc_send is available
4841	{
4842	// coherence request completed
4843	r_cc_receive_dcache_req = false;
4844	// request cleanup
4845	r_dcache_cc_send_req = true;
4846	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4847	r_dcache_cc_send_way = r_dcache_cc_way.read();
4848	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4849
4850	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4851	}
4852	//else wait for previous cc_send request to be sent
4853	break;
4854	}
4855	///////////////////////////
4856	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4857	// It makes assumption: m_itlb_sets == m_dtlb_sets
4858	// All ways are handled in parallel.
4859	// We enter this state when a DCACHE line is modified,
4860	// and there is a copy in itlb or dtlb.
4861	// It can be caused by:
4862	// - a coherence inval or updt transaction,
4863	// - a line inval caused by a cache miss
4864	// - a processor XTN inval request,
4865	// - a WRITE hit,
4866	// - a Dirty bit update
4867	// Input arguments are:
4868	// - r_dcache_tlb_inval_line
4869	// - r_dcache_tlb_inval_set
4870	// - r_dcache_fsm_scan_save
4871	{
4872	paddr_t line = r_dcache_tlb_inval_line.read();
4873	size_t set = r_dcache_tlb_inval_set.read();
4874	size_t way;
4875	bool ok;
4876
4877	for ( way = 0 ; way < m_itlb_ways ; way++ )
4878	{
4879	ok = r_itlb.inval( line, way, set );
4880
4881	#if DEBUG_DCACHE
4882	if ( m_debug_activated and ok )
4883	{
4884	std::cout << " <PROC " << name()
4885	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4886	<< " line = " << line << std::dec
4887	<< " / set = " << set
4888	<< " / way = " << way << std::endl;
4889	}
4890	#endif
4891	}
4892
4893	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4894	{
4895	ok = r_dtlb.inval( line, way, set );
4896
4897	#if DEBUG_DCACHE
4898	if ( m_debug_activated and ok )
4899	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
4900	<< " Invalidate DTLB entry" << std::hex
4901	<< " / line = " << line << std::dec
4902	<< " / set = " << set
4903	<< " / way = " << way << std::endl;
4904	#endif
4905	}
4906
4907	// return to the calling state when TLB inval completed
4908	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4909	{
4910	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4911	}
4912	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4913	break;
4914	}
4915	} // end switch r_dcache_fsm
4916
4917	///////////////// wbuf update ///////////////////////////////////////////////////////
4918	r_wbuf.update();
4919
4920	///////////////// llsc update ///////////////////////////////////////////////////////
4921	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4922	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4923
4924	//////////////// test processor frozen //////////////////////////////////////////////
4925	// The simulation exit if the number of consecutive frozen cycles
4926	// is larger than the m_max_frozen_cycles (constructor parameter)
4927	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4928	{
4929	m_cpt_frz_cycles++; // used for instrumentation
4930	m_cpt_stop_simulation++; // used for debug
4931	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4932	{
4933	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4934	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4935	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4936	<< std::endl;
4937	r_iss.dump();
4938	exit(1);
4939	}
4940	}
4941	else
4942	{
4943	m_cpt_stop_simulation = 0;
4944	}
4945
4946	/////////// execute one iss cycle /////////////////////////////////
4947	{
4948	uint32_t it = 0;
4949	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4950	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4951	}
4952
4953	////////////////////////////////////////////////////////////////////////////
4954	// The VCI_CMD FSM controls the following ressources:
4955	// - r_vci_cmd_fsm
4956	// - r_vci_cmd_min
4957	// - r_vci_cmd_max
4958	// - r_vci_cmd_cpt
4959	// - r_vci_cmd_imiss_prio
4960	// - wbuf (reset)
4961	// - r_icache_miss_req (reset)
4962	// - r_icache_unc_req (reset)
4963	// - r_dcache_vci_miss_req (reset)
4964	// - r_dcache_vci_unc_req (reset)
4965	// - r_dcache_vci_ll_req (reset)
4966	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4967	// - r_dcache_vci_cas_req (reset)
4968	//
4969	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4970	// There are 8 request types, with the following priorities :
4971	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4972	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4973	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4974	// 4 - Instruction Uncachable : r_icache_unc_req
4975	// 5 - Data Write : r_wbuf.rok()
4976	// 6 - Data Linked Load : r_dcache_vci_ll_req
4977	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4978	// 8 - Compare And Swap : r_dcache_vci_cas_req
4979	//
4980	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4981	// and the VCI_RSP_FSM are fully desynchronized.
4982	//
4983	// VCI formats:
4984	// According to the VCI advanced specification, all read requests packets
4985	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4986	// are one word packets.
4987	// For write burst packets, all words are in the same cache line,
4988	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4989	// The sc command packet implements actually a compare-and-swap mechanism
4990	// and the packet contains two flits.
4991	////////////////////////////////////////////////////////////////////////////////////
4992
4993
4994	switch ( r_vci_cmd_fsm.read() )
4995	{
4996	//////////////
4997	case CMD_IDLE:
4998	{
4999	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5000	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5001	// to check a possible pending write on the same cache line.
5002	// As there is only one possible access per cycle to write buffer, we implement
5003	// a round-robin priority between DCACHE and ICACHE for this access,
5004	// using the r_vci_cmd_imiss_prio flip-flop.
5005
5006	size_t wbuf_min;
5007	size_t wbuf_max;
5008
5009	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
5010	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5011
5012	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5013	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5014
5015	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5016	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5017
5018	bool icache_miss_req = r_icache_miss_req.read() and
5019	( not (r_dcache_vci_miss_req.read() or
5020	r_dcache_vci_ll_req.read() or
5021	r_dcache_vci_unc_req.read())
5022	or r_vci_cmd_imiss_prio.read() );
5023
5024	// 1 - Data Read Miss
5025	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
5026	{
5027	r_vci_cmd_fsm = CMD_DATA_MISS;
5028	r_dcache_vci_miss_req = false;
5029	r_vci_cmd_imiss_prio = true;
5030	// m_cpt_dmiss_transaction++;
5031	}
5032	// 2 - Data Read Uncachable
5033	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5034	{
5035	r_vci_cmd_fsm = CMD_DATA_UNC;
5036	r_dcache_vci_unc_req = false;
5037	// m_cpt_dunc_transaction++;
5038	}
5039	// 3 - Data Linked Load
5040	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5041	{
5042	r_dcache_vci_ll_req = false;
5043	r_vci_cmd_fsm = CMD_DATA_LL;
5044	// m_cpt_ll_transaction++;
5045	}
5046	// 4 - Instruction Miss
5047	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
5048	{
5049	r_vci_cmd_fsm = CMD_INS_MISS;
5050	r_icache_miss_req = false;
5051	r_vci_cmd_imiss_prio = false;
5052	// m_cpt_imiss_transaction++;
5053	}
5054	// 5 - Instruction Uncachable
5055	else if ( r_icache_unc_req.read() )
5056	{
5057	r_vci_cmd_fsm = CMD_INS_UNC;
5058	r_icache_unc_req = false;
5059	// m_cpt_iunc_transaction++;
5060	}
5061	// 6 - Data Write
5062	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
5063	{
5064	r_vci_cmd_fsm = CMD_DATA_WRITE;
5065	r_vci_cmd_cpt = wbuf_min;
5066	r_vci_cmd_min = wbuf_min;
5067	r_vci_cmd_max = wbuf_max;
5068	// m_cpt_write_transaction++;
5069	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
5070	}
5071	// 7 - Data Store Conditionnal
5072	else if ( r_dcache_vci_sc_req.read() )
5073	{
5074	r_dcache_vci_sc_req = false;
5075	r_vci_cmd_cpt = 0;
5076	r_vci_cmd_fsm = CMD_DATA_SC;
5077	// m_cpt_sc_transaction++;
5078	}
5079	// 8 - Compare And Swap
5080	else if ( r_dcache_vci_cas_req.read() )
5081	{
5082	r_vci_cmd_fsm = CMD_DATA_CAS;
5083	r_dcache_vci_cas_req = false;
5084	r_vci_cmd_cpt = 0;
5085	// m_cpt_cas_transaction++;
5086	}
5087
5088	#if DEBUG_CMD
5089	if ( m_debug_activated )
5090	{
5091	std::cout << " <PROC " << name() << " CMD_IDLE>"
5092	<< " / dmiss_req = " << dcache_miss_req
5093	<< " / imiss_req = " << icache_miss_req
5094	<< std::endl;
5095	}
5096	#endif
5097	break;
5098	}
5099	////////////////////
5100	case CMD_DATA_WRITE:
5101	{
5102	if ( p_vci.cmdack.read() )
5103	{
5104	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5105	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5106	{
5107	r_vci_cmd_fsm = CMD_IDLE ;
5108	r_wbuf.sent() ;
5109	}
5110	}
5111	break;
5112	}
5113	/////////////////
5114	case CMD_DATA_SC:
5115	case CMD_DATA_CAS:
5116	{
5117	// The CAS and SC VCI commands contain two flits
5118	if ( p_vci.cmdack.read() )
5119	{
5120	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5121	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5122	}
5123	break;
5124	}
5125	//////////////////
5126	case CMD_INS_MISS:
5127	case CMD_INS_UNC:
5128	case CMD_DATA_MISS:
5129	case CMD_DATA_UNC:
5130	case CMD_DATA_LL:
5131	{
5132	// all read VCI commands contain one single flit
5133	if ( p_vci.cmdack.read() ) {
5134	r_vci_cmd_fsm = CMD_IDLE;
5135	}
5136	break;
5137	}
5138
5139	} // end switch r_vci_cmd_fsm
5140
5141	//////////////////////////////////////////////////////////////////////////
5142	// The VCI_RSP FSM controls the following ressources:
5143	// - r_vci_rsp_fsm:
5144	// - r_vci_rsp_fifo_icache (push)
5145	// - r_vci_rsp_fifo_dcache (push)
5146	// - r_vci_rsp_data_error (set)
5147	// - r_vci_rsp_ins_error (set)
5148	// - r_vci_rsp_cpt
5149	// - r_dcache_vci_sc_req (reset when SC response recieved)
5150	//
5151	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5152	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5153	// to identify the transactions.
5154	//
5155	// VCI vormat:
5156	// This component checks the response packet length and accepts only
5157	// single word packets for write response packets.
5158	//
5159	// Error handling:
5160	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5161	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5162	// flip_flop and the error is signaled by the DCACHE FSM.
5163	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5164	// flip_flop and the error is signaled by the ICACHE FSM.
5165	// In case of Cleanup Error, the simulation stops with an error message...
5166	//////////////////////////////////////////////////////////////////////////
5167
5168	switch ( r_vci_rsp_fsm.read() )
5169	{
5170	//////////////
5171	case RSP_IDLE:
5172	{
5173	if ( p_vci.rspval.read() )
5174	{
5175	r_vci_rsp_cpt = 0;
5176
5177	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5178	{
5179	r_vci_rsp_fsm = RSP_DATA_UNC;
5180	}
5181	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5182	{
5183	r_vci_rsp_fsm = RSP_DATA_MISS;
5184	}
5185	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5186	{
5187	r_vci_rsp_fsm = RSP_INS_UNC;
5188	}
5189	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5190	{
5191	r_vci_rsp_fsm = RSP_INS_MISS;
5192	}
5193	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5194	{
5195	r_vci_rsp_fsm = RSP_DATA_WRITE;
5196	}
5197	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5198	{
5199	r_vci_rsp_fsm = RSP_DATA_UNC;
5200	}
5201	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5202	{
5203	r_vci_rsp_fsm = RSP_DATA_LL;
5204	}
5205	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5206	{
5207	r_vci_rsp_fsm = RSP_DATA_UNC;
5208	}
5209	else
5210	{
5211	assert(false and "Unexpected VCI response");
5212	}
5213	}
5214	break;
5215	}
5216	//////////////////
5217	case RSP_INS_MISS:
5218	{
5219	if ( p_vci.rspval.read() )
5220	{
5221	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5222	{
5223	r_vci_rsp_ins_error = true;
5224	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5225	}
5226	else // no error reported
5227	{
5228	if ( r_vci_rsp_fifo_icache.wok() )
5229	{
5230	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5231	"The VCI response packet for instruction miss is too long" );
5232
5233	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5234	vci_rsp_fifo_icache_put = true,
5235	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5236	if ( p_vci.reop.read() )
5237	{
5238	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5239	"The VCI response packet for instruction miss is too short");
5240
5241	r_vci_rsp_fsm = RSP_IDLE;
5242	}
5243	}
5244	}
5245	}
5246	break;
5247	}
5248	/////////////////
5249	case RSP_INS_UNC:
5250	{
5251	if (p_vci.rspval.read() )
5252	{
5253	assert( p_vci.reop.read() and
5254	"illegal VCI response packet for uncachable instruction");
5255
5256	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5257	{
5258	r_vci_rsp_ins_error = true;
5259	r_vci_rsp_fsm = RSP_IDLE;
5260	}
5261	else // no error reported
5262	{
5263	if ( r_vci_rsp_fifo_icache.wok())
5264	{
5265	vci_rsp_fifo_icache_put = true;
5266	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5267	r_vci_rsp_fsm = RSP_IDLE;
5268	}
5269	}
5270	}
5271	break;
5272	}
5273	///////////////////
5274	case RSP_DATA_MISS:
5275	{
5276	if ( p_vci.rspval.read() )
5277	{
5278	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5279	{
5280	r_vci_rsp_data_error = true;
5281	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5282	}
5283	else // no error reported
5284	{
5285	if ( r_vci_rsp_fifo_dcache.wok() )
5286	{
5287	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5288	"The VCI response packet for data miss is too long");
5289
5290	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5291	vci_rsp_fifo_dcache_put = true,
5292	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5293	if ( p_vci.reop.read() )
5294	{
5295	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5296	"The VCI response packet for data miss is too short");
5297
5298	r_vci_rsp_fsm = RSP_IDLE;
5299	}
5300	}
5301	}
5302	}
5303	break;
5304	}
5305	//////////////////
5306	case RSP_DATA_UNC:
5307	{
5308	if (p_vci.rspval.read() )
5309	{
5310	assert( p_vci.reop.read() and
5311	"illegal VCI response packet for uncachable read data");
5312
5313	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5314	{
5315	r_vci_rsp_data_error = true;
5316	r_vci_rsp_fsm = RSP_IDLE;
5317	}
5318	else // no error reported
5319	{
5320	if ( r_vci_rsp_fifo_dcache.wok())
5321	{
5322	vci_rsp_fifo_dcache_put = true;
5323	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5324	r_vci_rsp_fsm = RSP_IDLE;
5325	}
5326	}
5327	}
5328	break;
5329	}
5330	/////////////////
5331	case RSP_DATA_LL:
5332	{
5333	if ( p_vci.rspval.read() )
5334	{
5335	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5336	{
5337	r_vci_rsp_data_error = true;
5338	r_vci_rsp_fsm = RSP_IDLE;
5339	break;
5340	}
5341	if (r_vci_rsp_cpt.read() == 0) //first flit
5342	{
5343	if(r_vci_rsp_fifo_dcache.wok())
5344	{
5345	assert(!p_vci.reop.read() &&
5346	"illegal VCI response packet for LL");
5347	vci_rsp_fifo_dcache_put = true;
5348	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5349	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5350	}
5351	break;
5352	}
5353	else // last flit
5354	{
5355	if(r_vci_rsp_fifo_dcache.wok())
5356	{
5357	assert(p_vci.reop.read() &&
5358	"illegal VCI response packet for LL");
5359	vci_rsp_fifo_dcache_put = true;
5360	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5361	r_vci_rsp_fsm = RSP_IDLE;
5362	}
5363	break;
5364	}
5365	}
5366	break;
5367	}
5368	////////////////////
5369	case RSP_DATA_WRITE:
5370	{
5371	if (p_vci.rspval.read())
5372	{
5373	assert( p_vci.reop.read() and
5374	"a VCI response packet must contain one flit for a write transaction");
5375
5376	r_vci_rsp_fsm = RSP_IDLE;
5377	uint32_t wbuf_index = p_vci.rtrdid.read();
5378	bool cacheable = r_wbuf.completed(wbuf_index);
5379	if ( not cacheable ) r_dcache_pending_unc_write = false;
5380	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5381	}
5382	break;
5383	}
5384	} // end switch r_vci_rsp_fsm
5385
5386	/////////////////////////////////////////////////////////////////////////////////////
5387	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5388	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5389	// and ICACHE FSM) that are served with a round-robin priority.
5390	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5391	// soon as the request has been sent.
5392	/////////////////////////////////////////////////////////////////////////////////////
5393	switch ( r_cc_send_fsm.read() )
5394	{
5395	///////////////////////////
5396	case CC_SEND_IDLE:
5397	{
5398	///////////////////////////////////////////////////////
5399	// handling round robin between icache and dcache : //
5400	// we first check for the last client and listen for //
5401	// a request of the other, then update the client //
5402	// r_cc_send_last_client : 0 dcache / 1 icache
5403	///////////////////////////////////////////////////////
5404	bool update_last_client = r_cc_send_last_client.read();
5405	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5406	{
5407	if (r_icache_cc_send_req.read()) // request from icache
5408	update_last_client = 1; // update last client to icache
5409	}
5410	else // last client was icache
5411	{
5412	if (r_dcache_cc_send_req.read()) // request from dcache
5413	update_last_client = 0; // update last client to dcache
5414	}
5415	r_cc_send_last_client = update_last_client;
5416
5417	// if there is an actual request
5418	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5419	{
5420	// the new client is dcache and has a cleanup request
5421	if ( (update_last_client == 0) and
5422	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5423	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5424	// the new client is dcache and has a multi acknowledgement request
5425	else if ( (update_last_client == 0) and
5426	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5427	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5428	// the new client is icache and has a cleanup request
5429	else if ( (update_last_client == 1) and
5430	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5431	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5432	// the new client is icache and has a multi acknowledgement request
5433	else if ( (update_last_client == 1) and
5434	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5435	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5436	}
5437	break;
5438	}
5439	///////////////////////////
5440	case CC_SEND_CLEANUP_1:
5441	{
5442	// wait for the first flit to be consumed
5443	if (p_dspin_p2m.read.read())
5444	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5445
5446	break;
5447	}
5448	///////////////////////////
5449	case CC_SEND_CLEANUP_2:
5450	{
5451	// wait for the second flit to be consumed
5452	if (p_dspin_p2m.read.read())
5453	{
5454	if (r_cc_send_last_client.read() == 0) // dcache active request
5455	r_dcache_cc_send_req = false; // reset dcache request
5456	else // icache active request
5457	r_icache_cc_send_req = false; // reset icache request
5458
5459	// go back to idle state
5460	r_cc_send_fsm = CC_SEND_IDLE;
5461	}
5462	break;
5463	}
5464	///////////////////////////
5465	case CC_SEND_MULTI_ACK:
5466	{
5467	// wait for the flit to be consumed
5468	if(p_dspin_p2m.read.read())
5469	{
5470	if(r_cc_send_last_client.read() == 0) // dcache active request
5471	r_dcache_cc_send_req = false; // reset dcache request
5472	else // icache active request
5473	r_icache_cc_send_req = false; // reset icache request
5474	// go back to idle state
5475	r_cc_send_fsm = CC_SEND_IDLE;
5476	}
5477	break;
5478	}
5479	} // end switch CC_SEND FSM
5480
5481	///////////////////////////////////////////////////////////////////////////////
5482	// C_RECEIVE FSM
5483	// This FSM receive all coherence packets on a DSPIN40 port.
5484	// There is 7 packet types:
5485	// - CC_DATA_INVAL : DCACHE invalidate request
5486	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5487	// - CC_INST_INVAL : ICACHE invalidate request
5488	// - CC_INST_UPDT : ICACHE update request (multi-words)
5489	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5490	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5491	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5492	//////////////////////////////////////////////////////////////////////////////
5493	switch( r_cc_receive_fsm.read() )
5494	{
5495	/////////////////////
5496	case CC_RECEIVE_IDLE:
5497	{
5498	// a coherence request has arrived
5499	if (p_dspin_m2p.write.read())
5500	{
5501	// initialize dspin received data
5502	uint64_t receive_data = p_dspin_m2p.data.read();
5503	// initialize coherence packet type
5504	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5505	DspinDhccpParam::M2P_TYPE);
5506	// initialize data/ins flip_flop (0 data / 1 ins)
5507	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5508	// test for a broadcast
5509	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5510	{
5511	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5512	}
5513	// test for a multi updt
5514	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5515	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5516	{
5517	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5518	}
5519	// test for a multi inval
5520	else
5521	{
5522	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5523	}
5524	}
5525	break;
5526	}
5527	///////////////////////////////
5528	case CC_RECEIVE_BRDCAST_HEADER:
5529	{
5530	// no actual data in the HEADER, just skip to second flit
5531	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5532	break;
5533	}
5534	//////////////////////////////
5535	case CC_RECEIVE_BRDCAST_NLINE:
5536	{
5537	// initialize dspin received data
5538	uint64_t receive_data = p_dspin_m2p.data.read();
5539	// wait for both dcache and icache to take the request
5540	// TODO maybe we need to wait for both only to leave the state, but
5541	// not to actually post a request to an available cache => need a
5542	// flip_flop to check that ?
5543	if (not (r_cc_receive_icache_req.read()) and
5544	not (r_cc_receive_dcache_req.read()) and
5545	(p_dspin_m2p.write.read()))
5546	{
5547	// request dcache to handle the BROADCAST
5548	r_cc_receive_dcache_req = true;
5549	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5550	DspinDhccpParam::BROADCAST_NLINE);
5551	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5552	// request icache to handle the BROADCAST
5553	r_cc_receive_icache_req = true;
5554	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5555	DspinDhccpParam::BROADCAST_NLINE);
5556	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5557	// get back to idle state
5558	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5559	break;
5560	}
5561	// keep waiting for the caches to accept the request
5562	break;
5563	}
5564	/////////////////////////////
5565	case CC_RECEIVE_INVAL_HEADER:
5566	{
5567	// sample updt tab index in the HEADER, then skip to second flit
5568	uint64_t receive_data = p_dspin_m2p.data.read();
5569	// for data INVAL, wait for dcache to take the request
5570	if ((r_cc_receive_data_ins.read() == 0) and
5571	not (r_cc_receive_dcache_req.read()))
5572	{
5573	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5574	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5575	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5576	break;
5577	}
5578	// for ins INVAL, wait for icache to take the request
5579	if ((r_cc_receive_data_ins.read() == 1) and
5580	not (r_cc_receive_icache_req.read()))
5581	{
5582	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5583	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5584	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5585	break;
5586	}
5587	// keep waiting for the correct cache to accept the request
5588	break;
5589	}
5590	////////////////////////////
5591	case CC_RECEIVE_INVAL_NLINE:
5592	{
5593	// sample nline in the second flit
5594	uint64_t receive_data = p_dspin_m2p.data.read();
5595	// for data INVAL, wait for dcache to take the request
5596	if ( (r_cc_receive_data_ins.read() == 0) and
5597	not (r_cc_receive_dcache_req.read()) and
5598	(p_dspin_m2p.write.read()) )
5599	{
5600	// request dcache to handle the INVAL
5601	r_cc_receive_dcache_req = true;
5602	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5603	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5604	// get back to idle state
5605	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5606	break;
5607	}
5608	// for ins INVAL, wait for icache to take the request
5609	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read()))
5610	{
5611	// request icache to handle the INVAL
5612	r_cc_receive_icache_req = true;
5613	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5614	r_cc_receive_icache_type = CC_TYPE_INVAL;
5615	// get back to idle state
5616	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5617	break;
5618	}
5619	// we should never get there
5620	assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n");
5621	}
5622	////////////////////////////
5623	case CC_RECEIVE_UPDT_HEADER:
5624	{
5625	// sample updt tab index in the HEADER, than skip to second flit
5626	uint64_t receive_data = p_dspin_m2p.data.read();
5627	// for data INVAL, wait for dcache to take the request and fifo to
5628	// be empty
5629	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5630	{
5631	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5632	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5633	break;
5634	}
5635	// for ins INVAL, wait for icache to take the request and fifo to be
5636	// empty
5637	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5638	{
5639	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5640	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5641	break;
5642	}
5643	// keep waiting for the correct cache to accept the request
5644	break;
5645	}
5646	///////////////////////////
5647	case CC_RECEIVE_UPDT_NLINE:
5648	{
5649	// sample nline and word index in the second flit
5650	uint64_t receive_data = p_dspin_m2p.data.read();
5651	// for data INVAL, wait for dcache to take the request and fifo to
5652	// be empty
5653	if ( (r_cc_receive_data_ins.read() == 0) and
5654	not (r_cc_receive_dcache_req.read()) and
5655	r_cc_receive_updt_fifo_be.empty() and
5656	(p_dspin_m2p.write.read()) )
5657	{
5658	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5659	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5660	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5661	// get back to idle state
5662	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5663	break;
5664	}
5665	// for ins INVAL, wait for icache to take the request and fifo to be
5666	// empty
5667	if ( (r_cc_receive_data_ins.read() == 1) and
5668	not (r_cc_receive_icache_req.read()) and
5669	r_cc_receive_updt_fifo_be.empty() and
5670	(p_dspin_m2p.write.read()))
5671	{
5672	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5673	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5674	r_cc_receive_icache_type = CC_TYPE_UPDT;
5675	// get back to idle state
5676	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5677	break;
5678	}
5679	// we should never get there
5680	assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");
5681	break;
5682	}
5683	//////////////////////////
5684	case CC_RECEIVE_UPDT_DATA:
5685	{
5686	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read()))
5687	r_cc_receive_dcache_req = true;
5688	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read()))
5689	r_cc_receive_icache_req = true;
5690
5691	// wait for the fifo
5692	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5693	{
5694	uint64_t receive_data = p_dspin_m2p.data.read();
5695	bool receive_eop = p_dspin_m2p.eop.read();
5696	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5697	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5698	cc_receive_updt_fifo_eop = receive_eop;
5699	cc_receive_updt_fifo_put = true;
5700	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5701	}
5702	break;
5703	}
5704	} // end switch CC_RECEIVE FSM
5705
5706	///////////////// DSPIN CLACK interface ///////////////
5707
5708	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5709	DspinDhccpParam::CLACK_TYPE);
5710
5711	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5712	DspinDhccpParam::CLACK_WAY);
5713
5714	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5715	DspinDhccpParam::CLACK_SET);
5716
5717	bool dspin_clack_get = false;
5718	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5719	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5720
5721	if (r_dspin_clack_req.read())
5722	{
5723	// CLACK DATA: Send request to DCACHE FSM
5724	if (dcache_clack_request and not r_dcache_clack_req.read()){
5725	r_dcache_clack_req = true;
5726	r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5727	r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5728	dspin_clack_get = true;
5729	}
5730
5731	// CLACK INST: Send request to ICACHE FSM
5732	else if (icache_clack_request and not r_icache_clack_req.read()){
5733	r_icache_clack_req = true;
5734	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5735	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5736	dspin_clack_get = true;
5737	}
5738	}
5739	else
5740	{
5741	dspin_clack_get = true;
5742	}
5743
5744	if (dspin_clack_get)
5745	{
5746	r_dspin_clack_req = p_dspin_clack.write.read();
5747	r_dspin_clack_flit = p_dspin_clack.data.read();
5748	}
5749
5750	///////////////// Response FIFOs update //////////////////////
5751	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5752	vci_rsp_fifo_icache_put,
5753	vci_rsp_fifo_icache_data);
5754
5755	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5756	vci_rsp_fifo_dcache_put,
5757	vci_rsp_fifo_dcache_data);
5758
5759	///////////////// updt FIFO update //////////////////////
5760	//TODO check this
5761	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5762	cc_receive_updt_fifo_put,
5763	cc_receive_updt_fifo_be);
5764	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5765	cc_receive_updt_fifo_put,
5766	cc_receive_updt_fifo_data);
5767	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5768	cc_receive_updt_fifo_put,
5769	cc_receive_updt_fifo_eop);
5770
5771	} // end transition()
5772
5773	///////////////////////
5774	tmpl(void)::genMoore()
5775	///////////////////////
5776	{
5777
5778	// VCI initiator command on the direct network
5779	// it depends on the CMD FSM state
5780
5781	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5782	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5783
5784	p_vci.pktid = 0;
5785	p_vci.srcid = m_srcid;
5786	p_vci.cons = is_sc_or_cas;
5787	p_vci.contig = not is_sc_or_cas;
5788	p_vci.wrap = false;
5789	p_vci.clen = 0;
5790	p_vci.cfixed = false;
5791
5792	if ( m_monitor_ok ) {
5793	if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
5794	if (((p_vci.address.read()) >= m_monitor_base) and
5795	((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
5796	std::cout << "CC_VCACHE Monitor " << name() << std::hex
5797	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
5798	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
5799	<< " : address = " << p_vci.address.read()
5800	<< " / be = " << p_vci.be.read();
5801	if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
5802	std::cout << " / data = " << p_vci.wdata.read();
5803	}
5804	std::cout << std::dec << std::endl;
5805	}
5806	}
5807	}
5808
5809	switch ( r_vci_cmd_fsm.read() ) {
5810
5811	case CMD_IDLE:
5812	p_vci.cmdval = false;
5813	p_vci.address = 0;
5814	p_vci.wdata = 0;
5815	p_vci.be = 0;
5816	p_vci.trdid = 0;
5817	p_vci.pktid = 0;
5818	p_vci.plen = 0;
5819	p_vci.cmd = vci_param::CMD_NOP;
5820	p_vci.eop = false;
5821	break;
5822
5823	case CMD_INS_MISS:
5824	p_vci.cmdval = true;
5825	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5826	p_vci.wdata = 0;
5827	p_vci.be = 0xF;
5828	p_vci.trdid = 0;
5829	p_vci.pktid = TYPE_READ_INS_MISS;
5830	p_vci.plen = m_icache_words<<2;
5831	p_vci.cmd = vci_param::CMD_READ;
5832	p_vci.eop = true;
5833	break;
5834
5835	case CMD_INS_UNC:
5836	p_vci.cmdval = true;
5837	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5838	p_vci.wdata = 0;
5839	p_vci.be = 0xF;
5840	p_vci.trdid = 0;
5841	p_vci.pktid = TYPE_READ_INS_UNC;
5842	p_vci.plen = 4;
5843	p_vci.cmd = vci_param::CMD_READ;
5844	p_vci.eop = true;
5845	break;
5846
5847	case CMD_DATA_MISS:
5848	p_vci.cmdval = true;
5849	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5850	p_vci.wdata = 0;
5851	p_vci.be = 0xF;
5852	p_vci.trdid = 0;
5853	p_vci.pktid = TYPE_READ_DATA_MISS;
5854	p_vci.plen = m_dcache_words << 2;
5855	p_vci.cmd = vci_param::CMD_READ;
5856	p_vci.eop = true;
5857	break;
5858
5859	case CMD_DATA_UNC:
5860	p_vci.cmdval = true;
5861	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5862	p_vci.wdata = 0;
5863	p_vci.be = r_dcache_vci_unc_be.read();
5864	p_vci.trdid = 0;
5865	p_vci.pktid = TYPE_READ_DATA_UNC;
5866	p_vci.plen = 4;
5867	p_vci.cmd = vci_param::CMD_READ;
5868	p_vci.eop = true;
5869	break;
5870
5871	case CMD_DATA_WRITE:
5872	p_vci.cmdval = true;
5873	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5874	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5875	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5876	p_vci.trdid = r_wbuf.getIndex();
5877	p_vci.pktid = TYPE_WRITE;
5878	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5879	p_vci.cmd = vci_param::CMD_WRITE;
5880	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5881	break;
5882
5883	case CMD_DATA_LL:
5884	p_vci.cmdval = true;
5885	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5886	p_vci.wdata = 0;
5887	p_vci.be = 0xF;
5888	p_vci.trdid = 0;
5889	p_vci.pktid = TYPE_LL;
5890	p_vci.plen = 8;
5891	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5892	p_vci.eop = true;
5893	break;
5894
5895	case CMD_DATA_SC:
5896	p_vci.cmdval = true;
5897	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5898	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5899	else p_vci.wdata = r_dcache_vci_sc_data.read();
5900	p_vci.be = 0xF;
5901	p_vci.trdid = 0;
5902	p_vci.pktid = TYPE_SC;
5903	p_vci.plen = 8;
5904	p_vci.cmd = vci_param::CMD_NOP;
5905	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5906	break;
5907
5908	case CMD_DATA_CAS:
5909	p_vci.cmdval = true;
5910	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5911	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5912	else p_vci.wdata = r_dcache_vci_cas_new.read();
5913	p_vci.be = 0xF;
5914	p_vci.trdid = 0;
5915	p_vci.pktid = TYPE_CAS;
5916	p_vci.plen = 8;
5917	p_vci.cmd = vci_param::CMD_NOP;
5918	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5919	break;
5920	} // end switch r_vci_cmd_fsm
5921
5922	// VCI initiator response on the direct network
5923	// it depends on the VCI_RSP FSM
5924
5925	switch (r_vci_rsp_fsm.read() )
5926	{
5927	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5928	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5929	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5930	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5931	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5932	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5933	case RSP_IDLE : p_vci.rspack = false; break;
5934	} // end switch r_vci_rsp_fsm
5935
5936
5937	// Send coherence packets on DSPIN P2M
5938	// it depends on the CC_SEND FSM
5939
5940	uint64_t dspin_send_data = 0;
5941	switch ( r_cc_send_fsm.read() )
5942	{
5943	//////////////////
5944	case CC_SEND_IDLE:
5945	{
5946	p_dspin_p2m.write = false;
5947	break;
5948	}
5949	///////////////////////
5950	case CC_SEND_CLEANUP_1:
5951	{
5952	// initialize dspin send data
5953	// DspinDhccpParam::dspin_set(dspin_send_data,
5954	// 0,
5955	// DspinDhccpParam::P2M_EOP);
5956	DspinDhccpParam::dspin_set(dspin_send_data,
5957	m_cc_global_id,
5958	DspinDhccpParam::CLEANUP_SRCID);
5959	DspinDhccpParam::dspin_set(dspin_send_data,
5960	0,
5961	DspinDhccpParam::P2M_BC);
5962
5963	if(r_cc_send_last_client.read() == 0) // dcache active request
5964	{
5965	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5966	>> (m_nline_width - m_x_width - m_y_width)
5967	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5968
5969	DspinDhccpParam::dspin_set(dspin_send_data,
5970	dest,
5971	DspinDhccpParam::CLEANUP_DEST);
5972
5973	DspinDhccpParam::dspin_set(dspin_send_data,
5974	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
5975	DspinDhccpParam::CLEANUP_NLINE_MSB);
5976
5977	DspinDhccpParam::dspin_set(dspin_send_data,
5978	r_dcache_cc_send_way.read(),
5979	DspinDhccpParam::CLEANUP_WAY_INDEX);
5980
5981	DspinDhccpParam::dspin_set(dspin_send_data,
5982	DspinDhccpParam::TYPE_CLEANUP_DATA,
5983	DspinDhccpParam::P2M_TYPE);
5984	}
5985	else // icache active request
5986	{
5987	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5988	>> (m_nline_width - m_x_width - m_y_width)
5989	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5990
5991	DspinDhccpParam::dspin_set(dspin_send_data,
5992	dest,
5993	DspinDhccpParam::CLEANUP_DEST);
5994
5995	DspinDhccpParam::dspin_set(dspin_send_data,
5996	(r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
5997	DspinDhccpParam::CLEANUP_NLINE_MSB);
5998
5999	DspinDhccpParam::dspin_set(dspin_send_data,
6000	r_icache_cc_send_way.read(),
6001	DspinDhccpParam::CLEANUP_WAY_INDEX);
6002
6003	DspinDhccpParam::dspin_set(dspin_send_data,
6004	DspinDhccpParam::TYPE_CLEANUP_INST,
6005	DspinDhccpParam::P2M_TYPE);
6006	}
6007	// send flit
6008	p_dspin_p2m.data = dspin_send_data;
6009	p_dspin_p2m.write = true;
6010	p_dspin_p2m.eop = false;
6011	break;
6012	}
6013	///////////////////////
6014	case CC_SEND_CLEANUP_2:
6015	{
6016	// initialize dspin send data
6017	// DspinDhccpParam::dspin_set(dspin_send_data,
6018	// 1,
6019	// DspinDhccpParam::P2M_EOP);
6020
6021	if(r_cc_send_last_client.read() == 0) // dcache active request
6022	{
6023	DspinDhccpParam::dspin_set(dspin_send_data,
6024	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6025	DspinDhccpParam::CLEANUP_NLINE_LSB);
6026	}
6027	else // icache active request
6028	{
6029	DspinDhccpParam::dspin_set(dspin_send_data,
6030	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6031	DspinDhccpParam::CLEANUP_NLINE_LSB);
6032	}
6033	// send flit
6034	p_dspin_p2m.data = dspin_send_data;
6035	p_dspin_p2m.write = true;
6036	p_dspin_p2m.eop = true;
6037	break;
6038	}
6039	///////////////////////
6040	case CC_SEND_MULTI_ACK:
6041	{
6042	// initialize dspin send data
6043	// DspinDhccpParam::dspin_set(dspin_send_data,
6044	// 1,
6045	// DspinDhccpParam::P2M_EOP);
6046	DspinDhccpParam::dspin_set(dspin_send_data,
6047	0,
6048	DspinDhccpParam::P2M_BC);
6049	DspinDhccpParam::dspin_set(dspin_send_data,
6050	DspinDhccpParam::TYPE_MULTI_ACK,
6051	DspinDhccpParam::P2M_TYPE);
6052
6053	if(r_cc_send_last_client.read() == 0) // dcache active request
6054	{
6055	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6056	>> (m_nline_width - m_x_width - m_y_width)
6057	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6058
6059	DspinDhccpParam::dspin_set(dspin_send_data,
6060	dest,
6061	DspinDhccpParam::MULTI_ACK_DEST);
6062
6063	DspinDhccpParam::dspin_set(dspin_send_data,
6064	r_dcache_cc_send_updt_tab_idx.read(),
6065	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6066	}
6067	else // icache active request
6068	{
6069	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6070	>> (m_nline_width - m_x_width - m_y_width)
6071	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6072
6073
6074	DspinDhccpParam::dspin_set(dspin_send_data,
6075	dest,
6076	DspinDhccpParam::MULTI_ACK_DEST);
6077
6078	DspinDhccpParam::dspin_set(dspin_send_data,
6079	r_icache_cc_send_updt_tab_idx.read(),
6080	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6081	}
6082	// send flit
6083	p_dspin_p2m.data = dspin_send_data;
6084	p_dspin_p2m.write = true;
6085	p_dspin_p2m.eop = true;
6086
6087	break;
6088	}
6089	} // end switch CC_SEND FSM
6090
6091	// Receive coherence packets
6092	// It depends on the CC_RECEIVE FSM
6093
6094	switch( r_cc_receive_fsm.read() )
6095	{
6096	/////////////////////
6097	case CC_RECEIVE_IDLE:
6098	{
6099	p_dspin_m2p.read = false;
6100	break;
6101	}
6102	//////////////////////
6103	case CC_RECEIVE_CLACK:
6104	{
6105	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6106	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6107	p_dspin_m2p.read = true;
6108	else
6109	p_dspin_m2p.read = false;
6110	break;
6111	}
6112	///////////////////////////////
6113	case CC_RECEIVE_BRDCAST_HEADER:
6114	{
6115	p_dspin_m2p.read = true;
6116	break;
6117	}
6118	//////////////////////////////
6119	case CC_RECEIVE_BRDCAST_NLINE:
6120	{
6121	// TODO maybe we need to wait for both only to leave the state, but
6122	// not to actually post a request to an available cache => need a
6123	// flip_flop to check that ?
6124	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6125	p_dspin_m2p.read = true;
6126	else
6127	p_dspin_m2p.read = false;
6128	break;
6129	}
6130	/////////////////////////////
6131	case CC_RECEIVE_INVAL_HEADER:
6132	{
6133	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6134	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6135	p_dspin_m2p.read = true;
6136	else
6137	p_dspin_m2p.read = false;
6138	break;
6139	}
6140	////////////////////////////
6141	case CC_RECEIVE_INVAL_NLINE:
6142	{
6143	p_dspin_m2p.read = true;
6144	break;
6145	}
6146	////////////////////////////
6147	case CC_RECEIVE_UPDT_HEADER:
6148	{
6149	if (((r_cc_receive_data_ins.read() == 0) and
6150	not r_cc_receive_dcache_req.read() and
6151	r_cc_receive_updt_fifo_be.empty())
6152	or
6153	(((r_cc_receive_data_ins.read() == 1) and
6154	not r_cc_receive_icache_req.read()) and
6155	r_cc_receive_updt_fifo_be.empty()))
6156	p_dspin_m2p.read = true;
6157	else
6158	p_dspin_m2p.read = false;
6159	break;
6160	}
6161	///////////////////////////
6162	case CC_RECEIVE_UPDT_NLINE:
6163	{
6164	if (((r_cc_receive_data_ins.read() == 0) and
6165	not (r_cc_receive_dcache_req.read()) and
6166	r_cc_receive_updt_fifo_be.empty())
6167	or
6168	((r_cc_receive_data_ins.read() == 1) and
6169	not (r_cc_receive_icache_req.read()) and
6170	r_cc_receive_updt_fifo_be.empty()))
6171	p_dspin_m2p.read = true;
6172	else
6173	p_dspin_m2p.read = false;
6174	break;
6175	}
6176	//////////////////////////
6177	case CC_RECEIVE_UPDT_DATA:
6178	{
6179	if (r_cc_receive_updt_fifo_be.wok())
6180	p_dspin_m2p.read = true;
6181	else
6182	p_dspin_m2p.read = false;
6183	break;
6184	}
6185	} // end switch CC_RECEIVE FSM
6186
6187	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6188	DspinDhccpParam::CLACK_TYPE);
6189
6190	bool dspin_clack_get = false;
6191	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6192	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6193
6194	if (r_dspin_clack_req.read())
6195	{
6196	// CLACK DATA: wait if pending request to DCACHE FSM
6197	if (dcache_clack_request and not r_dcache_clack_req.read())
6198	{
6199	dspin_clack_get = true;
6200	}
6201
6202	// CLACK INST: wait if pending request to ICACHE FSM
6203	else if (icache_clack_request and not r_icache_clack_req.read())
6204	{
6205	dspin_clack_get = true;
6206	}
6207	}
6208	else
6209	{
6210	dspin_clack_get = true;
6211	}
6212
6213	p_dspin_clack.read = dspin_clack_get;
6214	} // end genMoore
6215
6216	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6217	// This version of monitor print both Read and Write request
6218	{
6219	m_monitor_ok = true;
6220	m_monitor_base = base;
6221	m_monitor_length = length;
6222	}
6223
6224	tmpl(void)::stop_monitor()
6225	{
6226	m_monitor_ok = false;
6227	}
6228
6229	}}
6230
6231	// Local Variables:
6232	// tab-width: 4
6233	// c-basic-offset: 4
6234	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6235	// indent-tabs-mode: nil
6236	// End:
6237
6238	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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