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source: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 454

Last change on this file since 454 was 454, checked in by haoliu, 11 years ago
modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new version V5
File size: 232.9 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CMD 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_UPDT",
65	"ICACHE_CC_INVAL",
66	};
67
68	const char *dcache_fsm_state_str[] = {
69	"DCACHE_IDLE",
70
71	"DCACHE_TLB_MISS",
72	"DCACHE_TLB_PTE1_GET",
73	"DCACHE_TLB_PTE1_SELECT",
74	"DCACHE_TLB_PTE1_UPDT",
75	"DCACHE_TLB_PTE2_GET",
76	"DCACHE_TLB_PTE2_SELECT",
77	"DCACHE_TLB_PTE2_UPDT",
78	"DCACHE_TLB_LR_UPDT",
79	"DCACHE_TLB_LR_WAIT",
80	"DCACHE_TLB_RETURN",
81
82	"DCACHE_XTN_SWITCH",
83	"DCACHE_XTN_SYNC",
84	"DCACHE_XTN_IC_INVAL_VA",
85	"DCACHE_XTN_IC_FLUSH",
86	"DCACHE_XTN_IC_INVAL_PA",
87	"DCACHE_XTN_IT_INVAL",
88	"DCACHE_XTN_DC_FLUSH",
89	"DCACHE_XTN_DC_FLUSH_GO",
90	"DCACHE_XTN_DC_INVAL_VA",
91	"DCACHE_XTN_DC_INVAL_PA",
92	"DCACHE_XTN_DC_INVAL_END",
93	"DCACHE_XTN_DC_INVAL_GO",
94	"DCACHE_XTN_DT_INVAL",
95
96	"DCACHE_DIRTY_GET_PTE",
97	"DCACHE_DIRTY_WAIT",
98
99	"DCACHE_MISS_SELECT",
100	"DCACHE_MISS_CLEAN",
101	"DCACHE_MISS_WAIT",
102	"DCACHE_MISS_DATA_UPDT",
103	"DCACHE_MISS_DIR_UPDT",
104
105	"DCACHE_UNC_WAIT",
106	"DCACHE_LL_WAIT",
107	"DCACHE_SC_WAIT",
108
109	"DCACHE_CC_CHECK",
110	"DCACHE_CC_UPDT",
111	"DCACHE_CC_INVAL",
112
113	"DCACHE_INVAL_TLB_SCAN",
114	};
115
116	const char *cmd_fsm_state_str[] = {
117	"CMD_IDLE",
118	"CMD_INS_MISS",
119	"CMD_INS_UNC",
120	"CMD_DATA_MISS",
121	"CMD_DATA_UNC",
122	"CMD_DATA_WRITE",
123	"CMD_DATA_LL",
124	"CMD_DATA_SC",
125	"CMD_DATA_CAS",
126	};
127
128	const char *vci_pktid_type_str[] = {
129	"TYPE_READ_DATA_UNC",
130	"TYPE_READ_DATA_MISS",
131	"TYPE_READ_INS_UNC",
132	"TYPE_READ_INS_MISS",
133	"TYPE_WRITE",
134	"TYPE_CAS",
135	"TYPE_LL",
136	"TYPE_SC",
137	};
138
139	const char *vci_cmd_type_str[] = {
140	"NOP or STORE_COND",
141	"READ",
142	"WRITE",
143	"LOCKED_READ"
144	};
145
146	const char *rsp_fsm_state_str[] = {
147	"RSP_IDLE",
148	"RSP_INS_MISS",
149	"RSP_INS_UNC",
150	"RSP_DATA_MISS",
151	"RSP_DATA_UNC",
152	"RSP_DATA_LL",
153	"RSP_DATA_WRITE",
154	};
155
156	const char *cc_receive_fsm_state_str[] = {
157	"CC_RECEIVE_IDLE",
158	"CC_RECEIVE_BRDCAST_HEADER",
159	"CC_RECEIVE_BRDCAST_NLINE",
160	"CC_RECEIVE_INS_INVAL_HEADER",
161	"CC_RECEIVE_INS_INVAL_NLINE",
162	"CC_RECEIVE_INS_UPDT_HEADER",
163	"CC_RECEIVE_INS_UPDT_NLINE",
164	"CC_RECEIVE_INS_UPDT_DATA",
165	"CC_RECEIVE_DATA_INVAL_HEADER",
166	"CC_RECEIVE_DATA_INVAL_NLINE",
167	"CC_RECEIVE_DATA_UPDT_HEADER",
168	"CC_RECEIVE_DATA_UPDT_NLINE",
169	"CC_RECEIVE_DATA_UPDT_DATA",
170	};
171
172	const char *cc_send_fsm_state_str[] = {
173	"CC_SEND_IDLE",
174	"CC_SEND_CLEANUP_1",
175	"CC_SEND_CLEANUP_2",
176	"CC_SEND_MULTI_ACK",
177	};
178	}
179
180	#define tmpl(...) \
181	template<typename vci_param, \
182	size_t dspin_in_width, \
183	size_t dspin_out_width, \
184	typename iss_t> __VA_ARGS__ \
185	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
186
187	using namespace soclib::common;
188
189	/////////////////////////////////
190	tmpl(/**/)::VciCcVCacheWrapper(
191	sc_module_name name,
192	const int proc_id,
193	const MappingTable &mtd,
194	const IntTab &srcid,
195	const size_t cc_global_id,
196	const size_t itlb_ways,
197	const size_t itlb_sets,
198	const size_t dtlb_ways,
199	const size_t dtlb_sets,
200	const size_t icache_ways,
201	const size_t icache_sets,
202	const size_t icache_words,
203	const size_t dcache_ways,
204	const size_t dcache_sets,
205	const size_t dcache_words,
206	const size_t wbuf_nlines,
207	const size_t wbuf_nwords,
208	const size_t x_width,
209	const size_t y_width,
210	const uint32_t max_frozen_cycles,
211	const uint32_t debug_start_cycle,
212	const bool debug_ok )
213	: soclib::caba::BaseModule(name),
214
215	p_clk("p_clk"),
216	p_resetn("p_resetn"),
217	p_vci("p_vci"),
218	p_dspin_m2p("p_dspin_m2p"),
219	p_dspin_p2m("p_dspin_p2m"),
220	p_dspin_clack("p_dspin_clack"),
221
222	m_cacheability_table( mtd.getCacheabilityTable() ),
223	m_srcid( mtd.indexForId(srcid) ),
224	m_cc_global_id( cc_global_id ),
225	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
226	m_itlb_ways( itlb_ways ),
227	m_itlb_sets( itlb_sets ),
228	m_dtlb_ways( dtlb_ways ),
229	m_dtlb_sets( dtlb_sets ),
230	m_icache_ways( icache_ways ),
231	m_icache_sets( icache_sets ),
232	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
233	m_icache_words( icache_words ),
234	m_dcache_ways( dcache_ways ),
235	m_dcache_sets( dcache_sets ),
236	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
237	m_dcache_words( dcache_words ),
238	m_x_width( x_width ),
239	m_y_width( y_width ),
240	m_proc_id( proc_id ),
241	m_max_frozen_cycles( max_frozen_cycles ),
242	m_paddr_nbits( vci_param::N ),
243	m_debug_start_cycle( debug_start_cycle ),
244	m_debug_ok( debug_ok ),
245
246	r_mmu_ptpr("r_mmu_ptpr"),
247	r_mmu_mode("r_mmu_mode"),
248	r_mmu_word_lo("r_mmu_word_lo"),
249	r_mmu_word_hi("r_mmu_word_hi"),
250	r_mmu_ibvar("r_mmu_ibvar"),
251	r_mmu_dbvar("r_mmu_dbvar"),
252	r_mmu_ietr("r_mmu_ietr"),
253	r_mmu_detr("r_mmu_detr"),
254
255	r_icache_fsm("r_icache_fsm"),
256	r_icache_fsm_save("r_icache_fsm_save"),
257	r_icache_vci_paddr("r_icache_vci_paddr"),
258	r_icache_vaddr_save("r_icache_vaddr_save"),
259
260	r_icache_miss_way("r_icache_miss_way"),
261	r_icache_miss_set("r_icache_miss_set"),
262	r_icache_miss_word("r_icache_miss_word"),
263	r_icache_miss_inval("r_icache_miss_inval"),
264	r_icache_miss_clack("r_icache_miss_clack"),
265
266	r_icache_cc_way("r_icache_cc_way"),
267	r_icache_cc_set("r_icache_cc_set"),
268	r_icache_cc_word("r_icache_cc_word"),
269	r_icache_cc_need_write("r_icache_cc_need_write"),
270
271	r_icache_flush_count("r_icache_flush_count"),
272
273	r_icache_miss_req("r_icache_miss_req"),
274	r_icache_unc_req("r_icache_unc_req"),
275
276	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
277	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
278
279	r_icache_cc_send_req("r_icache_cc_send_req"),
280	r_icache_cc_send_type("r_icache_cc_send_type"),
281	r_icache_cc_send_nline("r_icache_cc_send_nline"),
282	r_icache_cc_send_way("r_icache_cc_send_way"),
283	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
284
285	r_dcache_fsm("r_dcache_fsm"),
286	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
287	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
288
289	r_dcache_wbuf_req("r_dcache_wbuf_req"),
290	r_dcache_updt_req("r_dcache_updt_req"),
291	r_dcache_save_vaddr("r_dcache_save_vaddr"),
292	r_dcache_save_wdata("r_dcache_save_wdata"),
293	r_dcache_save_be("r_dcache_save_be"),
294	r_dcache_save_paddr("r_dcache_save_paddr"),
295	r_dcache_save_cacheable("r_dcache_save_cacheable"),
296	r_dcache_save_cache_way("r_dcache_save_cache_way"),
297	r_dcache_save_cache_set("r_dcache_save_cache_set"),
298	r_dcache_save_cache_word("r_dcache_save_cache_word"),
299
300	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
301	r_dcache_dirty_way("r_dcache_dirty_way"),
302	r_dcache_dirty_set("r_dcache_dirty_set"),
303
304	r_dcache_vci_paddr("r_dcache_vci_paddr"),
305	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
306	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
307	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
308	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
309	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
310	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
311	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
312	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
313	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
314
315	r_dcache_xtn_way("r_dcache_xtn_way"),
316	r_dcache_xtn_set("r_dcache_xtn_set"),
317
318	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
319
320	r_dcache_miss_type("r_dcache_miss_type"),
321	r_dcache_miss_word("r_dcache_miss_word"),
322	r_dcache_miss_way("r_dcache_miss_way"),
323	r_dcache_miss_set("r_dcache_miss_set"),
324	r_dcache_miss_inval("r_dcache_miss_inval"),
325
326	r_dcache_cc_way("r_dcache_cc_way"),
327	r_dcache_cc_set("r_dcache_cc_set"),
328	r_dcache_cc_word("r_dcache_cc_word"),
329	r_dcache_cc_need_write("r_dcache_cc_need_write"),
330
331	r_dcache_flush_count("r_dcache_flush_count"),
332
333	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
334
335	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
336	r_dcache_tlb_ins("r_dcache_tlb_ins"),
337	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
338	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
339	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
340	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
341	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
342	r_dcache_tlb_way("r_dcache_tlb_way"),
343	r_dcache_tlb_set("r_dcache_tlb_set"),
344
345	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
346	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
347
348	r_dcache_xtn_req("r_dcache_xtn_req"),
349	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
350
351	r_dcache_cc_send_req("r_dcache_cc_send_req"),
352	r_dcache_cc_send_type("r_dcache_cc_send_type"),
353	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
354	r_dcache_cc_send_way("r_dcache_cc_send_way"),
355	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
356
357	r_vci_cmd_fsm("r_vci_cmd_fsm"),
358	r_vci_cmd_min("r_vci_cmd_min"),
359	r_vci_cmd_max("r_vci_cmd_max"),
360	r_vci_cmd_cpt("r_vci_cmd_cpt"),
361	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
362
363	r_vci_rsp_fsm("r_vci_rsp_fsm"),
364	r_vci_rsp_cpt("r_vci_rsp_cpt"),
365	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
366	r_vci_rsp_data_error("r_vci_rsp_data_error"),
367	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
368	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
369
370	r_cc_send_fsm("r_cc_send_fsm"),
371	r_cc_send_last_client("r_cc_send_last_client"),
372
373	r_cc_receive_fsm("r_cc_receive_fsm"),
374	r_cc_receive_data_ins("r_cc_receive_data_ins"),
375	r_cc_receive_word_idx("r_cc_receive_word_idx"),
376	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
377	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
378	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
379
380	r_cc_receive_icache_req("r_cc_receive_icache_req"),
381	r_cc_receive_icache_type("r_cc_receive_icache_type"),
382	r_cc_receive_icache_way("r_cc_receive_icache_way"),
383	r_cc_receive_icache_set("r_cc_receive_icache_set"),
384	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
385	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
386
387	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
388	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
389	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
390	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
391	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
392	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
393
394	r_iss(this->name(), proc_id),
395	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
396	r_icache("icache", icache_ways, icache_sets, icache_words),
397	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
398	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
399	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
400	{
401	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
402
403	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
404	"Need more PLEN bits.");
405
406	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
407	"Need more TRDID bits.");
408
409	assert( (icache_words == dcache_words) and
410	"icache_words and dcache_words parameters must be equal");
411
412	assert( (itlb_sets == dtlb_sets) and
413	"itlb_sets and dtlb_sets parameters must be etqual");
414
415	assert( (itlb_ways == dtlb_ways) and
416	"itlb_ways and dtlb_ways parameters must be etqual");
417
418	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
419	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
420	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
421	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
422	(uint32_log2(m_icache_words<<2));
423
424	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
425
426	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
427	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
428
429	SC_METHOD(transition);
430	dont_initialize();
431	sensitive << p_clk.pos();
432
433	SC_METHOD(genMoore);
434	dont_initialize();
435	sensitive << p_clk.neg();
436
437	typename iss_t::CacheInfo cache_info;
438	cache_info.has_mmu = true;
439	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
440	cache_info.icache_assoc = icache_ways;
441	cache_info.icache_n_lines = icache_sets;
442	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
443	cache_info.dcache_assoc = dcache_ways;
444	cache_info.dcache_n_lines = dcache_sets;
445	r_iss.setCacheInfo(cache_info);
446	}
447
448	/////////////////////////////////////
449	tmpl(/**/)::~VciCcVCacheWrapper()
450	/////////////////////////////////////
451	{
452	delete [] r_dcache_in_tlb;
453	delete [] r_dcache_contains_ptd;
454	}
455
456	////////////////////////
457	tmpl(void)::print_cpi()
458	////////////////////////
459	{
460	std::cout << name() << " CPI = "
461	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
462	}
463
464	////////////////////////////////////
465	tmpl(void)::print_trace(size_t mode)
466	////////////////////////////////////
467	{
468	// b0 : write buffer trace
469	// b1 : write buffer verbose
470	// b2 : dcache trace
471	// b3 : icache trace
472	// b4 : dtlb trace
473	// b5 : itlb trace
474
475	std::cout << std::dec << "PROC " << name() << std::endl;
476
477	std::cout << " " << m_ireq << std::endl;
478	std::cout << " " << m_irsp << std::endl;
479	std::cout << " " << m_dreq << std::endl;
480	std::cout << " " << m_drsp << std::endl;
481
482	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
483	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
484	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
485	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
486	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
487	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
488	<< " \| MMU = " << r_mmu_mode.read();
489	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
490	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
491	std::cout << std::endl;
492
493	if(mode & 0x01)
494	{
495	r_wbuf.printTrace((mode>>1)&1);
496	}
497	if(mode & 0x04)
498	{
499	std::cout << " Data Cache" << std::endl;
500	r_dcache.printTrace();
501	}
502	if(mode & 0x08)
503	{
504	std::cout << " Instruction Cache" << std::endl;
505	r_icache.printTrace();
506	}
507	if(mode & 0x10)
508	{
509	std::cout << " Data TLB" << std::endl;
510	r_dtlb.printTrace();
511	}
512	if(mode & 0x20)
513	{
514	std::cout << " Instruction TLB" << std::endl;
515	r_itlb.printTrace();
516	}
517	}
518
519	//////////////////////////////////////////
520	tmpl(void)::cache_monitor( paddr_t addr )
521	//////////////////////////////////////////
522	{
523	bool cache_hit;
524	size_t cache_way = 0;
525	size_t cache_set = 0;
526	size_t cache_word = 0;
527	uint32_t cache_rdata = 0;
528
529	cache_hit = r_dcache.read_neutral( addr,
530	&cache_rdata,
531	&cache_way,
532	&cache_set,
533	&cache_word );
534
535	if ( cache_hit != m_debug_previous_d_hit )
536	{
537	std::cout << "Monitor PROC " << name()
538	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
539	<< " / HIT = " << cache_hit
540	<< " / PADDR = " << std::hex << addr
541	<< " / DATA = " << cache_rdata
542	<< " / WAY = " << cache_way << std::endl;
543	m_debug_previous_d_hit = cache_hit;
544	}
545
546	cache_hit = r_icache.read_neutral( addr,
547	&cache_rdata,
548	&cache_way,
549	&cache_set,
550	&cache_word );
551
552	if ( cache_hit != m_debug_previous_i_hit )
553	{
554	std::cout << "Monitor PROC " << name()
555	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
556	<< " / HIT = " << cache_hit
557	<< " / PADDR = " << std::hex << addr
558	<< " / DATA = " << cache_rdata
559	<< " / WAY = " << cache_way << std::endl;
560	m_debug_previous_i_hit = cache_hit;
561	}
562	}
563
564	/*
565	////////////////////////
566	tmpl(void)::print_stats()
567	////////////////////////
568	{
569	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
570	std::cout << name() << std::endl
571	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
572	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
573	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
574	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
575	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
576	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
577	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
578	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
579	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
580	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
581	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
582	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
583	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
584	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
585	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
586	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
587	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
588	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
589	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
590	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
591	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
592	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
593	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
594	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
595	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
596	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
597	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
598	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
599	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
600	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
601	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
602	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
603	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
604	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
605	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
606	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
607	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
608	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
609	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
610	}
611
612	////////////////////////
613	tmpl(void)::clear_stats()
614	////////////////////////
615	{
616	m_cpt_dcache_data_read = 0;
617	m_cpt_dcache_data_write = 0;
618	m_cpt_dcache_dir_read = 0;
619	m_cpt_dcache_dir_write = 0;
620	m_cpt_icache_data_read = 0;
621	m_cpt_icache_data_write = 0;
622	m_cpt_icache_dir_read = 0;
623	m_cpt_icache_dir_write = 0;
624
625	m_cpt_frz_cycles = 0;
626	m_cpt_dcache_frz_cycles = 0;
627	m_cpt_total_cycles = 0;
628
629	m_cpt_read = 0;
630	m_cpt_write = 0;
631	m_cpt_data_miss = 0;
632	m_cpt_ins_miss = 0;
633	m_cpt_unc_read = 0;
634	m_cpt_write_cached = 0;
635	m_cpt_ins_read = 0;
636
637	m_cost_write_frz = 0;
638	m_cost_data_miss_frz = 0;
639	m_cost_unc_read_frz = 0;
640	m_cost_ins_miss_frz = 0;
641
642	m_cpt_imiss_transaction = 0;
643	m_cpt_dmiss_transaction = 0;
644	m_cpt_unc_transaction = 0;
645	m_cpt_write_transaction = 0;
646	m_cpt_icache_unc_transaction = 0;
647
648	m_cost_imiss_transaction = 0;
649	m_cost_dmiss_transaction = 0;
650	m_cost_unc_transaction = 0;
651	m_cost_write_transaction = 0;
652	m_cost_icache_unc_transaction = 0;
653	m_length_write_transaction = 0;
654
655	m_cpt_ins_tlb_read = 0;
656	m_cpt_ins_tlb_miss = 0;
657	m_cpt_ins_tlb_update_acc = 0;
658
659	m_cpt_data_tlb_read = 0;
660	m_cpt_data_tlb_miss = 0;
661	m_cpt_data_tlb_update_acc = 0;
662	m_cpt_data_tlb_update_dirty = 0;
663	m_cpt_ins_tlb_hit_dcache = 0;
664	m_cpt_data_tlb_hit_dcache = 0;
665	m_cpt_ins_tlb_occup_cache = 0;
666	m_cpt_data_tlb_occup_cache = 0;
667
668	m_cost_ins_tlb_miss_frz = 0;
669	m_cost_data_tlb_miss_frz = 0;
670	m_cost_ins_tlb_update_acc_frz = 0;
671	m_cost_data_tlb_update_acc_frz = 0;
672	m_cost_data_tlb_update_dirty_frz = 0;
673	m_cost_ins_tlb_occup_cache_frz = 0;
674	m_cost_data_tlb_occup_cache_frz = 0;
675
676	m_cpt_itlbmiss_transaction = 0;
677	m_cpt_itlb_ll_transaction = 0;
678	m_cpt_itlb_sc_transaction = 0;
679	m_cpt_dtlbmiss_transaction = 0;
680	m_cpt_dtlb_ll_transaction = 0;
681	m_cpt_dtlb_sc_transaction = 0;
682	m_cpt_dtlb_ll_dirty_transaction = 0;
683	m_cpt_dtlb_sc_dirty_transaction = 0;
684
685	m_cost_itlbmiss_transaction = 0;
686	m_cost_itlb_ll_transaction = 0;
687	m_cost_itlb_sc_transaction = 0;
688	m_cost_dtlbmiss_transaction = 0;
689	m_cost_dtlb_ll_transaction = 0;
690	m_cost_dtlb_sc_transaction = 0;
691	m_cost_dtlb_ll_dirty_transaction = 0;
692	m_cost_dtlb_sc_dirty_transaction = 0;
693
694	m_cpt_cc_update_data = 0;
695	m_cpt_cc_inval_ins = 0;
696	m_cpt_cc_inval_data = 0;
697	m_cpt_cc_broadcast = 0;
698
699	m_cost_updt_data_frz = 0;
700	m_cost_inval_ins_frz = 0;
701	m_cost_inval_data_frz = 0;
702	m_cost_broadcast_frz = 0;
703
704	m_cpt_cc_cleanup_data = 0;
705	m_cpt_cc_cleanup_ins = 0;
706	}
707
708	*/
709
710	/////////////////////////
711	tmpl(void)::transition()
712	/////////////////////////
713	{
714	if ( not p_resetn.read() )
715	{
716	r_iss.reset();
717	r_wbuf.reset();
718	r_icache.reset();
719	r_dcache.reset();
720	r_itlb.reset();
721	r_dtlb.reset();
722
723	r_dcache_fsm = DCACHE_IDLE;
724	r_icache_fsm = ICACHE_IDLE;
725	r_vci_cmd_fsm = CMD_IDLE;
726	r_vci_rsp_fsm = RSP_IDLE;
727	r_cc_receive_fsm = CC_RECEIVE_IDLE;
728	r_cc_send_fsm = CC_SEND_IDLE;
729
730	// reset data physical address extension
731	r_dcache_paddr_ext = 0;
732
733	// reset dcache directory extension
734	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
735	{
736	r_dcache_in_tlb[i] = false;
737	r_dcache_contains_ptd[i] = false;
738	}
739
740	// Response FIFOs and cleanup buffer
741	r_vci_rsp_fifo_icache.init();
742	r_vci_rsp_fifo_dcache.init();
743
744	// ICACHE & DCACHE activated
745	// ITLB & DTLB desactivated
746	r_mmu_mode = 0x3;
747
748	// No request from ICACHE FSM to CMD FSM
749	r_icache_miss_req = false;
750	r_icache_unc_req = false;
751
752	// No request from ICACHE_FSM to DCACHE FSM
753	r_icache_tlb_miss_req = false;
754
755	// No request from ICACHE_FSM to CC_SEND FSM
756	r_icache_cc_send_req = false;
757
758	r_icache_clack_req = false;
759
760	// No pending write in pipeline
761	r_dcache_wbuf_req = false;
762	r_dcache_updt_req = false;
763
764	// No request from DCACHE_FSM to CMD_FSM
765	r_dcache_vci_miss_req = false;
766	r_dcache_vci_unc_req = false;
767	r_dcache_vci_cas_req = false;
768	r_dcache_vci_ll_req = false;
769	r_dcache_vci_sc_req = false;
770
771	// No uncacheable write pending
772	r_dcache_pending_unc_write = false;
773
774	// No processor XTN request pending
775	r_dcache_xtn_req = false;
776
777	// No request from DCACHE FSM to CC_SEND FSM
778	r_dcache_cc_send_req = false;
779
780	r_dcache_clack_req = false;
781
782	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
783	r_cc_receive_icache_req = false;
784	r_cc_receive_dcache_req = false;
785
786	// last cc_send client was dcache
787	r_cc_send_last_client = false;
788
789	// No pending cleanup after a replacement
790	r_icache_miss_clack = false;
791	r_dcache_miss_clack = false;
792
793	// No signalisation of a coherence request matching a pending miss
794	r_icache_miss_inval = false;
795	r_dcache_miss_inval = false;
796
797	r_dspin_clack_req = false;
798
799	// No signalisation of errors
800	r_vci_rsp_ins_error = false;
801	r_vci_rsp_data_error = false;
802
803	// Debug variables
804	m_debug_previous_i_hit = false;
805	m_debug_previous_d_hit = false;
806	m_debug_activated = false;
807
808	// activity counters
809	m_cpt_dcache_data_read = 0;
810	m_cpt_dcache_data_write = 0;
811	m_cpt_dcache_dir_read = 0;
812	m_cpt_dcache_dir_write = 0;
813	m_cpt_icache_data_read = 0;
814	m_cpt_icache_data_write = 0;
815	m_cpt_icache_dir_read = 0;
816	m_cpt_icache_dir_write = 0;
817
818	m_cpt_frz_cycles = 0;
819	m_cpt_total_cycles = 0;
820	m_cpt_stop_simulation = 0;
821
822	m_cpt_data_miss = 0;
823	m_cpt_ins_miss = 0;
824	m_cpt_unc_read = 0;
825	m_cpt_write_cached = 0;
826	m_cpt_ins_read = 0;
827
828	m_cost_write_frz = 0;
829	m_cost_data_miss_frz = 0;
830	m_cost_unc_read_frz = 0;
831	m_cost_ins_miss_frz = 0;
832
833	m_cpt_imiss_transaction = 0;
834	m_cpt_dmiss_transaction = 0;
835	m_cpt_unc_transaction = 0;
836	m_cpt_write_transaction = 0;
837	m_cpt_icache_unc_transaction = 0;
838
839	m_cost_imiss_transaction = 0;
840	m_cost_dmiss_transaction = 0;
841	m_cost_unc_transaction = 0;
842	m_cost_write_transaction = 0;
843	m_cost_icache_unc_transaction = 0;
844	m_length_write_transaction = 0;
845
846	m_cpt_ins_tlb_read = 0;
847	m_cpt_ins_tlb_miss = 0;
848	m_cpt_ins_tlb_update_acc = 0;
849
850	m_cpt_data_tlb_read = 0;
851	m_cpt_data_tlb_miss = 0;
852	m_cpt_data_tlb_update_acc = 0;
853	m_cpt_data_tlb_update_dirty = 0;
854	m_cpt_ins_tlb_hit_dcache = 0;
855	m_cpt_data_tlb_hit_dcache = 0;
856	m_cpt_ins_tlb_occup_cache = 0;
857	m_cpt_data_tlb_occup_cache = 0;
858
859	m_cost_ins_tlb_miss_frz = 0;
860	m_cost_data_tlb_miss_frz = 0;
861	m_cost_ins_tlb_update_acc_frz = 0;
862	m_cost_data_tlb_update_acc_frz = 0;
863	m_cost_data_tlb_update_dirty_frz = 0;
864	m_cost_ins_tlb_occup_cache_frz = 0;
865	m_cost_data_tlb_occup_cache_frz = 0;
866
867	m_cpt_ins_tlb_inval = 0;
868	m_cpt_data_tlb_inval = 0;
869	m_cost_ins_tlb_inval_frz = 0;
870	m_cost_data_tlb_inval_frz = 0;
871
872	m_cpt_cc_broadcast = 0;
873
874	m_cost_updt_data_frz = 0;
875	m_cost_inval_ins_frz = 0;
876	m_cost_inval_data_frz = 0;
877	m_cost_broadcast_frz = 0;
878
879	m_cpt_cc_cleanup_data = 0;
880	m_cpt_cc_cleanup_ins = 0;
881
882	m_cpt_itlbmiss_transaction = 0;
883	m_cpt_itlb_ll_transaction = 0;
884	m_cpt_itlb_sc_transaction = 0;
885	m_cpt_dtlbmiss_transaction = 0;
886	m_cpt_dtlb_ll_transaction = 0;
887	m_cpt_dtlb_sc_transaction = 0;
888	m_cpt_dtlb_ll_dirty_transaction = 0;
889	m_cpt_dtlb_sc_dirty_transaction = 0;
890
891	m_cost_itlbmiss_transaction = 0;
892	m_cost_itlb_ll_transaction = 0;
893	m_cost_itlb_sc_transaction = 0;
894	m_cost_dtlbmiss_transaction = 0;
895	m_cost_dtlb_ll_transaction = 0;
896	m_cost_dtlb_sc_transaction = 0;
897	m_cost_dtlb_ll_dirty_transaction = 0;
898	m_cost_dtlb_sc_dirty_transaction = 0;
899	/*
900	m_cpt_dcache_frz_cycles = 0;
901	m_cpt_read = 0;
902	m_cpt_write = 0;
903	m_cpt_cc_update_data = 0;
904	m_cpt_cc_inval_ins = 0;
905	m_cpt_cc_inval_data = 0;
906	*/
907
908	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
909	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
910	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
911	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
912
913	// init the llsc reservation buffer
914	r_dcache_llsc_valid = false;
915	m_monitor_ok = false;
916
917	return;
918	}
919
920	// Response FIFOs default values
921	bool vci_rsp_fifo_icache_get = false;
922	bool vci_rsp_fifo_icache_put = false;
923	uint32_t vci_rsp_fifo_icache_data = 0;
924
925	bool vci_rsp_fifo_dcache_get = false;
926	bool vci_rsp_fifo_dcache_put = false;
927	uint32_t vci_rsp_fifo_dcache_data = 0;
928
929	// updt fifo
930	bool cc_receive_updt_fifo_get = false;
931	bool cc_receive_updt_fifo_put = false;
932	uint32_t cc_receive_updt_fifo_be = 0;
933	uint32_t cc_receive_updt_fifo_data = 0;
934	bool cc_receive_updt_fifo_eop = false;
935
936	#ifdef INSTRUMENTATION
937	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
938	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
939	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
940	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
941	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
942	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
943	#endif
944
945	m_cpt_total_cycles++;
946
947	m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
948
949	/////////////////////////////////////////////////////////////////////
950	// Get data and instruction requests from processor
951	///////////////////////////////////////////////////////////////////////
952
953	r_iss.getRequests(m_ireq, m_dreq);
954
955	////////////////////////////////////////////////////////////////////////////////////
956	// ICACHE_FSM
957	//
958	// 1/ Coherence operations
959	// They are handled as interrupts generated by the CC_RECEIVE FSM.
960	// - There is a coherence request when r_tgt_icache_req is set.
961	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
962	// - There is a cleanup ack request when r_cleanup_icache_req is set.
963	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
964	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
965	// - For both types of requests, actions associated to the pre-empted state
966	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
967	// or CC_CLACK) to execute the requested coherence operation, and returns
968	// to the pre-empted state.
969	//
970	// 2/ Processor requests
971	// They are taken in IDLE state only. In case of cache miss, or uncacheable
972	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
973	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
974	// flip-flops are reset when the transaction starts.
975	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
976	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
977	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
978	// The availability of the missing cache line is signaled by the response fifo,
979	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
980	// and ICACHE_MISS_DIR_UPDT states.
981	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
982	// to wait the response from the RSP FSM, through the response fifo.
983	// The missing instruction is directly returned to processor in this state.
984	//
985	// 3/ TLB miss
986	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
987	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
988	// register, and goes to the ICACHE_TLB_WAIT state.
989	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
990	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
991	// to signal the completion.
992	//
993	// 4/ XTN requests
994	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
995	// using the r_dcache_xtn_req flip-flop.
996	// The request opcode and the address to be invalidated are transmitted
997	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
998	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
999	// is completed.
1000	//
1001	// 5/ Error Handling
1002	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1003	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1004	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1005	////////////////////////////////////////////////////////////////////////////////////////
1006
1007	// default value for m_irsp
1008	m_irsp.valid = false;
1009	m_irsp.error = false;
1010	m_irsp.instruction = 0;
1011
1012	switch( r_icache_fsm.read() )
1013	{
1014	/////////////////
1015	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1016	// and coherence requests with a fixed priority:
1017	// 1/ Coherence requests => ICACHE_CC_CHECK
1018	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1019	// 3/ tlb miss => ICACHE_TLB_WAIT
1020	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1021	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1022	{
1023	// coherence clack interrupt
1024	if ( r_icache_clack_req.read() )
1025	{
1026	r_icache_fsm = ICACHE_CC_CHECK;
1027	r_icache_fsm_save = r_icache_fsm.read();
1028	break;
1029	}
1030
1031	// coherence interrupt
1032	if ( r_cc_receive_icache_req.read() )
1033	{
1034	r_icache_fsm = ICACHE_CC_CHECK;
1035	r_icache_fsm_save = r_icache_fsm.read();
1036	break;
1037	}
1038
1039	// XTN requests sent by DCACHE FSM
1040	// These request are not executed in this IDLE state, because
1041	// they require access to icache or itlb, that are already accessed
1042	if ( r_dcache_xtn_req.read() )
1043	{
1044	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1045	{
1046	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1047	}
1048	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1049	{
1050	r_icache_flush_count = 0;
1051	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1052	}
1053	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1054	{
1055	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1056	}
1057	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1058	{
1059	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1060	}
1061	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1062	{
1063	if (sizeof(paddr_t) <= 32)
1064	{
1065	assert(r_mmu_word_hi.read() == 0 &&
1066	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1067	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1068	}
1069	else
1070	{
1071	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1072	(paddr_t)r_mmu_word_lo.read();
1073	}
1074	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1075	}
1076	else
1077	{
1078	assert( false and
1079	"undefined XTN request received by ICACHE FSM");
1080	}
1081	break;
1082	} // end if xtn_req
1083
1084	// processor request
1085	if ( m_ireq.valid )
1086	{
1087	bool cacheable;
1088	paddr_t paddr;
1089	bool tlb_hit = false;
1090	pte_info_t tlb_flags;
1091	size_t tlb_way;
1092	size_t tlb_set;
1093	paddr_t tlb_nline;
1094	uint32_t cache_inst = 0;
1095	size_t cache_way;
1096	size_t cache_set;
1097	size_t cache_word;
1098	int cache_state = CACHE_SLOT_STATE_EMPTY;
1099
1100	// We register processor request
1101	r_icache_vaddr_save = m_ireq.addr;
1102
1103	// sytematic itlb access (if activated)
1104	if ( r_mmu_mode.read() & INS_TLB_MASK )
1105	{
1106
1107	#ifdef INSTRUMENTATION
1108	m_cpt_itlb_read++;
1109	#endif
1110	tlb_hit = r_itlb.translate( m_ireq.addr,
1111	&paddr,
1112	&tlb_flags,
1113	&tlb_nline, // unused
1114	&tlb_way, // unused
1115	&tlb_set ); // unused
1116	}
1117	else
1118	{
1119	paddr = (paddr_t)m_ireq.addr;
1120	}
1121
1122	// systematic icache access (if activated)
1123	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1124	{
1125
1126
1127	#ifdef INSTRUMENTATION
1128	m_cpt_icache_data_read++;
1129	m_cpt_icache_dir_read++;
1130	#endif
1131	r_icache.read( paddr,
1132	&cache_inst,
1133	&cache_way,
1134	&cache_set,
1135	&cache_word,
1136	&cache_state );
1137	}
1138
1139	// We compute cacheability and check access rights:
1140	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1141	// and the access rights are defined by the U and X bits in the PTE.
1142	// - If MMU not activated : cacheability is defined by the segment table,
1143	// and there is no access rights checking
1144
1145	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1146	{
1147	// cacheability
1148	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1149	else cacheable = m_cacheability_table[m_ireq.addr];
1150	}
1151	else // itlb activated
1152	{
1153	if ( tlb_hit ) // ITLB hit
1154	{
1155	// cacheability
1156	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1157	else cacheable = tlb_flags.c;
1158
1159	// access rights checking
1160	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1161	{
1162	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1163	r_mmu_ibvar = m_ireq.addr;
1164	m_irsp.valid = true;
1165	m_irsp.error = true;
1166	m_irsp.instruction = 0;
1167	break;
1168	}
1169	else if ( not tlb_flags.x )
1170	{
1171	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1172	r_mmu_ibvar = m_ireq.addr;
1173	m_irsp.valid = true;
1174	m_irsp.error = true;
1175	m_irsp.instruction = 0;
1176	break;
1177	}
1178	}
1179	else // ITLB miss
1180	{
1181
1182	#ifdef INSTRUMENTATION
1183	m_cpt_itlb_miss++;
1184	#endif
1185	r_icache_fsm = ICACHE_TLB_WAIT;
1186	r_icache_tlb_miss_req = true;
1187	break;
1188	}
1189	} // end if itlb activated
1190
1191	// physical address registration
1192	r_icache_vci_paddr = paddr;
1193
1194	// Finally, we send the response to processor, and compute next state
1195	if ( cacheable )
1196	{
1197	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1198	{
1199
1200	#ifdef INSTRUMENTATION
1201	m_cpt_icache_miss++;
1202	#endif
1203	// we request a VCI transaction
1204	r_icache_fsm = ICACHE_MISS_SELECT;
1205	#if DEBUG_ICACHE
1206	if ( m_debug_activated )
1207	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1208	<< " : PADDR = " << std::hex << paddr << std::endl;
1209	#endif
1210	r_icache_miss_req = true;
1211	}
1212	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1213	{
1214	// stalled until cleanup is acknowledged
1215	r_icache_fsm = ICACHE_IDLE;
1216	}
1217	else // cache hit
1218	{
1219
1220	#ifdef INSTRUMENTATION
1221	m_cpt_ins_read++;
1222	#endif
1223	// return instruction to processor
1224	m_irsp.valid = true;
1225	m_irsp.instruction = cache_inst;
1226	r_icache_fsm = ICACHE_IDLE;
1227	#if DEBUG_ICACHE
1228	if ( m_debug_activated )
1229	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1230	<< " : PADDR = " << std::hex << paddr << std::endl;
1231	#endif
1232	}
1233	}
1234	else // non cacheable read
1235	{
1236	r_icache_unc_req = true;
1237	r_icache_fsm = ICACHE_UNC_WAIT;
1238
1239	#if DEBUG_ICACHE
1240	if ( m_debug_activated )
1241	{
1242	std::cout << " <PROC " << name()
1243	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1244	<< " : PADDR = " << std::hex << paddr << std::endl;
1245	}
1246	#endif
1247	}
1248	} // end if m_ireq.valid
1249	break;
1250	}
1251	/////////////////////
1252	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1253	// the itlb is udated by the DCACHE FSM, as well as the
1254	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1255	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1256	// reset the r_icache_tlb_miss_req flip-flop
1257	// external coherence request are accepted in this state.
1258	{
1259	// coherence clack interrupt
1260	if ( r_icache_clack_req.read() )
1261	{
1262	r_icache_fsm = ICACHE_CC_CHECK;
1263	r_icache_fsm_save = r_icache_fsm.read();
1264	break;
1265	}
1266
1267	// coherence interrupt
1268	if ( r_cc_receive_icache_req.read() )
1269	{
1270	r_icache_fsm = ICACHE_CC_CHECK;
1271	r_icache_fsm_save = r_icache_fsm.read();
1272	break;
1273	}
1274
1275	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1276
1277	// DCACHE FSM signals response by reseting the request flip-flop
1278	if ( not r_icache_tlb_miss_req.read() )
1279	{
1280	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1281	{
1282	r_icache_tlb_rsp_error = false;
1283	m_irsp.error = true;
1284	m_irsp.valid = true;
1285	r_icache_fsm = ICACHE_IDLE;
1286	}
1287	else // tlb updated : return to IDLE state
1288	{
1289	r_icache_fsm = ICACHE_IDLE;
1290	}
1291	}
1292	break;
1293	}
1294	//////////////////////////
1295	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1296	{
1297	r_itlb.flush();
1298	r_dcache_xtn_req = false;
1299	r_icache_fsm = ICACHE_IDLE;
1300	break;
1301	}
1302	////////////////////////////
1303	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1304	// r_icache_flush_count as a slot counter,
1305	// looping in this state until all slots are visited.
1306	// It can require two cycles per slot:
1307	// We test here the slot state, and make the actual inval
1308	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1309	// A cleanup request is generated for each valid line
1310	{
1311	// coherence clack interrupt
1312	if ( r_icache_clack_req.read() )
1313	{
1314	r_icache_fsm = ICACHE_CC_CHECK;
1315	r_icache_fsm_save = r_icache_fsm.read();
1316	break;
1317	}
1318
1319	// coherence request (from CC_RECEIVE FSM)
1320	if ( r_cc_receive_icache_req.read() )
1321	{
1322	r_icache_fsm = ICACHE_CC_CHECK;
1323	r_icache_fsm_save = r_icache_fsm.read();
1324	break;
1325	}
1326
1327	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1328	{
1329	int state;
1330	paddr_t tag;
1331	size_t way = r_icache_flush_count.read()/m_icache_sets;
1332	size_t set = r_icache_flush_count.read()%m_icache_sets;
1333
1334	#ifdef INSTRUMENTATION
1335	m_cpt_icache_dir_read++;
1336	#endif
1337	r_icache.read_dir( way,
1338	set,
1339	&tag,
1340	&state );
1341
1342	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1343	{
1344	// request cleanup
1345	r_icache_cc_send_req = true;
1346	r_icache_cc_send_nline = tag * m_icache_sets + set;
1347	r_icache_cc_send_way = way;
1348	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1349
1350	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1351	r_icache_miss_way = way;
1352	r_icache_miss_set = set;
1353	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1354	}
1355	else if ( r_icache_flush_count.read() ==
1356	(m_icache_sets*m_icache_ways - 1) ) // last slot
1357	{
1358	r_dcache_xtn_req = false;
1359	m_drsp.valid = true;
1360	r_icache_fsm = ICACHE_IDLE;
1361	}
1362
1363	// saturation counter, to have the same last slot condition
1364	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1365	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1366	{
1367	r_icache_flush_count = r_icache_flush_count.read() + 1;
1368	}
1369	}
1370	break;
1371	}
1372	///////////////////////////////
1373	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1374	{
1375	size_t way = r_icache_miss_way.read();
1376	size_t set = r_icache_miss_set.read();
1377
1378	#ifdef INSTRUMENTATION
1379	m_cpt_icache_dir_write++;
1380	#endif
1381
1382	r_icache.write_dir( way,
1383	set,
1384	CACHE_SLOT_STATE_ZOMBI );
1385
1386	if ( r_icache_flush_count.read() ==
1387	(m_icache_sets*m_icache_ways - 1) ) // last slot
1388	{
1389	r_dcache_xtn_req = false;
1390	m_drsp.valid = true;
1391	r_icache_fsm = ICACHE_IDLE;
1392	}
1393	else
1394	{
1395	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1396	}
1397	break;
1398	}
1399
1400	//////////////////////////
1401	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1402	// stored in the r_dcache_save_wdata register
1403	{
1404	r_itlb.inval(r_dcache_save_wdata.read());
1405	r_dcache_xtn_req = false;
1406	r_icache_fsm = ICACHE_IDLE;
1407	break;
1408	}
1409	///////////////////////////////
1410	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1411	// requires 3 cycles (in case of hit on itlb and icache).
1412	// In this state, access TLB to translate virtual address
1413	// stored in the r_dcache_save_wdata register.
1414	{
1415	paddr_t paddr;
1416	bool hit;
1417
1418	// read physical address in TLB when MMU activated
1419	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1420	{
1421
1422	#ifdef INSTRUMENTATION
1423	m_cpt_itlb_read++;
1424	#endif
1425	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1426	&paddr);
1427	}
1428	else // itlb not activated
1429	{
1430	paddr = (paddr_t)r_dcache_save_wdata.read();
1431	hit = true;
1432	}
1433
1434	if ( hit ) // continue the selective inval process
1435	{
1436	r_icache_vci_paddr = paddr;
1437	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1438	}
1439	else // miss : send a request to DCACHE FSM
1440	{
1441
1442	#ifdef INSTRUMENTATION
1443	m_cpt_itlb_miss++;
1444	#endif
1445	r_icache_tlb_miss_req = true;
1446	r_icache_vaddr_save = r_dcache_save_wdata.read();
1447	r_icache_fsm = ICACHE_TLB_WAIT;
1448	}
1449	break;
1450	}
1451	///////////////////////////////
1452	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1453	// require 2 cycles. In this state, we read directory
1454	// with address stored in r_icache_vci_paddr register.
1455	{
1456	int state;
1457	size_t way;
1458	size_t set;
1459	size_t word;
1460
1461	#ifdef INSTRUMENTATION
1462	m_cpt_icache_dir_read++;
1463	#endif
1464	r_icache.read_dir(r_icache_vci_paddr.read(),
1465	&state,
1466	&way,
1467	&set,
1468	&word);
1469
1470	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1471	{
1472	r_icache_miss_way = way;
1473	r_icache_miss_set = set;
1474	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1475	}
1476	else // miss : acknowlege the XTN request and return
1477	{
1478	r_dcache_xtn_req = false;
1479	r_icache_fsm = ICACHE_IDLE;
1480	}
1481	break;
1482	}
1483	///////////////////////////////
1484	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1485	{
1486	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1487	{
1488
1489	#ifdef INSTRUMENTATION
1490	m_cpt_icache_dir_write++;
1491	#endif
1492	r_icache.write_dir( r_icache_miss_way.read(),
1493	r_icache_miss_set.read(),
1494	CACHE_SLOT_STATE_ZOMBI );
1495
1496	// request cleanup
1497	r_icache_cc_send_req = true;
1498	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1499	r_icache_cc_send_way = r_icache_miss_way.read();
1500	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1501
1502	// acknowledge the XTN request and return
1503	r_dcache_xtn_req = false;
1504	r_icache_fsm = ICACHE_IDLE;
1505	}
1506	break;
1507	}
1508	////////////////////////
1509	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1510	// if previous cleanup has been sent.
1511	// Waiting in this state if no slot available.
1512	// Set the r_icache_cleanup_req flip-flop
1513	// and the r_icache_miss_clack flip-flop,
1514	// when a cleanup is required
1515	{
1516	if (m_ireq.valid) m_cost_ins_miss_frz++;
1517
1518	// coherence clack interrupt
1519	if ( r_icache_clack_req.read() )
1520	{
1521	r_icache_fsm = ICACHE_CC_CHECK;
1522	r_icache_fsm_save = r_icache_fsm.read();
1523	break;
1524	}
1525
1526	// coherence interrupt
1527	if ( r_cc_receive_icache_req.read() )
1528	{
1529	r_icache_fsm = ICACHE_CC_CHECK;
1530	r_icache_fsm_save = r_icache_fsm.read();
1531	break;
1532	}
1533
1534	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1535	{
1536	bool found;
1537	bool cleanup;
1538	size_t way;
1539	size_t set;
1540	paddr_t victim;
1541
1542	#ifdef INSTRUMENTATION
1543	m_cpt_icache_dir_read++;
1544	#endif
1545	r_icache.read_select(r_icache_vci_paddr.read(),
1546	&victim,
1547	&way,
1548	&set,
1549	&found,
1550	&cleanup );
1551	if ( found )
1552	{
1553	r_icache_miss_way = way;
1554	r_icache_miss_set = set;
1555
1556	if ( cleanup )
1557	{
1558	r_icache_fsm = ICACHE_MISS_CLEAN;
1559	r_icache_miss_clack = true;
1560	// request cleanup
1561	r_icache_cc_send_req = true;
1562	r_icache_cc_send_nline = victim;
1563	r_icache_cc_send_way = way;
1564	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1565	}
1566	else
1567	{
1568	r_icache_fsm = ICACHE_MISS_WAIT;
1569	}
1570
1571	#if DEBUG_ICACHE
1572	if ( m_debug_activated )
1573	{
1574	std::cout << " <PROC " << name()
1575	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1576	<< " / WAY = " << way
1577	<< " / SET = " << set;
1578	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1579	else std::cout << std::endl;
1580	}
1581	#endif
1582	}
1583	}
1584	break;
1585	}
1586	///////////////////////
1587	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1588	{
1589	if (m_ireq.valid) m_cost_ins_miss_frz++;
1590
1591	#ifdef INSTRUMENTATION
1592	m_cpt_icache_dir_write++;
1593	#endif
1594	r_icache.write_dir( r_icache_miss_way.read(),
1595	r_icache_miss_set.read(),
1596	CACHE_SLOT_STATE_ZOMBI);
1597	#if DEBUG_ICACHE
1598	if ( m_debug_activated )
1599	{
1600	std::cout << " <PROC " << name()
1601	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1602	<< " / WAY = " << r_icache_miss_way.read()
1603	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1604	}
1605	#endif
1606
1607	r_icache_fsm = ICACHE_MISS_WAIT;
1608	break;
1609	}
1610	//////////////////////
1611	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1612	{
1613	if (m_ireq.valid) m_cost_ins_miss_frz++;
1614
1615	// coherence clack interrupt
1616	if ( r_icache_clack_req.read() )
1617	{
1618	r_icache_fsm = ICACHE_CC_CHECK;
1619	r_icache_fsm_save = r_icache_fsm.read();
1620	break;
1621	}
1622
1623	// coherence interrupt
1624	if ( r_cc_receive_icache_req.read() )
1625	{
1626	r_icache_fsm = ICACHE_CC_CHECK;
1627	r_icache_fsm_save = r_icache_fsm.read();
1628	break;
1629	}
1630
1631	if ( r_vci_rsp_ins_error.read() ) // bus error
1632	{
1633	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1634	r_mmu_ibvar = r_icache_vaddr_save.read();
1635	m_irsp.valid = true;
1636	m_irsp.error = true;
1637	r_vci_rsp_ins_error = false;
1638	r_icache_fsm = ICACHE_IDLE;
1639	}
1640	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1641	{
1642	r_icache_miss_word = 0;
1643	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1644	}
1645	break;
1646	}
1647	///////////////////////////
1648	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1649	{
1650	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1651
1652	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1653	{
1654
1655	#ifdef INSTRUMENTATION
1656	m_cpt_icache_data_write++;
1657	#endif
1658	r_icache.write( r_icache_miss_way.read(),
1659	r_icache_miss_set.read(),
1660	r_icache_miss_word.read(),
1661	r_vci_rsp_fifo_icache.read() );
1662	#if DEBUG_ICACHE
1663	if ( m_debug_activated )
1664	{
1665	std::cout << " <PROC " << name()
1666	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1667	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1668	<< " WAY = " << r_icache_miss_way.read()
1669	<< " SET = " << r_icache_miss_set.read()
1670	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1671	}
1672	#endif
1673	vci_rsp_fifo_icache_get = true;
1674	r_icache_miss_word = r_icache_miss_word.read() + 1;
1675
1676	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1677	{
1678	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1679	}
1680	}
1681	break;
1682	}
1683	//////////////////////////
1684	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1685	// and the cleanup ack has not been received,
1686	// as indicated by r_icache_miss_clack.
1687	// - If no matching coherence request (r_icache_miss_inval)
1688	// switch directory slot to VALID state.
1689	// - If matching coherence request, switch directory slot
1690	// to ZOMBI state, and send a cleanup request.
1691	{
1692	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1693
1694	// coherence clack interrupt
1695	if ( r_icache_clack_req.read() )
1696	{
1697	r_icache_fsm = ICACHE_CC_CHECK;
1698	r_icache_fsm_save = r_icache_fsm.read();
1699	break;
1700	}
1701
1702	// coherence interrupt
1703	if ( r_cc_receive_icache_req.read() )
1704	{
1705	r_icache_fsm = ICACHE_CC_CHECK;
1706	r_icache_fsm_save = r_icache_fsm.read();
1707	break;
1708	}
1709
1710	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1711	{
1712	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1713	{
1714	if ( not r_icache_cc_send_req.read() )
1715	{
1716	r_icache_miss_inval = false;
1717	// request cleanup
1718	r_icache_cc_send_req = true;
1719	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1720	r_icache_cc_send_way = r_icache_miss_way.read();
1721	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1722
1723	#ifdef INSTRUMENTATION
1724	m_cpt_icache_dir_write++;
1725	#endif
1726	r_icache.write_dir( r_icache_vci_paddr.read(),
1727	r_icache_miss_way.read(),
1728	r_icache_miss_set.read(),
1729	CACHE_SLOT_STATE_ZOMBI );
1730	#if DEBUG_ICACHE
1731	if ( m_debug_activated )
1732	{
1733	std::cout << " <PROC " << name()
1734	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1735	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1736	<< " WAY = " << std::dec << r_icache_miss_way.read()
1737	<< " SET = " << r_icache_miss_set.read() << std::endl;
1738	}
1739	#endif
1740	}
1741	else
1742	break;
1743	}
1744	else // Switch slot to VALID state
1745	{
1746
1747	#ifdef INSTRUMENTATION
1748	m_cpt_icache_dir_write++;
1749	#endif
1750	r_icache.write_dir( r_icache_vci_paddr.read(),
1751	r_icache_miss_way.read(),
1752	r_icache_miss_set.read(),
1753	CACHE_SLOT_STATE_VALID );
1754	#if DEBUG_ICACHE
1755	if ( m_debug_activated )
1756	{
1757	std::cout << " <PROC " << name()
1758	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1759	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1760	<< " WAY = " << std::dec << r_icache_miss_way.read()
1761	<< " SET = " << r_icache_miss_set.read() << std::endl;
1762	}
1763	#endif
1764	}
1765
1766	r_icache_fsm = ICACHE_IDLE;
1767	}
1768	break;
1769	}
1770	////////////////////
1771	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1772	{
1773	// coherence clack interrupt
1774	if ( r_icache_clack_req.read() )
1775	{
1776	r_icache_fsm = ICACHE_CC_CHECK;
1777	r_icache_fsm_save = r_icache_fsm.read();
1778	break;
1779	}
1780
1781	// coherence interrupt
1782	if ( r_cc_receive_icache_req.read() )
1783	{
1784	r_icache_fsm = ICACHE_CC_CHECK;
1785	r_icache_fsm_save = r_icache_fsm.read();
1786	break;
1787	}
1788
1789	if ( r_vci_rsp_ins_error.read() ) // bus error
1790	{
1791	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1792	r_mmu_ibvar = m_ireq.addr;
1793	r_vci_rsp_ins_error = false;
1794	m_irsp.valid = true;
1795	m_irsp.error = true;
1796	r_icache_fsm = ICACHE_IDLE;
1797	}
1798	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1799	{
1800	vci_rsp_fifo_icache_get = true;
1801	r_icache_fsm = ICACHE_IDLE;
1802	if ( m_ireq.valid and
1803	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1804	{
1805	m_irsp.valid = true;
1806	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1807	}
1808	}
1809	break;
1810	}
1811	/////////////////////
1812	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1813	// handling coherence requests.
1814	// if there is a matching pending miss, it is
1815	// signaled in the r_icache_miss_inval flip-flop.
1816	// The return state is defined in r_icache_fsm_save.
1817	{
1818	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1819	paddr_t mask = ~((m_icache_words<<2)-1);
1820
1821	if ( r_icache_clack_req.read() )
1822	// We switch the directory slot to EMPTY state
1823	// and reset r_icache_miss_clack if the cleanup ack
1824	// is matching a pending miss
1825	{
1826
1827	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1828
1829	#ifdef INSTRUMENTATION
1830	m_cpt_icache_dir_write++;
1831	#endif
1832	r_icache.write_dir( 0,
1833	r_icache_clack_way.read(),
1834	r_icache_clack_set.read(),
1835	CACHE_SLOT_STATE_EMPTY);
1836
1837	if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
1838	(r_icache_miss_way.read() == r_icache_clack_way.read()) )
1839	r_icache_miss_clack = false;
1840
1841	r_icache_clack_req = false;
1842
1843	#if DEBUG_ICACHE
1844	if ( m_debug_activated )
1845	{
1846	std::cout << " <PROC " << name()
1847	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1848	<< " set = " << r_icache_clack_set.read()
1849	<< " / way = " << r_icache_clack_way.read() << std::endl;
1850	}
1851	#endif
1852	// we should handle the clack request first,
1853	// if the cc request is arrived simultaneously,
1854	// we stay here in next cycle for treating the cc request.
1855	if ( not r_cc_receive_icache_req.read() )
1856	r_icache_fsm = r_icache_fsm_save.read();
1857
1858	break;
1859	}
1860	else if( r_cc_receive_icache_req.read() and
1861	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1862	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1863	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1864	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1865	{
1866	// signaling the matching
1867	r_icache_miss_inval = true;
1868
1869	// in case of update, go to CC_UPDT
1870	// JUST TO POP THE FIFO
1871	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1872	{
1873	r_icache_fsm = ICACHE_CC_UPDT;
1874	r_icache_cc_word = r_cc_receive_word_idx.read();
1875	// just pop the fifo , don't write in icache
1876	r_icache_cc_need_write = false;
1877	}
1878	// the request is dealt with
1879	else
1880	{
1881	r_cc_receive_icache_req = false;
1882	r_icache_fsm = r_icache_fsm_save.read();
1883	}
1884	#if DEBUG_ICACHE
1885	if ( m_debug_activated )
1886	{
1887	std::cout << " <PROC " << name()
1888	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1889	<< " PADDR = " << std::hex << paddr << std::endl;
1890	}
1891	#endif
1892	}
1893	else // no match
1894	{
1895	int state = 0;
1896	size_t way = 0;
1897	size_t set = 0;
1898	size_t word = 0;
1899
1900	#ifdef INSTRUMENTATION
1901	m_cpt_icache_dir_read++;
1902	#endif
1903	r_icache.read_dir(paddr,
1904	&state,
1905	&way,
1906	&set,
1907	&word);
1908
1909	r_icache_cc_way = way;
1910	r_icache_cc_set = set;
1911
1912	if ( state == CACHE_SLOT_STATE_VALID) // hit
1913	{
1914	// need to update the cache state
1915	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1916	{
1917	r_icache_cc_need_write = true;
1918	r_icache_fsm = ICACHE_CC_UPDT;
1919	r_icache_cc_word = r_cc_receive_word_idx.read();
1920	}
1921	else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval
1922	{
1923	r_icache_fsm = ICACHE_CC_INVAL;
1924	}
1925	}
1926	else // miss
1927	{
1928	// multicast acknowledgement required in case of update
1929	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1930	{
1931	r_icache_fsm = ICACHE_CC_UPDT;
1932	r_icache_cc_word = r_cc_receive_word_idx.read();
1933	// just pop the fifo , don't write in icache
1934	r_icache_cc_need_write = false;
1935	}
1936	else // No response needed
1937	{
1938	r_cc_receive_icache_req = false;
1939	r_icache_fsm = r_icache_fsm_save.read();
1940	}
1941	}
1942	}
1943	break;
1944	}
1945	/////////////////////
1946	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
1947	{
1948
1949	#if DEBUG_ICACHE
1950	if ( m_debug_activated )
1951	{
1952	std::cout << " <PROC " << name()
1953	<< " ICACHE_CC_INVAL> slot returns to zombi state"
1954	<< " set = " << r_icache_cc_set.read()
1955	<< " / way = " << r_icache_cc_way.read() << std::endl;
1956	}
1957	#endif
1958
1959	#ifdef INSTRUMENTATION
1960	m_cpt_icache_dir_read++;
1961	#endif
1962	// send a cleanup request to cc_send_fsm
1963	if(not r_icache_cc_send_req.read()) // cc_send is available
1964	{
1965	r_icache.write_dir( 0,
1966	r_icache_cc_way.read(),
1967	r_icache_cc_set.read(),
1968	CACHE_SLOT_STATE_ZOMBI );
1969	// coherence request completed
1970	r_icache_cc_send_req = true;
1971	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1972	r_icache_cc_send_way = r_icache_cc_way.read();
1973	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1974
1975	r_icache_fsm = r_icache_fsm_save.read();
1976	}
1977	//else go to CC_CHECK
1978	else
1979	r_icache_fsm = ICACHE_CC_CHECK;
1980	break;
1981
1982	}
1983	////////////////////
1984	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1985	{
1986
1987	#if DEBUG_ICACHE
1988	if ( m_debug_activated )
1989	{
1990	std::cout << " <PROC " << name()
1991	<< " ICACHE_CC_UPDT> Write one word "
1992	<< " set = " << r_icache_cc_set.read()
1993	<< " / way = " << r_icache_cc_way.read()
1994	<< " / word = " << r_icache_cc_word.read() << std::endl;
1995	}
1996	#endif
1997
1998	#ifdef INSTRUMENTATION
1999	m_cpt_icache_data_write++;
2000	#endif
2001	size_t word = r_icache_cc_word.read();
2002	size_t way = r_icache_cc_way.read();
2003	size_t set = r_icache_cc_set.read();
2004
2005	if( (not r_icache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok() ) // cc_send is available
2006	{
2007	if (r_icache_cc_need_write.read())
2008	{
2009	r_icache.write( way,
2010	set,
2011	word,
2012	r_cc_receive_updt_fifo_data.read(),
2013	r_cc_receive_updt_fifo_be.read() );
2014
2015	r_icache_cc_word = word+1;
2016	}
2017	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
2018	{
2019	// no need to write in the cache anymore
2020	r_icache_cc_need_write = false;
2021	// coherence request completed
2022	r_cc_receive_icache_req = false;
2023	// request multicast acknowledgement
2024	r_icache_cc_send_req = true;
2025	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2026	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2027	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2028
2029	r_icache_fsm = r_icache_fsm_save.read();
2030	}
2031	//consume fifo if not eop
2032	cc_receive_updt_fifo_get = true;
2033	}
2034	else
2035	r_icache_fsm = ICACHE_CC_CHECK;
2036
2037	break;
2038	}
2039
2040	} // end switch r_icache_fsm
2041
2042	////////////////////////////////////////////////////////////////////////////////////
2043	// DCACHE FSM
2044	//
2045	// 1/ Coherence operations
2046	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2047	// - There is a coherence request when r_tgt_dcache_req is set.
2048	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2049	// and SC_WAIT states.
2050	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2051	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2052	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2053	// - For both types of requests, actions associated to the pre-empted state
2054	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2055	// or CC_CLACK) to execute the requested coherence operation, and returns
2056	// to the pre-empted state.
2057	//
2058	// 2/ TLB miss
2059	// The page tables are generally cacheable.
2060	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2061	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2062	// this sub-fsm implement the table-walk...
2063	//
2064	// 3/ processor requests
2065	// Processor requests are taken in IDLE state only.
2066	// The IDLE state implements a two stages pipe-line to handle write bursts:
2067	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2068	// - The registration in wbuf and the dcache update is done in stage P1
2069	// (if the processor request is a write).
2070	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2071	// the operations that must be done in P1 stage, and the access type
2072	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2073	// READ requests are delayed if a cache update is requested.
2074	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2075	// that is done (before handling the processor request) by a dedicated sub-fsm.
2076	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2077	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2078	//
2079	// 4/ Atomic instructions LL/SC
2080	// The LL/SC address are non cacheable (systematic access to memory).
2081	// The llsc buffer contains a registration for an active LL/SC operation
2082	// (with an address, a registration key, an aging counter and a valid bit).
2083	// - LL requests from the processor are transmitted as a one flit VCI command
2084	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2085	// be 8 as the response is 2 flits long (data and registration key)
2086	// - SC requests from the processor are systematically transmitted to the
2087	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2088	// as PKTID value). The first flit contains the registration key, the second
2089	// flit contains the data to write in case of success.
2090	// The cache is not updated, as this is done in case of success by the
2091	// coherence transaction.
2092	//
2093	// 5/ Non cacheable access:
2094	// This component implement a strong order between non cacheable access
2095	// (read or write) : A new non cacheable VCI transaction starts only when
2096	// the previous non cacheable transaction is completed. Both cacheable and
2097	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2098	// a non cacheable write transaction posted in the write buffer by setting the
2099	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2100	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2101	// pending non cacheable write transaction completes).
2102	//
2103	// 6/ Error handling:
2104	// When the MMU is not activated, Read Bus Errors are synchronous events,
2105	// but Write Bus Errors are asynchronous events (processor is not frozen).
2106	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2107	// r_vci_rsp_data_error flip-flop, without writing any data in the
2108	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2109	// by the DCACHE FSM.
2110	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2111	// the asynchronous error using the setWriteBerr() method.
2112	// When the MMU is activated bus error are rare events, as the MMU
2113	// checks the physical address before the VCI transaction starts.
2114	////////////////////////////////////////////////////////////////////////////////////////
2115
2116	// default value for m_drsp
2117	m_drsp.valid = false;
2118	m_drsp.error = false;
2119	m_drsp.rdata = 0;
2120
2121	switch ( r_dcache_fsm.read() )
2122	{
2123	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2124	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2125	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2126	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2127	// 4) XTN request (processor) => DCACHE_XTN_*
2128	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2129	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2130	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2131	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2132	// 9) LL access (processor) => DCACHE_LL_WAIT
2133	// 10) SC access (processor) => DCACHE_SC_WAIT
2134	//
2135	// There is a fixed priority to handle requests to DCACHE:
2136	// 1/ the ITLB/DTLB invalidate requests
2137	// 2/ the coherence requests,
2138	// 3/ the processor requests (including DTLB miss),
2139	// 4/ the ITLB miss requests,
2140	// The address space processor request are handled as follows:
2141	// - WRITE request is blocked if the Dirty bit mus be set.
2142	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2143	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2144	// - READ request generate a simultaneouss access to DCACHE.DATA
2145	// and DCACHE.DIR, but is delayed if DCACHE update required.
2146	//
2147	// There is 4 configurations defining the access type to
2148	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2149	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2150	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2151	// 0 / 0 / NOP / NOP / NOP /
2152	// 0 / 1 / NOP / NOP / WRITE /
2153	// 1 / 0 / READ / READ / NOP /
2154	// 1 / 1 / READ / READ / WRITE /
2155	// Those two registers are set at each cycle from the 3 signals
2156	// updt_request, wbuf_request, wbuf_write_miss.
2157	{
2158	paddr_t paddr; // physical address
2159	pte_info_t tlb_flags;
2160	size_t tlb_way;
2161	size_t tlb_set;
2162	paddr_t tlb_nline = 0;
2163	size_t cache_way;
2164	size_t cache_set;
2165	size_t cache_word;
2166	uint32_t cache_rdata = 0;
2167	bool tlb_hit = false;
2168	int cache_state = CACHE_SLOT_STATE_EMPTY;
2169
2170	bool tlb_inval_required = false; // request TLB inval after cache update
2171	bool wbuf_write_miss = false; // miss a WBUF write request
2172	bool updt_request = false; // request DCACHE update in P1 stage
2173	bool wbuf_request = false; // request WBUF write in P1 stage
2174
2175	// physical address computation : systematic DTLB access if activated)
2176	if ( m_dreq.valid )
2177	{
2178	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2179	{
2180	tlb_hit = r_dtlb.translate( m_dreq.addr,
2181	&paddr,
2182	&tlb_flags,
2183	&tlb_nline,
2184	&tlb_way,
2185	&tlb_set );
2186	#ifdef INSTRUMENTATION
2187	m_cpt_dtlb_read++;
2188	#endif
2189	}
2190	else // identity mapping
2191	{
2192	paddr = (paddr_t)m_dreq.addr;
2193	// we take into account the paddr extension
2194	if (vci_param::N > 32)
2195	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
2196	}
2197	} // end physical address computation
2198
2199	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2200	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2201	{
2202	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2203	{
2204	r_dcache.read_dir( paddr,
2205	&cache_state,
2206	&cache_way,
2207	&cache_set,
2208	&cache_word );
2209
2210	r_dcache.write( r_dcache_save_cache_way.read(),
2211	r_dcache_save_cache_set.read(),
2212	r_dcache_save_cache_word.read(),
2213	r_dcache_save_wdata.read(),
2214	r_dcache_save_be.read() );
2215	#ifdef INSTRUMENTATION
2216	m_cpt_dcache_dir_read++;
2217	m_cpt_dcache_data_write++;
2218	#endif
2219	}
2220	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2221	{
2222	r_dcache.read( paddr,
2223	&cache_rdata,
2224	&cache_way,
2225	&cache_set,
2226	&cache_word,
2227	&cache_state );
2228
2229	#ifdef INSTRUMENTATION
2230	m_cpt_dcache_dir_read++;
2231	m_cpt_dcache_data_read++;
2232	#endif
2233	}
2234	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2235	{
2236	r_dcache.write( r_dcache_save_cache_way.read(),
2237	r_dcache_save_cache_set.read(),
2238	r_dcache_save_cache_word.read(),
2239	r_dcache_save_wdata.read(),
2240	r_dcache_save_be.read() );
2241	#ifdef INSTRUMENTATION
2242	m_cpt_dcache_data_write++;
2243	#endif
2244	}
2245	} // end dcache access
2246
2247	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2248	if ( r_dcache_updt_req.read() )
2249	{
2250	size_t way = r_dcache_save_cache_way.read();
2251	size_t set = r_dcache_save_cache_set.read();
2252
2253	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2254	{
2255	tlb_inval_required = true;
2256	r_dcache_tlb_inval_set = 0;
2257	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2258	(uint32_log2(m_dcache_words<<2));
2259	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2260	}
2261	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2262	{
2263	r_itlb.reset();
2264	r_dtlb.reset();
2265	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2266	}
2267
2268	#if DEBUG_DCACHE
2269	if ( m_debug_activated )
2270	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2271	<< " Cache update in P1 stage" << std::dec
2272	<< " / WAY = " << r_dcache_save_cache_way.read()
2273	<< " / SET = " << r_dcache_save_cache_set.read()
2274	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2275	<< " / WDATA = " << r_dcache_save_wdata.read()
2276	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2277	#endif
2278	} // end test TLB inval
2279
2280	// Try WBUF update in P1 stage
2281	// Miss if the write request is non cacheable, and there is a pending
2282	// non cacheable write, or if the write buffer is full.
2283	if ( r_dcache_wbuf_req.read() )
2284	{
2285	// miss if write not cacheable, and previous non cacheable write registered
2286	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2287	{
2288	wbuf_write_miss = true;
2289	}
2290	else // try a registration into write buffer
2291	{
2292	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2293	r_dcache_save_be.read(),
2294	r_dcache_save_wdata.read(),
2295	r_dcache_save_cacheable.read() );
2296	#ifdef INSTRUMENTATION
2297	m_cpt_wbuf_write++;
2298	#endif
2299	if ( not wok ) // miss if write buffer full
2300	{
2301	wbuf_write_miss = true;
2302	}
2303	else // update the write_buffer state extension
2304	{
2305	if(not r_dcache_pending_unc_write.read())
2306	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2307	}
2308	}
2309	} // end WBUF update
2310
2311	// Computing the response to processor,
2312	// and the next value for r_dcache_fsm
2313
2314	// itlb/dtlb invalidation self-request
2315	if ( tlb_inval_required )
2316	{
2317	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2318	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2319	}
2320
2321	// coherence clack request (from DSPIN CLACK)
2322	else if ( r_dcache_clack_req.read() )
2323	{
2324	r_dcache_fsm = DCACHE_CC_CHECK;
2325	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2326	}
2327	// coherence request (from CC_RECEIVE FSM)
2328	else if ( r_cc_receive_dcache_req.read() )
2329	{
2330	r_dcache_fsm = DCACHE_CC_CHECK;
2331	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2332	}
2333
2334	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2335	// we don't take the processor request, and registers
2336	// are frozen in case of wbuf_write_miss
2337	else if ( m_dreq.valid and not wbuf_write_miss )
2338	{
2339	// register processor request and DCACHE response
2340	r_dcache_save_vaddr = m_dreq.addr;
2341	r_dcache_save_be = m_dreq.be;
2342	r_dcache_save_wdata = m_dreq.wdata;
2343	r_dcache_save_paddr = paddr;
2344	r_dcache_save_cache_way = cache_way;
2345	r_dcache_save_cache_set = cache_set;
2346	r_dcache_save_cache_word = cache_word;
2347
2348	// READ XTN requests from processor
2349	// They are executed in this DCACHE_IDLE state.
2350	// The processor must not be in user mode
2351	if (m_dreq.type == iss_t::XTN_READ)
2352	{
2353	int xtn_opcode = (int)m_dreq.addr/4;
2354
2355	// checking processor mode:
2356	if (m_dreq.mode == iss_t::MODE_USER)
2357	{
2358	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2359	r_mmu_dbvar = m_dreq.addr;
2360	m_drsp.valid = true;
2361	m_drsp.error = true;
2362	m_drsp.rdata = 0;
2363	r_dcache_fsm = DCACHE_IDLE;
2364	}
2365	else
2366	{
2367	switch( xtn_opcode )
2368	{
2369	case iss_t::XTN_INS_ERROR_TYPE:
2370	m_drsp.rdata = r_mmu_ietr.read();
2371	m_drsp.valid = true;
2372	m_drsp.error = false;
2373	break;
2374
2375	case iss_t::XTN_DATA_ERROR_TYPE:
2376	m_drsp.rdata = r_mmu_detr.read();
2377	m_drsp.valid = true;
2378	m_drsp.error = false;
2379	break;
2380
2381	case iss_t::XTN_INS_BAD_VADDR:
2382	m_drsp.rdata = r_mmu_ibvar.read();
2383	m_drsp.valid = true;
2384	m_drsp.error = false;
2385	break;
2386
2387	case iss_t::XTN_DATA_BAD_VADDR:
2388	m_drsp.rdata = r_mmu_dbvar.read();
2389	m_drsp.valid = true;
2390	m_drsp.error = false;
2391	break;
2392
2393	case iss_t::XTN_PTPR:
2394	m_drsp.rdata = r_mmu_ptpr.read();
2395	m_drsp.valid = true;
2396	m_drsp.error = false;
2397	break;
2398
2399	case iss_t::XTN_TLB_MODE:
2400	m_drsp.rdata = r_mmu_mode.read();
2401	m_drsp.valid = true;
2402	m_drsp.error = false;
2403	break;
2404
2405	case iss_t::XTN_MMU_PARAMS:
2406	m_drsp.rdata = r_mmu_params;
2407	m_drsp.valid = true;
2408	m_drsp.error = false;
2409	break;
2410
2411	case iss_t::XTN_MMU_RELEASE:
2412	m_drsp.rdata = r_mmu_release;
2413	m_drsp.valid = true;
2414	m_drsp.error = false;
2415	break;
2416
2417	case iss_t::XTN_MMU_WORD_LO:
2418	m_drsp.rdata = r_mmu_word_lo.read();
2419	m_drsp.valid = true;
2420	m_drsp.error = false;
2421	break;
2422
2423	case iss_t::XTN_MMU_WORD_HI:
2424	m_drsp.rdata = r_mmu_word_hi.read();
2425	m_drsp.valid = true;
2426	m_drsp.error = false;
2427	break;
2428
2429	case iss_t::XTN_DATA_PADDR_EXT:
2430	m_drsp.rdata = r_dcache_paddr_ext.read();
2431	m_drsp.valid = true;
2432	m_drsp.error = false;
2433	break;
2434
2435	default:
2436	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2437	r_mmu_dbvar = m_dreq.addr;
2438	m_drsp.valid = true;
2439	m_drsp.error = true;
2440	m_drsp.rdata = 0;
2441	break;
2442	} // end switch xtn_opcode
2443	} // end else
2444	} // end if XTN_READ
2445
2446	// Handling WRITE XTN requests from processor.
2447	// They are not executed in this DCACHE_IDLE state
2448	// if they require access to the caches or the TLBs
2449	// that are already accessed.
2450	// Caches can be invalidated or flushed in user mode,
2451	// and the sync instruction can be executed in user mode
2452	else if (m_dreq.type == iss_t::XTN_WRITE)
2453	{
2454	int xtn_opcode = (int)m_dreq.addr/4;
2455	r_dcache_xtn_opcode = xtn_opcode;
2456
2457	// checking processor mode:
2458	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2459	(xtn_opcode != iss_t::XTN_SYNC) &&
2460	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2461	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2462	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2463	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2464	{
2465	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2466	r_mmu_dbvar = m_dreq.addr;
2467	m_drsp.valid = true;
2468	m_drsp.error = true;
2469	m_drsp.rdata = 0;
2470	r_dcache_fsm = DCACHE_IDLE;
2471	}
2472	else
2473	{
2474	switch( xtn_opcode )
2475	{
2476	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2477	r_dcache_xtn_req = true;
2478	r_dcache_fsm = DCACHE_XTN_SWITCH;
2479	break;
2480
2481	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2482	r_mmu_mode = m_dreq.wdata;
2483	m_drsp.valid = true;
2484	r_dcache_fsm = DCACHE_IDLE;
2485	break;
2486
2487	case iss_t::XTN_DTLB_INVAL: // dtlb access
2488	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2489	break;
2490
2491	case iss_t::XTN_ITLB_INVAL: // itlb access
2492	r_dcache_xtn_req = true;
2493	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2494	break;
2495
2496	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2497	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2498	break;
2499
2500	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2501	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2502	if (sizeof(paddr_t) <= 32)
2503	{
2504	assert(r_mmu_word_hi.read() == 0 &&
2505	"high bits should be 0 for 32bit paddr");
2506	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2507	}
2508	else
2509	{
2510	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2511	(paddr_t)r_mmu_word_lo.read();
2512	}
2513	break;
2514
2515	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2516	r_dcache_flush_count = 0;
2517	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2518	break;
2519
2520	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2521	r_dcache_xtn_req = true;
2522	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2523	break;
2524
2525	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2526	r_dcache_xtn_req = true;
2527	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2528	break;
2529
2530	case iss_t::XTN_ICACHE_FLUSH: // icache access
2531	r_dcache_xtn_req = true;
2532	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2533	break;
2534
2535	case iss_t::XTN_SYNC: // wait until write buffer empty
2536	r_dcache_fsm = DCACHE_XTN_SYNC;
2537	break;
2538
2539	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2540	r_mmu_word_lo = m_dreq.wdata;
2541	m_drsp.valid = true;
2542	r_dcache_fsm = DCACHE_IDLE;
2543	break;
2544
2545	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2546	r_mmu_word_hi = m_dreq.wdata;
2547	m_drsp.valid = true;
2548	r_dcache_fsm = DCACHE_IDLE;
2549	break;
2550
2551	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2552	r_dcache_llsc_valid = false;
2553	m_drsp.valid = true;
2554	r_dcache_fsm = DCACHE_IDLE;
2555	break;
2556
2557	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2558	r_dcache_paddr_ext = m_dreq.wdata;
2559	m_drsp.valid = true;
2560	r_dcache_fsm = DCACHE_IDLE;
2561	break;
2562
2563	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2564	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2565	m_drsp.valid = true;
2566	r_dcache_fsm = DCACHE_IDLE;
2567	break;
2568
2569	default:
2570	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2571	r_mmu_dbvar = m_dreq.addr;
2572	m_drsp.valid = true;
2573	m_drsp.error = true;
2574	r_dcache_fsm = DCACHE_IDLE;
2575	break;
2576	} // end switch xtn_opcode
2577	} // end else
2578	} // end if XTN_WRITE
2579
2580	// Handling processor requests to address space (READ/WRITE/LL/SC)
2581	// The dtlb and dcache can be activated or not.
2582	// We compute the cacheability, and check processor request validity:
2583	// - If DTLB not activated : cacheability is defined by the segment table,
2584	// and there is no access rights checking.
2585	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2586	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2587	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2588	else
2589	{
2590	bool valid_req;
2591	bool cacheable;
2592
2593	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2594	{
2595	valid_req = true;
2596
2597	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2598	else cacheable = m_cacheability_table[m_dreq.addr];
2599	}
2600	else // dtlb activated
2601	{
2602	if ( tlb_hit ) // tlb hit
2603	{
2604	// cacheability
2605	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2606	else cacheable = tlb_flags.c;
2607
2608	// access rights checking
2609	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2610	{
2611	if ( (m_dreq.type == iss_t::DATA_READ) or
2612	(m_dreq.type == iss_t::DATA_LL) )
2613	{
2614	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2615	}
2616	else
2617	{
2618	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2619	}
2620	valid_req = false;
2621	r_mmu_dbvar = m_dreq.addr;
2622	m_drsp.valid = true;
2623	m_drsp.error = true;
2624	m_drsp.rdata = 0;
2625	#if DEBUG_DCACHE
2626	if ( m_debug_activated )
2627	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2628	<< " HIT in dtlb, but privilege violation" << std::endl;
2629	#endif
2630	}
2631	else if ( not tlb_flags.w and
2632	((m_dreq.type == iss_t::DATA_WRITE) or
2633	(m_dreq.type == iss_t::DATA_SC)) )
2634	{
2635	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2636	valid_req = false;
2637	r_mmu_dbvar = m_dreq.addr;
2638	m_drsp.valid = true;
2639	m_drsp.error = true;
2640	m_drsp.rdata = 0;
2641	#if DEBUG_DCACHE
2642	if ( m_debug_activated )
2643	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2644	<< " HIT in dtlb, but writable violation" << std::endl;
2645	#endif
2646	}
2647	else
2648	{
2649	valid_req = true;
2650	}
2651	}
2652	else // tlb miss
2653	{
2654	valid_req = false;
2655	r_dcache_tlb_vaddr = m_dreq.addr;
2656	r_dcache_tlb_ins = false;
2657	r_dcache_fsm = DCACHE_TLB_MISS;
2658	}
2659	} // end DTLB activated
2660
2661	if ( valid_req ) // processor request is valid (after MMU check)
2662	{
2663	r_dcache_save_cacheable = cacheable;
2664
2665	// READ request
2666	// The read requests are taken only if there is no cache update.
2667	// We request a VCI transaction to CMD FSM if miss or uncachable
2668
2669	if ( ((m_dreq.type == iss_t::DATA_READ))
2670	and not r_dcache_updt_req.read() )
2671	{
2672	if ( cacheable ) // cacheable read
2673	{
2674	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2675	{
2676	#ifdef INSTRUMENTATION
2677	m_cpt_dcache_miss++;
2678	#endif
2679	// request a VCI DMISS transaction
2680	r_dcache_vci_paddr = paddr;
2681	r_dcache_vci_miss_req = true;
2682	r_dcache_miss_type = PROC_MISS;
2683	r_dcache_fsm = DCACHE_MISS_SELECT;
2684	#if DEBUG_DCACHE
2685	if ( m_debug_activated )
2686	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2687	<< " READ MISS in dcache"
2688	<< " / PADDR = " << std::hex << paddr << std::endl;
2689	#endif
2690	}
2691	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2692	{
2693	// stalled until cleanup is acknowledged
2694	r_dcache_fsm = DCACHE_IDLE;
2695	#if DEBUG_DCACHE
2696	if ( m_debug_activated )
2697	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2698	<< " Pending cleanup, stalled until cleanup acknowledge"
2699	<< " / PADDR = " << std::hex << paddr << std::endl;
2700	#endif
2701	}
2702	else // cache hit
2703	{
2704	#ifdef INSTRUMENTATION
2705	m_cpt_data_read++;
2706	#endif
2707	// returns data to processor
2708	m_drsp.valid = true;
2709	m_drsp.error = false;
2710	m_drsp.rdata = cache_rdata;
2711	#if DEBUG_DCACHE
2712	if ( m_debug_activated )
2713	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2714	<< " READ HIT in dcache"
2715	<< " / PADDR = " << std::hex << paddr << std::endl;
2716	#endif
2717	}
2718	}
2719	else // uncacheable read
2720	{
2721	r_dcache_vci_paddr = paddr;
2722	r_dcache_vci_unc_be = m_dreq.be;
2723	r_dcache_vci_unc_req = true;
2724	r_dcache_fsm = DCACHE_UNC_WAIT;
2725	#if DEBUG_DCACHE
2726	if ( m_debug_activated )
2727	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2728	<< " READ UNCACHEABLE in dcache"
2729	<< " / PADDR = " << std::hex << paddr << std::endl;
2730	#endif
2731	}
2732	} // end READ
2733
2734	// LL request (non cachable)
2735	// We request a VCI LL transaction to CMD FSM and register
2736	// the LL/SC operation in llsc buffer.
2737	else if (m_dreq.type == iss_t::DATA_LL)
2738	{
2739	// register paddr in LLSC buffer
2740	r_dcache_llsc_paddr = paddr;
2741	r_dcache_llsc_count = LLSC_TIMEOUT;
2742	r_dcache_llsc_valid = true;
2743
2744	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2745	r_dcache_vci_ll_req = true;
2746	r_dcache_vci_paddr = paddr;
2747	r_dcache_ll_rsp_count = 0;
2748	r_dcache_fsm = DCACHE_LL_WAIT;
2749
2750	}// end LL
2751
2752	// WRITE request:
2753	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2754	// the processor and set the Dirty bit before handling the write request,
2755	// going to the DCACHE_DIRTY_GT_PTE state.
2756	// If we don't need to set the Dirty bit, we can acknowledge
2757	// the processor request, as the write arguments (including the
2758	// physical address) are registered in r_dcache_save registers,
2759	// and the write will be done in the P1 pipeline stage.
2760	else if ( m_dreq.type == iss_t::DATA_WRITE )
2761	{
2762	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2763	and not tlb_flags.d ) // Dirty bit must be set
2764	{
2765	// The PTE physical address is obtained from the nline value (dtlb),
2766	// and from the virtual address (word index)
2767	if ( tlb_flags.b ) // PTE1
2768	{
2769	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2770	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2771	}
2772	else // PTE2
2773	{
2774	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2775	(paddr_t)((m_dreq.addr>>9) & 0x38);
2776	}
2777	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2778	}
2779	else // Write request accepted
2780	{
2781	#ifdef INSTRUMENTATION
2782	m_cpt_data_write++;
2783	#endif
2784	// cleaning llsc buffer if address matching
2785	if ( paddr == r_dcache_llsc_paddr.read() )
2786	r_dcache_llsc_valid = false;
2787
2788	// response to processor
2789	m_drsp.valid = true;
2790
2791	// activating P1 stage
2792	wbuf_request = true;
2793	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2794	}
2795	} // end WRITE
2796
2797	// SC request:
2798	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2799	// the processor and set the Dirty bit before handling the write request,
2800	// going to the DCACHE_DIRTY_GT_PTE state.
2801	// If we don't need to set the Dirty bit, we test the llsc buffer:
2802	// If failure, we send a negative response to processor.
2803	// If success, we request a SC transaction to CMD FSM and go
2804	// to DCACHE_SC_WAIT state.
2805	// We don't check a possible write hit in dcache, as the cache update
2806	// is done by the coherence transaction induced by the SC...
2807	else if ( m_dreq.type == iss_t::DATA_SC )
2808	{
2809	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2810	and not tlb_flags.d ) // Dirty bit must be set
2811	{
2812	// The PTE physical address is obtained from the nline value (dtlb),
2813	// and the word index (virtual address)
2814	if ( tlb_flags.b ) // PTE1
2815	{
2816	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2817	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2818	}
2819	else // PTE2
2820	{
2821	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2822	(paddr_t)((m_dreq.addr>>9) & 0x38);
2823	}
2824	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2825	m_drsp.valid = false;
2826	m_drsp.error = false;
2827	m_drsp.rdata = 0;
2828	}
2829	else // SC request accepted
2830	{
2831	#ifdef INSTRUMENTATION
2832	m_cpt_data_sc++;
2833	#endif
2834	// checking local success
2835	if( r_dcache_llsc_valid.read() and
2836	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2837	{
2838	// request an SC CMD and go to DCACHE_SC_WAIT state
2839	r_dcache_vci_paddr = paddr;
2840	r_dcache_vci_sc_req = true;
2841	r_dcache_vci_sc_data = m_dreq.wdata;
2842	r_dcache_fsm = DCACHE_SC_WAIT;
2843	}
2844	else // local fail
2845	{
2846	m_drsp.valid = true;
2847	m_drsp.error = false;
2848	m_drsp.rdata = 0x1;
2849	}
2850	}
2851	} // end SC
2852	} // end valid_req
2853	} // end if read/write/ll/sc request
2854	} // end processor request
2855
2856	// itlb miss request
2857	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2858	{
2859	r_dcache_tlb_ins = true;
2860	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2861	r_dcache_fsm = DCACHE_TLB_MISS;
2862	}
2863
2864	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2865	r_dcache_updt_req = updt_request;
2866	r_dcache_wbuf_req = wbuf_request or
2867	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2868	break;
2869	}
2870	/////////////////////
2871	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2872	// Input arguments are:
2873	// - r_dcache_tlb_vaddr
2874	// - r_dcache_tlb_ins (true when itlb miss)
2875	// The sub-fsm access the dcache to find the missing TLB entry,
2876	// and activates the cache miss procedure in case of miss.
2877	// It bypass the first level page table access if possible.
2878	// It uses atomic access to update the R/L access bits
2879	// in the page table if required.
2880	// It directly updates the itlb or dtlb, and writes into the
2881	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2882	{
2883	uint32_t ptba = 0;
2884	bool bypass;
2885	paddr_t pte_paddr;
2886
2887	// evaluate bypass in order to skip first level page table access
2888	if ( r_dcache_tlb_ins.read() ) // itlb miss
2889	{
2890	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2891	}
2892	else // dtlb miss
2893	{
2894	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2895	}
2896
2897	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2898	{
2899	pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) \|
2900	((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
2901	r_dcache_tlb_paddr = pte_paddr;
2902	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2903	}
2904	else // Try to read PTE2 in dcache
2905	{
2906	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2907	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2908	r_dcache_tlb_paddr = pte_paddr;
2909	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2910	}
2911
2912	#if DEBUG_DCACHE
2913	if ( m_debug_activated )
2914	{
2915	if ( r_dcache_tlb_ins.read() )
2916	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
2917	else
2918	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
2919	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2920	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
2921	<< " / BYPASS = " << bypass
2922	<< " / PTE_ADR = " << pte_paddr << std::endl;
2923	}
2924	#endif
2925
2926	break;
2927	}
2928	/////////////////////////
2929	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2930	{
2931	// coherence clack request (from DSPIN CLACK)
2932	if ( r_dcache_clack_req.read() )
2933	{
2934	r_dcache_fsm = DCACHE_CC_CHECK;
2935	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2936	break;
2937	}
2938
2939	// coherence request (from CC_RECEIVE FSM)
2940	if ( r_cc_receive_dcache_req.read() )
2941	{
2942	r_dcache_fsm = DCACHE_CC_CHECK;
2943	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2944	break;
2945	}
2946
2947	uint32_t entry;
2948	size_t way;
2949	size_t set;
2950	size_t word;
2951	int cache_state;
2952	r_dcache.read( r_dcache_tlb_paddr.read(),
2953	&entry,
2954	&way,
2955	&set,
2956	&word,
2957	&cache_state );
2958	#ifdef INSTRUMENTATION
2959	m_cpt_dcache_data_read++;
2960	m_cpt_dcache_dir_read++;
2961	#endif
2962	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2963	{
2964	if ( not (entry & PTE_V_MASK) ) // unmapped
2965	{
2966	if ( r_dcache_tlb_ins.read() )
2967	{
2968	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2969	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2970	r_icache_tlb_miss_req = false;
2971	r_icache_tlb_rsp_error = true;
2972	}
2973	else
2974	{
2975	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2976	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2977	m_drsp.valid = true;
2978	m_drsp.error = true;
2979	}
2980	r_dcache_fsm = DCACHE_IDLE;
2981
2982	#if DEBUG_DCACHE
2983	if ( m_debug_activated )
2984	{
2985	std::cout << " <PROC " << name()
2986	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2987	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2988	<< std::dec << " / way = " << way
2989	<< std::dec << " / set = " << set
2990	<< std::dec << " / word = " << word
2991	<< std::hex << " / PTE1 = " << entry << std::endl;
2992	}
2993	#endif
2994
2995	}
2996	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2997	{
2998	// mark the cache line ac containing a PTD
2999	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
3000
3001	// register bypass
3002	if ( r_dcache_tlb_ins.read() ) // itlb
3003	{
3004	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3005	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3006	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
3007	}
3008	else // dtlb
3009	{
3010	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3011	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3012	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
3013	}
3014	r_dcache_tlb_paddr =
3015	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3016	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3017	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3018
3019	#if DEBUG_DCACHE
3020	if ( m_debug_activated )
3021	{
3022	std::cout << " <PROC " << name()
3023	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3024	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3025	<< std::dec << " / way = " << way
3026	<< std::dec << " / set = " << set
3027	<< std::dec << " / word = " << word
3028	<< std::hex << " / PTD = " << entry << std::endl;
3029	}
3030	#endif
3031	}
3032	else // PTE1 : we must update the TLB
3033	{
3034	r_dcache_in_tlb[m_icache_sets*way+set] = true;
3035	r_dcache_tlb_pte_flags = entry;
3036	r_dcache_tlb_cache_way = way;
3037	r_dcache_tlb_cache_set = set;
3038	r_dcache_tlb_cache_word = word;
3039	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3040
3041	#if DEBUG_DCACHE
3042	if ( m_debug_activated )
3043	{
3044	std::cout << " <PROC " << name()
3045	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3046	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3047	<< std::dec << " / way = " << way
3048	<< std::dec << " / set = " << set
3049	<< std::dec << " / word = " << word
3050	<< std::hex << " / PTE1 = " << entry << std::endl;
3051	}
3052	#endif
3053	}
3054	}
3055	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3056	{
3057	// stalled until cleanup is acknowledged
3058	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3059	}
3060	else // we must load the missing cache line in dcache
3061	{
3062	r_dcache_vci_miss_req = true;
3063	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3064	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3065	r_dcache_miss_type = PTE1_MISS;
3066	r_dcache_fsm = DCACHE_MISS_SELECT;
3067
3068	#if DEBUG_DCACHE
3069	if ( m_debug_activated )
3070	{
3071	std::cout << " <PROC " << name()
3072	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3073	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3074	}
3075	#endif
3076	}
3077	break;
3078	}
3079	////////////////////////////
3080	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3081	{
3082	size_t way;
3083	size_t set;
3084
3085	if ( r_dcache_tlb_ins.read() )
3086	{
3087	r_itlb.select( r_dcache_tlb_vaddr.read(),
3088	true, // PTE1
3089	&way,
3090	&set );
3091	#ifdef INSTRUMENTATION
3092	m_cpt_itlb_read++;
3093	#endif
3094	}
3095	else
3096	{
3097	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3098	true, // PTE1
3099	&way,
3100	&set );
3101	#ifdef INSTRUMENTATION
3102	m_cpt_dtlb_read++;
3103	#endif
3104	}
3105	r_dcache_tlb_way = way;
3106	r_dcache_tlb_set = set;
3107	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3108
3109	#if DEBUG_DCACHE
3110	if ( m_debug_activated )
3111	{
3112	if ( r_dcache_tlb_ins.read() )
3113	std::cout << " <PROC " << name()
3114	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3115	else
3116	std::cout << " <PROC " << name()
3117	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3118	std::cout << " way = " << std::dec << way
3119	<< " / set = " << set << std::endl;
3120	}
3121	#endif
3122	break;
3123	}
3124	//////////////////////////
3125	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3126	// - if L/R bit already set, exit the sub-fsm.
3127	// - if not, we update the page table but we dont write
3128	// neither in DCACHE, nor in TLB, as this will be done by
3129	// the coherence mechanism.
3130	{
3131	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3132	uint32_t pte = r_dcache_tlb_pte_flags.read();
3133	bool pt_updt = false;
3134	bool local = true;
3135
3136	// We should compute the access locality:
3137	// The PPN MSB bits define the destination cluster index.
3138	// The m_srcid MSB bits define the source cluster index.
3139	// The number of bits to compare depends on the number of clusters,
3140	// and can be obtained in the mapping table.
3141	// As long as this computation is not done, all access are local.
3142
3143	if ( local ) // local access
3144	{
3145	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3146	{
3147	pt_updt = true;
3148	r_dcache_vci_cas_old = pte;
3149	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3150	pte = pte \| PTE_L_MASK;
3151	r_dcache_tlb_pte_flags = pte;
3152	}
3153	}
3154	else // remote access
3155	{
3156	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3157	{
3158	pt_updt = true;
3159	r_dcache_vci_cas_old = pte;
3160	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3161	pte = pte \| PTE_R_MASK;
3162	r_dcache_tlb_pte_flags = pte;
3163	}
3164	}
3165
3166	if ( not pt_updt ) // update TLB and return
3167	{
3168	if ( r_dcache_tlb_ins.read() )
3169	{
3170	r_itlb.write( true, // 2M page
3171	pte,
3172	0, // argument unused for a PTE1
3173	r_dcache_tlb_vaddr.read(),
3174	r_dcache_tlb_way.read(),
3175	r_dcache_tlb_set.read(),
3176	nline );
3177	#ifdef INSTRUMENTATION
3178	m_cpt_itlb_write++;
3179	#endif
3180
3181	#if DEBUG_DCACHE
3182	if ( m_debug_activated )
3183	{
3184	std::cout << " <PROC " << name()
3185	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3186	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3187	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3188	r_itlb.printTrace();
3189	}
3190	#endif
3191	}
3192	else
3193	{
3194	r_dtlb.write( true, // 2M page
3195	pte,
3196	0, // argument unused for a PTE1
3197	r_dcache_tlb_vaddr.read(),
3198	r_dcache_tlb_way.read(),
3199	r_dcache_tlb_set.read(),
3200	nline );
3201	#ifdef INSTRUMENTATION
3202	m_cpt_dtlb_write++;
3203	#endif
3204
3205	#if DEBUG_DCACHE
3206	if ( m_debug_activated )
3207	{
3208	std::cout << " <PROC " << name()
3209	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3210	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3211	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3212	r_dtlb.printTrace();
3213	}
3214	#endif
3215	}
3216	r_dcache_fsm = DCACHE_TLB_RETURN;
3217	}
3218	else // update page table but not TLB
3219	{
3220	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3221
3222	#if DEBUG_DCACHE
3223	if ( m_debug_activated )
3224	{
3225	std::cout << " <PROC " << name()
3226	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3227	<< std::endl;
3228	}
3229	#endif
3230	}
3231	break;
3232	}
3233	/////////////////////////
3234	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3235	{
3236	// coherence clack request (from DSPIN CLACK)
3237	if ( r_dcache_clack_req.read() )
3238	{
3239	r_dcache_fsm = DCACHE_CC_CHECK;
3240	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3241	break;
3242	}
3243
3244	// coherence request (from CC_RECEIVE FSM)
3245	if ( r_cc_receive_dcache_req.read() )
3246	{
3247	r_dcache_fsm = DCACHE_CC_CHECK;
3248	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3249	break;
3250	}
3251
3252	uint32_t pte_flags;
3253	uint32_t pte_ppn;
3254	size_t way;
3255	size_t set;
3256	size_t word;
3257	int cache_state;
3258
3259	r_dcache.read( r_dcache_tlb_paddr.read(),
3260	&pte_flags,
3261	&pte_ppn,
3262	&way,
3263	&set,
3264	&word,
3265	&cache_state );
3266	#ifdef INSTRUMENTATION
3267	m_cpt_dcache_data_read++;
3268	m_cpt_dcache_dir_read++;
3269	#endif
3270	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3271	{
3272	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3273	{
3274	if ( r_dcache_tlb_ins.read() )
3275	{
3276	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3277	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3278	r_icache_tlb_miss_req = false;
3279	r_icache_tlb_rsp_error = true;
3280	}
3281	else
3282	{
3283	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3284	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3285	m_drsp.valid = true;
3286	m_drsp.error = true;
3287	}
3288	r_dcache_fsm = DCACHE_IDLE;
3289
3290	#if DEBUG_DCACHE
3291	if ( m_debug_activated )
3292	{
3293	std::cout << " <PROC " << name()
3294	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3295	<< " PTE_FLAGS = " << std::hex << pte_flags
3296	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3297	}
3298	#endif
3299	}
3300	else // mapped : we must update the TLB
3301	{
3302	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3303	r_dcache_tlb_pte_flags = pte_flags;
3304	r_dcache_tlb_pte_ppn = pte_ppn;
3305	r_dcache_tlb_cache_way = way;
3306	r_dcache_tlb_cache_set = set;
3307	r_dcache_tlb_cache_word = word;
3308	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3309
3310	#if DEBUG_DCACHE
3311	if ( m_debug_activated )
3312	{
3313	std::cout << " <PROC " << name()
3314	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3315	<< " PTE_FLAGS = " << std::hex << pte_flags
3316	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3317	}
3318	#endif
3319	}
3320	}
3321	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3322	{
3323	// stalled until cleanup is acknowledged
3324	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3325
3326	#if DEBUG_DCACHE
3327	if ( m_debug_activated )
3328	{
3329	std::cout << " <PROC " << name()
3330	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3331	<< std::endl;
3332	}
3333	#endif
3334	}
3335	else // we must load the missing cache line in dcache
3336	{
3337	r_dcache_fsm = DCACHE_MISS_SELECT;
3338	r_dcache_vci_miss_req = true;
3339	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3340	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3341	r_dcache_miss_type = PTE2_MISS;
3342
3343	#if DEBUG_DCACHE
3344	if ( m_debug_activated )
3345	{
3346	std::cout << " <PROC " << name()
3347	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3348	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3349	}
3350	#endif
3351	}
3352	break;
3353	}
3354	////////////////////////////
3355	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3356	{
3357	size_t way;
3358	size_t set;
3359
3360	if ( r_dcache_tlb_ins.read() )
3361	{
3362	r_itlb.select( r_dcache_tlb_vaddr.read(),
3363	false, // PTE2
3364	&way,
3365	&set );
3366	#ifdef INSTRUMENTATION
3367	m_cpt_itlb_read++;
3368	#endif
3369	}
3370	else
3371	{
3372	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3373	false, // PTE2
3374	&way,
3375	&set );
3376	#ifdef INSTRUMENTATION
3377	m_cpt_dtlb_read++;
3378	#endif
3379	}
3380
3381	#if DEBUG_DCACHE
3382	if ( m_debug_activated )
3383	{
3384	if ( r_dcache_tlb_ins.read() )
3385	std::cout << " <PROC " << name()
3386	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3387	else
3388	std::cout << " <PROC " << name()
3389	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3390	std::cout << " way = " << std::dec << way
3391	<< " / set = " << set << std::endl;
3392	}
3393	#endif
3394	r_dcache_tlb_way = way;
3395	r_dcache_tlb_set = set;
3396	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3397	break;
3398	}
3399	//////////////////////////
3400	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3401	// - if L/R bit already set, exit the sub-fsm.
3402	// - if not, we update the page table but we dont write
3403	// neither in DCACHE, nor in TLB, as this will be done by
3404	// the coherence mechanism.
3405	{
3406	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3407	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3408	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3409	bool pt_updt = false;
3410	bool local = true;
3411
3412	// We should compute the access locality:
3413	// The PPN MSB bits define the destination cluster index.
3414	// The m_srcid MSB bits define the source cluster index.
3415	// The number of bits to compare depends on the number of clusters,
3416	// and can be obtained in the mapping table.
3417	// As long as this computation is not done, all access are local.
3418
3419	if ( local ) // local access
3420	{
3421	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3422	{
3423	pt_updt = true;
3424	r_dcache_vci_cas_old = pte_flags;
3425	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3426	pte_flags = pte_flags \| PTE_L_MASK;
3427	r_dcache_tlb_pte_flags = pte_flags;
3428	}
3429	}
3430	else // remote access
3431	{
3432	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3433	{
3434	pt_updt = true;
3435	r_dcache_vci_cas_old = pte_flags;
3436	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3437	pte_flags = pte_flags \| PTE_R_MASK;
3438	r_dcache_tlb_pte_flags = pte_flags;
3439	}
3440	}
3441
3442	if ( not pt_updt ) // update TLB
3443	{
3444	if ( r_dcache_tlb_ins.read() )
3445	{
3446	r_itlb.write( false, // 4K page
3447	pte_flags,
3448	pte_ppn,
3449	r_dcache_tlb_vaddr.read(),
3450	r_dcache_tlb_way.read(),
3451	r_dcache_tlb_set.read(),
3452	nline );
3453	#ifdef INSTRUMENTATION
3454	m_cpt_itlb_write++;
3455	#endif
3456
3457	#if DEBUG_DCACHE
3458	if ( m_debug_activated )
3459	{
3460	std::cout << " <PROC " << name()
3461	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3462	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3463	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3464	r_itlb.printTrace();
3465	}
3466	#endif
3467	}
3468	else
3469	{
3470	r_dtlb.write( false, // 4K page
3471	pte_flags,
3472	pte_ppn,
3473	r_dcache_tlb_vaddr.read(),
3474	r_dcache_tlb_way.read(),
3475	r_dcache_tlb_set.read(),
3476	nline );
3477	#ifdef INSTRUMENTATION
3478	m_cpt_dtlb_write++;
3479	#endif
3480
3481	#if DEBUG_DCACHE
3482	if ( m_debug_activated )
3483	{
3484	std::cout << " <PROC " << name()
3485	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3486	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3487	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3488	r_dtlb.printTrace();
3489	}
3490	#endif
3491
3492	}
3493	r_dcache_fsm = DCACHE_TLB_RETURN;
3494	}
3495	else // update page table but not TLB
3496	{
3497	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3498
3499	#if DEBUG_DCACHE
3500	if ( m_debug_activated )
3501	{
3502	std::cout << " <PROC " << name()
3503	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3504	}
3505	#endif
3506	}
3507	break;
3508	}
3509	////////////////////////
3510	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3511	{
3512	#if DEBUG_DCACHE
3513	if ( m_debug_activated )
3514	{
3515	std::cout << " <PROC " << name()
3516	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3517	}
3518	#endif
3519	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3520	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3521
3522	// checking llsc reservation buffer
3523	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3524	r_dcache_llsc_valid = false;
3525
3526	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3527	r_dcache_vci_cas_req = true;
3528	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3529	break;
3530	}
3531	////////////////////////
3532	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3533	// We consume the response in rsp FIFO,
3534	// and exit the sub-fsm, but we don't
3535	// analyse the response, because we don't
3536	// care if the L/R bit update is not done.
3537	// We must take the coherence requests because
3538	// there is a risk of dead-lock
3539
3540	{
3541	// coherence clack request (from DSPIN CLACK)
3542	if ( r_dcache_clack_req.read() )
3543	{
3544	r_dcache_fsm = DCACHE_CC_CHECK;
3545	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3546	break;
3547	}
3548
3549	// coherence request (from CC_RECEIVE FSM)
3550	if ( r_cc_receive_dcache_req.read() )
3551	{
3552	r_dcache_fsm = DCACHE_CC_CHECK;
3553	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3554	break;
3555	}
3556
3557	if ( r_vci_rsp_data_error.read() ) // bus error
3558	{
3559	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3560	std::cout << "This should not happen in this state" << std::endl;
3561	exit(0);
3562	}
3563	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3564	{
3565	#if DEBUG_DCACHE
3566	if ( m_debug_activated )
3567	{
3568	std::cout << " <PROC " << name()
3569	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3570	}
3571	#endif
3572	vci_rsp_fifo_dcache_get = true;
3573	r_dcache_fsm = DCACHE_TLB_RETURN;
3574	}
3575	break;
3576	}
3577	///////////////////////
3578	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3579	{
3580	#if DEBUG_DCACHE
3581	if ( m_debug_activated )
3582	{
3583	std::cout << " <PROC " << name()
3584	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3585	}
3586	#endif
3587	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3588	r_dcache_fsm = DCACHE_IDLE;
3589	break;
3590	}
3591	///////////////////////
3592	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3593	// and both itlb and dtlb must be flushed.
3594	// Caution : the itlb miss requests must be taken
3595	// to avoid dead-lock in case of simultaneous ITLB miss
3596	{
3597	// itlb miss request
3598	if ( r_icache_tlb_miss_req.read() )
3599	{
3600	r_dcache_tlb_ins = true;
3601	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3602	r_dcache_fsm = DCACHE_TLB_MISS;
3603	break;
3604	}
3605
3606	if ( not r_dcache_xtn_req.read() )
3607	{
3608	r_dtlb.flush();
3609	r_mmu_ptpr = m_dreq.wdata;
3610	r_dcache_fsm = DCACHE_IDLE;
3611	m_drsp.valid = true;
3612	}
3613	break;
3614	}
3615	/////////////////////
3616	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3617	// The coherence request must be taken
3618	// as there is a risk of dead-lock
3619	{
3620	// coherence clack request (from DSPIN CLACK)
3621	if ( r_dcache_clack_req.read() )
3622	{
3623	r_dcache_fsm = DCACHE_CC_CHECK;
3624	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3625	break;
3626	}
3627
3628	// coherence request (from CC_RECEIVE FSM)
3629	if ( r_cc_receive_dcache_req.read() )
3630	{
3631	r_dcache_fsm = DCACHE_CC_CHECK;
3632	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3633	break;
3634	}
3635
3636	if ( r_wbuf.empty() )
3637	{
3638	m_drsp.valid = true;
3639	r_dcache_fsm = DCACHE_IDLE;
3640	}
3641	break;
3642	}
3643	////////////////////////
3644	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3645	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3646	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3647	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3648	// and because it can exist a simultaneous ITLB miss
3649	{
3650	// coherence clack request (from DSPIN CLACK)
3651	if ( r_dcache_clack_req.read() )
3652	{
3653	r_dcache_fsm = DCACHE_CC_CHECK;
3654	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3655	break;
3656	}
3657
3658	// coherence request (from CC_RECEIVE FSM)
3659	if ( r_cc_receive_dcache_req.read() )
3660	{
3661	r_dcache_fsm = DCACHE_CC_CHECK;
3662	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3663	break;
3664	}
3665
3666	// itlb miss request
3667	if ( r_icache_tlb_miss_req.read() )
3668	{
3669	r_dcache_tlb_ins = true;
3670	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3671	r_dcache_fsm = DCACHE_TLB_MISS;
3672	break;
3673	}
3674
3675	// test if XTN request to icache completed
3676	if ( not r_dcache_xtn_req.read() )
3677	{
3678	r_dcache_fsm = DCACHE_IDLE;
3679	m_drsp.valid = true;
3680	}
3681	break;
3682	}
3683	/////////////////////////
3684	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3685	// r_dcache_flush_count as a slot counter,
3686	// looping in this state until all slots have been visited.
3687	// It can require two cycles per slot:
3688	// We test here the slot state, and make the actual inval
3689	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3690	// A cleanup request is generated for each valid line.
3691	// returns to IDLE and flush TLBs when last slot
3692	{
3693	// coherence clack request (from DSPIN CLACK)
3694	if ( r_dcache_clack_req.read() )
3695	{
3696	r_dcache_fsm = DCACHE_CC_CHECK;
3697	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3698	break;
3699	}
3700
3701	// coherence request (from CC_RECEIVE FSM)
3702	if ( r_cc_receive_dcache_req.read() )
3703	{
3704	r_dcache_fsm = DCACHE_CC_CHECK;
3705	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3706	break;
3707	}
3708
3709	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3710	{
3711	int state;
3712	paddr_t tag;
3713	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3714	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3715
3716	#ifdef INSTRUMENTATION
3717	m_cpt_dcache_dir_read++;
3718	#endif
3719	r_dcache.read_dir( way,
3720	set,
3721	&tag,
3722	&state );
3723
3724	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3725	{
3726	// request cleanup
3727	r_dcache_cc_send_req = true;
3728	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3729	r_dcache_cc_send_way = way;
3730	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3731
3732	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3733	r_dcache_miss_way = way;
3734	r_dcache_miss_set = set;
3735	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3736	}
3737	else if ( r_dcache_flush_count.read() ==
3738	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3739	{
3740	r_dtlb.reset();
3741	r_itlb.reset();
3742	r_dcache_fsm = DCACHE_IDLE;
3743	m_drsp.valid = true;
3744	}
3745
3746	// saturation counter
3747	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3748	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3749	}
3750	break;
3751	}
3752	////////////////////////////
3753	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3754	// and reset directory extension.
3755	// returns to IDLE and flush TLBs when last slot
3756	{
3757	size_t way = r_dcache_miss_way.read();
3758	size_t set = r_dcache_miss_set.read();
3759
3760	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3761	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3762
3763	#ifdef INSTRUMENTATION
3764	m_cpt_dcache_dir_write++;
3765	#endif
3766	r_dcache.write_dir( way,
3767	set,
3768	CACHE_SLOT_STATE_ZOMBI );
3769
3770	if ( r_dcache_flush_count.read() ==
3771	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3772	{
3773	r_dtlb.reset();
3774	r_itlb.reset();
3775	r_dcache_fsm = DCACHE_IDLE;
3776	m_drsp.valid = true;
3777	}
3778	else
3779	{
3780	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3781	}
3782	break;
3783	}
3784	/////////////////////////
3785	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3786	{
3787	r_dtlb.inval(r_dcache_save_wdata.read());
3788	r_dcache_fsm = DCACHE_IDLE;
3789	m_drsp.valid = true;
3790	break;
3791	}
3792	////////////////////////////
3793	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3794	// requires 3 cycles: access tlb, read cache, inval cache
3795	// we compute the physical address in this state
3796	{
3797	paddr_t paddr;
3798	bool hit;
3799
3800	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3801	{
3802
3803	#ifdef INSTRUMENTATION
3804	m_cpt_dtlb_read++;
3805	#endif
3806	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3807	&paddr );
3808	}
3809	else // dtlb not activated
3810	{
3811	paddr = (paddr_t)r_dcache_save_wdata.read();
3812	hit = true;
3813	}
3814
3815	if ( hit ) // tlb hit
3816	{
3817	r_dcache_save_paddr = paddr;
3818	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3819	}
3820	else // tlb miss
3821	{
3822
3823	#ifdef INSTRUMENTATION
3824	m_cpt_dtlb_miss++;
3825	#endif
3826	r_dcache_tlb_ins = false; // dtlb
3827	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3828	r_dcache_fsm = DCACHE_TLB_MISS;
3829	}
3830
3831	#if DEBUG_DCACHE
3832	if ( m_debug_activated )
3833	{
3834	std::cout << " <PROC " << name()
3835	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3836	<< " / VADDR = " << r_dcache_save_wdata.read()
3837	<< " / PADDR = " << paddr << std::endl;
3838	}
3839	#endif
3840
3841	break;
3842	}
3843	////////////////////////////
3844	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3845	// requires 2 cycles: read cache / inval cache
3846	// In this state we read dcache.
3847	{
3848	size_t way;
3849	size_t set;
3850	size_t word;
3851	int state;
3852
3853	#ifdef INSTRUMENTATION
3854	m_cpt_dcache_dir_read++;
3855	#endif
3856	r_dcache.read_dir( r_dcache_save_paddr.read(),
3857	&state,
3858	&way,
3859	&set,
3860	&word );
3861
3862	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3863	{
3864	r_dcache_xtn_way = way;
3865	r_dcache_xtn_set = set;
3866	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3867	}
3868	else // miss : nothing to do
3869	{
3870	r_dcache_fsm = DCACHE_IDLE;
3871	m_drsp.valid = true;
3872	}
3873
3874	#if DEBUG_DCACHE
3875	if ( m_debug_activated )
3876	{
3877	std::cout << " <PROC " << name()
3878	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3879	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3880	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3881	<< " / SET = " << set
3882	<< " / WAY = " << way << std::endl;
3883	}
3884	#endif
3885	break;
3886	}
3887	////////////////////////////
3888	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3889	// Blocked if previous cleanup not completed
3890	// Test if itlb or dtlb inval is required
3891	{
3892	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3893	{
3894	size_t way = r_dcache_xtn_way.read();
3895	size_t set = r_dcache_xtn_set.read();
3896	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3897
3898	#ifdef INSTRUMENTATION
3899	m_cpt_dcache_dir_write++;
3900	#endif
3901	r_dcache.write_dir( way,
3902	set,
3903	CACHE_SLOT_STATE_ZOMBI );
3904
3905	// request cleanup
3906	r_dcache_cc_send_req = true;
3907	r_dcache_cc_send_nline = nline;
3908	r_dcache_cc_send_way = way;
3909	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3910
3911	// possible itlb & dtlb invalidate
3912	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3913	{
3914	r_dcache_tlb_inval_line = nline;
3915	r_dcache_tlb_inval_set = 0;
3916	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3917	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3918	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3919	}
3920	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3921	{
3922	r_itlb.reset();
3923	r_dtlb.reset();
3924	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3925	r_dcache_fsm = DCACHE_IDLE;
3926	m_drsp.valid = true;
3927	}
3928	else
3929	{
3930	r_dcache_fsm = DCACHE_IDLE;
3931	m_drsp.valid = true;
3932	}
3933
3934	#if DEBUG_DCACHE
3935	if ( m_debug_activated )
3936	{
3937	std::cout << " <PROC " << name()
3938	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3939	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3940	}
3941	#endif
3942	}
3943	break;
3944	}
3945	//////////////////////////////
3946	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3947	{
3948	r_dcache_fsm = DCACHE_IDLE;
3949	m_drsp.valid = true;
3950	break;
3951	}
3952	////////////////////////
3953	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3954	// if previous cleanup has been sent.
3955	// Waiting in this state if no slot available
3956	// Set the r_dcache_cleanup_req flip-flop
3957	// and the r_dcache_miss_clack flip-flop
3958	// when a cleanup is required
3959	{
3960	if ( m_dreq.valid) m_cost_data_miss_frz++;
3961
3962	// coherence clack request (from DSPIN CLACK)
3963	if ( r_dcache_clack_req.read() )
3964	{
3965	r_dcache_fsm = DCACHE_CC_CHECK;
3966	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3967	break;
3968	}
3969
3970	// coherence request (from CC_RECEIVE FSM)
3971	if ( r_cc_receive_dcache_req.read() )
3972	{
3973	r_dcache_fsm = DCACHE_CC_CHECK;
3974	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3975	break;
3976	}
3977
3978	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3979	{
3980	bool found = false;
3981	bool cleanup = false;
3982	size_t way = 0;
3983	size_t set = 0;
3984	paddr_t victim = 0;
3985
3986	#ifdef INSTRUMENTATION
3987	m_cpt_dcache_dir_read++;
3988	#endif
3989	r_dcache.read_select( r_dcache_save_paddr.read(),
3990	&victim,
3991	&way,
3992	&set,
3993	&found,
3994	&cleanup );
3995
3996	if ( found )
3997	{
3998	r_dcache_miss_way = way;
3999	r_dcache_miss_set = set;
4000
4001	if ( cleanup )
4002	{
4003	r_dcache_miss_clack = true;
4004	r_dcache_fsm = DCACHE_MISS_CLEAN;
4005	// request cleanup
4006	r_dcache_cc_send_req = true;
4007	r_dcache_cc_send_nline = victim;
4008	r_dcache_cc_send_way = way;
4009	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4010	}
4011	else
4012	{
4013	r_dcache_fsm = DCACHE_MISS_WAIT;
4014	}
4015
4016	#if DEBUG_DCACHE
4017	if ( m_debug_activated )
4018	{
4019	std::cout << " <PROC " << name()
4020	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4021	<< " / WAY = " << way
4022	<< " / SET = " << set
4023	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4024	if(cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4025	else std::cout << std::endl;
4026	}
4027	#endif
4028	} // end found
4029	}
4030	break;
4031	}
4032	///////////////////////
4033	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4034	// and possibly request itlb or dtlb invalidate
4035	{
4036	if ( m_dreq.valid) m_cost_data_miss_frz++;
4037
4038	size_t way = r_dcache_miss_way.read();
4039	size_t set = r_dcache_miss_set.read();
4040
4041	#ifdef INSTRUMENTATION
4042	m_cpt_dcache_dir_read++;
4043	#endif
4044	r_dcache.write_dir( way,
4045	set,
4046	CACHE_SLOT_STATE_ZOMBI );
4047	#if DEBUG_DCACHE
4048	if ( m_debug_activated )
4049	{
4050	std::cout << " <PROC " << name()
4051	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4052	<< " / way = " << way
4053	<< " / set = " << set << std::endl;
4054	}
4055	#endif
4056	// if selective itlb & dtlb invalidate are required
4057	// the miss response is not handled before invalidate completed
4058	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
4059	{
4060	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4061	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
4062	r_dcache_tlb_inval_set = 0;
4063	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4064	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4065	}
4066	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
4067	{
4068	r_itlb.reset();
4069	r_dtlb.reset();
4070	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4071	r_dcache_fsm = DCACHE_MISS_WAIT;
4072	}
4073	else
4074	{
4075	r_dcache_fsm = DCACHE_MISS_WAIT;
4076	}
4077	break;
4078	}
4079	//////////////////////
4080	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4081	// This state is in charge of error signaling
4082	// There is 5 types of error depending on the requester
4083	{
4084	if ( m_dreq.valid) m_cost_data_miss_frz++;
4085
4086	// coherence clack request (from DSPIN CLACK)
4087	if ( r_dcache_clack_req.read() )
4088	{
4089	r_dcache_fsm = DCACHE_CC_CHECK;
4090	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4091	break;
4092	}
4093
4094	// coherence request (from CC_RECEIVE FSM)
4095	if ( r_cc_receive_dcache_req.read() )
4096	{
4097	r_dcache_fsm = DCACHE_CC_CHECK;
4098	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4099	break;
4100	}
4101
4102	if ( r_vci_rsp_data_error.read() ) // bus error
4103	{
4104	switch ( r_dcache_miss_type.read() )
4105	{
4106	case PROC_MISS:
4107	{
4108	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4109	r_mmu_dbvar = r_dcache_save_vaddr.read();
4110	m_drsp.valid = true;
4111	m_drsp.error = true;
4112	r_dcache_fsm = DCACHE_IDLE;
4113	break;
4114	}
4115	case PTE1_MISS:
4116	{
4117	if ( r_dcache_tlb_ins.read() )
4118	{
4119	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4120	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4121	r_icache_tlb_miss_req = false;
4122	r_icache_tlb_rsp_error = true;
4123	}
4124	else
4125	{
4126	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4127	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4128	m_drsp.valid = true;
4129	m_drsp.error = true;
4130	}
4131	r_dcache_fsm = DCACHE_IDLE;
4132	break;
4133	}
4134	case PTE2_MISS:
4135	{
4136	if ( r_dcache_tlb_ins.read() )
4137	{
4138	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4139	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4140	r_icache_tlb_miss_req = false;
4141	r_icache_tlb_rsp_error = true;
4142	}
4143	else
4144	{
4145	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4146	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4147	m_drsp.valid = true;
4148	m_drsp.error = true;
4149	}
4150	r_dcache_fsm = DCACHE_IDLE;
4151	break;
4152	}
4153	} // end switch type
4154	r_vci_rsp_data_error = false;
4155	}
4156	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4157	{
4158	r_dcache_miss_word = 0;
4159	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4160	}
4161	break;
4162	}
4163	//////////////////////////
4164	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4165	{
4166	if ( m_dreq.valid) m_cost_data_miss_frz++;
4167
4168	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4169	{
4170	#ifdef INSTRUMENTATION
4171	m_cpt_dcache_data_write++;
4172	#endif
4173	r_dcache.write( r_dcache_miss_way.read(),
4174	r_dcache_miss_set.read(),
4175	r_dcache_miss_word.read(),
4176	r_vci_rsp_fifo_dcache.read() );
4177	#if DEBUG_DCACHE
4178	if ( m_debug_activated )
4179	{
4180	std::cout << " <PROC " << name()
4181	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4182	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4183	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4184	<< " / SET = " << r_dcache_miss_set.read()
4185	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4186	}
4187	#endif
4188	vci_rsp_fifo_dcache_get = true;
4189	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4190
4191	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4192	{
4193	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4194	}
4195	}
4196	break;
4197	}
4198	//////////////////////////
4199	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4200	// and the cleanup ack has not been received,
4201	// as indicated by the r_dcache_miss clack.
4202	// - If no matching coherence request (r_dcache_inval_miss)
4203	// switch directory slot to VALID state.
4204	// - If matching coherence request, switch directory slot
4205	// to ZOMBI state, and send a cleanup request.
4206	{
4207	if ( m_dreq.valid) m_cost_data_miss_frz++;
4208
4209	// coherence clack request (from DSPIN CLACK)
4210	if ( r_dcache_clack_req.read() )
4211	{
4212	r_dcache_fsm = DCACHE_CC_CHECK;
4213	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4214	break;
4215	}
4216
4217	// coherence request (from CC_RECEIVE FSM)
4218	if ( r_cc_receive_dcache_req.read() )
4219	{
4220	r_dcache_fsm = DCACHE_CC_CHECK;
4221	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4222	break;
4223	}
4224
4225	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4226	{
4227	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4228	{
4229	if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
4230	{
4231	r_dcache_miss_inval = false;
4232	// request cleanup
4233	r_dcache_cc_send_req = true;
4234	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4235	r_dcache_cc_send_way = r_dcache_miss_way.read();
4236	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4237
4238	#ifdef INSTRUMENTATION
4239	m_cpt_dcache_dir_write++;
4240	#endif
4241	r_dcache.write_dir( r_dcache_save_paddr.read(),
4242	r_dcache_miss_way.read(),
4243	r_dcache_miss_set.read(),
4244	CACHE_SLOT_STATE_ZOMBI );
4245	#if DEBUG_DCACHE
4246	if ( m_debug_activated )
4247	std::cout << " <PROC " << name()
4248	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4249	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4250	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4251	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4252	#endif
4253	}
4254	else
4255	break;
4256	}
4257	else // switch slot to VALID state
4258	{
4259
4260	#ifdef INSTRUMENTATION
4261	m_cpt_dcache_dir_write++;
4262	#endif
4263	r_dcache.write_dir( r_dcache_save_paddr.read(),
4264	r_dcache_miss_way.read(),
4265	r_dcache_miss_set.read(),
4266	CACHE_SLOT_STATE_VALID );
4267
4268	#if DEBUG_DCACHE
4269	if ( m_debug_activated )
4270	std::cout << " <PROC " << name()
4271	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4272	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4273	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4274	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4275	#endif
4276	// reset directory extension
4277	size_t way = r_dcache_miss_way.read();
4278	size_t set = r_dcache_miss_set.read();
4279	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4280	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4281	}
4282	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4283	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4284	else r_dcache_fsm = DCACHE_IDLE;
4285	}
4286	break;
4287	}
4288	/////////////////////
4289	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4290	{
4291	// coherence clack request (from DSPIN CLACK)
4292	if ( r_dcache_clack_req.read() )
4293	{
4294	r_dcache_fsm = DCACHE_CC_CHECK;
4295	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4296	break;
4297	}
4298
4299	// coherence request (from CC_RECEIVE FSM)
4300	if ( r_cc_receive_dcache_req.read() )
4301	{
4302	r_dcache_fsm = DCACHE_CC_CHECK;
4303	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4304	break;
4305	}
4306
4307	if ( r_vci_rsp_data_error.read() ) // bus error
4308	{
4309	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4310	r_mmu_dbvar = m_dreq.addr;
4311	r_vci_rsp_data_error = false;
4312	m_drsp.error = true;
4313	m_drsp.valid = true;
4314	r_dcache_fsm = DCACHE_IDLE;
4315	break;
4316	}
4317	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4318	{
4319	// consume data
4320	vci_rsp_fifo_dcache_get = true;
4321	r_dcache_fsm = DCACHE_IDLE;
4322
4323	// acknowledge the processor request if it has not been modified
4324	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4325	{
4326	m_drsp.valid = true;
4327	m_drsp.error = false;
4328	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4329	}
4330	}
4331	break;
4332	}
4333	/////////////////////
4334	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4335	{
4336	// coherence clack request (from DSPIN CLACK)
4337	if ( r_dcache_clack_req.read() )
4338	{
4339	r_dcache_fsm = DCACHE_CC_CHECK;
4340	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4341	break;
4342	}
4343
4344	// coherence request (from CC_RECEIVE FSM)
4345	if ( r_cc_receive_dcache_req.read() )
4346	{
4347	r_dcache_fsm = DCACHE_CC_CHECK;
4348	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4349	break;
4350	}
4351
4352	if ( r_vci_rsp_data_error.read() ) // bus error
4353	{
4354	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4355	r_mmu_dbvar = m_dreq.addr;
4356	r_vci_rsp_data_error = false;
4357	m_drsp.error = true;
4358	m_drsp.valid = true;
4359	r_dcache_fsm = DCACHE_IDLE;
4360	break;
4361	}
4362	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4363	{
4364	// consume data
4365	vci_rsp_fifo_dcache_get = true;
4366
4367	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4368	{
4369	// set key value in llsc reservation buffer
4370	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4371	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4372	}
4373	else // last flit
4374	{
4375	// acknowledge the processor request if it has not been modified
4376	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4377	{
4378	m_drsp.valid = true;
4379	m_drsp.error = false;
4380	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4381	}
4382	r_dcache_fsm = DCACHE_IDLE;
4383	}
4384	}
4385	break;
4386	}
4387	////////////////////
4388	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4389	{
4390	// coherence clack request (from DSPIN CLACK)
4391	if ( r_dcache_clack_req.read() )
4392	{
4393	r_dcache_fsm = DCACHE_CC_CHECK;
4394	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4395	break;
4396	}
4397
4398	// coherence request (from CC_RECEIVE FSM)
4399	if ( r_cc_receive_dcache_req.read() )
4400	{
4401	r_dcache_fsm = DCACHE_CC_CHECK;
4402	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4403	break;
4404	}
4405
4406	if ( r_vci_rsp_data_error.read() ) // bus error
4407	{
4408	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4409	r_mmu_dbvar = m_dreq.addr;
4410	r_vci_rsp_data_error = false;
4411	m_drsp.error = true;
4412	m_drsp.valid = true;
4413	r_dcache_fsm = DCACHE_IDLE;
4414	break;
4415	}
4416	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4417	{
4418	// consume response
4419	vci_rsp_fifo_dcache_get = true;
4420	m_drsp.valid = true;
4421	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4422	r_dcache_fsm = DCACHE_IDLE;
4423	}
4424	break;
4425	}
4426	//////////////////////////
4427	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4428	// before handling a processor WRITE or SC request
4429	// Input argument is r_dcache_dirty_paddr
4430	// In this first state, we get PTE value in dcache
4431	// and post a CAS request to CMD FSM
4432	{
4433	// get PTE in dcache
4434	uint32_t pte;
4435	size_t way;
4436	size_t set;
4437	size_t word; // unused
4438	int state;
4439
4440	#ifdef INSTRUMENTATION
4441	m_cpt_dcache_data_read++;
4442	m_cpt_dcache_dir_read++;
4443	#endif
4444	r_dcache.read( r_dcache_dirty_paddr.read(),
4445	&pte,
4446	&way,
4447	&set,
4448	&word,
4449	&state );
4450
4451	assert( (state == CACHE_SLOT_STATE_VALID) and
4452	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4453
4454	// request CAS transaction to CMD_FSM
4455	r_dcache_dirty_way = way;
4456	r_dcache_dirty_set = set;
4457
4458	// check llsc reservation buffer
4459	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4460	r_dcache_llsc_valid = false;
4461
4462	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4463	r_dcache_vci_cas_req = true;
4464	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4465	r_dcache_vci_cas_old = pte;
4466	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4467	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4468
4469	#if DEBUG_DCACHE
4470	if ( m_debug_activated )
4471	{
4472	std::cout << " <PROC " << name()
4473	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4474	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4475	<< " / PTE_VALUE = " << pte << std::dec
4476	<< " / SET = " << set
4477	<< " / WAY = " << way << std::endl;
4478	}
4479	#endif
4480	break;
4481	}
4482	///////////////////////
4483	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4484	// and return to IDLE state when response is received.
4485	// we don't care if the CAS is a failure:
4486	// - if the CAS is a success, the coherence mechanism
4487	// updates the local copy.
4488	// - if the CAS is a failure, we just retry the write.
4489	{
4490	// coherence clack request (from DSPIN CLACK)
4491	if ( r_dcache_clack_req.read() )
4492	{
4493	r_dcache_fsm = DCACHE_CC_CHECK;
4494	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4495	break;
4496	}
4497
4498	// coherence request (from CC_RECEIVE FSM)
4499	if ( r_cc_receive_dcache_req.read() )
4500	{
4501	r_dcache_fsm = DCACHE_CC_CHECK;
4502	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4503	break;
4504	}
4505
4506	if ( r_vci_rsp_data_error.read() ) // bus error
4507	{
4508	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4509	std::cout << "This should not happen in this state" << std::endl;
4510	exit(0);
4511	}
4512	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4513	{
4514	vci_rsp_fifo_dcache_get = true;
4515	r_dcache_fsm = DCACHE_IDLE;
4516
4517	#if DEBUG_DCACHE
4518	if ( m_debug_activated )
4519	{
4520	std::cout << " <PROC " << name()
4521	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4522	}
4523	#endif
4524	}
4525	break;
4526	}
4527	/////////////////////
4528	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4529	// handling coherence requests for DCACHE.
4530	// If there is a matching pending miss on the modified cache
4531	// line this is signaled in the r_dcache_miss inval flip-flop.
4532	// If the updated (or invalidated) cache line has copies in TLBs
4533	// these TLB copies are invalidated.
4534	// The return state is defined in r_dcache_fsm_cc_save
4535	{
4536	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4537	paddr_t mask = ~((m_dcache_words<<2)-1);
4538
4539	#if DEBUG_DCACHE
4540	if ( m_debug_activated )
4541	{
4542	std::cout << " <PROC " << name()
4543	<< " DCACHE_CC_CHECK> paddr = " << paddr
4544	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4545	<< " mask = " << mask
4546	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = "
4547	<< (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4548	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = "
4549	<< (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4550	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = "
4551	<< ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4552	<<std::endl;
4553	}
4554	#endif
4555
4556	if ( r_dcache_clack_req.read() )
4557	// We switch the directory slot to EMPTY state
4558	// and reset r_icache_miss_clack if the cleanup ack
4559	// is matching a pending miss.
4560	{
4561
4562	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4563
4564	#ifdef INSTRUMENTATION
4565	m_cpt_dcache_dir_write++;
4566	#endif
4567	r_dcache.write_dir( 0,
4568	r_dcache_clack_way.read(),
4569	r_dcache_clack_set.read(),
4570	CACHE_SLOT_STATE_EMPTY);
4571
4572	if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4573	(r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
4574	r_dcache_miss_clack = false;
4575
4576	r_dcache_clack_req = false;
4577	#if DEBUG_DCACHE
4578	if ( m_debug_activated )
4579	{
4580	std::cout << " <PROC " << name()
4581	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4582	<< " set = " << r_dcache_clack_set.read()
4583	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4584	}
4585	#endif
4586	if ( not r_cc_receive_dcache_req.read() )
4587	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4588
4589	break;
4590	}
4591	else if( r_cc_receive_dcache_req.read() and
4592	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4593	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4594	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4595	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4596	{
4597	// signaling matching
4598	r_dcache_miss_inval = true;
4599
4600	// in case of update, go to CC_UPDT
4601	// JUST TO POP THE FIFO
4602	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4603	{
4604	r_dcache_fsm = DCACHE_CC_UPDT;
4605	r_dcache_cc_word = r_cc_receive_word_idx.read();
4606	// just pop the fifo , don't write in icache
4607	r_dcache_cc_need_write = false;
4608	}
4609	// the request is dealt with
4610	else
4611	{
4612	r_cc_receive_dcache_req = false;
4613	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4614	}
4615
4616	#if DEBUG_DCACHE
4617	if ( m_debug_activated )
4618	{
4619	std::cout << " <PROC " << name()
4620	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4621	<< " PADDR = " << std::hex << paddr << std::endl;
4622	}
4623	#endif
4624
4625	}
4626	else // no match
4627	{
4628	int state = 0;
4629	size_t way = 0;
4630	size_t set = 0;
4631	size_t word = 0;
4632
4633	#ifdef INSTRUMENTATION
4634	m_cpt_dcache_dir_read++;
4635	#endif
4636	r_dcache.read_dir( paddr,
4637	&state,
4638	&way,
4639	&set,
4640	&word ); // unused
4641
4642	r_dcache_cc_way = way;
4643	r_dcache_cc_set = set;
4644
4645	if ( state == CACHE_SLOT_STATE_VALID) // hit
4646	{
4647	// need to update the cache state
4648	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4649	{
4650	r_dcache_cc_need_write = true;
4651	r_dcache_fsm = DCACHE_CC_UPDT;
4652	r_dcache_cc_word = r_cc_receive_word_idx.read();
4653	}
4654	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval
4655	{
4656	r_dcache_fsm = DCACHE_CC_INVAL;
4657	}
4658	}
4659	else // miss
4660	{
4661	// multicast acknowledgement required in case of update
4662	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4663	{
4664	r_dcache_fsm = DCACHE_CC_UPDT;
4665	r_dcache_cc_word = r_cc_receive_word_idx.read();
4666	// just pop the fifo , don't write in icache
4667	r_dcache_cc_need_write = false;
4668	}
4669	else // No response needed
4670	{
4671	r_cc_receive_dcache_req = false;
4672	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4673	}
4674	}
4675
4676	#if DEBUG_DCACHE
4677	if ( m_debug_activated )
4678	{
4679	std::cout << " <PROC " << name()
4680	<< " DCACHE_CC_CHECK> Coherence request received:"
4681	<< " PADDR = " << std::hex << paddr
4682	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4683	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4684	}
4685	#endif
4686	}
4687	break;
4688	}
4689	/////////////////////
4690	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4691	// after possible invalidation of copies in TLBs
4692	{
4693	size_t way = r_dcache_cc_way.read();
4694	size_t set = r_dcache_cc_set.read();
4695
4696	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4697	{
4698	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4699	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4700	r_dcache_tlb_inval_set = 0;
4701	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4702	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4703	break;
4704	}
4705
4706	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4707	{
4708	r_itlb.reset();
4709	r_dtlb.reset();
4710	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4711
4712	#if DEBUG_DCACHE
4713	if ( m_debug_activated )
4714	{
4715	std::cout << " <PROC " << name()
4716	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4717	}
4718	#endif
4719	}
4720
4721	if ( not r_dcache_cc_send_req.read() ) // cc_send is available
4722	{
4723	r_dcache.write_dir( 0,
4724	way,
4725	set,
4726	CACHE_SLOT_STATE_ZOMBI );
4727
4728	#if DEBUG_DCACHE
4729	if ( m_debug_activated )
4730	{
4731	std::cout << " <PROC " << name()
4732	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4733	<< " / WAY = " << way
4734	<< " / SET = " << set << std::endl;
4735	}
4736	#endif
4737	// coherence request completed
4738	r_cc_receive_dcache_req = false;
4739	r_dcache_cc_send_req = true;
4740	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4741	r_dcache_cc_send_way = r_dcache_cc_way.read();
4742	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4743
4744	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4745	}
4746	//else go to DCACHE_CC_CHECK
4747	else
4748	r_dcache_fsm = DCACHE_CC_CHECK;
4749
4750	break;
4751	}
4752	///////////////////
4753	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4754	// after possible invalidation of copies in TLBs
4755	{
4756	size_t word = r_dcache_cc_word.read();
4757	size_t way = r_dcache_cc_way.read();
4758	size_t set = r_dcache_cc_set.read();
4759
4760	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4761	{
4762	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4763	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4764	r_dcache_tlb_inval_set = 0;
4765	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4766	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4767	break;
4768	}
4769
4770	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4771	{
4772	r_itlb.reset();
4773	r_dtlb.reset();
4774	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4775
4776	#if DEBUG_DCACHE
4777	if ( m_debug_activated )
4778	{
4779	std::cout << " <PROC " << name()
4780	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4781	}
4782	#endif
4783	}
4784
4785	if ( (not r_dcache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok())
4786	{
4787	if (r_dcache_cc_need_write.read())
4788	{
4789
4790	#ifdef INSTRUMENTATION
4791	m_cpt_dcache_data_write++;
4792	#endif
4793	r_dcache.write( way,
4794	set,
4795	word,
4796	r_cc_receive_updt_fifo_data.read(),
4797	r_cc_receive_updt_fifo_be.read() );
4798
4799	r_dcache_cc_word = word + 1;
4800
4801	#if DEBUG_DCACHE
4802	if ( m_debug_activated )
4803	{
4804	std::cout << " <PROC " << name()
4805	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4806	<< " / WAY = " << way
4807	<< " / SET = " << set
4808	<< " / WORD = " << word
4809	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4810	}
4811	#endif
4812	}
4813
4814	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4815	{
4816	// no need to write in the cache anymore
4817	r_dcache_cc_need_write = false;
4818
4819	// coherence request completed
4820	r_cc_receive_dcache_req = false;
4821
4822	// request multicast acknowledgement
4823	r_dcache_cc_send_req = true;
4824	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4825	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4826	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4827
4828	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4829	}
4830
4831	//consume fifo if not eop
4832	cc_receive_updt_fifo_get = true;
4833	}
4834	else
4835	r_dcache_fsm = DCACHE_CC_CHECK;
4836
4837	break;
4838	}
4839	///////////////////////////
4840	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4841	// It makes assumption: m_itlb_sets == m_dtlb_sets
4842	// All ways are handled in parallel.
4843	// We enter this state when a DCACHE line is modified,
4844	// and there is a copy in itlb or dtlb.
4845	// It can be caused by:
4846	// - a coherence inval or updt transaction,
4847	// - a line inval caused by a cache miss
4848	// - a processor XTN inval request,
4849	// - a WRITE hit,
4850	// - a Dirty bit update
4851	// Input arguments are:
4852	// - r_dcache_tlb_inval_line
4853	// - r_dcache_tlb_inval_set
4854	// - r_dcache_fsm_scan_save
4855	{
4856	paddr_t line = r_dcache_tlb_inval_line.read();
4857	size_t set = r_dcache_tlb_inval_set.read();
4858	size_t way;
4859	bool ok;
4860
4861	for ( way = 0 ; way < m_itlb_ways ; way++ )
4862	{
4863	ok = r_itlb.inval( line, way, set );
4864
4865	#if DEBUG_DCACHE
4866	if ( m_debug_activated and ok )
4867	{
4868	std::cout << " <PROC " << name()
4869	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4870	<< " line = " << line << std::dec
4871	<< " / set = " << set
4872	<< " / way = " << way << std::endl;
4873	}
4874	#endif
4875	}
4876
4877	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4878	{
4879	ok = r_dtlb.inval( line, way, set );
4880
4881	#if DEBUG_DCACHE
4882	if ( m_debug_activated and ok )
4883	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
4884	<< " Invalidate DTLB entry" << std::hex
4885	<< " / line = " << line << std::dec
4886	<< " / set = " << set
4887	<< " / way = " << way << std::endl;
4888	#endif
4889	}
4890
4891	// return to the calling state when TLB inval completed
4892	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4893	{
4894	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4895	}
4896	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4897	break;
4898	}
4899	} // end switch r_dcache_fsm
4900
4901	///////////////// wbuf update ///////////////////////////////////////////////////////
4902	r_wbuf.update();
4903
4904	///////////////// llsc update ///////////////////////////////////////////////////////
4905	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4906	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4907
4908	//////////////// test processor frozen //////////////////////////////////////////////
4909	// The simulation exit if the number of consecutive frozen cycles
4910	// is larger than the m_max_frozen_cycles (constructor parameter)
4911	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4912	{
4913	m_cpt_frz_cycles++; // used for instrumentation
4914	m_cpt_stop_simulation++; // used for debug
4915	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4916	{
4917	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4918	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4919	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4920	<< std::endl;
4921	r_iss.dump();
4922	exit(1);
4923	}
4924	}
4925	else
4926	{
4927	m_cpt_stop_simulation = 0;
4928	}
4929
4930	/////////// execute one iss cycle /////////////////////////////////
4931	{
4932	uint32_t it = 0;
4933	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4934	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4935	}
4936
4937	////////////////////////////////////////////////////////////////////////////
4938	// The VCI_CMD FSM controls the following ressources:
4939	// - r_vci_cmd_fsm
4940	// - r_vci_cmd_min
4941	// - r_vci_cmd_max
4942	// - r_vci_cmd_cpt
4943	// - r_vci_cmd_imiss_prio
4944	// - wbuf (reset)
4945	// - r_icache_miss_req (reset)
4946	// - r_icache_unc_req (reset)
4947	// - r_dcache_vci_miss_req (reset)
4948	// - r_dcache_vci_unc_req (reset)
4949	// - r_dcache_vci_ll_req (reset)
4950	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4951	// - r_dcache_vci_cas_req (reset)
4952	//
4953	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4954	// There are 8 request types, with the following priorities :
4955	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4956	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4957	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4958	// 4 - Instruction Uncachable : r_icache_unc_req
4959	// 5 - Data Write : r_wbuf.rok()
4960	// 6 - Data Linked Load : r_dcache_vci_ll_req
4961	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4962	// 8 - Compare And Swap : r_dcache_vci_cas_req
4963	//
4964	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4965	// and the VCI_RSP_FSM are fully desynchronized.
4966	//
4967	// VCI formats:
4968	// According to the VCI advanced specification, all read requests packets
4969	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4970	// are one word packets.
4971	// For write burst packets, all words are in the same cache line,
4972	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4973	// The sc command packet implements actually a compare-and-swap mechanism
4974	// and the packet contains two flits.
4975	////////////////////////////////////////////////////////////////////////////////////
4976
4977
4978	switch ( r_vci_cmd_fsm.read() )
4979	{
4980	//////////////
4981	case CMD_IDLE:
4982	{
4983	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4984	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4985	// to check a possible pending write on the same cache line.
4986	// As there is only one possible access per cycle to write buffer, we implement
4987	// a round-robin priority between DCACHE and ICACHE for this access,
4988	// using the r_vci_cmd_imiss_prio flip-flop.
4989
4990	size_t wbuf_min;
4991	size_t wbuf_max;
4992
4993	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4994	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4995
4996	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4997	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4998
4999	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5000	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5001
5002	bool icache_miss_req = r_icache_miss_req.read() and
5003	( not (r_dcache_vci_miss_req.read() or
5004	r_dcache_vci_ll_req.read() or
5005	r_dcache_vci_unc_req.read())
5006	or r_vci_cmd_imiss_prio.read() );
5007
5008	// 1 - Data Read Miss
5009	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
5010	{
5011	r_vci_cmd_fsm = CMD_DATA_MISS;
5012	r_dcache_vci_miss_req = false;
5013	r_vci_cmd_imiss_prio = true;
5014	// m_cpt_dmiss_transaction++;
5015	}
5016	// 2 - Data Read Uncachable
5017	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5018	{
5019	r_vci_cmd_fsm = CMD_DATA_UNC;
5020	r_dcache_vci_unc_req = false;
5021	// m_cpt_dunc_transaction++;
5022	}
5023	// 3 - Data Linked Load
5024	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5025	{
5026	r_dcache_vci_ll_req = false;
5027	r_vci_cmd_fsm = CMD_DATA_LL;
5028	// m_cpt_ll_transaction++;
5029	}
5030	// 4 - Instruction Miss
5031	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
5032	{
5033	r_vci_cmd_fsm = CMD_INS_MISS;
5034	r_icache_miss_req = false;
5035	r_vci_cmd_imiss_prio = false;
5036	// m_cpt_imiss_transaction++;
5037	}
5038	// 5 - Instruction Uncachable
5039	else if ( r_icache_unc_req.read() )
5040	{
5041	r_vci_cmd_fsm = CMD_INS_UNC;
5042	r_icache_unc_req = false;
5043	// m_cpt_iunc_transaction++;
5044	}
5045	// 6 - Data Write
5046	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
5047	{
5048	r_vci_cmd_fsm = CMD_DATA_WRITE;
5049	r_vci_cmd_cpt = wbuf_min;
5050	r_vci_cmd_min = wbuf_min;
5051	r_vci_cmd_max = wbuf_max;
5052	// m_cpt_write_transaction++;
5053	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
5054	}
5055	// 7 - Data Store Conditionnal
5056	else if ( r_dcache_vci_sc_req.read() )
5057	{
5058	r_dcache_vci_sc_req = false;
5059	r_vci_cmd_cpt = 0;
5060	r_vci_cmd_fsm = CMD_DATA_SC;
5061	// m_cpt_sc_transaction++;
5062	}
5063	// 8 - Compare And Swap
5064	else if ( r_dcache_vci_cas_req.read() )
5065	{
5066	r_vci_cmd_fsm = CMD_DATA_CAS;
5067	r_dcache_vci_cas_req = false;
5068	r_vci_cmd_cpt = 0;
5069	// m_cpt_cas_transaction++;
5070	}
5071
5072	#if DEBUG_CMD
5073	if ( m_debug_activated )
5074	{
5075	std::cout << " <PROC " << name() << " CMD_IDLE>"
5076	<< " / dmiss_req = " << dcache_miss_req
5077	<< " / imiss_req = " << icache_miss_req
5078	<< std::endl;
5079	}
5080	#endif
5081	break;
5082	}
5083	////////////////////
5084	case CMD_DATA_WRITE:
5085	{
5086	if ( p_vci.cmdack.read() )
5087	{
5088	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5089	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5090	{
5091	r_vci_cmd_fsm = CMD_IDLE ;
5092	r_wbuf.sent() ;
5093	}
5094	}
5095	break;
5096	}
5097	/////////////////
5098	case CMD_DATA_SC:
5099	case CMD_DATA_CAS:
5100	{
5101	// The CAS and SC VCI commands contain two flits
5102	if ( p_vci.cmdack.read() )
5103	{
5104	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5105	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5106	}
5107	break;
5108	}
5109	//////////////////
5110	case CMD_INS_MISS:
5111	case CMD_INS_UNC:
5112	case CMD_DATA_MISS:
5113	case CMD_DATA_UNC:
5114	case CMD_DATA_LL:
5115	{
5116	// all read VCI commands contain one single flit
5117	if ( p_vci.cmdack.read() ) {
5118	r_vci_cmd_fsm = CMD_IDLE;
5119	}
5120	break;
5121	}
5122
5123	} // end switch r_vci_cmd_fsm
5124
5125	//////////////////////////////////////////////////////////////////////////
5126	// The VCI_RSP FSM controls the following ressources:
5127	// - r_vci_rsp_fsm:
5128	// - r_vci_rsp_fifo_icache (push)
5129	// - r_vci_rsp_fifo_dcache (push)
5130	// - r_vci_rsp_data_error (set)
5131	// - r_vci_rsp_ins_error (set)
5132	// - r_vci_rsp_cpt
5133	// - r_dcache_vci_sc_req (reset when SC response recieved)
5134	//
5135	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5136	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5137	// to identify the transactions.
5138	//
5139	// VCI vormat:
5140	// This component checks the response packet length and accepts only
5141	// single word packets for write response packets.
5142	//
5143	// Error handling:
5144	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5145	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5146	// flip_flop and the error is signaled by the DCACHE FSM.
5147	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5148	// flip_flop and the error is signaled by the ICACHE FSM.
5149	// In case of Cleanup Error, the simulation stops with an error message...
5150	//////////////////////////////////////////////////////////////////////////
5151
5152	switch ( r_vci_rsp_fsm.read() )
5153	{
5154	//////////////
5155	case RSP_IDLE:
5156	{
5157	if ( p_vci.rspval.read() )
5158	{
5159	r_vci_rsp_cpt = 0;
5160
5161	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5162	{
5163	r_vci_rsp_fsm = RSP_DATA_UNC;
5164	}
5165	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5166	{
5167	r_vci_rsp_fsm = RSP_DATA_MISS;
5168	}
5169	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5170	{
5171	r_vci_rsp_fsm = RSP_INS_UNC;
5172	}
5173	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5174	{
5175	r_vci_rsp_fsm = RSP_INS_MISS;
5176	}
5177	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5178	{
5179	r_vci_rsp_fsm = RSP_DATA_WRITE;
5180	}
5181	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5182	{
5183	r_vci_rsp_fsm = RSP_DATA_UNC;
5184	}
5185	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5186	{
5187	r_vci_rsp_fsm = RSP_DATA_LL;
5188	}
5189	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5190	{
5191	r_vci_rsp_fsm = RSP_DATA_UNC;
5192	}
5193	else
5194	{
5195	assert(false and "Unexpected VCI response");
5196	}
5197	}
5198	break;
5199	}
5200	//////////////////
5201	case RSP_INS_MISS:
5202	{
5203	if ( p_vci.rspval.read() )
5204	{
5205	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5206	{
5207	r_vci_rsp_ins_error = true;
5208	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5209	}
5210	else // no error reported
5211	{
5212	if ( r_vci_rsp_fifo_icache.wok() )
5213	{
5214	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5215	"The VCI response packet for instruction miss is too long" );
5216
5217	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5218	vci_rsp_fifo_icache_put = true,
5219	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5220	if ( p_vci.reop.read() )
5221	{
5222	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5223	"The VCI response packet for instruction miss is too short");
5224
5225	r_vci_rsp_fsm = RSP_IDLE;
5226	}
5227	}
5228	}
5229	}
5230	break;
5231	}
5232	/////////////////
5233	case RSP_INS_UNC:
5234	{
5235	if (p_vci.rspval.read() )
5236	{
5237	assert( p_vci.reop.read() and
5238	"illegal VCI response packet for uncachable instruction");
5239
5240	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5241	{
5242	r_vci_rsp_ins_error = true;
5243	r_vci_rsp_fsm = RSP_IDLE;
5244	}
5245	else // no error reported
5246	{
5247	if ( r_vci_rsp_fifo_icache.wok())
5248	{
5249	vci_rsp_fifo_icache_put = true;
5250	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5251	r_vci_rsp_fsm = RSP_IDLE;
5252	}
5253	}
5254	}
5255	break;
5256	}
5257	///////////////////
5258	case RSP_DATA_MISS:
5259	{
5260	if ( p_vci.rspval.read() )
5261	{
5262	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5263	{
5264	r_vci_rsp_data_error = true;
5265	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5266	}
5267	else // no error reported
5268	{
5269	if ( r_vci_rsp_fifo_dcache.wok() )
5270	{
5271	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5272	"The VCI response packet for data miss is too long");
5273
5274	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5275	vci_rsp_fifo_dcache_put = true,
5276	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5277	if ( p_vci.reop.read() )
5278	{
5279	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5280	"The VCI response packet for data miss is too short");
5281
5282	r_vci_rsp_fsm = RSP_IDLE;
5283	}
5284	}
5285	}
5286	}
5287	break;
5288	}
5289	//////////////////
5290	case RSP_DATA_UNC:
5291	{
5292	if (p_vci.rspval.read() )
5293	{
5294	assert( p_vci.reop.read() and
5295	"illegal VCI response packet for uncachable read data");
5296
5297	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5298	{
5299	r_vci_rsp_data_error = true;
5300	r_vci_rsp_fsm = RSP_IDLE;
5301	}
5302	else // no error reported
5303	{
5304	if ( r_vci_rsp_fifo_dcache.wok())
5305	{
5306	vci_rsp_fifo_dcache_put = true;
5307	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5308	r_vci_rsp_fsm = RSP_IDLE;
5309	}
5310	}
5311	}
5312	break;
5313	}
5314	/////////////////
5315	case RSP_DATA_LL:
5316	{
5317	if ( p_vci.rspval.read() )
5318	{
5319	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5320	{
5321	r_vci_rsp_data_error = true;
5322	r_vci_rsp_fsm = RSP_IDLE;
5323	break;
5324	}
5325	if (r_vci_rsp_cpt.read() == 0) //first flit
5326	{
5327	if(r_vci_rsp_fifo_dcache.wok())
5328	{
5329	assert(!p_vci.reop.read() &&
5330	"illegal VCI response packet for LL");
5331	vci_rsp_fifo_dcache_put = true;
5332	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5333	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5334	}
5335	break;
5336	}
5337	else // last flit
5338	{
5339	if(r_vci_rsp_fifo_dcache.wok())
5340	{
5341	assert(p_vci.reop.read() &&
5342	"illegal VCI response packet for LL");
5343	vci_rsp_fifo_dcache_put = true;
5344	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5345	r_vci_rsp_fsm = RSP_IDLE;
5346	}
5347	break;
5348	}
5349	}
5350	break;
5351	}
5352	////////////////////
5353	case RSP_DATA_WRITE:
5354	{
5355	if (p_vci.rspval.read())
5356	{
5357	assert( p_vci.reop.read() and
5358	"a VCI response packet must contain one flit for a write transaction");
5359
5360	r_vci_rsp_fsm = RSP_IDLE;
5361	uint32_t wbuf_index = p_vci.rtrdid.read();
5362	bool cacheable = r_wbuf.completed(wbuf_index);
5363	if ( not cacheable ) r_dcache_pending_unc_write = false;
5364	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5365	}
5366	break;
5367	}
5368	} // end switch r_vci_rsp_fsm
5369
5370	/////////////////////////////////////////////////////////////////////////////////////
5371	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5372	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5373	// and ICACHE FSM) that are served with a round-robin priority.
5374	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5375	// soon as the request has been sent.
5376	/////////////////////////////////////////////////////////////////////////////////////
5377	switch ( r_cc_send_fsm.read() )
5378	{
5379	///////////////////////////
5380	case CC_SEND_IDLE:
5381	{
5382	///////////////////////////////////////////////////////
5383	// handling round robin between icache and dcache : //
5384	// we first check for the last client and listen for //
5385	// a request of the other, then update the client //
5386	// r_cc_send_last_client : 0 dcache / 1 icache
5387	///////////////////////////////////////////////////////
5388	bool update_last_client = r_cc_send_last_client.read();
5389	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5390	{
5391	if (r_icache_cc_send_req.read()) // request from icache
5392	update_last_client = 1; // update last client to icache
5393	}
5394	else // last client was icache
5395	{
5396	if (r_dcache_cc_send_req.read()) // request from dcache
5397	update_last_client = 0; // update last client to dcache
5398	}
5399	r_cc_send_last_client = update_last_client;
5400
5401	// if there is an actual request
5402	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5403	{
5404	// the new client is dcache and has a cleanup request
5405	if ( (update_last_client == 0) and
5406	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5407	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5408	// the new client is dcache and has a multi acknowledgement request
5409	else if ( (update_last_client == 0) and
5410	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5411	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5412	// the new client is icache and has a cleanup request
5413	else if ( (update_last_client == 1) and
5414	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5415	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5416	// the new client is icache and has a multi acknowledgement request
5417	else if ( (update_last_client == 1) and
5418	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5419	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5420	}
5421	break;
5422	}
5423	///////////////////////////
5424	case CC_SEND_CLEANUP_1:
5425	{
5426	// wait for the first flit to be consumed
5427	if (p_dspin_p2m.read.read())
5428	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5429
5430	break;
5431	}
5432	///////////////////////////
5433	case CC_SEND_CLEANUP_2:
5434	{
5435	// wait for the second flit to be consumed
5436	if (p_dspin_p2m.read.read())
5437	{
5438	if (r_cc_send_last_client.read() == 0) // dcache active request
5439	r_dcache_cc_send_req = false; // reset dcache request
5440	else // icache active request
5441	r_icache_cc_send_req = false; // reset icache request
5442
5443	// go back to idle state
5444	r_cc_send_fsm = CC_SEND_IDLE;
5445	}
5446	break;
5447	}
5448	///////////////////////////
5449	case CC_SEND_MULTI_ACK:
5450	{
5451	// wait for the flit to be consumed
5452	if(p_dspin_p2m.read.read())
5453	{
5454	if(r_cc_send_last_client.read() == 0) // dcache active request
5455	r_dcache_cc_send_req = false; // reset dcache request
5456	else // icache active request
5457	r_icache_cc_send_req = false; // reset icache request
5458	// go back to idle state
5459	r_cc_send_fsm = CC_SEND_IDLE;
5460	}
5461	break;
5462	}
5463	} // end switch CC_SEND FSM
5464
5465	///////////////////////////////////////////////////////////////////////////////
5466	// CC_RECEIVE FSM
5467	// This FSM receive all coherence packets on a DSPIN40 port.
5468	// There is 5 packet types:
5469	// - CC_DATA_INVAL : DCACHE invalidate request
5470	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5471	// - CC_INST_INVAL : ICACHE invalidate request
5472	// - CC_INST_UPDT : ICACHE update request (multi-words)
5473	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5474	//////////////////////////////////////////////////////////////////////////////
5475	switch( r_cc_receive_fsm.read() )
5476	{
5477	/////////////////////
5478	case CC_RECEIVE_IDLE:
5479	{
5480	// a coherence request has arrived
5481	if (p_dspin_m2p.write.read())
5482	{
5483	// initialize dspin received data
5484	uint64_t receive_data = p_dspin_m2p.data.read();
5485	// initialize coherence packet type
5486	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5487	DspinDhccpParam::M2P_TYPE);
5488	// test for a broadcast
5489	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5490	{
5491	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5492	}
5493	// test for a multi updt
5494	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5495	{
5496	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5497	}
5498	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5499	{
5500	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5501	}
5502	// test for a multi inval
5503	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5504	{
5505	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5506	}
5507	else
5508	{
5509	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5510	}
5511	}
5512	break;
5513	}
5514	///////////////////////////////
5515	case CC_RECEIVE_BRDCAST_HEADER:
5516	{
5517	// no actual data in the HEADER, just skip to second flit
5518	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5519	break;
5520	}
5521	//////////////////////////////
5522	case CC_RECEIVE_BRDCAST_NLINE:
5523	{
5524	// initialize dspin received data
5525	uint64_t receive_data = p_dspin_m2p.data.read();
5526	// wait for both dcache and icache to take the request
5527	// TODO maybe we need to wait for both only to leave the state, but
5528	// not to actually post a request to an available cache => need a
5529	// flip_flop to check that ?
5530	if (not (r_cc_receive_icache_req.read()) and
5531	not (r_cc_receive_dcache_req.read()) and
5532	(p_dspin_m2p.write.read()))
5533	{
5534	// request dcache to handle the BROADCAST
5535	r_cc_receive_dcache_req = true;
5536	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5537	DspinDhccpParam::BROADCAST_NLINE);
5538	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5539	// request icache to handle the BROADCAST
5540	r_cc_receive_icache_req = true;
5541	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5542	DspinDhccpParam::BROADCAST_NLINE);
5543	r_cc_receive_icache_type = CC_TYPE_INVAL;
5544	// get back to idle state
5545	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5546	break;
5547	}
5548	// keep waiting for the caches to accept the request
5549	break;
5550	}
5551	/////////////////////////////
5552	case CC_RECEIVE_DATA_INVAL_HEADER:
5553	{
5554	// sample updt tab index in the HEADER, then skip to second flit
5555	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5556	break;
5557	}
5558	/////////////////////////////
5559	case CC_RECEIVE_INS_INVAL_HEADER:
5560	{
5561	// sample updt tab index in the HEADER, then skip to second flit
5562	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5563	break;
5564	}
5565	////////////////////////////
5566	case CC_RECEIVE_DATA_INVAL_NLINE:
5567	{
5568	// sample nline in the second flit
5569	uint64_t receive_data = p_dspin_m2p.data.read();
5570	// for data INVAL, wait for dcache to take the request
5571	if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read())
5572	{
5573	// request dcache to handle the INVAL
5574	r_cc_receive_dcache_req = true;
5575	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5576	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5577	// get back to idle state
5578	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5579	break;
5580	}
5581	break;
5582	}
5583	//////////////////////////////
5584	case CC_RECEIVE_INS_INVAL_NLINE:
5585	{
5586	// sample nline in the second flit
5587	uint64_t receive_data = p_dspin_m2p.data.read();
5588	// for ins INVAL, wait for icache to take the request
5589	if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read())
5590	{
5591	// request icache to handle the INVAL
5592	r_cc_receive_icache_req = true;
5593	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5594	r_cc_receive_icache_type = CC_TYPE_INVAL;
5595	// get back to idle state
5596	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5597	break;
5598	}
5599	break;
5600	}
5601	////////////////////////////
5602	case CC_RECEIVE_DATA_UPDT_HEADER:
5603	{
5604	// sample updt tab index in the HEADER, than skip to second flit
5605	uint64_t receive_data = p_dspin_m2p.data.read();
5606	// for data INVAL, wait for dcache to take the request and fifo to
5607	// be empty
5608	if (not r_cc_receive_dcache_req.read())
5609	{
5610	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5611	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5612	break;
5613	}
5614	break;
5615	}
5616	////////////////////////////
5617	case CC_RECEIVE_INS_UPDT_HEADER:
5618	{
5619	// sample updt tab index in the HEADER, than skip to second flit
5620	uint64_t receive_data = p_dspin_m2p.data.read();
5621	// for ins INVAL, wait for icache to take the request and fifo to be
5622	// empty
5623	if (not r_cc_receive_icache_req.read())
5624	{
5625	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5626	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5627	break;
5628	}
5629	// keep waiting for the correct cache to accept the request
5630	break;
5631	}
5632	///////////////////////////
5633	case CC_RECEIVE_DATA_UPDT_NLINE:
5634	{
5635	// sample nline and word index in the second flit
5636	uint64_t receive_data = p_dspin_m2p.data.read();
5637	// for data INVAL, wait for dcache to take the request and fifo to
5638	// be empty
5639	if ( r_cc_receive_updt_fifo_be.empty() and
5640	p_dspin_m2p.write.read() )
5641	{
5642	r_cc_receive_dcache_req = true;
5643	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5644	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5645	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5646	// get back to idle state
5647	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5648	break;
5649	}
5650	break;
5651	}
5652	////////////////////////////
5653	case CC_RECEIVE_INS_UPDT_NLINE:
5654	{
5655	// sample nline and word index in the second flit
5656	uint64_t receive_data = p_dspin_m2p.data.read();
5657	// for ins INVAL, wait for icache to take the request and fifo to be
5658	// empty
5659	if ( r_cc_receive_updt_fifo_be.empty() and
5660	p_dspin_m2p.write.read() )
5661	{
5662	r_cc_receive_icache_req = true;
5663	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5664	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5665	r_cc_receive_icache_type = CC_TYPE_UPDT;
5666	// get back to idle state
5667	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5668	break;
5669	}
5670	break;
5671	}
5672	//////////////////////////
5673	case CC_RECEIVE_DATA_UPDT_DATA:
5674	{
5675	// wait for the fifo
5676	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5677	{
5678	uint64_t receive_data = p_dspin_m2p.data.read();
5679	bool receive_eop = p_dspin_m2p.eop.read();
5680	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5681	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5682	cc_receive_updt_fifo_eop = receive_eop;
5683	cc_receive_updt_fifo_put = true;
5684	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5685	}
5686	break;
5687	}
5688	//////////////////////////
5689	case CC_RECEIVE_INS_UPDT_DATA:
5690	{
5691	// wait for the fifo
5692	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5693	{
5694	uint64_t receive_data = p_dspin_m2p.data.read();
5695	bool receive_eop = p_dspin_m2p.eop.read();
5696	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5697	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5698	cc_receive_updt_fifo_eop = receive_eop;
5699	cc_receive_updt_fifo_put = true;
5700	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5701	}
5702	break;
5703	}
5704
5705	} // end switch CC_RECEIVE FSM
5706
5707	///////////////// DSPIN CLACK interface ///////////////
5708
5709	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5710	DspinDhccpParam::CLACK_TYPE);
5711
5712	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5713	DspinDhccpParam::CLACK_WAY);
5714
5715	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5716	DspinDhccpParam::CLACK_SET);
5717
5718	bool dspin_clack_get = false;
5719	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5720	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5721
5722	if (r_dspin_clack_req.read())
5723	{
5724	// CLACK DATA: Send request to DCACHE FSM
5725	if (dcache_clack_request and not r_dcache_clack_req.read()){
5726	r_dcache_clack_req = true;
5727	r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5728	r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5729	dspin_clack_get = true;
5730	}
5731
5732	// CLACK INST: Send request to ICACHE FSM
5733	else if (icache_clack_request and not r_icache_clack_req.read()){
5734	r_icache_clack_req = true;
5735	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5736	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5737	dspin_clack_get = true;
5738	}
5739	}
5740	else
5741	{
5742	dspin_clack_get = true;
5743	}
5744
5745	if (dspin_clack_get)
5746	{
5747	r_dspin_clack_req = p_dspin_clack.write.read();
5748	r_dspin_clack_flit = p_dspin_clack.data.read();
5749	}
5750
5751	///////////////// Response FIFOs update //////////////////////
5752	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5753	vci_rsp_fifo_icache_put,
5754	vci_rsp_fifo_icache_data);
5755
5756	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5757	vci_rsp_fifo_dcache_put,
5758	vci_rsp_fifo_dcache_data);
5759
5760	///////////////// updt FIFO update //////////////////////
5761	//TODO check this
5762	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5763	cc_receive_updt_fifo_put,
5764	cc_receive_updt_fifo_be);
5765	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5766	cc_receive_updt_fifo_put,
5767	cc_receive_updt_fifo_data);
5768	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5769	cc_receive_updt_fifo_put,
5770	cc_receive_updt_fifo_eop);
5771
5772	} // end transition()
5773
5774	///////////////////////
5775	tmpl(void)::genMoore()
5776	///////////////////////
5777	{
5778
5779	// VCI initiator command on the direct network
5780	// it depends on the CMD FSM state
5781
5782	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5783	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5784
5785	p_vci.pktid = 0;
5786	p_vci.srcid = m_srcid;
5787	p_vci.cons = is_sc_or_cas;
5788	p_vci.contig = not is_sc_or_cas;
5789	p_vci.wrap = false;
5790	p_vci.clen = 0;
5791	p_vci.cfixed = false;
5792
5793	if ( m_monitor_ok ) {
5794	if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
5795	if (((p_vci.address.read()) >= m_monitor_base) and
5796	((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
5797	std::cout << "CC_VCACHE Monitor " << name() << std::hex
5798	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
5799	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
5800	<< " : address = " << p_vci.address.read()
5801	<< " / be = " << p_vci.be.read();
5802	if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
5803	std::cout << " / data = " << p_vci.wdata.read();
5804	}
5805	std::cout << std::dec << std::endl;
5806	}
5807	}
5808	}
5809
5810	switch ( r_vci_cmd_fsm.read() ) {
5811
5812	case CMD_IDLE:
5813	p_vci.cmdval = false;
5814	p_vci.address = 0;
5815	p_vci.wdata = 0;
5816	p_vci.be = 0;
5817	p_vci.trdid = 0;
5818	p_vci.pktid = 0;
5819	p_vci.plen = 0;
5820	p_vci.cmd = vci_param::CMD_NOP;
5821	p_vci.eop = false;
5822	break;
5823
5824	case CMD_INS_MISS:
5825	p_vci.cmdval = true;
5826	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5827	p_vci.wdata = 0;
5828	p_vci.be = 0xF;
5829	p_vci.trdid = 0;
5830	p_vci.pktid = TYPE_READ_INS_MISS;
5831	p_vci.plen = m_icache_words<<2;
5832	p_vci.cmd = vci_param::CMD_READ;
5833	p_vci.eop = true;
5834	break;
5835
5836	case CMD_INS_UNC:
5837	p_vci.cmdval = true;
5838	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5839	p_vci.wdata = 0;
5840	p_vci.be = 0xF;
5841	p_vci.trdid = 0;
5842	p_vci.pktid = TYPE_READ_INS_UNC;
5843	p_vci.plen = 4;
5844	p_vci.cmd = vci_param::CMD_READ;
5845	p_vci.eop = true;
5846	break;
5847
5848	case CMD_DATA_MISS:
5849	p_vci.cmdval = true;
5850	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5851	p_vci.wdata = 0;
5852	p_vci.be = 0xF;
5853	p_vci.trdid = 0;
5854	p_vci.pktid = TYPE_READ_DATA_MISS;
5855	p_vci.plen = m_dcache_words << 2;
5856	p_vci.cmd = vci_param::CMD_READ;
5857	p_vci.eop = true;
5858	break;
5859
5860	case CMD_DATA_UNC:
5861	p_vci.cmdval = true;
5862	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5863	p_vci.wdata = 0;
5864	p_vci.be = r_dcache_vci_unc_be.read();
5865	p_vci.trdid = 0;
5866	p_vci.pktid = TYPE_READ_DATA_UNC;
5867	p_vci.plen = 4;
5868	p_vci.cmd = vci_param::CMD_READ;
5869	p_vci.eop = true;
5870	break;
5871
5872	case CMD_DATA_WRITE:
5873	p_vci.cmdval = true;
5874	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5875	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5876	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5877	p_vci.trdid = r_wbuf.getIndex();
5878	p_vci.pktid = TYPE_WRITE;
5879	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5880	p_vci.cmd = vci_param::CMD_WRITE;
5881	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5882	break;
5883
5884	case CMD_DATA_LL:
5885	p_vci.cmdval = true;
5886	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5887	p_vci.wdata = 0;
5888	p_vci.be = 0xF;
5889	p_vci.trdid = 0;
5890	p_vci.pktid = TYPE_LL;
5891	p_vci.plen = 8;
5892	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5893	p_vci.eop = true;
5894	break;
5895
5896	case CMD_DATA_SC:
5897	p_vci.cmdval = true;
5898	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5899	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5900	else p_vci.wdata = r_dcache_vci_sc_data.read();
5901	p_vci.be = 0xF;
5902	p_vci.trdid = 0;
5903	p_vci.pktid = TYPE_SC;
5904	p_vci.plen = 8;
5905	p_vci.cmd = vci_param::CMD_NOP;
5906	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5907	break;
5908
5909	case CMD_DATA_CAS:
5910	p_vci.cmdval = true;
5911	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5912	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5913	else p_vci.wdata = r_dcache_vci_cas_new.read();
5914	p_vci.be = 0xF;
5915	p_vci.trdid = 0;
5916	p_vci.pktid = TYPE_CAS;
5917	p_vci.plen = 8;
5918	p_vci.cmd = vci_param::CMD_NOP;
5919	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5920	break;
5921	} // end switch r_vci_cmd_fsm
5922
5923	// VCI initiator response on the direct network
5924	// it depends on the VCI_RSP FSM
5925
5926	switch (r_vci_rsp_fsm.read() )
5927	{
5928	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5929	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5930	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5931	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5932	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5933	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5934	case RSP_IDLE : p_vci.rspack = false; break;
5935	} // end switch r_vci_rsp_fsm
5936
5937
5938	// Send coherence packets on DSPIN P2M
5939	// it depends on the CC_SEND FSM
5940
5941	uint64_t dspin_send_data = 0;
5942	switch ( r_cc_send_fsm.read() )
5943	{
5944	//////////////////
5945	case CC_SEND_IDLE:
5946	{
5947	p_dspin_p2m.write = false;
5948	break;
5949	}
5950	///////////////////////
5951	case CC_SEND_CLEANUP_1:
5952	{
5953	// initialize dspin send data
5954	// DspinDhccpParam::dspin_set(dspin_send_data,
5955	// 0,
5956	// DspinDhccpParam::P2M_EOP);
5957	DspinDhccpParam::dspin_set(dspin_send_data,
5958	m_cc_global_id,
5959	DspinDhccpParam::CLEANUP_SRCID);
5960	DspinDhccpParam::dspin_set(dspin_send_data,
5961	0,
5962	DspinDhccpParam::P2M_BC);
5963
5964	if(r_cc_send_last_client.read() == 0) // dcache active request
5965	{
5966	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5967	>> (m_nline_width - m_x_width - m_y_width)
5968	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5969
5970	DspinDhccpParam::dspin_set(dspin_send_data,
5971	dest,
5972	DspinDhccpParam::CLEANUP_DEST);
5973
5974	DspinDhccpParam::dspin_set(dspin_send_data,
5975	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
5976	DspinDhccpParam::CLEANUP_NLINE_MSB);
5977
5978	DspinDhccpParam::dspin_set(dspin_send_data,
5979	r_dcache_cc_send_way.read(),
5980	DspinDhccpParam::CLEANUP_WAY_INDEX);
5981
5982	DspinDhccpParam::dspin_set(dspin_send_data,
5983	DspinDhccpParam::TYPE_CLEANUP_DATA,
5984	DspinDhccpParam::P2M_TYPE);
5985	}
5986	else // icache active request
5987	{
5988	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5989	>> (m_nline_width - m_x_width - m_y_width)
5990	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5991
5992	DspinDhccpParam::dspin_set(dspin_send_data,
5993	dest,
5994	DspinDhccpParam::CLEANUP_DEST);
5995
5996	DspinDhccpParam::dspin_set(dspin_send_data,
5997	(r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
5998	DspinDhccpParam::CLEANUP_NLINE_MSB);
5999
6000	DspinDhccpParam::dspin_set(dspin_send_data,
6001	r_icache_cc_send_way.read(),
6002	DspinDhccpParam::CLEANUP_WAY_INDEX);
6003
6004	DspinDhccpParam::dspin_set(dspin_send_data,
6005	DspinDhccpParam::TYPE_CLEANUP_INST,
6006	DspinDhccpParam::P2M_TYPE);
6007	}
6008	// send flit
6009	p_dspin_p2m.data = dspin_send_data;
6010	p_dspin_p2m.write = true;
6011	p_dspin_p2m.eop = false;
6012	break;
6013	}
6014	///////////////////////
6015	case CC_SEND_CLEANUP_2:
6016	{
6017	// initialize dspin send data
6018	// DspinDhccpParam::dspin_set(dspin_send_data,
6019	// 1,
6020	// DspinDhccpParam::P2M_EOP);
6021
6022	if(r_cc_send_last_client.read() == 0) // dcache active request
6023	{
6024	DspinDhccpParam::dspin_set(dspin_send_data,
6025	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6026	DspinDhccpParam::CLEANUP_NLINE_LSB);
6027	}
6028	else // icache active request
6029	{
6030	DspinDhccpParam::dspin_set(dspin_send_data,
6031	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6032	DspinDhccpParam::CLEANUP_NLINE_LSB);
6033	}
6034	// send flit
6035	p_dspin_p2m.data = dspin_send_data;
6036	p_dspin_p2m.write = true;
6037	p_dspin_p2m.eop = true;
6038	break;
6039	}
6040	///////////////////////
6041	case CC_SEND_MULTI_ACK:
6042	{
6043	// initialize dspin send data
6044	// DspinDhccpParam::dspin_set(dspin_send_data,
6045	// 1,
6046	// DspinDhccpParam::P2M_EOP);
6047	DspinDhccpParam::dspin_set(dspin_send_data,
6048	0,
6049	DspinDhccpParam::P2M_BC);
6050	DspinDhccpParam::dspin_set(dspin_send_data,
6051	DspinDhccpParam::TYPE_MULTI_ACK,
6052	DspinDhccpParam::P2M_TYPE);
6053
6054	if(r_cc_send_last_client.read() == 0) // dcache active request
6055	{
6056	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6057	>> (m_nline_width - m_x_width - m_y_width)
6058	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6059
6060	DspinDhccpParam::dspin_set(dspin_send_data,
6061	dest,
6062	DspinDhccpParam::MULTI_ACK_DEST);
6063
6064	DspinDhccpParam::dspin_set(dspin_send_data,
6065	r_dcache_cc_send_updt_tab_idx.read(),
6066	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6067	}
6068	else // icache active request
6069	{
6070	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6071	>> (m_nline_width - m_x_width - m_y_width)
6072	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6073
6074
6075	DspinDhccpParam::dspin_set(dspin_send_data,
6076	dest,
6077	DspinDhccpParam::MULTI_ACK_DEST);
6078
6079	DspinDhccpParam::dspin_set(dspin_send_data,
6080	r_icache_cc_send_updt_tab_idx.read(),
6081	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6082	}
6083	// send flit
6084	p_dspin_p2m.data = dspin_send_data;
6085	p_dspin_p2m.write = true;
6086	p_dspin_p2m.eop = true;
6087
6088	break;
6089	}
6090	} // end switch CC_SEND FSM
6091
6092	// Receive coherence packets
6093	// It depends on the CC_RECEIVE FSM
6094	switch( r_cc_receive_fsm.read() )
6095	{
6096	/////////////////////
6097	case CC_RECEIVE_IDLE:
6098	{
6099	p_dspin_m2p.read = false;
6100	break;
6101	}
6102	///////////////////////////////
6103	case CC_RECEIVE_BRDCAST_HEADER:
6104	{
6105	p_dspin_m2p.read = true;
6106	break;
6107	}
6108	//////////////////////////////
6109	case CC_RECEIVE_BRDCAST_NLINE:
6110	{
6111	// TODO maybe we need to wait for both only to leave the state, but
6112	// not to actually post a request to an available cache => need a
6113	// flip_flop to check that ?
6114	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6115	p_dspin_m2p.read = true;
6116	else
6117	p_dspin_m2p.read = false;
6118	break;
6119	}
6120	/////////////////////////////
6121	case CC_RECEIVE_DATA_INVAL_HEADER:
6122	case CC_RECEIVE_INS_INVAL_HEADER:
6123	{
6124	p_dspin_m2p.read = true;
6125	break;
6126	}
6127	////////////////////////////
6128	case CC_RECEIVE_DATA_INVAL_NLINE:
6129	{
6130	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6131	break;
6132	}
6133	case CC_RECEIVE_INS_INVAL_NLINE:
6134	{
6135	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6136	break;
6137	}
6138	///////////////////////////
6139	case CC_RECEIVE_DATA_UPDT_HEADER:
6140	{
6141	if (not r_cc_receive_dcache_req.read())
6142	p_dspin_m2p.read = true;
6143	else
6144	p_dspin_m2p.read = false;
6145	break;
6146	}
6147	////////////////////////////
6148	case CC_RECEIVE_INS_UPDT_HEADER:
6149	{
6150	if ( not r_cc_receive_icache_req.read())
6151	p_dspin_m2p.read = true;
6152	else
6153	p_dspin_m2p.read = false;
6154	break;
6155	}
6156	///////////////////////////
6157	case CC_RECEIVE_DATA_UPDT_NLINE:
6158	case CC_RECEIVE_INS_UPDT_NLINE:
6159	{
6160	if(r_cc_receive_updt_fifo_be.empty())
6161	p_dspin_m2p.read = true;
6162	else
6163	p_dspin_m2p.read = false;
6164	break;
6165	}
6166	///////////////////////////
6167	case CC_RECEIVE_DATA_UPDT_DATA:
6168	case CC_RECEIVE_INS_UPDT_DATA:
6169	{
6170	if (r_cc_receive_updt_fifo_be.wok())
6171	p_dspin_m2p.read = true;
6172	else
6173	p_dspin_m2p.read = false;
6174	break;
6175	}
6176	} // end switch CC_RECEIVE FSM
6177
6178
6179	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6180	DspinDhccpParam::CLACK_TYPE);
6181
6182	bool dspin_clack_get = false;
6183	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6184	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6185
6186	if (r_dspin_clack_req.read())
6187	{
6188	// CLACK DATA: wait if pending request to DCACHE FSM
6189	if (dcache_clack_request and not r_dcache_clack_req.read())
6190	{
6191	dspin_clack_get = true;
6192	}
6193
6194	// CLACK INST: wait if pending request to ICACHE FSM
6195	else if (icache_clack_request and not r_icache_clack_req.read())
6196	{
6197	dspin_clack_get = true;
6198	}
6199	}
6200	else
6201	{
6202	dspin_clack_get = true;
6203	}
6204
6205	p_dspin_clack.read = dspin_clack_get;
6206	} // end genMoore
6207
6208	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6209	// This version of monitor print both Read and Write request
6210	{
6211	m_monitor_ok = true;
6212	m_monitor_base = base;
6213	m_monitor_length = length;
6214	}
6215
6216	tmpl(void)::stop_monitor()
6217	{
6218	m_monitor_ok = false;
6219	}
6220
6221	}}
6222
6223	// Local Variables:
6224	// tab-width: 4
6225	// c-basic-offset: 4
6226	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6227	// indent-tabs-mode: nil
6228	// End:
6229
6230	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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Project-Id-Version: Trac 0.12
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PO-Revision-Date: 2010-07-19 23:05+0200
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