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source: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper.cpp @ 323

Last change on this file since 323 was 323, checked in by joannou, 11 years ago
removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction (added an "=" sign) in declaration of the arrau of string of state names
File size: 227.3 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using soclib::common::uint32_log2;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	int proc_id,
170	const soclib::common::MappingTable &mtd,
171	const soclib::common::MappingTable &mtc,
172	const soclib::common::IntTab &initiator_index_d,
173	const soclib::common::IntTab &initiator_index_c,
174	const soclib::common::IntTab &target_index_c,
175	size_t itlb_ways,
176	size_t itlb_sets,
177	size_t dtlb_ways,
178	size_t dtlb_sets,
179	size_t icache_ways,
180	size_t icache_sets,
181	size_t icache_words,
182	size_t dcache_ways,
183	size_t dcache_sets,
184	size_t dcache_words,
185	size_t wbuf_nlines,
186	size_t wbuf_nwords,
187	size_t x_width,
188	size_t y_width,
189	uint32_t memory_cache_local_id,
190	uint32_t max_frozen_cycles,
191	uint32_t debug_start_cycle,
192	bool debug_ok)
193	: soclib::caba::BaseModule(name),
194
195	p_clk("clk"),
196	p_resetn("resetn"),
197	p_vci_ini_d("vci_ini_d"),
198	p_dspin_in("dspin_in"),
199	p_dspin_out("dspin_out"),
200
201	m_cacheability_table(mtd.getCacheabilityTable()),
202	m_segment(mtc.getSegment(target_index_c)),
203	m_srcid_d(mtd.indexForId(initiator_index_d)),
204	m_srcid_c(mtc.indexForId(initiator_index_c)),
205
206	m_itlb_ways(itlb_ways),
207	m_itlb_sets(itlb_sets),
208
209	m_dtlb_ways(dtlb_ways),
210	m_dtlb_sets(dtlb_sets),
211
212	m_icache_ways(icache_ways),
213	m_icache_sets(icache_sets),
214	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
215	m_icache_words(icache_words),
216
217	m_dcache_ways(dcache_ways),
218	m_dcache_sets(dcache_sets),
219	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
220	m_dcache_words(dcache_words),
221
222	m_x_width(x_width),
223	m_y_width(y_width),
224
225	m_memory_cache_local_id(memory_cache_local_id),
226	m_proc_id(proc_id),
227	m_max_frozen_cycles(max_frozen_cycles),
228	m_paddr_nbits(vci_param::N),
229
230	m_debug_start_cycle(debug_start_cycle),
231	m_debug_ok(debug_ok),
232
233	r_mmu_ptpr("r_mmu_ptpr"),
234	r_mmu_mode("r_mmu_mode"),
235	r_mmu_word_lo("r_mmu_word_lo"),
236	r_mmu_word_hi("r_mmu_word_hi"),
237	r_mmu_ibvar("r_mmu_ibvar"),
238	r_mmu_dbvar("r_mmu_dbvar"),
239	r_mmu_ietr("r_mmu_ietr"),
240	r_mmu_detr("r_mmu_detr"),
241
242	r_icache_fsm("r_icache_fsm"),
243	r_icache_fsm_save("r_icache_fsm_save"),
244	r_icache_vci_paddr("r_icache_vci_paddr"),
245	r_icache_vaddr_save("r_icache_vaddr_save"),
246
247	r_icache_miss_way("r_icache_miss_way"),
248	r_icache_miss_set("r_icache_miss_set"),
249	r_icache_miss_word("r_icache_miss_word"),
250	r_icache_miss_inval("r_icache_miss_inval"),
251	r_icache_miss_clack("r_icache_miss_clack"),
252
253	r_icache_cc_way("r_icache_cc_way"),
254	r_icache_cc_set("r_icache_cc_set"),
255	r_icache_cc_word("r_icache_cc_word"),
256	r_icache_cc_need_write("r_icache_cc_need_write"),
257
258	r_icache_flush_count("r_icache_flush_count"),
259
260	r_icache_miss_req("r_icache_miss_req"),
261	r_icache_unc_req("r_icache_unc_req"),
262
263	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
264	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
265
266	r_icache_cc_send_req("r_icache_cc_send_req"),
267	r_icache_cc_send_type("r_icache_cc_send_type"),
268	r_icache_cc_send_nline("r_icache_cc_send_nline"),
269	r_icache_cc_send_way("r_icache_cc_send_way"),
270	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
271
272	r_dcache_fsm("r_dcache_fsm"),
273	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
274	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
275
276	r_dcache_wbuf_req("r_dcache_wbuf_req"),
277	r_dcache_updt_req("r_dcache_updt_req"),
278	r_dcache_save_vaddr("r_dcache_save_vaddr"),
279	r_dcache_save_wdata("r_dcache_save_wdata"),
280	r_dcache_save_be("r_dcache_save_be"),
281	r_dcache_save_paddr("r_dcache_save_paddr"),
282	r_dcache_save_cacheable("r_dcache_save_cacheable"),
283	r_dcache_save_cache_way("r_dcache_save_cache_way"),
284	r_dcache_save_cache_set("r_dcache_save_cache_set"),
285	r_dcache_save_cache_word("r_dcache_save_cache_word"),
286
287	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
288	r_dcache_dirty_way("r_dcache_dirty_way"),
289	r_dcache_dirty_set("r_dcache_dirty_set"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
296	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
297	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
298	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
299	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
300	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
301
302	r_dcache_xtn_way("r_dcache_xtn_way"),
303	r_dcache_xtn_set("r_dcache_xtn_set"),
304
305	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
306
307	r_dcache_miss_type("r_dcache_miss_type"),
308	r_dcache_miss_word("r_dcache_miss_word"),
309	r_dcache_miss_way("r_dcache_miss_way"),
310	r_dcache_miss_set("r_dcache_miss_set"),
311	r_dcache_miss_inval("r_dcache_miss_inval"),
312
313	r_dcache_cc_way("r_dcache_cc_way"),
314	r_dcache_cc_set("r_dcache_cc_set"),
315	r_dcache_cc_word("r_dcache_cc_word"),
316	r_dcache_cc_need_write("r_dcache_cc_need_write"),
317
318	r_dcache_flush_count("r_dcache_flush_count"),
319
320	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
321
322	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
323	r_dcache_tlb_ins("r_dcache_tlb_ins"),
324	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
325	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
326	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
327	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
328	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
329	r_dcache_tlb_way("r_dcache_tlb_way"),
330	r_dcache_tlb_set("r_dcache_tlb_set"),
331
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
334
335	r_dcache_xtn_req("r_dcache_xtn_req"),
336	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
337
338	r_dcache_cc_send_req("r_dcache_cc_send_req"),
339	r_dcache_cc_send_type("r_dcache_cc_send_type"),
340	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
341	r_dcache_cc_send_way("r_dcache_cc_send_way"),
342	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
343
344	r_vci_cmd_fsm("r_vci_cmd_fsm"),
345	r_vci_cmd_min("r_vci_cmd_min"),
346	r_vci_cmd_max("r_vci_cmd_max"),
347	r_vci_cmd_cpt("r_vci_cmd_cpt"),
348	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
349
350	r_vci_rsp_fsm("r_vci_rsp_fsm"),
351	r_vci_rsp_cpt("r_vci_rsp_cpt"),
352	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
353	r_vci_rsp_data_error("r_vci_rsp_data_error"),
354	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
355	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
356
357	r_cc_send_fsm("r_cc_send_fsm"),
358	r_cc_send_last_client("r_cc_send_last_client"),
359
360	r_cc_receive_fsm("r_cc_receive_fsm"),
361	r_cc_receive_data_ins("r_cc_receive_data_ins"),
362	r_cc_receive_word_idx("r_cc_receive_word_idx"),
363	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
364	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
365	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
366
367	r_cc_receive_icache_req("r_cc_receive_icache_req"),
368	r_cc_receive_icache_type("r_cc_receive_icache_type"),
369	r_cc_receive_icache_way("r_cc_receive_icache_way"),
370	r_cc_receive_icache_set("r_cc_receive_icache_set"),
371	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
372	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
373
374	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
375	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
376	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
377	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
378	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
379	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
380
381	r_iss(this->name(), proc_id),
382	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
383	r_icache("icache", icache_ways, icache_sets, icache_words),
384	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
385	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
386	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
387	{
388	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
389	"Need more PLEN bits.");
390
391	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
392	"Need more TRDID bits.");
393
394	assert( (icache_words == dcache_words) and
395	"icache_words and dcache_words parameters must be equal");
396
397	assert( (itlb_sets == dtlb_sets) and
398	"itlb_sets and dtlb_sets parameters must be etqual");
399
400	assert( (itlb_ways == dtlb_ways) and
401	"itlb_ways and dtlb_ways parameters must be etqual");
402
403	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
404	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
405	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
406	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
407	(uint32_log2(m_icache_words<<2));
408
409	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
410
411	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
412	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
413
414	SC_METHOD(transition);
415	dont_initialize();
416	sensitive << p_clk.pos();
417
418	SC_METHOD(genMoore);
419	dont_initialize();
420	sensitive << p_clk.neg();
421
422	typename iss_t::CacheInfo cache_info;
423	cache_info.has_mmu = true;
424	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
425	cache_info.icache_assoc = icache_ways;
426	cache_info.icache_n_lines = icache_sets;
427	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
428	cache_info.dcache_assoc = dcache_ways;
429	cache_info.dcache_n_lines = dcache_sets;
430	r_iss.setCacheInfo(cache_info);
431	}
432
433	/////////////////////////////////////
434	tmpl(/**/)::~VciCcVCacheWrapper()
435	/////////////////////////////////////
436	{
437	delete [] r_dcache_in_tlb;
438	delete [] r_dcache_contains_ptd;
439	}
440
441	////////////////////////
442	tmpl(void)::print_cpi()
443	////////////////////////
444	{
445	std::cout << name() << " CPI = "
446	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
447	}
448
449	////////////////////////////////////
450	tmpl(void)::print_trace(size_t mode)
451	////////////////////////////////////
452	{
453	// b0 : write buffer trace
454	// b1 : write buffer verbose
455	// b2 : dcache trace
456	// b3 : icache trace
457	// b4 : dtlb trace
458	// b5 : itlb trace
459
460	std::cout << std::dec << "PROC " << name() << std::endl;
461
462	std::cout << " " << m_ireq << std::endl;
463	std::cout << " " << m_irsp << std::endl;
464	std::cout << " " << m_dreq << std::endl;
465	std::cout << " " << m_drsp << std::endl;
466
467	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
468	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
469	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
470	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
471	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
472	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
473	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
474	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
475	std::cout << std::endl;
476
477	if(mode & 0x01)
478	{
479	r_wbuf.printTrace((mode>>1)&1);
480	}
481	if(mode & 0x04)
482	{
483	std::cout << " Data Cache" << std::endl;
484	r_dcache.printTrace();
485	}
486	if(mode & 0x08)
487	{
488	std::cout << " Instruction Cache" << std::endl;
489	r_icache.printTrace();
490	}
491	if(mode & 0x10)
492	{
493	std::cout << " Data TLB" << std::endl;
494	r_dtlb.printTrace();
495	}
496	if(mode & 0x20)
497	{
498	std::cout << " Instruction TLB" << std::endl;
499	r_itlb.printTrace();
500	}
501	}
502
503	//////////////////////////////////////////
504	tmpl(void)::cache_monitor( paddr_t addr )
505	//////////////////////////////////////////
506	{
507	size_t cache_way;
508	size_t cache_set;
509	size_t cache_word;
510	uint32_t cache_rdata;
511	bool cache_hit = r_dcache.read_neutral( addr,
512	&cache_rdata,
513	&cache_way,
514	&cache_set,
515	&cache_word );
516	bool icache_hit = r_icache.read_neutral( addr,
517	&cache_rdata,
518	&cache_way,
519	&cache_set,
520	&cache_word );
521	if ( cache_hit != m_debug_previous_hit )
522	{
523	std::cout << "PROC " << name()
524	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
525	<< " for adresse " << std::hex << addr
526	<< " / HIT = " << std::dec << cache_hit << std::endl;
527	m_debug_previous_hit = cache_hit;
528	}
529	if ( icache_hit != m_idebug_previous_hit )
530	{
531	std::cout << "PROC " << name()
532	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
533	<< " for adresse " << std::hex << addr
534	<< " / HIT = " << icache_hit << std::endl;
535	m_idebug_previous_hit = icache_hit;
536	}
537	}
538
539	/*
540	////////////////////////
541	tmpl(void)::print_stats()
542	////////////////////////
543	{
544	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
545	std::cout << name() << std::endl
546	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
547	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
548	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
549	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
550	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
551	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
552	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
553	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
554	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
555	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
556	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
557	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
558	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
559	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
560	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
561	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
563	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
564	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
565	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
566	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
567	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
568	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
569	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
570	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
571	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
572	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
573	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
574	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
575	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
576	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
577	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
578	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
579	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
580	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
581	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
583	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
584	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
585	}
586
587	////////////////////////
588	tmpl(void)::clear_stats()
589	////////////////////////
590	{
591	m_cpt_dcache_data_read = 0;
592	m_cpt_dcache_data_write = 0;
593	m_cpt_dcache_dir_read = 0;
594	m_cpt_dcache_dir_write = 0;
595	m_cpt_icache_data_read = 0;
596	m_cpt_icache_data_write = 0;
597	m_cpt_icache_dir_read = 0;
598	m_cpt_icache_dir_write = 0;
599
600	m_cpt_frz_cycles = 0;
601	m_cpt_dcache_frz_cycles = 0;
602	m_cpt_total_cycles = 0;
603
604	m_cpt_read = 0;
605	m_cpt_write = 0;
606	m_cpt_data_miss = 0;
607	m_cpt_ins_miss = 0;
608	m_cpt_unc_read = 0;
609	m_cpt_write_cached = 0;
610	m_cpt_ins_read = 0;
611
612	m_cost_write_frz = 0;
613	m_cost_data_miss_frz = 0;
614	m_cost_unc_read_frz = 0;
615	m_cost_ins_miss_frz = 0;
616
617	m_cpt_imiss_transaction = 0;
618	m_cpt_dmiss_transaction = 0;
619	m_cpt_unc_transaction = 0;
620	m_cpt_write_transaction = 0;
621	m_cpt_icache_unc_transaction = 0;
622
623	m_cost_imiss_transaction = 0;
624	m_cost_dmiss_transaction = 0;
625	m_cost_unc_transaction = 0;
626	m_cost_write_transaction = 0;
627	m_cost_icache_unc_transaction = 0;
628	m_length_write_transaction = 0;
629
630	m_cpt_ins_tlb_read = 0;
631	m_cpt_ins_tlb_miss = 0;
632	m_cpt_ins_tlb_update_acc = 0;
633
634	m_cpt_data_tlb_read = 0;
635	m_cpt_data_tlb_miss = 0;
636	m_cpt_data_tlb_update_acc = 0;
637	m_cpt_data_tlb_update_dirty = 0;
638	m_cpt_ins_tlb_hit_dcache = 0;
639	m_cpt_data_tlb_hit_dcache = 0;
640	m_cpt_ins_tlb_occup_cache = 0;
641	m_cpt_data_tlb_occup_cache = 0;
642
643	m_cost_ins_tlb_miss_frz = 0;
644	m_cost_data_tlb_miss_frz = 0;
645	m_cost_ins_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_acc_frz = 0;
647	m_cost_data_tlb_update_dirty_frz = 0;
648	m_cost_ins_tlb_occup_cache_frz = 0;
649	m_cost_data_tlb_occup_cache_frz = 0;
650
651	m_cpt_itlbmiss_transaction = 0;
652	m_cpt_itlb_ll_transaction = 0;
653	m_cpt_itlb_sc_transaction = 0;
654	m_cpt_dtlbmiss_transaction = 0;
655	m_cpt_dtlb_ll_transaction = 0;
656	m_cpt_dtlb_sc_transaction = 0;
657	m_cpt_dtlb_ll_dirty_transaction = 0;
658	m_cpt_dtlb_sc_dirty_transaction = 0;
659
660	m_cost_itlbmiss_transaction = 0;
661	m_cost_itlb_ll_transaction = 0;
662	m_cost_itlb_sc_transaction = 0;
663	m_cost_dtlbmiss_transaction = 0;
664	m_cost_dtlb_ll_transaction = 0;
665	m_cost_dtlb_sc_transaction = 0;
666	m_cost_dtlb_ll_dirty_transaction = 0;
667	m_cost_dtlb_sc_dirty_transaction = 0;
668
669	m_cpt_cc_update_data = 0;
670	m_cpt_cc_inval_ins = 0;
671	m_cpt_cc_inval_data = 0;
672	m_cpt_cc_broadcast = 0;
673
674	m_cost_updt_data_frz = 0;
675	m_cost_inval_ins_frz = 0;
676	m_cost_inval_data_frz = 0;
677	m_cost_broadcast_frz = 0;
678
679	m_cpt_cc_cleanup_data = 0;
680	m_cpt_cc_cleanup_ins = 0;
681	}
682
683	*/
684
685	/////////////////////////
686	tmpl(void)::transition()
687	/////////////////////////
688	{
689	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
690	if ( not p_resetn.read() )
691	{
692	r_iss.reset();
693	r_wbuf.reset();
694	r_icache.reset();
695	r_dcache.reset();
696	r_itlb.reset();
697	r_dtlb.reset();
698
699	r_dcache_fsm = DCACHE_IDLE;
700	r_icache_fsm = ICACHE_IDLE;
701	r_vci_cmd_fsm = CMD_IDLE;
702	r_vci_rsp_fsm = RSP_IDLE;
703	r_cc_receive_fsm = CC_RECEIVE_IDLE;
704	r_cc_send_fsm = CC_SEND_IDLE;
705
706	// reset dcache directory extension
707	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
708	{
709	r_dcache_in_tlb[i] = false;
710	r_dcache_contains_ptd[i] = false;
711	}
712
713	// Response FIFOs and cleanup buffer
714	r_vci_rsp_fifo_icache.init();
715	r_vci_rsp_fifo_dcache.init();
716
717	// ICACHE & DCACHE activated
718	r_mmu_mode = 0x3;
719
720	// No request from ICACHE FSM to CMD FSM
721	r_icache_miss_req = false;
722	r_icache_unc_req = false;
723
724	// No request from ICACHE_FSM to DCACHE FSM
725	r_icache_tlb_miss_req = false;
726
727	// No request from ICACHE_FSM to CC_SEND FSM
728	r_icache_cc_send_req = false;
729
730	// No pending write in pipeline
731	r_dcache_wbuf_req = false;
732	r_dcache_updt_req = false;
733
734	// No request from DCACHE_FSM to CMD_FSM
735	r_dcache_vci_miss_req = false;
736	r_dcache_vci_unc_req = false;
737	r_dcache_vci_cas_req = false;
738	r_dcache_vci_ll_req = false;
739	r_dcache_vci_sc_req = false;
740
741	// No uncacheable write pending
742	r_dcache_pending_unc_write = false;
743
744	// No processor XTN request pending
745	r_dcache_xtn_req = false;
746
747	// No request from DCACHE FSM to CC_SEND FSM
748	r_dcache_cc_send_req = false;
749
750	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
751	r_cc_receive_icache_req = false;
752	r_cc_receive_dcache_req = false;
753
754	// last cc_send client was dcache
755	r_cc_send_last_client = false;
756
757	// No pending cleanup after a replacement
758	r_icache_miss_clack = false;
759	r_dcache_miss_clack = false;
760
761	// No signalisation of a coherence request matching a pending miss
762	r_icache_miss_inval = false;
763	r_dcache_miss_inval = false;
764
765	// No signalisation of errors
766	r_vci_rsp_ins_error = false;
767	r_vci_rsp_data_error = false;
768
769	// Debug variables
770	m_debug_previous_hit = false;
771	m_idebug_previous_hit = false;
772	m_debug_dcache_fsm = false;
773	m_debug_icache_fsm = false;
774
775	// activity counters
776	m_cpt_dcache_data_read = 0;
777	m_cpt_dcache_data_write = 0;
778	m_cpt_dcache_dir_read = 0;
779	m_cpt_dcache_dir_write = 0;
780	m_cpt_icache_data_read = 0;
781	m_cpt_icache_data_write = 0;
782	m_cpt_icache_dir_read = 0;
783	m_cpt_icache_dir_write = 0;
784
785	m_cpt_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787	m_cpt_stop_simulation = 0;
788
789	m_cpt_data_miss = 0;
790	m_cpt_ins_miss = 0;
791	m_cpt_unc_read = 0;
792	m_cpt_write_cached = 0;
793	m_cpt_ins_read = 0;
794
795	m_cost_write_frz = 0;
796	m_cost_data_miss_frz = 0;
797	m_cost_unc_read_frz = 0;
798	m_cost_ins_miss_frz = 0;
799
800	m_cpt_imiss_transaction = 0;
801	m_cpt_dmiss_transaction = 0;
802	m_cpt_unc_transaction = 0;
803	m_cpt_write_transaction = 0;
804	m_cpt_icache_unc_transaction = 0;
805
806	m_cost_imiss_transaction = 0;
807	m_cost_dmiss_transaction = 0;
808	m_cost_unc_transaction = 0;
809	m_cost_write_transaction = 0;
810	m_cost_icache_unc_transaction = 0;
811	m_length_write_transaction = 0;
812
813	m_cpt_ins_tlb_read = 0;
814	m_cpt_ins_tlb_miss = 0;
815	m_cpt_ins_tlb_update_acc = 0;
816
817	m_cpt_data_tlb_read = 0;
818	m_cpt_data_tlb_miss = 0;
819	m_cpt_data_tlb_update_acc = 0;
820	m_cpt_data_tlb_update_dirty = 0;
821	m_cpt_ins_tlb_hit_dcache = 0;
822	m_cpt_data_tlb_hit_dcache = 0;
823	m_cpt_ins_tlb_occup_cache = 0;
824	m_cpt_data_tlb_occup_cache = 0;
825
826	m_cost_ins_tlb_miss_frz = 0;
827	m_cost_data_tlb_miss_frz = 0;
828	m_cost_ins_tlb_update_acc_frz = 0;
829	m_cost_data_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_dirty_frz = 0;
831	m_cost_ins_tlb_occup_cache_frz = 0;
832	m_cost_data_tlb_occup_cache_frz = 0;
833
834	m_cpt_ins_tlb_inval = 0;
835	m_cpt_data_tlb_inval = 0;
836	m_cost_ins_tlb_inval_frz = 0;
837	m_cost_data_tlb_inval_frz = 0;
838
839	m_cpt_cc_broadcast = 0;
840
841	m_cost_updt_data_frz = 0;
842	m_cost_inval_ins_frz = 0;
843	m_cost_inval_data_frz = 0;
844	m_cost_broadcast_frz = 0;
845
846	m_cpt_cc_cleanup_data = 0;
847	m_cpt_cc_cleanup_ins = 0;
848
849	m_cpt_itlbmiss_transaction = 0;
850	m_cpt_itlb_ll_transaction = 0;
851	m_cpt_itlb_sc_transaction = 0;
852	m_cpt_dtlbmiss_transaction = 0;
853	m_cpt_dtlb_ll_transaction = 0;
854	m_cpt_dtlb_sc_transaction = 0;
855	m_cpt_dtlb_ll_dirty_transaction = 0;
856	m_cpt_dtlb_sc_dirty_transaction = 0;
857
858	m_cost_itlbmiss_transaction = 0;
859	m_cost_itlb_ll_transaction = 0;
860	m_cost_itlb_sc_transaction = 0;
861	m_cost_dtlbmiss_transaction = 0;
862	m_cost_dtlb_ll_transaction = 0;
863	m_cost_dtlb_sc_transaction = 0;
864	m_cost_dtlb_ll_dirty_transaction = 0;
865	m_cost_dtlb_sc_dirty_transaction = 0;
866	/*
867	m_cpt_dcache_frz_cycles = 0;
868	m_cpt_read = 0;
869	m_cpt_write = 0;
870	m_cpt_cc_update_data = 0;
871	m_cpt_cc_inval_ins = 0;
872	m_cpt_cc_inval_data = 0;
873	*/
874
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
878	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
879
880	// init the llsc reservation buffer
881	r_dcache_llsc_valid = false;
882
883	return;
884	}
885
886	// Response FIFOs default values
887	bool vci_rsp_fifo_icache_get = false;
888	bool vci_rsp_fifo_icache_put = false;
889	uint32_t vci_rsp_fifo_icache_data = 0;
890
891	bool vci_rsp_fifo_dcache_get = false;
892	bool vci_rsp_fifo_dcache_put = false;
893	uint32_t vci_rsp_fifo_dcache_data = 0;
894
895	// updt fifo
896	bool cc_receive_updt_fifo_get = false;
897	bool cc_receive_updt_fifo_put = false;
898	uint32_t cc_receive_updt_fifo_be = 0;
899	uint32_t cc_receive_updt_fifo_data = 0;
900	bool cc_receive_updt_fifo_eop = false;
901
902	#ifdef INSTRUMENTATION
903	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
904	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
905	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
906	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
907	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
908	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
909	#endif
910
911	m_cpt_total_cycles++;
912
913	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
914	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
915
916	/////////////////////////////////////////////////////////////////////
917	// Get data and instruction requests from processor
918	///////////////////////////////////////////////////////////////////////
919
920	r_iss.getRequests(m_ireq, m_dreq);
921
922	////////////////////////////////////////////////////////////////////////////////////
923	// ICACHE_FSM
924	//
925	// 1/ Coherence operations
926	// They are handled as interrupts generated by the CC_RECEIVE FSM.
927	// - There is a coherence request when r_tgt_icache_req is set.
928	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
929	// - There is a cleanup ack request when r_cleanup_icache_req is set.
930	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
931	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
932	// - For both types of requests, actions associated to the pre-empted state
933	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
934	// or CC_CLACK) to execute the requested coherence operation, and returns
935	// to the pre-empted state.
936	//
937	// 2/ Processor requests
938	// They are taken in IDLE state only. In case of cache miss, or uncacheable
939	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
940	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
941	// flip-flops are reset when the transaction starts.
942	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
943	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
944	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
945	// The availability of the missing cache line is signaled by the response fifo,
946	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
947	// and ICACHE_MISS_DIR_UPDT states.
948	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
949	// to wait the response from the RSP FSM, through the response fifo.
950	// The missing instruction is directly returned to processor in this state.
951	//
952	// 3/ TLB miss
953	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
954	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
955	// register, and goes to the ICACHE_TLB_WAIT state.
956	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
957	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
958	// to signal the completion.
959	//
960	// 4/ XTN requests
961	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
962	// using the r_dcache_xtn_req flip-flop.
963	// The request opcode and the address to be invalidated are transmitted
964	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
965	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
966	// is completed.
967	//
968	// 5/ Error Handling
969	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
970	// in a cache miss or uncacheable read VCI transaction. Nothing is written
971	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
972	////////////////////////////////////////////////////////////////////////////////////////
973
974	// default value for m_irsp
975	m_irsp.valid = false;
976	m_irsp.error = false;
977	m_irsp.instruction = 0;
978
979	switch( r_icache_fsm.read() )
980	{
981	/////////////////
982	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
983	// and coherence requests with a fixed priority:
984	// 1/ Coherence requests => ICACHE_CC_CHECK
985	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
986	// 3/ tlb miss => ICACHE_TLB_WAIT
987	// 4/ cacheable read miss => ICACHE_MISS_SELECT
988	// 5/ uncacheable read miss => ICACHE_UNC_REQ
989	{
990	// coherence interrupt
991	if ( r_cc_receive_icache_req.read() )
992	{
993	r_icache_fsm = ICACHE_CC_CHECK;
994	r_icache_fsm_save = r_icache_fsm.read();
995	break;
996	}
997
998	// XTN requests sent by DCACHE FSM
999	// These request are not executed in this IDLE state, because
1000	// they require access to icache or itlb, that are already accessed
1001	if ( r_dcache_xtn_req.read() )
1002	{
1003	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1004	{
1005	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1006	}
1007	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1008	{
1009	r_icache_flush_count = 0;
1010	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1011	}
1012	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1013	{
1014	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1015	}
1016	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1017	{
1018	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1019	}
1020	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1021	{
1022	if (sizeof(paddr_t) <= 32)
1023	{
1024	assert(r_mmu_word_hi.read() == 0 &&
1025	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1026	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1027	}
1028	else
1029	{
1030	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1031	(paddr_t)r_mmu_word_lo.read();
1032	}
1033	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1034	}
1035	else
1036	{
1037	assert( false and
1038	"undefined XTN request received by ICACHE FSM");
1039	}
1040	break;
1041	} // end if xtn_req
1042
1043	// processor request
1044	if ( m_ireq.valid )
1045	{
1046	bool cacheable;
1047	paddr_t paddr;
1048	bool tlb_hit = false;
1049	pte_info_t tlb_flags;
1050	size_t tlb_way;
1051	size_t tlb_set;
1052	paddr_t tlb_nline;
1053	uint32_t cache_inst = 0;
1054	size_t cache_way;
1055	size_t cache_set;
1056	size_t cache_word;
1057	int cache_state = CACHE_SLOT_STATE_EMPTY;
1058
1059	// We register processor request
1060	r_icache_vaddr_save = m_ireq.addr;
1061
1062	// sytematic itlb access (if activated)
1063	if ( r_mmu_mode.read() & INS_TLB_MASK )
1064	{
1065
1066	#ifdef INSTRUMENTATION
1067	m_cpt_itlb_read++;
1068	#endif
1069	tlb_hit = r_itlb.translate( m_ireq.addr,
1070	&paddr,
1071	&tlb_flags,
1072	&tlb_nline, // unused
1073	&tlb_way, // unused
1074	&tlb_set ); // unused
1075	}
1076	else
1077	{
1078	paddr = (paddr_t)m_ireq.addr;
1079	}
1080
1081	// systematic icache access (if activated)
1082	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1083	{
1084
1085
1086	#ifdef INSTRUMENTATION
1087	m_cpt_icache_data_read++;
1088	m_cpt_icache_dir_read++;
1089	#endif
1090	r_icache.read( paddr,
1091	&cache_inst,
1092	&cache_way,
1093	&cache_set,
1094	&cache_word,
1095	&cache_state );
1096	}
1097
1098	// We compute cacheability and check access rights:
1099	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1100	// and the access rights are defined by the U and X bits in the PTE.
1101	// - If MMU not activated : cacheability is defined by the segment table,
1102	// and there is no access rights checking
1103
1104	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1105	{
1106	// cacheability
1107	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1108	else cacheable = m_cacheability_table[m_ireq.addr];
1109	}
1110	else // itlb activated
1111	{
1112	if ( tlb_hit ) // ITLB hit
1113	{
1114	// cacheability
1115	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1116	else cacheable = tlb_flags.c;
1117
1118	// access rights checking
1119	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1120	{
1121	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1122	r_mmu_ibvar = m_ireq.addr;
1123	m_irsp.valid = true;
1124	m_irsp.error = true;
1125	m_irsp.instruction = 0;
1126	break;
1127	}
1128	else if ( not tlb_flags.x )
1129	{
1130	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1131	r_mmu_ibvar = m_ireq.addr;
1132	m_irsp.valid = true;
1133	m_irsp.error = true;
1134	m_irsp.instruction = 0;
1135	break;
1136	}
1137	}
1138	else // ITLB miss
1139	{
1140
1141	#ifdef INSTRUMENTATION
1142	m_cpt_itlb_miss++;
1143	#endif
1144	r_icache_fsm = ICACHE_TLB_WAIT;
1145	r_icache_tlb_miss_req = true;
1146	break;
1147	}
1148	} // end if itlb activated
1149
1150	// physical address registration
1151	r_icache_vci_paddr = paddr;
1152
1153	// Finally, we send the response to processor, and compute next state
1154	if ( cacheable )
1155	{
1156	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1157	{
1158
1159	#ifdef INSTRUMENTATION
1160	m_cpt_icache_miss++;
1161	#endif
1162	// we request a VCI transaction
1163	r_icache_fsm = ICACHE_MISS_SELECT;
1164	r_icache_miss_req = true;
1165	}
1166	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1167	{
1168	// stalled until cleanup is acknowledged
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	else // cache hit
1172	{
1173
1174	#ifdef INSTRUMENTATION
1175	m_cpt_ins_read++;
1176	#endif
1177	// return instruction to processor
1178	m_irsp.valid = true;
1179	m_irsp.instruction = cache_inst;
1180	r_icache_fsm = ICACHE_IDLE;
1181	}
1182	}
1183	else // non cacheable read
1184	{
1185	r_icache_unc_req = true;
1186	r_icache_fsm = ICACHE_UNC_WAIT;
1187	}
1188	} // end if m_ireq.valid
1189	break;
1190	}
1191	/////////////////////
1192	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1193	// the itlb is udated by the DCACHE FSM, as well as the
1194	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1195	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1196	// reset the r_icache_tlb_miss_req flip-flop
1197	// external coherence request are accepted in this state.
1198	{
1199	// coherence interrupt
1200	if ( r_cc_receive_icache_req.read() )
1201	{
1202	r_icache_fsm = ICACHE_CC_CHECK;
1203	r_icache_fsm_save = r_icache_fsm.read();
1204	break;
1205	}
1206
1207	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1208
1209	// DCACHE FSM signals response by reseting the request flip-flop
1210	if ( not r_icache_tlb_miss_req.read() )
1211	{
1212	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1213	{
1214	r_icache_tlb_rsp_error = false;
1215	m_irsp.error = true;
1216	m_irsp.valid = true;
1217	r_icache_fsm = ICACHE_IDLE;
1218	}
1219	else // tlb updated : return to IDLE state
1220	{
1221	r_icache_fsm = ICACHE_IDLE;
1222	}
1223	}
1224	break;
1225	}
1226	//////////////////////////
1227	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1228	{
1229	r_itlb.flush();
1230	r_dcache_xtn_req = false;
1231	r_icache_fsm = ICACHE_IDLE;
1232	break;
1233	}
1234	////////////////////////////
1235	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1236	// r_icache_flush_count as a slot counter,
1237	// looping in this state until all slots are visited.
1238	// It can require two cycles per slot:
1239	// We test here the slot state, and make the actual inval
1240	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1241	// A cleanup request is generated for each valid line
1242	{
1243	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1244	{
1245	int state;
1246	uint32_t tag;
1247	size_t way = r_icache_flush_count.read()/m_icache_sets;
1248	size_t set = r_icache_flush_count.read()%m_icache_sets;
1249
1250	#ifdef INSTRUMENTATION
1251	m_cpt_icache_dir_read++;
1252	#endif
1253	r_icache.read_dir( way,
1254	set,
1255	&tag,
1256	&state );
1257
1258	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1259	{
1260	// request cleanup
1261	r_icache_cc_send_req = true;
1262	r_icache_cc_send_nline = tag * m_icache_sets;
1263	r_icache_cc_send_way = way;
1264	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1265
1266	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1267	r_icache_miss_way = way;
1268	r_icache_miss_set = set;
1269	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1270	}
1271	else if ( r_icache_flush_count.read() ==
1272	(m_icache_sets*m_icache_ways - 1) ) // last slot
1273	{
1274	r_dcache_xtn_req = false;
1275	m_drsp.valid = true;
1276	r_icache_fsm = ICACHE_IDLE;
1277	}
1278
1279	// saturation counter, to have the same last slot condition
1280	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1281	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1282	{
1283	r_icache_flush_count = r_icache_flush_count.read() + 1;
1284	}
1285	}
1286	break;
1287	}
1288	///////////////////////////////
1289	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1290	{
1291	size_t way = r_icache_miss_way.read();
1292	size_t set = r_icache_miss_set.read();
1293
1294	#ifdef INSTRUMENTATION
1295	m_cpt_icache_dir_write++;
1296	#endif
1297
1298	r_icache.write_dir( 0,
1299	way,
1300	set,
1301	CACHE_SLOT_STATE_ZOMBI );
1302
1303	if ( r_icache_flush_count.read() ==
1304	(m_icache_sets*m_icache_ways - 1) ) // last slot
1305	{
1306	r_dcache_xtn_req = false;
1307	m_drsp.valid = true;
1308	r_icache_fsm = ICACHE_IDLE;
1309	}
1310	else
1311	{
1312	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1313	}
1314	break;
1315	}
1316
1317	//////////////////////////
1318	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1319	// stored in the r_dcache_save_wdata register
1320	{
1321	r_itlb.inval(r_dcache_save_wdata.read());
1322	r_dcache_xtn_req = false;
1323	r_icache_fsm = ICACHE_IDLE;
1324	break;
1325	}
1326	///////////////////////////////
1327	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1328	// requires 3 cycles (in case of hit on itlb and icache).
1329	// In this state, access TLB to translate virtual address
1330	// stored in the r_dcache_save_wdata register.
1331	{
1332	paddr_t paddr;
1333	bool hit;
1334
1335	// read physical address in TLB when MMU activated
1336	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1337	{
1338
1339	#ifdef INSTRUMENTATION
1340	m_cpt_itlb_read++;
1341	#endif
1342	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1343	&paddr);
1344	}
1345	else // itlb not activated
1346	{
1347	paddr = (paddr_t)r_dcache_save_wdata.read();
1348	hit = true;
1349	}
1350
1351	if ( hit ) // continue the selective inval process
1352	{
1353	r_icache_vci_paddr = paddr;
1354	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1355	}
1356	else // miss : send a request to DCACHE FSM
1357	{
1358
1359	#ifdef INSTRUMENTATION
1360	m_cpt_itlb_miss++;
1361	#endif
1362	r_icache_tlb_miss_req = true;
1363	r_icache_vaddr_save = r_dcache_save_wdata.read();
1364	r_icache_fsm = ICACHE_TLB_WAIT;
1365	}
1366	break;
1367	}
1368	///////////////////////////////
1369	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1370	// require 2 cycles. In this state, we read directory
1371	// with address stored in r_icache_vci_paddr register.
1372	{
1373	int state;
1374	size_t way;
1375	size_t set;
1376	size_t word;
1377
1378	#ifdef INSTRUMENTATION
1379	m_cpt_icache_dir_read++;
1380	#endif
1381	r_icache.read_dir(r_icache_vci_paddr.read(),
1382	&state,
1383	&way,
1384	&set,
1385	&word);
1386
1387	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1388	{
1389	r_icache_miss_way = way;
1390	r_icache_miss_set = set;
1391	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1392	}
1393	else // miss : acknowlege the XTN request and return
1394	{
1395	r_dcache_xtn_req = false;
1396	r_icache_fsm = ICACHE_IDLE;
1397	}
1398	break;
1399	}
1400	///////////////////////////////
1401	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1402	{
1403	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1404	{
1405
1406	#ifdef INSTRUMENTATION
1407	m_cpt_icache_dir_write++;
1408	#endif
1409	r_icache.write_dir( 0,
1410	r_icache_miss_way.read(),
1411	r_icache_miss_set.read(),
1412	CACHE_SLOT_STATE_ZOMBI );
1413
1414	// request cleanup
1415	r_icache_cc_send_req = true;
1416	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1417	r_icache_cc_send_way = r_icache_miss_way.read();
1418	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1419
1420	// acknowledge the XTN request and return
1421	r_dcache_xtn_req = false;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424	break;
1425	}
1426	////////////////////////
1427	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1428	// if previous cleanup has been sent.
1429	// Waiting in this state if no slot available.
1430	// Set the r_icache_cleanup_req flip-flop
1431	// and the r_icache_miss_clack flip-flop,
1432	// when a cleanup is required
1433	{
1434	if (m_ireq.valid) m_cost_ins_miss_frz++;
1435
1436	// coherence interrupt
1437	if ( r_cc_receive_icache_req.read() )
1438	{
1439	r_icache_fsm = ICACHE_CC_CHECK;
1440	r_icache_fsm_save = r_icache_fsm.read();
1441	break;
1442	}
1443
1444	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1445	{
1446	bool found;
1447	bool cleanup;
1448	size_t way;
1449	size_t set;
1450	paddr_t victim;
1451
1452	#ifdef INSTRUMENTATION
1453	m_cpt_icache_dir_read++;
1454	#endif
1455	r_icache.read_select(r_icache_vci_paddr.read(),
1456	&victim,
1457	&way,
1458	&set,
1459	&found,
1460	&cleanup );
1461	if ( found )
1462	{
1463	r_icache_miss_way = way;
1464	r_icache_miss_set = set;
1465
1466	if ( cleanup )
1467	{
1468	r_icache_fsm = ICACHE_MISS_CLEAN;
1469	r_icache_miss_clack = true;
1470	// request cleanup
1471	r_icache_cc_send_req = true;
1472	r_icache_cc_send_nline = victim;
1473	r_icache_cc_send_way = way;
1474	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1475	}
1476	else
1477	{
1478	r_icache_fsm = ICACHE_MISS_WAIT;
1479	}
1480
1481	#if DEBUG_ICACHE
1482	if ( m_debug_dcache_fsm )
1483	{
1484	std::cout << " <PROC " << name()
1485	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1486	<< " / WAY = " << way
1487	<< " / SET = " << set;
1488	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1489	else std::cout << std::endl;
1490	}
1491	#endif
1492	}
1493	}
1494	break;
1495	}
1496	///////////////////////
1497	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1498	{
1499	if (m_ireq.valid) m_cost_ins_miss_frz++;
1500
1501	// coherence interrupt
1502	if ( r_cc_receive_icache_req.read() )
1503	{
1504	r_icache_fsm = ICACHE_CC_CHECK;
1505	r_icache_fsm_save = r_icache_fsm.read();
1506	break;
1507	}
1508
1509	#ifdef INSTRUMENTATION
1510	m_cpt_icache_dir_write++;
1511	#endif
1512	r_icache.write_dir( 0,
1513	r_icache_miss_way.read(),
1514	r_icache_miss_set.read(),
1515	CACHE_SLOT_STATE_ZOMBI);
1516	#if DEBUG_ICACHE
1517	if ( m_debug_dcache_fsm )
1518	{
1519	std::cout << " <PROC " << name()
1520	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1521	<< " / WAY = " << r_icache_miss_way.read()
1522	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1523	}
1524	#endif
1525
1526	r_icache_fsm = ICACHE_MISS_WAIT;
1527	break;
1528	}
1529	//////////////////////
1530	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1531	{
1532	if (m_ireq.valid) m_cost_ins_miss_frz++;
1533
1534	// coherence interrupt
1535	if ( r_cc_receive_icache_req.read() )
1536	{
1537	r_icache_fsm = ICACHE_CC_CHECK;
1538	r_icache_fsm_save = r_icache_fsm.read();
1539	break;
1540	}
1541
1542	if ( r_vci_rsp_ins_error.read() ) // bus error
1543	{
1544	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1545	r_mmu_ibvar = r_icache_vaddr_save.read();
1546	m_irsp.valid = true;
1547	m_irsp.error = true;
1548	r_vci_rsp_ins_error = false;
1549	r_icache_fsm = ICACHE_IDLE;
1550	}
1551	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1552	{
1553	r_icache_miss_word = 0;
1554	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1555	}
1556	break;
1557	}
1558	///////////////////////////
1559	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1560	{
1561	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1562
1563	// coherence interrupt
1564	if ( r_cc_receive_icache_req.read() )
1565	{
1566	r_icache_fsm = ICACHE_CC_CHECK;
1567	r_icache_fsm_save = r_icache_fsm.read();
1568	break;
1569	}
1570
1571	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1572	{
1573
1574	#ifdef INSTRUMENTATION
1575	m_cpt_icache_data_write++;
1576	#endif
1577	r_icache.write( r_icache_miss_way.read(),
1578	r_icache_miss_set.read(),
1579	r_icache_miss_word.read(),
1580	r_vci_rsp_fifo_icache.read() );
1581	#if DEBUG_ICACHE
1582	if ( m_debug_icache_fsm )
1583	{
1584	std::cout << " <PROC " << name()
1585	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1586	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1587	<< " WAY = " << r_icache_miss_way.read()
1588	<< " SET = " << r_icache_miss_set.read()
1589	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1590	}
1591	#endif
1592	vci_rsp_fifo_icache_get = true;
1593	r_icache_miss_word = r_icache_miss_word.read() + 1;
1594
1595	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1596	{
1597	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1598	}
1599	}
1600	break;
1601	}
1602	//////////////////////////
1603	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1604	// and the cleanup ack has not been received,
1605	// as indicated by r_icache_miss_clack.
1606	// - If no matching coherence request (r_icache_miss_inval)
1607	// switch directory slot to VALID state.
1608	// - If matching coherence request, switch directory slot
1609	// to ZOMBI state, and send a cleanup request.
1610	{
1611	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1612
1613	// coherence interrupt
1614	if ( r_cc_receive_icache_req.read() )
1615	{
1616	r_icache_fsm = ICACHE_CC_CHECK;
1617	r_icache_fsm_save = r_icache_fsm.read();
1618	break;
1619	}
1620
1621	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1622	{
1623	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1624	{
1625	if ( not r_icache_cc_send_req.read() )
1626	{
1627	r_icache_miss_inval = false;
1628	// request cleanup
1629	r_icache_cc_send_req = true;
1630	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1631	r_icache_cc_send_way = r_icache_miss_way.read();
1632	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1633
1634	#ifdef INSTRUMENTATION
1635	m_cpt_icache_dir_write++;
1636	#endif
1637	r_icache.write_dir( r_icache_vci_paddr.read(),
1638	r_icache_miss_way.read(),
1639	r_icache_miss_set.read(),
1640	CACHE_SLOT_STATE_ZOMBI );
1641	#if DEBUG_ICACHE
1642	if ( m_debug_icache_fsm )
1643	{
1644	std::cout << " <PROC " << name()
1645	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1646	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1647	<< " WAY = " << std::dec << r_icache_miss_way.read()
1648	<< " SET = " << r_icache_miss_set.read() << std::endl;
1649	}
1650	#endif
1651	}
1652	}
1653	else // Switch slot to VALID state
1654	{
1655
1656	#ifdef INSTRUMENTATION
1657	m_cpt_icache_dir_write++;
1658	#endif
1659	r_icache.write_dir( r_icache_vci_paddr.read(),
1660	r_icache_miss_way.read(),
1661	r_icache_miss_set.read(),
1662	CACHE_SLOT_STATE_VALID );
1663	#if DEBUG_ICACHE
1664	if ( m_debug_icache_fsm )
1665	{
1666	std::cout << " <PROC " << name()
1667	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1668	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1669	<< " WAY = " << std::dec << r_icache_miss_way.read()
1670	<< " SET = " << r_icache_miss_set.read() << std::endl;
1671	}
1672	#endif
1673	}
1674
1675	r_icache_fsm = ICACHE_IDLE;
1676	}
1677	break;
1678	}
1679	////////////////////
1680	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1681	{
1682	// coherence interrupt
1683	if ( r_cc_receive_icache_req.read() )
1684	{
1685	r_icache_fsm = ICACHE_CC_CHECK;
1686	r_icache_fsm_save = r_icache_fsm.read();
1687	break;
1688	}
1689
1690	if ( r_vci_rsp_ins_error.read() ) // bus error
1691	{
1692	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1693	r_mmu_ibvar = m_ireq.addr;
1694	r_vci_rsp_ins_error = false;
1695	m_irsp.valid = true;
1696	m_irsp.error = true;
1697	r_icache_fsm = ICACHE_IDLE;
1698	}
1699	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1700	{
1701	vci_rsp_fifo_icache_get = true;
1702	r_icache_fsm = ICACHE_IDLE;
1703	if ( m_ireq.valid and
1704	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1705	{
1706	m_irsp.valid = true;
1707	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1708	}
1709	}
1710	break;
1711	}
1712	/////////////////////
1713	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1714	// handling coherence requests.
1715	// if there is a matching pending miss, it is
1716	// signaled in the r_icache_miss_inval flip-flop.
1717	// The return state is defined in r_icache_fsm_save.
1718	{
1719	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1720	paddr_t mask = ~((m_icache_words<<2)-1);
1721
1722	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1723	// We switch the directory slot to EMPTY state
1724	// and reset r_icache_miss_clack if the cleanup ack
1725	// is matching a pending miss
1726	{
1727
1728	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1729
1730	#ifdef INSTRUMENTATION
1731	m_cpt_icache_dir_write++;
1732	#endif
1733	r_icache.write_dir( 0,
1734	r_cc_receive_icache_way.read(),
1735	r_cc_receive_icache_set.read(),
1736	CACHE_SLOT_STATE_EMPTY);
1737
1738	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1739	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1740	r_icache_miss_clack = false;
1741
1742	r_icache_fsm = r_icache_fsm_save.read() ;
1743	r_cc_receive_icache_req = false;
1744
1745	#if DEBUG_ICACHE
1746	if ( m_debug_icache_fsm )
1747	{
1748	std::cout << " <PROC " << name()
1749	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1750	<< " set = " << r_cc_receive_icache_set.read()
1751	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1752	}
1753	#endif
1754	}
1755	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1756	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1757	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1758	{
1759	// signaling the matching
1760	r_icache_miss_inval = true;
1761
1762	// in case of update, go to CC_UPDT
1763	// JUST TO POP THE FIFO
1764	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1765	{
1766	r_icache_fsm = ICACHE_CC_UPDT;
1767	r_icache_cc_word = r_cc_receive_word_idx.read();
1768	// just pop the fifo , don't write in icache
1769	r_icache_cc_need_write = false;
1770	}
1771	// the request is dealt with
1772	else
1773	{
1774	r_cc_receive_icache_req = false;
1775	r_icache_fsm = r_icache_fsm_save.read();
1776	}
1777	#if DEBUG_ICACHE
1778	if ( m_debug_icache_fsm )
1779	{
1780	std::cout << " <PROC " << name()
1781	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1782	<< " PADDR = " << std::hex << paddr << std::endl;
1783	}
1784	#endif
1785	}
1786	else // no match
1787	{
1788	int state;
1789	size_t way;
1790	size_t set;
1791	size_t word;
1792
1793	#ifdef INSTRUMENTATION
1794	m_cpt_icache_dir_read++;
1795	#endif
1796	r_icache.read_dir(paddr,
1797	&state,
1798	&way,
1799	&set,
1800	&word);
1801
1802	r_icache_cc_way = way;
1803	r_icache_cc_set = set;
1804
1805	if ( state == CACHE_SLOT_STATE_VALID) // hit
1806	{
1807	// need to update the cache state
1808	r_icache_cc_need_write = true;
1809	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1810	{
1811	r_icache_fsm = ICACHE_CC_UPDT;
1812	r_icache_cc_word = r_cc_receive_word_idx.read();
1813	}
1814	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1815	{
1816	r_icache_fsm = ICACHE_CC_INVAL;
1817	}
1818	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1819	{
1820	r_icache_fsm = ICACHE_CC_BROADCAST;
1821	}
1822	}
1823	else // miss
1824	{
1825	// multicast acknowledgement required in case of update
1826	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1827	{
1828	r_icache_fsm = ICACHE_CC_UPDT;
1829	r_icache_cc_word = r_cc_receive_word_idx.read();
1830	// just pop the fifo , don't write in icache
1831	r_icache_cc_need_write = false;
1832	}
1833	else // No response needed
1834	{
1835	r_cc_receive_icache_req = false;
1836	r_icache_fsm = r_icache_fsm_save.read();
1837	}
1838	}
1839	}
1840	break;
1841	}
1842	/////////////////////
1843	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1844	{
1845
1846	#if DEBUG_ICACHE
1847	if ( m_debug_icache_fsm )
1848	{
1849	std::cout << " <PROC " << name()
1850	<< " ICACHE_CC_INVAL> slot returns to empty state"
1851	<< " set = " << r_icache_cc_set.read()
1852	<< " / way = " << r_icache_cc_way.read() << std::endl;
1853	}
1854	#endif
1855
1856	#ifdef INSTRUMENTATION
1857	m_cpt_icache_dir_read++;
1858	#endif
1859	if (r_icache_cc_need_write.read())
1860	{
1861	r_icache.write_dir( 0,
1862	r_icache_cc_way.read(),
1863	r_icache_cc_set.read(),
1864	CACHE_SLOT_STATE_EMPTY );
1865	// no need to write in the cache anymore
1866	r_icache_cc_need_write = false;
1867	}
1868
1869	// multicast acknowledgement
1870	// send a request to cc_send_fsm
1871	if(not r_icache_cc_send_req.read()) // cc_send is available
1872	{
1873	// coherence request completed
1874	r_cc_receive_icache_req = false;
1875	// request multicast acknowledgement
1876	r_icache_cc_send_req = true;
1877	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1878	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1879
1880	r_icache_fsm = r_icache_fsm_save.read();
1881	}
1882	//else wait for previous cc_send request to be sent
1883	break;
1884	}
1885	////////////////////
1886	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1887	{
1888
1889	#if DEBUG_ICACHE
1890	if ( m_debug_icache_fsm )
1891	{
1892	std::cout << " <PROC " << name()
1893	<< " ICACHE_CC_UPDT> Write one word "
1894	<< " set = " << r_icache_cc_set.read()
1895	<< " / way = " << r_icache_cc_way.read()
1896	<< " / word = " << r_icache_cc_word.read() << std::endl;
1897	}
1898	#endif
1899
1900	#ifdef INSTRUMENTATION
1901	m_cpt_icache_data_write++;
1902	#endif
1903	size_t word = r_icache_cc_word.read();
1904	size_t way = r_icache_cc_way.read();
1905	size_t set = r_icache_cc_set.read();
1906
1907	if (r_cc_receive_updt_fifo_be.rok())
1908	{
1909	if (r_icache_cc_need_write.read())
1910	{
1911	r_icache.write( way,
1912	set,
1913	word,
1914	r_cc_receive_updt_fifo_data.read(),
1915	r_cc_receive_updt_fifo_be.read() );
1916
1917	r_icache_cc_word = word+1;
1918	}
1919	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1920	{
1921	// no need to write in the cache anymore
1922	r_icache_cc_need_write = false;
1923	// wait to send a request to cc_send_fsm
1924	if(not r_icache_cc_send_req.read()) // cc_send is available
1925	{
1926	// coherence request completed
1927	r_cc_receive_icache_req = false;
1928	// request multicast acknowledgement
1929	r_icache_cc_send_req = true;
1930	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1931	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1932
1933	r_icache_fsm = r_icache_fsm_save.read();
1934	}
1935	}
1936	else
1937	{
1938	//consume fifo if not eop
1939	cc_receive_updt_fifo_get = true;
1940	}
1941	}
1942	break;
1943	}
1944	/////////////////////////
1945	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1946	// and request a cleanup
1947	{
1948
1949	#if DEBUG_ICACHE
1950	if ( m_debug_icache_fsm )
1951	{
1952	std::cout << " <PROC " << name()
1953	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1954	<< " set = " << r_icache_cc_set.read()
1955	<< " / way = " << r_icache_cc_way.read() << std::endl;
1956	}
1957	#endif
1958
1959	#ifdef INSTRUMENTATION
1960	m_cpt_icache_dir_write++;
1961	#endif
1962	if (r_icache_cc_need_write.read())
1963	{
1964	r_icache.write_dir( 0,
1965	r_icache_cc_way.read(),
1966	r_icache_cc_set.read(),
1967	CACHE_SLOT_STATE_ZOMBI );
1968	// no need to write in the cache anymore
1969	r_icache_cc_need_write = false;
1970	}
1971
1972	// cleanup
1973	// send a request to cc_send_fsm
1974	if(not r_icache_cc_send_req.read()) // cc_send is available
1975	{
1976	// coherence request completed
1977	r_cc_receive_icache_req = false;
1978	// request cleanup
1979	r_icache_cc_send_req = true;
1980	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1981	r_icache_cc_send_way = r_icache_cc_way.read();
1982	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1983
1984	r_icache_fsm = r_icache_fsm_save.read();
1985	}
1986	//else wait for previous cc_send request to be sent
1987	break;
1988	}
1989	} // end switch r_icache_fsm
1990
1991	////////////////////////////////////////////////////////////////////////////////////
1992	// DCACHE FSM
1993	//
1994	// 1/ Coherence operations
1995	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1996	// - There is a coherence request when r_tgt_dcache_req is set.
1997	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1998	// and SC_WAIT states.
1999	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2000	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2001	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2002	// - For both types of requests, actions associated to the pre-empted state
2003	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2004	// or CC_CLACK) to execute the requested coherence operation, and returns
2005	// to the pre-empted state.
2006	//
2007	// 2/ TLB miss
2008	// The page tables are generally cacheable.
2009	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2010	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2011	// this sub-fsm implement the table-walk...
2012	//
2013	// 3/ processor requests
2014	// Processor requests are taken in IDLE state only.
2015	// The IDLE state implements a two stages pipe-line to handle write bursts:
2016	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2017	// - The registration in wbuf and the dcache update is done in stage P1
2018	// (if the processor request is a write).
2019	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2020	// the operations that must be done in P1 stage, and the access type
2021	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2022	// READ requests are delayed if a cache update is requested.
2023	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2024	// that is done (before handling the processor request) by a dedicated sub-fsm.
2025	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2026	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2027	//
2028	// 4/ Atomic instructions LL/SC
2029	// The LL/SC address are non cacheable (systematic access to memory).
2030	// The llsc buffer contains a registration for an active LL/SC operation
2031	// (with an address, a registration key, an aging counter and a valid bit).
2032	// - LL requests from the processor are transmitted as a one flit VCI command
2033	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2034	// be 8 as the response is 2 flits long (data and registration key)
2035	// - SC requests from the processor are systematically transmitted to the
2036	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2037	// as PKTID value). The first flit contains the registration key, the second
2038	// flit contains the data to write in case of success.
2039	// The cache is not updated, as this is done in case of success by the
2040	// coherence transaction.
2041	//
2042	// 5/ Non cacheable access:
2043	// This component implement a strong order between non cacheable access
2044	// (read or write) : A new non cacheable VCI transaction starts only when
2045	// the previous non cacheable transaction is completed. Both cacheable and
2046	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2047	// a non cacheable write transaction posted in the write buffer by setting the
2048	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2049	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2050	// pending non cacheable write transaction completes).
2051	//
2052	// 6/ Error handling:
2053	// When the MMU is not activated, Read Bus Errors are synchronous events,
2054	// but Write Bus Errors are asynchronous events (processor is not frozen).
2055	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2056	// r_vci_rsp_data_error flip-flop, without writing any data in the
2057	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2058	// by the DCACHE FSM.
2059	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2060	// the asynchronous error using the setWriteBerr() method.
2061	// When the MMU is activated bus error are rare events, as the MMU
2062	// checks the physical address before the VCI transaction starts.
2063	////////////////////////////////////////////////////////////////////////////////////////
2064
2065	// default value for m_drsp
2066	m_drsp.valid = false;
2067	m_drsp.error = false;
2068	m_drsp.rdata = 0;
2069
2070	switch ( r_dcache_fsm.read() )
2071	{
2072	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2073	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2074	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2075	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2076	// 4) XTN request (processor) => DCACHE_XTN_*
2077	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2078	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2079	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2080	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2081	// 9) LL access (processor) => DCACHE_LL_WAIT
2082	// 10) SC access (processor) => DCACHE_SC_WAIT
2083	//
2084	// There is a fixed priority to handle requests to DCACHE:
2085	// 1/ the ITLB/DTLB invalidate requests
2086	// 2/ the coherence requests,
2087	// 3/ the processor requests (including DTLB miss),
2088	// 4/ the ITLB miss requests,
2089	// The address space processor request are handled as follows:
2090	// - WRITE request is blocked if the Dirty bit mus be set.
2091	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2092	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2093	// - READ request generate a simultaneouss access to DCACHE.DATA
2094	// and DCACHE.DIR, but is delayed if DCACHE update required.
2095	//
2096	// There is 4 configurations defining the access type to
2097	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2098	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2099	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2100	// 0 / 0 / NOP / NOP / NOP /
2101	// 0 / 1 / NOP / NOP / WRITE /
2102	// 1 / 0 / READ / READ / NOP /
2103	// 1 / 1 / READ / READ / WRITE /
2104	// Those two registers are set at each cycle from the 3 signals
2105	// updt_request, wbuf_request, wbuf_write_miss.
2106	{
2107	paddr_t paddr; // physical address
2108	pte_info_t tlb_flags;
2109	size_t tlb_way;
2110	size_t tlb_set;
2111	paddr_t tlb_nline;
2112	size_t cache_way;
2113	size_t cache_set;
2114	size_t cache_word;
2115	uint32_t cache_rdata = 0;
2116	bool tlb_hit = false;
2117	int cache_state = CACHE_SLOT_STATE_EMPTY;
2118
2119	bool tlb_inval_required = false; // request TLB inval after cache update
2120	bool wbuf_write_miss = false; // miss a WBUF write request
2121	bool updt_request = false; // request DCACHE update in P1 stage
2122	bool wbuf_request = false; // request WBUF write in P1 stage
2123
2124	// physical address computation : systematic DTLB access if activated)
2125	if ( m_dreq.valid )
2126	{
2127	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2128	{
2129	tlb_hit = r_dtlb.translate( m_dreq.addr,
2130	&paddr,
2131	&tlb_flags,
2132	&tlb_nline,
2133	&tlb_way,
2134	&tlb_set );
2135	#ifdef INSTRUMENTATION
2136	m_cpt_dtlb_read++;
2137	#endif
2138	}
2139	else // identity mapping
2140	{
2141	paddr = (paddr_t)m_dreq.addr;
2142	}
2143	} // end physical address computation
2144
2145	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2146	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2147	{
2148	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2149	{
2150	r_dcache.read_dir( paddr,
2151	&cache_state,
2152	&cache_way,
2153	&cache_set,
2154	&cache_word );
2155
2156	r_dcache.write( r_dcache_save_cache_way.read(),
2157	r_dcache_save_cache_set.read(),
2158	r_dcache_save_cache_word.read(),
2159	r_dcache_save_wdata.read(),
2160	r_dcache_save_be.read() );
2161	#ifdef INSTRUMENTATION
2162	m_cpt_dcache_dir_read++;
2163	m_cpt_dcache_data_write++;
2164	#endif
2165	}
2166	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2167	{
2168	r_dcache.read( paddr,
2169	&cache_rdata,
2170	&cache_way,
2171	&cache_set,
2172	&cache_word,
2173	&cache_state );
2174	#ifdef INSTRUMENTATION
2175	m_cpt_dcache_dir_read++;
2176	m_cpt_dcache_data_read++;
2177	#endif
2178	}
2179	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2180	{
2181	r_dcache.write( r_dcache_save_cache_way.read(),
2182	r_dcache_save_cache_set.read(),
2183	r_dcache_save_cache_word.read(),
2184	r_dcache_save_wdata.read(),
2185	r_dcache_save_be.read() );
2186	#ifdef INSTRUMENTATION
2187	m_cpt_dcache_data_write++;
2188	#endif
2189	}
2190	} // end dcache access
2191
2192	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2193	if ( r_dcache_updt_req.read() )
2194	{
2195	size_t way = r_dcache_save_cache_way.read();
2196	size_t set = r_dcache_save_cache_set.read();
2197
2198	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2199	{
2200	tlb_inval_required = true;
2201	r_dcache_tlb_inval_set = 0;
2202	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2203	(uint32_log2(m_dcache_words<<2));
2204	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2205	}
2206	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2207	{
2208	r_itlb.reset();
2209	r_dtlb.reset();
2210	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2211	}
2212
2213	#if DEBUG_DCACHE
2214	if ( m_debug_dcache_fsm )
2215	{
2216	std::cout << " <PROC " << name()
2217	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2218	<< " / WAY = " << r_dcache_save_cache_way.read()
2219	<< " / SET = " << r_dcache_save_cache_set.read()
2220	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2221	<< " / DATA = " << r_dcache_save_wdata.read()
2222	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2223	}
2224	#endif
2225	} // end test TLB inval
2226
2227	// Try WBUF update in P1 stage
2228	// Miss if the write request is non cacheable, and there is a pending
2229	// non cacheable write, or if the write buffer is full.
2230	if ( r_dcache_wbuf_req.read() )
2231	{
2232	// miss if write not cacheable, and previous non cacheable write registered
2233	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2234	{
2235	wbuf_write_miss = true;
2236	}
2237	else // try a registration into write buffer
2238	{
2239	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2240	r_dcache_save_be.read(),
2241	r_dcache_save_wdata.read(),
2242	r_dcache_save_cacheable.read() );
2243	#ifdef INSTRUMENTATION
2244	m_cpt_wbuf_write++;
2245	#endif
2246	if ( not wok ) // miss if write buffer full
2247	{
2248	wbuf_write_miss = true;
2249	}
2250	else // update the write_buffer state extension
2251	{
2252	if(not r_dcache_pending_unc_write.read())
2253	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2254	}
2255	}
2256	} // end WBUF update
2257
2258	// Computing the response to processor,
2259	// and the next value for r_dcache_fsm
2260
2261	// itlb/dtlb invalidation self-request
2262	if ( tlb_inval_required )
2263	{
2264	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2265	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2266	}
2267
2268	// coherence request (from CC_RECEIVE FSM)
2269	else if ( r_cc_receive_dcache_req.read() )
2270	{
2271	r_dcache_fsm = DCACHE_CC_CHECK;
2272	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2273	}
2274
2275	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2276	// we don't take the processor request, and registers
2277	// are frozen in case of wbuf_write_miss
2278	else if ( m_dreq.valid and not wbuf_write_miss )
2279	{
2280	// register processor request and DCACHE response
2281	r_dcache_save_vaddr = m_dreq.addr;
2282	r_dcache_save_be = m_dreq.be;
2283	r_dcache_save_wdata = m_dreq.wdata;
2284	r_dcache_save_paddr = paddr;
2285	r_dcache_save_cache_way = cache_way;
2286	r_dcache_save_cache_set = cache_set;
2287	r_dcache_save_cache_word = cache_word;
2288
2289	// READ XTN requests from processor
2290	// They are executed in this DCACHE_IDLE state.
2291	// The processor must not be in user mode
2292	if (m_dreq.type == iss_t::XTN_READ)
2293	{
2294	int xtn_opcode = (int)m_dreq.addr/4;
2295
2296	// checking processor mode:
2297	if (m_dreq.mode == iss_t::MODE_USER)
2298	{
2299	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2300	r_mmu_dbvar = m_dreq.addr;
2301	m_drsp.valid = true;
2302	m_drsp.error = true;
2303	m_drsp.rdata = 0;
2304	r_dcache_fsm = DCACHE_IDLE;
2305	}
2306	else
2307	{
2308	switch( xtn_opcode )
2309	{
2310	case iss_t::XTN_INS_ERROR_TYPE:
2311	m_drsp.rdata = r_mmu_ietr.read();
2312	m_drsp.valid = true;
2313	m_drsp.error = false;
2314	break;
2315
2316	case iss_t::XTN_DATA_ERROR_TYPE:
2317	m_drsp.rdata = r_mmu_detr.read();
2318	m_drsp.valid = true;
2319	m_drsp.error = false;
2320	break;
2321
2322	case iss_t::XTN_INS_BAD_VADDR:
2323	m_drsp.rdata = r_mmu_ibvar.read();
2324	m_drsp.valid = true;
2325	m_drsp.error = false;
2326	break;
2327
2328	case iss_t::XTN_DATA_BAD_VADDR:
2329	m_drsp.rdata = r_mmu_dbvar.read();
2330	m_drsp.valid = true;
2331	m_drsp.error = false;
2332	break;
2333
2334	case iss_t::XTN_PTPR:
2335	m_drsp.rdata = r_mmu_ptpr.read();
2336	m_drsp.valid = true;
2337	m_drsp.error = false;
2338	break;
2339
2340	case iss_t::XTN_TLB_MODE:
2341	m_drsp.rdata = r_mmu_mode.read();
2342	m_drsp.valid = true;
2343	m_drsp.error = false;
2344	break;
2345
2346	case iss_t::XTN_MMU_PARAMS:
2347	m_drsp.rdata = r_mmu_params;
2348	m_drsp.valid = true;
2349	m_drsp.error = false;
2350	break;
2351
2352	case iss_t::XTN_MMU_RELEASE:
2353	m_drsp.rdata = r_mmu_release;
2354	m_drsp.valid = true;
2355	m_drsp.error = false;
2356	break;
2357
2358	case iss_t::XTN_MMU_WORD_LO:
2359	m_drsp.rdata = r_mmu_word_lo.read();
2360	m_drsp.valid = true;
2361	m_drsp.error = false;
2362	break;
2363
2364	case iss_t::XTN_MMU_WORD_HI:
2365	m_drsp.rdata = r_mmu_word_hi.read();
2366	m_drsp.valid = true;
2367	m_drsp.error = false;
2368	break;
2369
2370	default:
2371	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2372	r_mmu_dbvar = m_dreq.addr;
2373	m_drsp.valid = true;
2374	m_drsp.error = true;
2375	m_drsp.rdata = 0;
2376	break;
2377	} // end switch xtn_opcode
2378	} // end else
2379	} // end if XTN_READ
2380
2381	// Handling WRITE XTN requests from processor.
2382	// They are not executed in this DCACHE_IDLE state
2383	// if they require access to the caches or the TLBs
2384	// that are already accessed.
2385	// Caches can be invalidated or flushed in user mode,
2386	// and the sync instruction can be executed in user mode
2387	else if (m_dreq.type == iss_t::XTN_WRITE)
2388	{
2389	int xtn_opcode = (int)m_dreq.addr/4;
2390	r_dcache_xtn_opcode = xtn_opcode;
2391
2392	// checking processor mode:
2393	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2394	(xtn_opcode != iss_t:: XTN_SYNC) &&
2395	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2396	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2397	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2398	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2399	{
2400	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2401	r_mmu_dbvar = m_dreq.addr;
2402	m_drsp.valid = true;
2403	m_drsp.error = true;
2404	m_drsp.rdata = 0;
2405	r_dcache_fsm = DCACHE_IDLE;
2406	}
2407	else
2408	{
2409	switch( xtn_opcode )
2410	{
2411	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2412	r_dcache_xtn_req = true;
2413	r_dcache_fsm = DCACHE_XTN_SWITCH;
2414	break;
2415
2416	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2417	r_mmu_mode = m_dreq.wdata;
2418	m_drsp.valid = true;
2419	r_dcache_fsm = DCACHE_IDLE;
2420	break;
2421
2422	case iss_t::XTN_DTLB_INVAL: // dtlb access
2423	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2424	break;
2425
2426	case iss_t::XTN_ITLB_INVAL: // itlb access
2427	r_dcache_xtn_req = true;
2428	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2429	break;
2430
2431	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2432	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2433	break;
2434
2435	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2436	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2437	if (sizeof(paddr_t) <= 32)
2438	{
2439	assert(r_mmu_word_hi.read() == 0 &&
2440	"high bits should be 0 for 32bit paddr");
2441	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2442	}
2443	else
2444	{
2445	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2446	(paddr_t)r_mmu_word_lo.read();
2447	}
2448	break;
2449
2450	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2451	r_dcache_flush_count = 0;
2452	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2453	break;
2454
2455	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2456	r_dcache_xtn_req = true;
2457	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2458	break;
2459
2460	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2461	r_dcache_xtn_req = true;
2462	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2463	break;
2464
2465	case iss_t::XTN_ICACHE_FLUSH: // icache access
2466	r_dcache_xtn_req = true;
2467	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2468	break;
2469
2470	case iss_t::XTN_SYNC: // wait until write buffer empty
2471	r_dcache_fsm = DCACHE_XTN_SYNC;
2472	break;
2473
2474	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2475	r_mmu_word_lo = m_dreq.wdata;
2476	m_drsp.valid = true;
2477	r_dcache_fsm = DCACHE_IDLE;
2478	break;
2479
2480	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2481	r_mmu_word_hi = m_dreq.wdata;
2482	m_drsp.valid = true;
2483	r_dcache_fsm = DCACHE_IDLE;
2484	break;
2485
2486	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2487	r_dcache_llsc_valid = false;
2488	m_drsp.valid = true;
2489	r_dcache_fsm = DCACHE_IDLE;
2490	break;
2491
2492	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2493	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2494	m_drsp.valid = true;
2495	r_dcache_fsm = DCACHE_IDLE;
2496	break;
2497
2498	default:
2499	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2500	r_mmu_dbvar = m_dreq.addr;
2501	m_drsp.valid = true;
2502	m_drsp.error = true;
2503	r_dcache_fsm = DCACHE_IDLE;
2504	break;
2505	} // end switch xtn_opcode
2506	} // end else
2507	} // end if XTN_WRITE
2508
2509	// Handling processor requests to address space (READ/WRITE/LL/SC)
2510	// The dtlb and dcache can be activated or not.
2511	// We compute the cacheability, and check processor request validity:
2512	// - If DTLB not activated : cacheability is defined by the segment table,
2513	// and there is no access rights checking.
2514	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2515	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2516	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2517	else
2518	{
2519	bool valid_req;
2520	bool cacheable;
2521
2522	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2523	{
2524	valid_req = true;
2525
2526	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2527	else cacheable = m_cacheability_table[m_dreq.addr];
2528	}
2529	else // dtlb activated
2530	{
2531	if ( tlb_hit ) // tlb hit
2532	{
2533	// cacheability
2534	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2535	else cacheable = tlb_flags.c;
2536
2537	// access rights checking
2538	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2539	{
2540	if ( (m_dreq.type == iss_t::DATA_READ) or
2541	(m_dreq.type == iss_t::DATA_LL) )
2542	{
2543	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2544	}
2545	else
2546	{
2547	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2548	}
2549	valid_req = false;
2550	r_mmu_dbvar = m_dreq.addr;
2551	m_drsp.valid = true;
2552	m_drsp.error = true;
2553	m_drsp.rdata = 0;
2554	#if DEBUG_DCACHE
2555	if ( m_debug_dcache_fsm )
2556	{
2557	std::cout << " <PROC " << name()
2558	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2559	}
2560	#endif
2561	}
2562	else if ( not tlb_flags.w and
2563	((m_dreq.type == iss_t::DATA_WRITE) or
2564	(m_dreq.type == iss_t::DATA_SC)) )
2565	{
2566	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2567	valid_req = false;
2568	r_mmu_dbvar = m_dreq.addr;
2569	m_drsp.valid = true;
2570	m_drsp.error = true;
2571	m_drsp.rdata = 0;
2572	#if DEBUG_DCACHE
2573	if ( m_debug_dcache_fsm )
2574	{
2575	std::cout << " <PROC " << name()
2576	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2577	}
2578	#endif
2579	}
2580	else
2581	{
2582	valid_req = true;
2583	}
2584	}
2585	else // tlb miss
2586	{
2587	valid_req = false;
2588	r_dcache_tlb_vaddr = m_dreq.addr;
2589	r_dcache_tlb_ins = false;
2590	r_dcache_fsm = DCACHE_TLB_MISS;
2591	}
2592	} // end DTLB activated
2593
2594	if ( valid_req ) // processor request is valid after TLB check
2595	{
2596	r_dcache_save_cacheable = cacheable;
2597
2598	// READ request
2599	// The read requests are taken only if there is no cache update.
2600	// We request a VCI transaction to CMD FSM if miss or uncachable
2601	if ( ((m_dreq.type == iss_t::DATA_READ))
2602	and not r_dcache_updt_req.read() )
2603	{
2604	if ( cacheable ) // cacheable read
2605	{
2606	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2607	{
2608	#ifdef INSTRUMENTATION
2609	m_cpt_dcache_miss++;
2610	#endif
2611	// request a VCI DMISS transaction
2612	r_dcache_vci_paddr = paddr;
2613	r_dcache_vci_miss_req = true;
2614	r_dcache_miss_type = PROC_MISS;
2615	r_dcache_fsm = DCACHE_MISS_SELECT;
2616	#if DEBUG_DCACHE
2617	if ( m_debug_dcache_fsm )
2618	{
2619	std::cout << " <PROC " << name()
2620	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2621	}
2622	#endif
2623	}
2624	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2625	{
2626	// stalled until cleanup is acknowledged
2627	r_dcache_fsm = DCACHE_IDLE;
2628	}
2629	else // cache hit
2630	{
2631	#ifdef INSTRUMENTATION
2632	m_cpt_data_read++;
2633	#endif
2634	// returns data to processor
2635	m_drsp.valid = true;
2636	m_drsp.error = false;
2637	m_drsp.rdata = cache_rdata;
2638	#if DEBUG_DCACHE
2639	if ( m_debug_dcache_fsm )
2640	{
2641	std::cout << " <PROC " << name()
2642	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2643	}
2644	#endif
2645	}
2646	}
2647	else // uncacheable read
2648	{
2649	r_dcache_vci_paddr = paddr;
2650	r_dcache_vci_unc_be = m_dreq.be;
2651	r_dcache_vci_unc_req = true;
2652	r_dcache_fsm = DCACHE_UNC_WAIT;
2653	#if DEBUG_DCACHE
2654	if ( m_debug_dcache_fsm )
2655	{
2656	std::cout << " <PROC " << name()
2657	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2658	}
2659	#endif
2660	}
2661	} // end READ
2662
2663	// LL request (non cachable)
2664	// We request a VCI LL transaction to CMD FSM and register
2665	// the LL/SC operation in llsc buffer.
2666	else if (m_dreq.type == iss_t::DATA_LL)
2667	{
2668	// register paddr in LLSC buffer
2669	r_dcache_llsc_paddr = paddr;
2670	r_dcache_llsc_count = LLSC_TIMEOUT;
2671	r_dcache_llsc_valid = true;
2672
2673	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2674	r_dcache_vci_ll_req = true;
2675	r_dcache_vci_paddr = paddr;
2676	r_dcache_ll_rsp_count = 0;
2677	r_dcache_fsm = DCACHE_LL_WAIT;
2678
2679	}// end LL
2680
2681	// WRITE request:
2682	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2683	// the processor and set the Dirty bit before handling the write request,
2684	// going to the DCACHE_DIRTY_GT_PTE state.
2685	// If we don't need to set the Dirty bit, we can acknowledge
2686	// the processor request, as the write arguments (including the
2687	// physical address) are registered in r_dcache_save registers,
2688	// and the write will be done in the P1 pipeline stage.
2689	else if ( m_dreq.type == iss_t::DATA_WRITE )
2690	{
2691	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2692	and not tlb_flags.d ) // Dirty bit must be set
2693	{
2694	// The PTE physical address is obtained from the nline value (dtlb),
2695	// and from the virtual address (word index)
2696	if ( tlb_flags.b ) // PTE1
2697	{
2698	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2699	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2700	}
2701	else // PTE2
2702	{
2703	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2704	(paddr_t)((m_dreq.addr>>9) & 0x38);
2705	}
2706	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2707	}
2708	else // Write request accepted
2709	{
2710	#ifdef INSTRUMENTATION
2711	m_cpt_data_write++;
2712	#endif
2713	// cleaning llsc buffer if address matching
2714	if ( paddr == r_dcache_llsc_paddr.read() )
2715	r_dcache_llsc_valid = false;
2716
2717	// response to processor
2718	m_drsp.valid = true;
2719
2720	// activating P1 stage
2721	wbuf_request = true;
2722	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2723	}
2724	} // end WRITE
2725
2726	// SC request:
2727	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2728	// the processor and set the Dirty bit before handling the write request,
2729	// going to the DCACHE_DIRTY_GT_PTE state.
2730	// If we don't need to set the Dirty bit, we test the llsc buffer:
2731	// If failure, we send a negative response to processor.
2732	// If success, we request a SC transaction to CMD FSM and go
2733	// to DCACHE_SC_WAIT state.
2734	// We don't check a possible write hit in dcache, as the cache update
2735	// is done by the coherence transaction induced by the SC...
2736	else if ( m_dreq.type == iss_t::DATA_SC )
2737	{
2738	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2739	and not tlb_flags.d ) // Dirty bit must be set
2740	{
2741	// The PTE physical address is obtained from the nline value (dtlb),
2742	// and the word index (virtual address)
2743	if ( tlb_flags.b ) // PTE1
2744	{
2745	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2746	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2747	}
2748	else // PTE2
2749	{
2750	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2751	(paddr_t)((m_dreq.addr>>9) & 0x38);
2752	}
2753	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2754	m_drsp.valid = false;
2755	m_drsp.error = false;
2756	m_drsp.rdata = 0;
2757	}
2758	else // SC request accepted
2759	{
2760	#ifdef INSTRUMENTATION
2761	m_cpt_data_sc++;
2762	#endif
2763	// checking local success
2764	if( r_dcache_llsc_valid.read() and
2765	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2766	{
2767	// request an SC CMD and go to DCACHE_SC_WAIT state
2768	r_dcache_vci_paddr = paddr;
2769	r_dcache_vci_sc_req = true;
2770	r_dcache_vci_sc_data = m_dreq.wdata;
2771	r_dcache_fsm = DCACHE_SC_WAIT;
2772	}
2773	else // local fail
2774	{
2775	m_drsp.valid = true;
2776	m_drsp.error = false;
2777	m_drsp.rdata = 0x1;
2778	}
2779	}
2780	} // end SC
2781	} // end valid_req
2782	} // end if read/write/ll/sc request
2783	} // end processor request
2784
2785	// itlb miss request
2786	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2787	{
2788	r_dcache_tlb_ins = true;
2789	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2790	r_dcache_fsm = DCACHE_TLB_MISS;
2791	}
2792
2793	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2794	r_dcache_updt_req = updt_request;
2795	r_dcache_wbuf_req = wbuf_request or
2796	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2797	break;
2798	}
2799	/////////////////////
2800	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2801	// Input arguments are:
2802	// - r_dcache_tlb_vaddr
2803	// - r_dcache_tlb_ins (true when itlb miss)
2804	// The sub-fsm access the dcache to find the missing TLB entry,
2805	// and activates the cache miss procedure in case of miss.
2806	// It bypass the first level page table access if possible.
2807	// It uses atomic access to update the R/L access bits
2808	// in the page table if required.
2809	// It directly updates the itlb or dtlb, and writes into the
2810	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2811	{
2812	uint32_t ptba = 0;
2813	bool bypass;
2814	paddr_t pte_paddr;
2815
2816	// evaluate bypass in order to skip first level page table access
2817	if ( r_dcache_tlb_ins.read() ) // itlb miss
2818	{
2819	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2820	}
2821	else // dtlb miss
2822	{
2823	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2824	}
2825
2826	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2827	{
2828	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2829	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2830	r_dcache_tlb_paddr = pte_paddr;
2831	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2832	}
2833	else // Try to read PTE2 in dcache
2834	{
2835	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2836	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2837	r_dcache_tlb_paddr = pte_paddr;
2838	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2839	}
2840
2841	#if DEBUG_DCACHE
2842	if ( m_debug_dcache_fsm )
2843	{
2844	if ( r_dcache_tlb_ins.read() )
2845	{
2846	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2847	}
2848	else
2849	{
2850	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2851	}
2852	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2853	<< " / BYPASS = " << bypass
2854	<< " / PTE_ADR = " << pte_paddr << std::endl;
2855	}
2856	#endif
2857
2858	break;
2859	}
2860	/////////////////////////
2861	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2862	{
2863	uint32_t entry;
2864	size_t way;
2865	size_t set;
2866	size_t word;
2867
2868	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2869	&entry,
2870	&way,
2871	&set,
2872	&word );
2873	#ifdef INSTRUMENTATION
2874	m_cpt_dcache_data_read++;
2875	m_cpt_dcache_dir_read++;
2876	#endif
2877	if ( hit ) // hit in dcache
2878	{
2879	if ( not (entry & PTE_V_MASK) ) // unmapped
2880	{
2881	if ( r_dcache_tlb_ins.read() )
2882	{
2883	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2884	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2885	r_icache_tlb_miss_req = false;
2886	r_icache_tlb_rsp_error = true;
2887	}
2888	else
2889	{
2890	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2891	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2892	m_drsp.valid = true;
2893	m_drsp.error = true;
2894	}
2895	r_dcache_fsm = DCACHE_IDLE;
2896
2897	#if DEBUG_DCACHE
2898	if ( m_debug_dcache_fsm )
2899	{
2900	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2901	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2902	<< std::dec << " / way = " << way
2903	<< std::dec << " / set = " << set
2904	<< std::dec << " / word = " << word
2905	<< std::hex << " / PTE1 = " << entry << std::endl;
2906	}
2907	#endif
2908
2909	}
2910	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2911	{
2912	// mark the cache line ac containing a PTD
2913	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2914
2915	// register bypass
2916	if ( r_dcache_tlb_ins.read() ) // itlb
2917	{
2918	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2919	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2920	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2921	}
2922	else // dtlb
2923	{
2924	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2925	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2926	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2927	}
2928	r_dcache_tlb_paddr =
2929	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2930	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2931	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2932
2933	#if DEBUG_DCACHE
2934	if ( m_debug_dcache_fsm )
2935	{
2936	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2937	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2938	<< std::dec << " / way = " << way
2939	<< std::dec << " / set = " << set
2940	<< std::dec << " / word = " << word
2941	<< std::hex << " / PTD = " << entry << std::endl;
2942	}
2943	#endif
2944	}
2945	else // PTE1 : we must update the TLB
2946	{
2947	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2948	r_dcache_tlb_pte_flags = entry;
2949	r_dcache_tlb_cache_way = way;
2950	r_dcache_tlb_cache_set = set;
2951	r_dcache_tlb_cache_word = word;
2952	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2953
2954	#if DEBUG_DCACHE
2955	if ( m_debug_dcache_fsm )
2956	{
2957	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2958	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2959	<< std::dec << " / way = " << way
2960	<< std::dec << " / set = " << set
2961	<< std::dec << " / word = " << word
2962	<< std::hex << " / PTE1 = " << entry << std::endl;
2963	}
2964	#endif
2965	}
2966	}
2967	else // we must load the missing cache line in dcache
2968	{
2969	r_dcache_vci_miss_req = true;
2970	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2971	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2972	r_dcache_miss_type = PTE1_MISS;
2973	r_dcache_fsm = DCACHE_MISS_SELECT;
2974
2975	#if DEBUG_DCACHE
2976	if ( m_debug_dcache_fsm )
2977	{
2978	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2979	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2980	}
2981	#endif
2982	}
2983	break;
2984	}
2985	////////////////////////////
2986	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2987	{
2988	size_t way;
2989	size_t set;
2990
2991	if ( r_dcache_tlb_ins.read() )
2992	{
2993	r_itlb.select( r_dcache_tlb_vaddr.read(),
2994	true, // PTE1
2995	&way,
2996	&set );
2997	#ifdef INSTRUMENTATION
2998	m_cpt_itlb_read++;
2999	#endif
3000	}
3001	else
3002	{
3003	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3004	true, // PTE1
3005	&way,
3006	&set );
3007	#ifdef INSTRUMENTATION
3008	m_cpt_dtlb_read++;
3009	#endif
3010	}
3011	r_dcache_tlb_way = way;
3012	r_dcache_tlb_set = set;
3013	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3014
3015	#if DEBUG_DCACHE
3016	if ( m_debug_dcache_fsm )
3017	{
3018	if ( r_dcache_tlb_ins.read() )
3019	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3020	else
3021	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3022	std::cout << " way = " << std::dec << way
3023	<< " / set = " << set << std::endl;
3024	}
3025	#endif
3026	break;
3027	}
3028	//////////////////////////
3029	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3030	// - if L/R bit already set, exit the sub-fsm.
3031	// - if not, we update the page table but we dont write
3032	// neither in DCACHE, nor in TLB, as this will be done by
3033	// the coherence mechanism.
3034	{
3035	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3036	uint32_t pte = r_dcache_tlb_pte_flags.read();
3037	bool pt_updt = false;
3038	bool local = true;
3039
3040	// We should compute the access locality:
3041	// The PPN MSB bits define the destination cluster index.
3042	// The m_srcid_d MSB bits define the source cluster index.
3043	// The number of bits to compare depends on the number of clusters,
3044	// and can be obtained in the mapping table.
3045	// As long as this computation is not done, all access are local.
3046
3047	if ( local ) // local access
3048	{
3049	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3050	{
3051	pt_updt = true;
3052	r_dcache_vci_cas_old = pte;
3053	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3054	pte = pte \| PTE_L_MASK;
3055	r_dcache_tlb_pte_flags = pte;
3056	}
3057	}
3058	else // remote access
3059	{
3060	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3061	{
3062	pt_updt = true;
3063	r_dcache_vci_cas_old = pte;
3064	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3065	pte = pte \| PTE_R_MASK;
3066	r_dcache_tlb_pte_flags = pte;
3067	}
3068	}
3069
3070	if ( not pt_updt ) // update TLB and return
3071	{
3072	if ( r_dcache_tlb_ins.read() )
3073	{
3074	r_itlb.write( true, // 2M page
3075	pte,
3076	0, // argument unused for a PTE1
3077	r_dcache_tlb_vaddr.read(),
3078	r_dcache_tlb_way.read(),
3079	r_dcache_tlb_set.read(),
3080	nline );
3081	#ifdef INSTRUMENTATION
3082	m_cpt_itlb_write++;
3083	#endif
3084
3085	#if DEBUG_DCACHE
3086	if ( m_debug_dcache_fsm )
3087	{
3088	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3089	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3090	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3091	r_itlb.printTrace();
3092	}
3093	#endif
3094	}
3095	else
3096	{
3097	r_dtlb.write( true, // 2M page
3098	pte,
3099	0, // argument unused for a PTE1
3100	r_dcache_tlb_vaddr.read(),
3101	r_dcache_tlb_way.read(),
3102	r_dcache_tlb_set.read(),
3103	nline );
3104	#ifdef INSTRUMENTATION
3105	m_cpt_dtlb_write++;
3106	#endif
3107
3108	#if DEBUG_DCACHE
3109	if ( m_debug_dcache_fsm )
3110	{
3111	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3112	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3113	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3114	r_dtlb.printTrace();
3115	}
3116	#endif
3117	}
3118	r_dcache_fsm = DCACHE_TLB_RETURN;
3119	}
3120	else // update page table but not TLB
3121	{
3122	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3123
3124	#if DEBUG_DCACHE
3125	if ( m_debug_dcache_fsm )
3126	{
3127	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3128	<< std::endl;
3129	}
3130	#endif
3131	}
3132	break;
3133	}
3134	/////////////////////////
3135	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3136	{
3137	uint32_t pte_flags;
3138	uint32_t pte_ppn;
3139	size_t way;
3140	size_t set;
3141	size_t word;
3142
3143	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3144	&pte_flags,
3145	&pte_ppn,
3146	&way,
3147	&set,
3148	&word );
3149	#ifdef INSTRUMENTATION
3150	m_cpt_dcache_data_read++;
3151	m_cpt_dcache_dir_read++;
3152	#endif
3153	if ( hit ) // request hits in dcache
3154	{
3155	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3156	{
3157	if ( r_dcache_tlb_ins.read() )
3158	{
3159	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3160	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3161	r_icache_tlb_miss_req = false;
3162	r_icache_tlb_rsp_error = true;
3163	}
3164	else
3165	{
3166	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3167	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3168	m_drsp.valid = true;
3169	m_drsp.error = true;
3170	}
3171	r_dcache_fsm = DCACHE_IDLE;
3172
3173	#if DEBUG_DCACHE
3174	if ( m_debug_dcache_fsm )
3175	{
3176	std::cout << " <PROC " << name()
3177	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3178	<< " PTE_FLAGS = " << std::hex << pte_flags
3179	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3180	}
3181	#endif
3182	}
3183	else // mapped : we must update the TLB
3184	{
3185	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3186	r_dcache_tlb_pte_flags = pte_flags;
3187	r_dcache_tlb_pte_ppn = pte_ppn;
3188	r_dcache_tlb_cache_way = way;
3189	r_dcache_tlb_cache_set = set;
3190	r_dcache_tlb_cache_word = word;
3191	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3192
3193	#if DEBUG_DCACHE
3194	if ( m_debug_dcache_fsm )
3195	{
3196	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3197	<< " PTE_FLAGS = " << std::hex << pte_flags
3198	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3199	}
3200	#endif
3201	}
3202	}
3203	else // we must load the missing cache line in dcache
3204	{
3205	r_dcache_fsm = DCACHE_MISS_SELECT;
3206	r_dcache_vci_miss_req = true;
3207	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3208	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3209	r_dcache_miss_type = PTE2_MISS;
3210
3211	#if DEBUG_DCACHE
3212	if ( m_debug_dcache_fsm )
3213	{
3214	std::cout << " <PROC " << name()
3215	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3216	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3217	}
3218	#endif
3219	}
3220	break;
3221	}
3222	////////////////////////////
3223	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3224	{
3225	size_t way;
3226	size_t set;
3227
3228	if ( r_dcache_tlb_ins.read() )
3229	{
3230	r_itlb.select( r_dcache_tlb_vaddr.read(),
3231	false, // PTE2
3232	&way,
3233	&set );
3234	#ifdef INSTRUMENTATION
3235	m_cpt_itlb_read++;
3236	#endif
3237	}
3238	else
3239	{
3240	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3241	false, // PTE2
3242	&way,
3243	&set );
3244	#ifdef INSTRUMENTATION
3245	m_cpt_dtlb_read++;
3246	#endif
3247	}
3248
3249	#if DEBUG_DCACHE
3250	if ( m_debug_dcache_fsm )
3251	{
3252	if ( r_dcache_tlb_ins.read() )
3253	std::cout << " <PROC " << name()
3254	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3255	else
3256	std::cout << " <PROC " << name()
3257	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3258	std::cout << " way = " << std::dec << way
3259	<< " / set = " << set << std::endl;
3260	}
3261	#endif
3262	r_dcache_tlb_way = way;
3263	r_dcache_tlb_set = set;
3264	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3265	break;
3266	}
3267	//////////////////////////
3268	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3269	// - if L/R bit already set, exit the sub-fsm.
3270	// - if not, we update the page table but we dont write
3271	// neither in DCACHE, nor in TLB, as this will be done by
3272	// the coherence mechanism.
3273	{
3274	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3275	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3276	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3277	bool pt_updt = false;
3278	bool local = true;
3279
3280	// We should compute the access locality:
3281	// The PPN MSB bits define the destination cluster index.
3282	// The m_srcid_d MSB bits define the source cluster index.
3283	// The number of bits to compare depends on the number of clusters,
3284	// and can be obtained in the mapping table.
3285	// As long as this computation is not done, all access are local.
3286
3287	if ( local ) // local access
3288	{
3289	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3290	{
3291	pt_updt = true;
3292	r_dcache_vci_cas_old = pte_flags;
3293	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3294	pte_flags = pte_flags \| PTE_L_MASK;
3295	r_dcache_tlb_pte_flags = pte_flags;
3296	}
3297	}
3298	else // remote access
3299	{
3300	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3301	{
3302	pt_updt = true;
3303	r_dcache_vci_cas_old = pte_flags;
3304	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3305	pte_flags = pte_flags \| PTE_R_MASK;
3306	r_dcache_tlb_pte_flags = pte_flags;
3307	}
3308	}
3309
3310	if ( not pt_updt ) // update TLB
3311	{
3312	if ( r_dcache_tlb_ins.read() )
3313	{
3314	r_itlb.write( false, // 4K page
3315	pte_flags,
3316	pte_ppn,
3317	r_dcache_tlb_vaddr.read(),
3318	r_dcache_tlb_way.read(),
3319	r_dcache_tlb_set.read(),
3320	nline );
3321	#ifdef INSTRUMENTATION
3322	m_cpt_itlb_write++;
3323	#endif
3324
3325	#if DEBUG_DCACHE
3326	if ( m_debug_dcache_fsm )
3327	{
3328	std::cout << " <PROC " << name()
3329	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3330	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3331	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3332	r_itlb.printTrace();
3333	}
3334	#endif
3335	}
3336	else
3337	{
3338	r_dtlb.write( false, // 4K page
3339	pte_flags,
3340	pte_ppn,
3341	r_dcache_tlb_vaddr.read(),
3342	r_dcache_tlb_way.read(),
3343	r_dcache_tlb_set.read(),
3344	nline );
3345	#ifdef INSTRUMENTATION
3346	m_cpt_dtlb_write++;
3347	#endif
3348
3349	#if DEBUG_DCACHE
3350	if ( m_debug_dcache_fsm )
3351	{
3352	std::cout << " <PROC " << name()
3353	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3354	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3355	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3356	r_dtlb.printTrace();
3357	}
3358	#endif
3359
3360	}
3361	r_dcache_fsm = DCACHE_TLB_RETURN;
3362	}
3363	else // update page table but not TLB
3364	{
3365	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3366
3367	#if DEBUG_DCACHE
3368	if ( m_debug_dcache_fsm )
3369	{
3370	std::cout << " <PROC " << name()
3371	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3372	}
3373	#endif
3374	}
3375	break;
3376	}
3377	////////////////////////
3378	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3379	{
3380	#if DEBUG_DCACHE
3381	if ( m_debug_dcache_fsm )
3382	{
3383	std::cout << " <PROC " << name()
3384	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3385	}
3386	#endif
3387	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3388	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3389
3390	// checking llsc reservation buffer
3391	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3392	r_dcache_llsc_valid = false;
3393
3394	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3395	r_dcache_vci_cas_req = true;
3396	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3397	break;
3398	}
3399	////////////////////////
3400	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3401	// We consume the response in rsp FIFO,
3402	// and exit the sub-fsm, but we don't
3403	// analyse the response, because we don't
3404	// care if the L/R bit update is not done.
3405	// We must take the coherence requests because
3406	// there is a risk of dead-lock
3407
3408	{
3409	// coherence request (from CC_RECEIVE FSM)
3410	if ( r_cc_receive_dcache_req.read() )
3411	{
3412	r_dcache_fsm = DCACHE_CC_CHECK;
3413	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3414	break;
3415	}
3416
3417	if ( r_vci_rsp_data_error.read() ) // bus error
3418	{
3419	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3420	std::cout << "This should not happen in this state" << std::endl;
3421	exit(0);
3422	}
3423	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3424	{
3425	#if DEBUG_DCACHE
3426	if ( m_debug_dcache_fsm )
3427	{
3428	std::cout << " <PROC " << name()
3429	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3430	}
3431	#endif
3432	vci_rsp_fifo_dcache_get = true;
3433	r_dcache_fsm = DCACHE_TLB_RETURN;
3434	}
3435	break;
3436	}
3437	///////////////////////
3438	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3439	{
3440	#if DEBUG_DCACHE
3441	if ( m_debug_dcache_fsm )
3442	{
3443	std::cout << " <PROC " << name()
3444	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3445	}
3446	#endif
3447	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3448	r_dcache_fsm = DCACHE_IDLE;
3449	break;
3450	}
3451	///////////////////////
3452	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3453	// and both itlb and dtlb must be flushed.
3454	// Caution : the itlb miss requests must be taken
3455	// to avoid dead-lock in case of simultaneous ITLB miss
3456	{
3457	// itlb miss request
3458	if ( r_icache_tlb_miss_req.read() )
3459	{
3460	r_dcache_tlb_ins = true;
3461	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3462	r_dcache_fsm = DCACHE_TLB_MISS;
3463	break;
3464	}
3465
3466	if ( not r_dcache_xtn_req.read() )
3467	{
3468	r_dtlb.flush();
3469	r_mmu_ptpr = m_dreq.wdata;
3470	r_dcache_fsm = DCACHE_IDLE;
3471	m_drsp.valid = true;
3472	}
3473	break;
3474	}
3475	/////////////////////
3476	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3477	// The coherence request must be taken
3478	// as there is a risk of dead-lock
3479	{
3480	// coherence request (from CC_RECEIVE FSM)
3481	if ( r_cc_receive_dcache_req.read() )
3482	{
3483	r_dcache_fsm = DCACHE_CC_CHECK;
3484	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3485	}
3486
3487	if ( r_wbuf.empty() )
3488	{
3489	m_drsp.valid = true;
3490	r_dcache_fsm = DCACHE_IDLE;
3491	}
3492	break;
3493	}
3494	////////////////////////
3495	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3496	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3497	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3498	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3499	// and because it can exist a simultaneous ITLB miss
3500	{
3501	// coherence request (from CC_RECEIVE FSM)
3502	if ( r_cc_receive_dcache_req.read() )
3503	{
3504	r_dcache_fsm = DCACHE_CC_CHECK;
3505	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3506	break;
3507	}
3508
3509	// itlb miss request
3510	if ( r_icache_tlb_miss_req.read() )
3511	{
3512	r_dcache_tlb_ins = true;
3513	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3514	r_dcache_fsm = DCACHE_TLB_MISS;
3515	break;
3516	}
3517
3518	// test if XTN request to icache completed
3519	if ( not r_dcache_xtn_req.read() )
3520	{
3521	r_dcache_fsm = DCACHE_IDLE;
3522	m_drsp.valid = true;
3523	}
3524	break;
3525	}
3526	/////////////////////////
3527	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3528	// r_dcache_flush_count as a slot counter,
3529	// looping in this state until all slots have been visited.
3530	// It can require two cycles per slot:
3531	// We test here the slot state, and make the actual inval
3532	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3533	// A cleanup request is generated for each valid line.
3534	// returns to IDLE and flush TLBs when last slot
3535	{
3536	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3537	{
3538	int state;
3539	uint32_t tag;
3540	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3541	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3542
3543	#ifdef INSTRUMENTATION
3544	m_cpt_dcache_dir_read++;
3545	#endif
3546	r_dcache.read_dir( way,
3547	set,
3548	&tag,
3549	&state );
3550
3551	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3552	{
3553	// request cleanup
3554	r_dcache_cc_send_req = true;
3555	r_dcache_cc_send_nline = tag * m_dcache_sets;
3556	r_dcache_cc_send_way = way;
3557	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3558
3559	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3560	r_dcache_miss_way = way;
3561	r_dcache_miss_set = set;
3562	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3563	}
3564	else if ( r_dcache_flush_count.read() ==
3565	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3566	{
3567	r_dtlb.reset();
3568	r_itlb.reset();
3569	r_dcache_fsm = DCACHE_IDLE;
3570	m_drsp.valid = true;
3571	}
3572
3573	// saturation counter
3574	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3575	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3576	}
3577	break;
3578	}
3579	////////////////////////////
3580	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3581	// and reset directory extension.
3582	// returns to IDLE and flush TLBs when last slot
3583	{
3584	size_t way = r_dcache_miss_way.read();
3585	size_t set = r_dcache_miss_set.read();
3586
3587	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3588	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3589
3590	#ifdef INSTRUMENTATION
3591	m_cpt_dcache_dir_write++;
3592	#endif
3593	r_dcache.write_dir( 0,
3594	way,
3595	set,
3596	CACHE_SLOT_STATE_ZOMBI );
3597
3598	if ( r_dcache_flush_count.read() ==
3599	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3600	{
3601	r_dtlb.reset();
3602	r_itlb.reset();
3603	r_dcache_fsm = DCACHE_IDLE;
3604	m_drsp.valid = true;
3605	}
3606	else
3607	{
3608	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3609	}
3610	break;
3611	}
3612	/////////////////////////
3613	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3614	{
3615	r_dtlb.inval(r_dcache_save_wdata.read());
3616	r_dcache_fsm = DCACHE_IDLE;
3617	m_drsp.valid = true;
3618	break;
3619	}
3620	////////////////////////////
3621	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3622	// requires 3 cycles: access tlb, read cache, inval cache
3623	// we compute the physical address in this state
3624	{
3625	paddr_t paddr;
3626	bool hit;
3627
3628	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3629	{
3630
3631	#ifdef INSTRUMENTATION
3632	m_cpt_dtlb_read++;
3633	#endif
3634	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3635	&paddr );
3636	}
3637	else // dtlb not activated
3638	{
3639	paddr = (paddr_t)r_dcache_save_wdata.read();
3640	hit = true;
3641	}
3642
3643	if ( hit ) // tlb hit
3644	{
3645	r_dcache_save_paddr = paddr;
3646	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3647	}
3648	else // tlb miss
3649	{
3650
3651	#ifdef INSTRUMENTATION
3652	m_cpt_dtlb_miss++;
3653	#endif
3654	r_dcache_tlb_ins = false; // dtlb
3655	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3656	r_dcache_fsm = DCACHE_TLB_MISS;
3657	}
3658
3659	#if DEBUG_DCACHE
3660	if ( m_debug_dcache_fsm )
3661	{
3662	std::cout << " <PROC " << name()
3663	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3664	<< " / VADDR = " << r_dcache_save_wdata.read()
3665	<< " / PADDR = " << paddr << std::endl;
3666	}
3667	#endif
3668
3669	break;
3670	}
3671	////////////////////////////
3672	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3673	// requires 2 cycles: read cache / inval cache
3674	// In this state we read dcache.
3675	{
3676	size_t way;
3677	size_t set;
3678	size_t word;
3679	int state;
3680
3681	#ifdef INSTRUMENTATION
3682	m_cpt_dcache_dir_read++;
3683	#endif
3684	r_dcache.read_dir( r_dcache_save_paddr.read(),
3685	&state,
3686	&way,
3687	&set,
3688	&word );
3689
3690	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3691	{
3692	r_dcache_xtn_way = way;
3693	r_dcache_xtn_set = set;
3694	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3695	}
3696	else // miss : nothing to do
3697	{
3698	r_dcache_fsm = DCACHE_IDLE;
3699	m_drsp.valid = true;
3700	}
3701
3702	#if DEBUG_DCACHE
3703	if ( m_debug_dcache_fsm )
3704	{
3705	std::cout << " <PROC " << name()
3706	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3707	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3708	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3709	<< " / SET = " << set
3710	<< " / WAY = " << way << std::endl;
3711	}
3712	#endif
3713	break;
3714	}
3715	////////////////////////////
3716	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3717	// Blocked if previous cleanup not completed
3718	// Test if itlb or dtlb inval is required
3719	{
3720	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3721	{
3722	size_t way = r_dcache_xtn_way.read();
3723	size_t set = r_dcache_xtn_set.read();
3724	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3725
3726	#ifdef INSTRUMENTATION
3727	m_cpt_dcache_dir_write++;
3728	#endif
3729	r_dcache.write_dir( 0,
3730	way,
3731	set,
3732	CACHE_SLOT_STATE_EMPTY );
3733
3734	// request cleanup
3735	r_dcache_cc_send_req = true;
3736	r_dcache_cc_send_nline = nline;
3737	r_dcache_cc_send_way = way;
3738	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3739
3740	// possible itlb & dtlb invalidate
3741	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3742	{
3743	r_dcache_tlb_inval_line = nline;
3744	r_dcache_tlb_inval_set = 0;
3745	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3746	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3747	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3748	}
3749	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3750	{
3751	r_itlb.reset();
3752	r_dtlb.reset();
3753	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3754	r_dcache_fsm = DCACHE_IDLE;
3755	m_drsp.valid = true;
3756	}
3757	else
3758	{
3759	r_dcache_fsm = DCACHE_IDLE;
3760	m_drsp.valid = true;
3761	}
3762
3763	#if DEBUG_DCACHE
3764	if ( m_debug_dcache_fsm )
3765	{
3766	std::cout << " <PROC " << name()
3767	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3768	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3769	}
3770	#endif
3771	}
3772	break;
3773	}
3774	//////////////////////////////
3775	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3776	{
3777	r_dcache_fsm = DCACHE_IDLE;
3778	m_drsp.valid = true;
3779	break;
3780	}
3781	////////////////////////
3782	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3783	// if previous cleanup has been sent.
3784	// Waiting in this state if no slot available
3785	// Set the r_dcache_cleanup_req flip-flop
3786	// and the r_dcache_miss_clack flip-flop
3787	// when a cleanup is required
3788	{
3789	if ( m_dreq.valid) m_cost_data_miss_frz++;
3790
3791	// coherence request (from CC_RECEIVE FSM)
3792	if ( r_cc_receive_dcache_req.read() )
3793	{
3794	r_dcache_fsm = DCACHE_CC_CHECK;
3795	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3796	break;
3797	}
3798
3799	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3800	{
3801	bool found;
3802	bool cleanup;
3803	size_t way;
3804	size_t set;
3805	paddr_t victim;
3806
3807	#ifdef INSTRUMENTATION
3808	m_cpt_dcache_dir_read++;
3809	#endif
3810	r_dcache.read_select( r_dcache_save_paddr.read(),
3811	&victim,
3812	&way,
3813	&set,
3814	&found,
3815	&cleanup );
3816	if ( found )
3817	{
3818	r_dcache_miss_way = way;
3819	r_dcache_miss_set = set;
3820
3821	if ( cleanup )
3822	{
3823	r_dcache_miss_clack = true;
3824	r_dcache_fsm = DCACHE_MISS_CLEAN;
3825	// request cleanup
3826	r_dcache_cc_send_req = true;
3827	r_dcache_cc_send_nline = victim;
3828	r_dcache_cc_send_way = way;
3829	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3830	}
3831	else
3832	{
3833	r_dcache_fsm = DCACHE_MISS_WAIT;
3834	}
3835
3836	#if DEBUG_DCACHE
3837	if ( m_debug_dcache_fsm )
3838	{
3839	std::cout << " <PROC " << name()
3840	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3841	<< " / WAY = " << way
3842	<< " / SET = " << set
3843	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3844	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3845	else std::cout << std::endl;
3846	}
3847	#endif
3848	} // end found
3849	}
3850	break;
3851	}
3852	///////////////////////
3853	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3854	// and possibly request itlb or dtlb invalidate
3855	{
3856	if ( m_dreq.valid) m_cost_data_miss_frz++;
3857
3858	// coherence request (from CC_RECEIVE FSM)
3859	if ( r_cc_receive_dcache_req.read() )
3860	{
3861	r_dcache_fsm = DCACHE_CC_CHECK;
3862	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3863	break;
3864	}
3865
3866	size_t way = r_dcache_miss_way.read();
3867	size_t set = r_dcache_miss_set.read();
3868	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3869
3870	#ifdef INSTRUMENTATION
3871	m_cpt_dcache_dir_read++;
3872	#endif
3873	r_dcache.write_dir( 0,
3874	way,
3875	set,
3876	CACHE_SLOT_STATE_ZOMBI );
3877	#if DEBUG_DCACHE
3878	if ( m_debug_dcache_fsm )
3879	{
3880	std::cout << " <PROC " << name()
3881	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3882	<< " / way = " << way
3883	<< " / set = " << set << std::endl;
3884	}
3885	#endif
3886	// if selective itlb & dtlb invalidate are required
3887	// the miss response is not handled before invalidate completed
3888	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3889	{
3890	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3891	r_dcache_tlb_inval_line = nline;
3892	r_dcache_tlb_inval_set = 0;
3893	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3894	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3895	}
3896	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3897	{
3898	r_itlb.reset();
3899	r_dtlb.reset();
3900	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3901	r_dcache_fsm = DCACHE_MISS_WAIT;
3902	}
3903	else
3904	{
3905	r_dcache_fsm = DCACHE_MISS_WAIT;
3906	}
3907	break;
3908	}
3909	//////////////////////
3910	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3911	// This state is in charge of error signaling
3912	// There is 5 types of error depending on the requester
3913	{
3914	if ( m_dreq.valid) m_cost_data_miss_frz++;
3915
3916	// coherence request (from CC_RECEIVE FSM)
3917	if ( r_cc_receive_dcache_req.read() )
3918	{
3919	r_dcache_fsm = DCACHE_CC_CHECK;
3920	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3921	break;
3922	}
3923
3924	if ( r_vci_rsp_data_error.read() ) // bus error
3925	{
3926	switch ( r_dcache_miss_type.read() )
3927	{
3928	case PROC_MISS:
3929	{
3930	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3931	r_mmu_dbvar = r_dcache_save_vaddr.read();
3932	m_drsp.valid = true;
3933	m_drsp.error = true;
3934	r_dcache_fsm = DCACHE_IDLE;
3935	break;
3936	}
3937	case PTE1_MISS:
3938	{
3939	if ( r_dcache_tlb_ins.read() )
3940	{
3941	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3942	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3943	r_icache_tlb_miss_req = false;
3944	r_icache_tlb_rsp_error = true;
3945	}
3946	else
3947	{
3948	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3949	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3950	m_drsp.valid = true;
3951	m_drsp.error = true;
3952	}
3953	r_dcache_fsm = DCACHE_IDLE;
3954	break;
3955	}
3956	case PTE2_MISS:
3957	{
3958	if ( r_dcache_tlb_ins.read() )
3959	{
3960	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3961	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3962	r_icache_tlb_miss_req = false;
3963	r_icache_tlb_rsp_error = true;
3964	}
3965	else
3966	{
3967	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3968	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3969	m_drsp.valid = true;
3970	m_drsp.error = true;
3971	}
3972	r_dcache_fsm = DCACHE_IDLE;
3973	break;
3974	}
3975	} // end switch type
3976	r_vci_rsp_data_error = false;
3977	}
3978	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3979	{
3980	r_dcache_miss_word = 0;
3981	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3982	}
3983	break;
3984	}
3985	//////////////////////////
3986	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3987	{
3988	if ( m_dreq.valid) m_cost_data_miss_frz++;
3989
3990	// coherence request (from CC_RECEIVE FSM)
3991	if ( r_cc_receive_dcache_req.read() )
3992	{
3993	r_dcache_fsm = DCACHE_CC_CHECK;
3994	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3995	break;
3996	}
3997
3998	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3999	{
4000	#ifdef INSTRUMENTATION
4001	m_cpt_dcache_data_write++;
4002	#endif
4003	r_dcache.write( r_dcache_miss_way.read(),
4004	r_dcache_miss_set.read(),
4005	r_dcache_miss_word.read(),
4006	r_vci_rsp_fifo_dcache.read() );
4007	#if DEBUG_DCACHE
4008	if ( m_debug_dcache_fsm )
4009	{
4010	std::cout << " <PROC " << name()
4011	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4012	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4013	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4014	<< " / SET = " << r_dcache_miss_set.read()
4015	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4016	}
4017	#endif
4018	vci_rsp_fifo_dcache_get = true;
4019	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4020
4021	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4022	{
4023	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4024	}
4025	}
4026	break;
4027	}
4028	//////////////////////////
4029	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4030	// and the cleanup ack has not been received,
4031	// as indicated by the r_dcache_miss clack.
4032	// - If no matching coherence request (r_dcache_inval_miss)
4033	// switch directory slot to VALID state.
4034	// - If matching coherence request, switch directory slot
4035	// to ZOMBI state, and send a cleanup request.
4036	{
4037	if ( m_dreq.valid) m_cost_data_miss_frz++;
4038
4039	// coherence request (from CC_RECEIVE FSM)
4040	if ( r_cc_receive_dcache_req.read() )
4041	{
4042	r_dcache_fsm = DCACHE_CC_CHECK;
4043	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4044	break;
4045	}
4046
4047	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4048	{
4049	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4050	{
4051	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4052	{
4053	r_dcache_miss_inval = false;
4054	// request cleanup
4055	r_dcache_cc_send_req = true;
4056	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4057	r_dcache_cc_send_way = r_dcache_miss_way.read();
4058	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4059
4060	#ifdef INSTRUMENTATION
4061	m_cpt_dcache_dir_write++;
4062	#endif
4063	r_dcache.write_dir( r_dcache_save_paddr.read(),
4064	r_dcache_miss_way.read(),
4065	r_dcache_miss_set.read(),
4066	CACHE_SLOT_STATE_ZOMBI );
4067	#if DEBUG_DCACHE
4068	if ( m_debug_dcache_fsm )
4069	{
4070	std::cout << " <PROC " << name()
4071	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4072	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4073	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4074	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4075	}
4076	#endif
4077	}
4078	}
4079	else // switch slot to VALID state
4080	{
4081
4082	#ifdef INSTRUMENTATION
4083	m_cpt_dcache_dir_write++;
4084	#endif
4085	r_dcache.write_dir( r_dcache_save_paddr.read(),
4086	r_dcache_miss_way.read(),
4087	r_dcache_miss_set.read(),
4088	CACHE_SLOT_STATE_VALID );
4089
4090	#if DEBUG_DCACHE
4091	if ( m_debug_dcache_fsm )
4092	{
4093	std::cout << " <PROC " << name()
4094	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4095	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4096	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4097	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4098
4099	r_dcache.printTrace();
4100
4101
4102	}
4103	#endif
4104	// reset directory extension
4105	size_t way = r_dcache_miss_way.read();
4106	size_t set = r_dcache_miss_set.read();
4107	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4108	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4109	}
4110
4111	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4112	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4113	else r_dcache_fsm = DCACHE_IDLE;
4114	}
4115	break;
4116	}
4117	/////////////////////
4118	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4119	{
4120	// coherence request (from CC_RECEIVE FSM)
4121	if ( r_cc_receive_dcache_req.read() )
4122	{
4123	r_dcache_fsm = DCACHE_CC_CHECK;
4124	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4125	break;
4126	}
4127
4128	if ( r_vci_rsp_data_error.read() ) // bus error
4129	{
4130	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4131	r_mmu_dbvar = m_dreq.addr;
4132	r_vci_rsp_data_error = false;
4133	m_drsp.error = true;
4134	m_drsp.valid = true;
4135	r_dcache_fsm = DCACHE_IDLE;
4136	break;
4137	}
4138	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4139	{
4140	// consume data
4141	vci_rsp_fifo_dcache_get = true;
4142	r_dcache_fsm = DCACHE_IDLE;
4143
4144	// acknowledge the processor request if it has not been modified
4145	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4146	{
4147	m_drsp.valid = true;
4148	m_drsp.error = false;
4149	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4150	}
4151	}
4152	break;
4153	}
4154	/////////////////////
4155	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4156	{
4157	// coherence request (from CC_RECEIVE FSM)
4158	if ( r_cc_receive_dcache_req.read() )
4159	{
4160	r_dcache_fsm = DCACHE_CC_CHECK;
4161	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4162	break;
4163	}
4164
4165	if ( r_vci_rsp_data_error.read() ) // bus error
4166	{
4167	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4168	r_mmu_dbvar = m_dreq.addr;
4169	r_vci_rsp_data_error = false;
4170	m_drsp.error = true;
4171	m_drsp.valid = true;
4172	r_dcache_fsm = DCACHE_IDLE;
4173	break;
4174	}
4175	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4176	{
4177	// consume data
4178	vci_rsp_fifo_dcache_get = true;
4179
4180	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4181	{
4182	// set key value in llsc reservation buffer
4183	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4184	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4185	}
4186	else // last flit
4187	{
4188	// acknowledge the processor request if it has not been modified
4189	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4190	{
4191	m_drsp.valid = true;
4192	m_drsp.error = false;
4193	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4194	}
4195	r_dcache_fsm = DCACHE_IDLE;
4196	}
4197	}
4198	break;
4199	}
4200	////////////////////
4201	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4202	{
4203	// coherence request (from CC_RECEIVE FSM)
4204	if ( r_cc_receive_dcache_req.read() )
4205	{
4206	r_dcache_fsm = DCACHE_CC_CHECK;
4207	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4208	break;
4209	}
4210
4211	if ( r_vci_rsp_data_error.read() ) // bus error
4212	{
4213	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4214	r_mmu_dbvar = m_dreq.addr;
4215	r_vci_rsp_data_error = false;
4216	m_drsp.error = true;
4217	m_drsp.valid = true;
4218	r_dcache_fsm = DCACHE_IDLE;
4219	break;
4220	}
4221	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4222	{
4223	// consume response
4224	vci_rsp_fifo_dcache_get = true;
4225	m_drsp.valid = true;
4226	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4227	r_dcache_fsm = DCACHE_IDLE;
4228	}
4229	break;
4230	}
4231	//////////////////////////
4232	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4233	// before handling a processor WRITE or SC request
4234	// Input argument is r_dcache_dirty_paddr
4235	// In this first state, we get PTE value in dcache
4236	// and post a CAS request to CMD FSM
4237	{
4238	// get PTE in dcache
4239	uint32_t pte;
4240	size_t way;
4241	size_t set;
4242	size_t word; // unused
4243	int state;
4244
4245	#ifdef INSTRUMENTATION
4246	m_cpt_dcache_data_read++;
4247	m_cpt_dcache_dir_read++;
4248	#endif
4249	r_dcache.read( r_dcache_dirty_paddr.read(),
4250	&pte,
4251	&way,
4252	&set,
4253	&word,
4254	&state );
4255
4256	assert( (state == CACHE_SLOT_STATE_VALID) and
4257	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4258
4259	// request CAS transaction to CMD_FSM
4260	r_dcache_dirty_way = way;
4261	r_dcache_dirty_set = set;
4262
4263	// check llsc reservation buffer
4264	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4265	r_dcache_llsc_valid = false;
4266
4267	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4268	r_dcache_vci_cas_req = true;
4269	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4270	r_dcache_vci_cas_old = pte;
4271	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4272	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4273
4274	#if DEBUG_DCACHE
4275	if ( m_debug_dcache_fsm )
4276	{
4277	std::cout << " <PROC " << name()
4278	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4279	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4280	<< " / PTE_VALUE = " << pte << std::dec
4281	<< " / SET = " << set
4282	<< " / WAY = " << way << std::endl;
4283	}
4284	#endif
4285	break;
4286	}
4287	///////////////////////
4288	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4289	// and return to IDLE state when response is received.
4290	// we don't care if the CAS is a failure:
4291	// - if the CAS is a success, the coherence mechanism
4292	// updates the local copy.
4293	// - if the CAS is a failure, we just retry the write.
4294	{
4295	// coherence request (from CC_RECEIVE FSM)
4296	if ( r_cc_receive_dcache_req.read() )
4297	{
4298	r_dcache_fsm = DCACHE_CC_CHECK;
4299	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4300	break;
4301	}
4302
4303	if ( r_vci_rsp_data_error.read() ) // bus error
4304	{
4305	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4306	std::cout << "This should not happen in this state" << std::endl;
4307	exit(0);
4308	}
4309	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4310	{
4311	vci_rsp_fifo_dcache_get = true;
4312	r_dcache_fsm = DCACHE_IDLE;
4313
4314	#if DEBUG_DCACHE
4315	if ( m_debug_dcache_fsm )
4316	{
4317	std::cout << " <PROC " << name()
4318	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4319	}
4320	#endif
4321	}
4322	break;
4323	}
4324	/////////////////////
4325	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4326	// handling coherence requests for DCACHE.
4327	// If there is a matching pending miss on the modified cache
4328	// line this is signaled in the r_dcache_miss inval flip-flop.
4329	// If the updated (or invalidated) cache line has copies in TLBs
4330	// these TLB copies are invalidated.
4331	// The return state is defined in r_dcache_fsm_cc_save
4332	{
4333	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4334	paddr_t mask = ~((m_dcache_words<<2)-1);
4335
4336
4337	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4338	// We switch the directory slot to EMPTY state
4339	// and reset r_icache_miss_clack if the cleanup ack
4340	// is matching a pending miss.
4341	{
4342
4343	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4344
4345	#ifdef INSTRUMENTATION
4346	m_cpt_dcache_dir_write++;
4347	#endif
4348	r_dcache.write_dir( 0,
4349	r_cc_receive_dcache_way.read(),
4350	r_cc_receive_dcache_set.read(),
4351	CACHE_SLOT_STATE_EMPTY);
4352
4353	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4354	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4355	r_dcache_miss_clack = false;
4356
4357	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4358	r_cc_receive_dcache_req = false;
4359	#if DEBUG_DCACHE
4360	if ( m_debug_dcache_fsm )
4361	{
4362	std::cout << " <PROC " << name()
4363	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4364	<< " set = " << r_cc_receive_dcache_set.read()
4365	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4366	}
4367	#endif
4368	}
4369	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4370	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4371	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4372	{
4373	// signaling matching
4374	r_dcache_miss_inval = true;
4375
4376	// in case of update, go to CC_UPDT
4377	// JUST TO POP THE FIFO
4378	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4379	{
4380	r_dcache_fsm = DCACHE_CC_UPDT;
4381	r_dcache_cc_word = r_cc_receive_word_idx.read();
4382	// just pop the fifo , don't write in icache
4383	r_dcache_cc_need_write = false;
4384	}
4385	// the request is dealt with
4386	else
4387	{
4388	r_cc_receive_dcache_req = false;
4389	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4390	}
4391
4392	#if DEBUG_DCACHE
4393	if ( m_debug_dcache_fsm )
4394	{
4395	std::cout << " <PROC " << name()
4396	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4397	<< " PADDR = " << std::hex << paddr << std::endl;
4398	}
4399	#endif
4400
4401	}
4402	else // no match
4403	{
4404	int state;
4405	size_t way;
4406	size_t set;
4407	size_t word;
4408
4409	#ifdef INSTRUMENTATION
4410	m_cpt_dcache_dir_read++;
4411	#endif
4412	r_dcache.read_dir( paddr,
4413	&state,
4414	&way,
4415	&set,
4416	&word ); // unused
4417
4418	r_dcache_cc_way = way;
4419	r_dcache_cc_set = set;
4420
4421	if ( state == CACHE_SLOT_STATE_VALID) // hit
4422	{
4423	// need to update the cache state
4424	r_dcache_cc_need_write = true;
4425	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4426	{
4427	r_dcache_fsm = DCACHE_CC_UPDT;
4428	r_dcache_cc_word = r_cc_receive_word_idx.read();
4429	}
4430	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4431	{
4432	r_dcache_fsm = DCACHE_CC_INVAL;
4433	}
4434	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4435	{
4436	r_dcache_fsm = DCACHE_CC_BROADCAST;
4437	}
4438	}
4439	else // miss
4440	{
4441	// multicast acknowledgement required in case of update
4442	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4443	{
4444	r_dcache_fsm = DCACHE_CC_UPDT;
4445	r_dcache_cc_word = r_cc_receive_word_idx.read();
4446	// just pop the fifo , don't write in icache
4447	r_dcache_cc_need_write = false;
4448	}
4449	else // No response needed
4450	{
4451	r_cc_receive_dcache_req = false;
4452	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4453	}
4454	}
4455
4456	#if DEBUG_DCACHE
4457	if ( m_debug_dcache_fsm )
4458	{
4459	std::cout << " <PROC " << name()
4460	<< " DCACHE_CC_CHECK> Coherence request received:"
4461	<< " PADDR = " << std::hex << paddr
4462	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4463	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4464	}
4465	#endif
4466	}
4467	break;
4468	}
4469	/////////////////////
4470	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4471	// after possible invalidation of copies in TLBs
4472	{
4473	size_t way = r_dcache_cc_way.read();
4474	size_t set = r_dcache_cc_set.read();
4475
4476	if (r_dcache_cc_need_write.read())
4477	{
4478	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4479	{
4480	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4481	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read() / (m_dcache_words<<2);
4482	r_dcache_tlb_inval_set = 0;
4483	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4484	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4485	}
4486	else
4487	{
4488	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4489	{
4490	r_itlb.reset();
4491	r_dtlb.reset();
4492	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4493
4494	#if DEBUG_DCACHE
4495	if ( m_debug_dcache_fsm )
4496	{
4497	std::cout << " <PROC " << name()
4498	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4499	}
4500	#endif
4501	}
4502
4503	r_dcache.write_dir( 0,
4504	way,
4505	set,
4506	CACHE_SLOT_STATE_EMPTY );
4507
4508	r_dcache_cc_need_write = false;
4509
4510	#if DEBUG_DCACHE
4511	if ( m_debug_dcache_fsm )
4512	{
4513	std::cout << " <PROC " << name()
4514	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4515	<< " / WAY = " << way
4516	<< " / SET = " << set << std::endl;
4517	}
4518	#endif
4519	}
4520	}
4521	// multicast acknowledgement
4522	// send a request to cc_send_fsm
4523	if(not r_dcache_cc_send_req.read()) // cc_send is available
4524	{
4525	// coherence request completed
4526	r_cc_receive_dcache_req = false;
4527	// request multicast acknowledgement
4528	r_dcache_cc_send_req = true;
4529	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4530	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4531
4532	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4533	}
4534	//else wait for previous cc_send request to be sent
4535	break;
4536	}
4537	///////////////////
4538	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4539	// after possible invalidation of copies in TLBs
4540	{
4541	size_t word = r_dcache_cc_word.read();
4542	size_t way = r_dcache_cc_way.read();
4543	size_t set = r_dcache_cc_set.read();
4544
4545	if (r_cc_receive_updt_fifo_be.rok())
4546	{
4547	if (r_dcache_cc_need_write.read())
4548	{
4549	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4550	{
4551	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4552	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read() / (m_dcache_words<<2);
4553	r_dcache_tlb_inval_set = 0;
4554	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4555	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4556	break;
4557	}
4558	else
4559	{
4560	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4561	{
4562	r_itlb.reset();
4563	r_dtlb.reset();
4564	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4565
4566	#if DEBUG_DCACHE
4567	if ( m_debug_dcache_fsm )
4568	{
4569	std::cout << " <PROC " << name()
4570	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4571	}
4572	#endif
4573	}
4574
4575	#ifdef INSTRUMENTATION
4576	m_cpt_dcache_data_write++;
4577	#endif
4578	r_dcache.write( way,
4579	set,
4580	word,
4581	r_cc_receive_updt_fifo_data.read(),
4582	r_cc_receive_updt_fifo_be.read() );
4583
4584	r_dcache_cc_word = word + 1;
4585
4586	#if DEBUG_DCACHE
4587	if ( m_debug_dcache_fsm )
4588	{
4589	std::cout << " <PROC " << name()
4590	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4591	<< " / WAY = " << way
4592	<< " / SET = " << set
4593	<< " / WORD = " << word
4594	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4595	}
4596	#endif
4597	}
4598	}
4599
4600	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4601	{
4602	// no need to write in the cache anymore
4603	r_dcache_cc_need_write = false;
4604
4605	// wait to send a request to cc_send_fsm
4606	if(not r_icache_cc_send_req.read())
4607	// cc_send is available
4608	{
4609	//consume last fifo flit if eop and request to cc_send possible
4610	cc_receive_updt_fifo_get = true;
4611
4612	// coherence request completed
4613	r_cc_receive_dcache_req = false;
4614
4615	// request multicast acknowledgement
4616	r_dcache_cc_send_req = true;
4617	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4618	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4619
4620	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4621	}
4622	}
4623	else
4624	{
4625	//consume fifo if not eop
4626	cc_receive_updt_fifo_get = true;
4627	}
4628
4629	}
4630	break;
4631	}
4632	/////////////////////////
4633	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4634	// and request a cleanup, after possible
4635	// invalidation of copies in TLBs
4636	{
4637	size_t way = r_dcache_cc_way.read();
4638	size_t set = r_dcache_cc_set.read();
4639	paddr_t nline = r_cc_receive_dcache_nline.read() / (m_dcache_words<<2);
4640
4641	if (r_dcache_cc_need_write.read())
4642	{
4643	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4644	{
4645	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4646	r_dcache_tlb_inval_line = nline;
4647	r_dcache_tlb_inval_set = 0;
4648	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4649	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4650	}
4651	else
4652	{
4653	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4654	{
4655	r_itlb.reset();
4656	r_dtlb.reset();
4657	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4658
4659	#if DEBUG_DCACHE
4660	if ( m_debug_dcache_fsm )
4661	{
4662	std::cout << " <PROC " << name()
4663	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4664	}
4665	#endif
4666	}
4667
4668	#ifdef INSTRUMENTATION
4669	m_cpt_dcache_dir_write++;
4670	#endif
4671	r_dcache.write_dir( 0,
4672	way,
4673	set,
4674	CACHE_SLOT_STATE_ZOMBI );
4675
4676	r_dcache_cc_need_write = false;
4677	#if DEBUG_DCACHE
4678	if ( m_debug_dcache_fsm )
4679	{
4680	std::cout << " <PROC " << name()
4681	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4682	<< " SET = " << set
4683	<< " / WAY = " << way << std::endl;
4684	}
4685	#endif
4686	}
4687	}
4688	// cleanup
4689	// send a request to cc_send_fsm
4690	if(not r_dcache_cc_send_req.read()) // cc_send is available
4691	{
4692	// coherence request completed
4693	r_cc_receive_dcache_req = false;
4694	// request cleanup
4695	r_dcache_cc_send_req = true;
4696	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4697	r_dcache_cc_send_way = r_dcache_cc_way.read();
4698	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4699
4700	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4701	}
4702	//else wait for previous cc_send request to be sent
4703	break;
4704	}
4705	///////////////////////////
4706	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4707	// It makes assumption: m_itlb_sets == m_dtlb_sets
4708	// All ways are handled in parallel.
4709	// We enter this state when a DCACHE line is modified,
4710	// and there is a copy in itlb or dtlb.
4711	// It can be caused by:
4712	// - a coherence inval or updt transaction,
4713	// - a line inval caused by a cache miss
4714	// - a processor XTN inval request,
4715	// - a WRITE hit,
4716	// - a Dirty bit update
4717	// Input arguments are:
4718	// - r_dcache_tlb_inval_line
4719	// - r_dcache_tlb_inval_set
4720	// - r_dcache_fsm_scan_save
4721	{
4722	paddr_t line = r_dcache_tlb_inval_line.read();
4723	size_t set = r_dcache_tlb_inval_set.read();
4724	size_t way;
4725	bool ok;
4726
4727	for ( way = 0 ; way < m_itlb_ways ; way++ )
4728	{
4729	ok = r_itlb.inval( line, way, set );
4730
4731	#if DEBUG_DCACHE
4732	if ( m_debug_dcache_fsm and ok )
4733	{
4734	std::cout << " <PROC " << name()
4735	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4736	<< " line = " << line << std::dec
4737	<< " / set = " << set
4738	<< " / way = " << way << std::endl;
4739	}
4740	#endif
4741	}
4742
4743	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4744	{
4745	ok = r_dtlb.inval( line, way, set );
4746
4747	#if DEBUG_DCACHE
4748	if ( m_debug_dcache_fsm and ok )
4749	{
4750	std::cout << " <PROC " << name()
4751	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4752	<< " line = " << line << std::dec
4753	<< " / set = " << set
4754	<< " / way = " << way << std::endl;
4755	}
4756	#endif
4757	}
4758
4759	// return to the calling state when TLB inval completed
4760	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4761	{
4762	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4763	}
4764	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4765	break;
4766	}
4767	} // end switch r_dcache_fsm
4768
4769	///////////////// wbuf update ///////////////////////////////////////////////////////
4770	r_wbuf.update();
4771
4772	///////////////// llsc update ///////////////////////////////////////////////////////
4773	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4774	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4775
4776	//////////////// test processor frozen //////////////////////////////////////////////
4777	// The simulation exit if the number of consecutive frozen cycles
4778	// is larger than the m_max_frozen_cycles (constructor parameter)
4779	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4780	{
4781	m_cpt_frz_cycles++; // used for instrumentation
4782	m_cpt_stop_simulation++; // used for debug
4783	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4784	{
4785	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4786	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4787	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4788	<< std::endl;
4789	r_iss.dump();
4790	exit(1);
4791	}
4792	}
4793	else
4794	{
4795	m_cpt_stop_simulation = 0;
4796	}
4797
4798	/////////// execute one iss cycle /////////////////////////////////
4799	{
4800	uint32_t it = 0;
4801	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4802	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4803	}
4804
4805	////////////////////////////////////////////////////////////////////////////
4806	// The VCI_CMD FSM controls the following ressources:
4807	// - r_vci_cmd_fsm
4808	// - r_vci_cmd_min
4809	// - r_vci_cmd_max
4810	// - r_vci_cmd_cpt
4811	// - r_vci_cmd_imiss_prio
4812	// - wbuf (reset)
4813	// - r_icache_miss_req (reset)
4814	// - r_icache_unc_req (reset)
4815	// - r_dcache_vci_miss_req (reset)
4816	// - r_dcache_vci_unc_req (reset)
4817	// - r_dcache_vci_ll_req (reset)
4818	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4819	// - r_dcache_vci_cas_req (reset)
4820	//
4821	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4822	// There are 8 request types, with the following priorities :
4823	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4824	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4825	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4826	// 4 - Instruction Uncachable : r_icache_unc_req
4827	// 5 - Data Write : r_wbuf.rok()
4828	// 6 - Data Linked Load : r_dcache_vci_ll_req
4829	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4830	// 8 - Compare And Swap : r_dcache_vci_cas_req
4831	//
4832	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4833	// and the VCI_RSP_FSM are fully desynchronized.
4834	//
4835	// VCI formats:
4836	// According to the VCI advanced specification, all read requests packets
4837	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4838	// are one word packets.
4839	// For write burst packets, all words are in the same cache line,
4840	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4841	// The sc command packet implements actually a compare-and-swap mechanism
4842	// and the packet contains two flits.
4843	////////////////////////////////////////////////////////////////////////////////////
4844
4845	switch ( r_vci_cmd_fsm.read() )
4846	{
4847	//////////////
4848	case CMD_IDLE:
4849	{
4850	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4851	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4852	// to check a possible pending write on the same cache line.
4853	// As there is only one possible access per cycle to write buffer, we implement
4854	// a round-robin priority between DCACHE and ICACHE for this access,
4855	// using the r_vci_cmd_imiss_prio flip-flop.
4856
4857	size_t wbuf_min;
4858	size_t wbuf_max;
4859
4860	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4861	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4862
4863	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4864	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4865
4866	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4867	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4868
4869	bool icache_miss_req = r_icache_miss_req.read() and
4870	( not (r_dcache_vci_miss_req.read() or
4871	r_dcache_vci_ll_req.read() or
4872	r_dcache_vci_unc_req.read())
4873	or r_vci_cmd_imiss_prio.read() ) ;
4874
4875	// 1 - Data Read Miss
4876	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4877	{
4878	r_vci_cmd_fsm = CMD_DATA_MISS;
4879	r_dcache_vci_miss_req = false;
4880	r_vci_cmd_imiss_prio = true;
4881	// m_cpt_dmiss_transaction++;
4882	}
4883	// 2 - Data Read Uncachable
4884	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4885	{
4886	r_vci_cmd_fsm = CMD_DATA_UNC;
4887	r_dcache_vci_unc_req = false;
4888	// m_cpt_dunc_transaction++;
4889	}
4890	// 3 - Data Linked Load
4891	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4892	{
4893	r_dcache_vci_ll_req = false;
4894	r_vci_cmd_fsm = CMD_DATA_LL;
4895	// m_cpt_ll_transaction++;
4896	}
4897	// 4 - Instruction Miss
4898	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4899	{
4900	r_vci_cmd_fsm = CMD_INS_MISS;
4901	r_icache_miss_req = false;
4902	r_vci_cmd_imiss_prio = false;
4903	// m_cpt_imiss_transaction++;
4904	}
4905	// 5 - Instruction Uncachable
4906	else if ( r_icache_unc_req.read() )
4907	{
4908	r_vci_cmd_fsm = CMD_INS_UNC;
4909	r_icache_unc_req = false;
4910	// m_cpt_iunc_transaction++;
4911	}
4912	// 6 - Data Write
4913	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4914	{
4915	r_vci_cmd_fsm = CMD_DATA_WRITE;
4916	r_vci_cmd_cpt = wbuf_min;
4917	r_vci_cmd_min = wbuf_min;
4918	r_vci_cmd_max = wbuf_max;
4919	// m_cpt_write_transaction++;
4920	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4921	}
4922	// 7 - Data Store Conditionnal
4923	else if ( r_dcache_vci_sc_req.read() )
4924	{
4925	r_dcache_vci_sc_req = false;
4926	r_vci_cmd_cpt = 0;
4927	r_vci_cmd_fsm = CMD_DATA_SC;
4928	// m_cpt_sc_transaction++;
4929	}
4930	// 8 - Compare And Swap
4931	else if ( r_dcache_vci_cas_req.read() )
4932	{
4933	r_vci_cmd_fsm = CMD_DATA_CAS;
4934	r_dcache_vci_cas_req = false;
4935	r_vci_cmd_cpt = 0;
4936	// m_cpt_cas_transaction++;
4937	}
4938	break;
4939	}
4940	////////////////////
4941	case CMD_DATA_WRITE:
4942	{
4943	if ( p_vci_ini_d.cmdack.read() )
4944	{
4945	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4946	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4947	{
4948	r_vci_cmd_fsm = CMD_IDLE ;
4949	r_wbuf.sent() ;
4950	}
4951	}
4952	break;
4953	}
4954	/////////////////
4955	case CMD_DATA_SC:
4956	case CMD_DATA_CAS:
4957	{
4958	// The CAS and SC VCI commands contain two flits
4959	if ( p_vci_ini_d.cmdack.read() )
4960	{
4961	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4962	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4963	}
4964	break;
4965	}
4966	//////////////////
4967	case CMD_INS_MISS:
4968	case CMD_INS_UNC:
4969	case CMD_DATA_MISS:
4970	case CMD_DATA_UNC:
4971	case CMD_DATA_LL:
4972	{
4973	// all read VCI commands contain one single flit
4974	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4975	break;
4976	}
4977
4978	} // end switch r_vci_cmd_fsm
4979
4980	//////////////////////////////////////////////////////////////////////////
4981	// The VCI_RSP FSM controls the following ressources:
4982	// - r_vci_rsp_fsm:
4983	// - r_vci_rsp_fifo_icache (push)
4984	// - r_vci_rsp_fifo_dcache (push)
4985	// - r_vci_rsp_data_error (set)
4986	// - r_vci_rsp_ins_error (set)
4987	// - r_vci_rsp_cpt
4988	// - r_dcache_vci_sc_req (reset when SC response recieved)
4989	//
4990	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4991	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4992	// to identify the transactions.
4993	//
4994	// VCI vormat:
4995	// This component checks the response packet length and accepts only
4996	// single word packets for write response packets.
4997	//
4998	// Error handling:
4999	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5000	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5001	// flip_flop and the error is signaled by the DCACHE FSM.
5002	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5003	// flip_flop and the error is signaled by the ICACHE FSM.
5004	// In case of Cleanup Error, the simulation stops with an error message...
5005	//////////////////////////////////////////////////////////////////////////
5006
5007	switch ( r_vci_rsp_fsm.read() )
5008	{
5009	//////////////
5010	case RSP_IDLE:
5011	{
5012	if ( p_vci_ini_d.rspval.read() )
5013	{
5014	r_vci_rsp_cpt = 0;
5015
5016	if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5017	{
5018	r_vci_rsp_fsm = RSP_DATA_UNC;
5019	}
5020	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5021	{
5022	r_vci_rsp_fsm = RSP_DATA_MISS;
5023	}
5024	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5025	{
5026	r_vci_rsp_fsm = RSP_INS_UNC;
5027	}
5028	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5029	{
5030	r_vci_rsp_fsm = RSP_INS_MISS;
5031	}
5032	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE )
5033	{
5034	r_vci_rsp_fsm = RSP_DATA_WRITE;
5035	}
5036	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS )
5037	{
5038	r_vci_rsp_fsm = RSP_DATA_UNC;
5039	}
5040	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL )
5041	{
5042	r_vci_rsp_fsm = RSP_DATA_LL;
5043	}
5044	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC )
5045	{
5046	r_vci_rsp_fsm = RSP_DATA_UNC;
5047	}
5048	else
5049	{
5050	assert(false and "Unexpected VCI response");
5051	}
5052	}
5053	break;
5054	}
5055	//////////////////
5056	case RSP_INS_MISS:
5057	{
5058	if ( p_vci_ini_d.rspval.read() )
5059	{
5060	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5061	{
5062	r_vci_rsp_ins_error = true;
5063	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5064	}
5065	else // no error reported
5066	{
5067	if ( r_vci_rsp_fifo_icache.wok() )
5068	{
5069	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5070	"The VCI response packet for instruction miss is too long" );
5071
5072	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5073	vci_rsp_fifo_icache_put = true,
5074	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5075	if ( p_vci_ini_d.reop.read() )
5076	{
5077	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5078	"The VCI response packet for instruction miss is too short");
5079
5080	r_vci_rsp_fsm = RSP_IDLE;
5081	}
5082	}
5083	}
5084	}
5085	break;
5086	}
5087	/////////////////
5088	case RSP_INS_UNC:
5089	{
5090	if (p_vci_ini_d.rspval.read() )
5091	{
5092	assert( p_vci_ini_d.reop.read() and
5093	"illegal VCI response packet for uncachable instruction");
5094
5095	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5096	{
5097	r_vci_rsp_ins_error = true;
5098	r_vci_rsp_fsm = RSP_IDLE;
5099	}
5100	else // no error reported
5101	{
5102	if ( r_vci_rsp_fifo_icache.wok())
5103	{
5104	vci_rsp_fifo_icache_put = true;
5105	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5106	r_vci_rsp_fsm = RSP_IDLE;
5107	}
5108	}
5109	}
5110	break;
5111	}
5112	///////////////////
5113	case RSP_DATA_MISS:
5114	{
5115	if ( p_vci_ini_d.rspval.read() )
5116	{
5117	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5118	{
5119	r_vci_rsp_data_error = true;
5120	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5121	}
5122	else // no error reported
5123	{
5124	if ( r_vci_rsp_fifo_dcache.wok() )
5125	{
5126	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5127	"The VCI response packet for data miss is too long");
5128
5129	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5130	vci_rsp_fifo_dcache_put = true,
5131	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5132	if ( p_vci_ini_d.reop.read() )
5133	{
5134	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5135	"The VCI response packet for data miss is too short");
5136
5137	r_vci_rsp_fsm = RSP_IDLE;
5138	}
5139	}
5140	}
5141	}
5142	break;
5143	}
5144	//////////////////
5145	case RSP_DATA_UNC:
5146	{
5147	if (p_vci_ini_d.rspval.read() )
5148	{
5149	assert( p_vci_ini_d.reop.read() and
5150	"illegal VCI response packet for uncachable read data");
5151
5152	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5153	{
5154	r_vci_rsp_data_error = true;
5155	r_vci_rsp_fsm = RSP_IDLE;
5156	}
5157	else // no error reported
5158	{
5159	if ( r_vci_rsp_fifo_dcache.wok())
5160	{
5161	vci_rsp_fifo_dcache_put = true;
5162	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5163	r_vci_rsp_fsm = RSP_IDLE;
5164	}
5165	}
5166	}
5167	break;
5168	}
5169	////////////////////
5170	case RSP_DATA_LL:
5171	{
5172	if ( p_vci_ini_d.rspval.read() )
5173	{
5174	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5175	{
5176	r_vci_rsp_data_error = true;
5177	r_vci_rsp_fsm = RSP_IDLE;
5178	}
5179	if (r_vci_rsp_cpt.read() == 0) //first flit
5180	{
5181	if(r_vci_rsp_fifo_dcache.wok())
5182	{
5183	assert(!p_vci_ini_d.reop.read() &&
5184	"illegal VCI response packet for LL");
5185	vci_rsp_fifo_dcache_put = true;
5186	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5187	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5188	}
5189	break;
5190	}
5191	else // last flit
5192	{
5193	if(r_vci_rsp_fifo_dcache.wok())
5194	{
5195	assert(p_vci_ini_d.reop.read() &&
5196	"illegal VCI response packet for LL");
5197	vci_rsp_fifo_dcache_put = true;
5198	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5199	r_vci_rsp_fsm = RSP_IDLE;
5200	}
5201	break;
5202	}
5203	}
5204	break;
5205	}
5206	////////////////////
5207	case RSP_DATA_WRITE:
5208	{
5209	if (p_vci_ini_d.rspval.read())
5210	{
5211	assert( p_vci_ini_d.reop.read() and
5212	"a VCI response packet must contain one flit for a write transaction");
5213
5214	r_vci_rsp_fsm = RSP_IDLE;
5215	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read();
5216	bool cacheable = r_wbuf.completed(wbuf_index);
5217	if ( not cacheable ) r_dcache_pending_unc_write = false;
5218	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5219	}
5220	break;
5221	}
5222	} // end switch r_vci_rsp_fsm
5223
5224	/////////////////////////////////////////////////////////////////////////////////////
5225	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5226	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5227	// and ICACHE FSM) that are served with a round-robin priority.
5228	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5229	// soon as the request has been sent.
5230	/////////////////////////////////////////////////////////////////////////////////////
5231	switch ( r_cc_send_fsm.read() )
5232	{
5233	///////////////////////////
5234	case CC_SEND_IDLE:
5235	{
5236	///////////////////////////////////////////////////////
5237	// handling round robin between icache and dcache : //
5238	// we first check for the last client and listen for //
5239	// a request of the other, then update the client //
5240	///////////////////////////////////////////////////////
5241	// r_cc_send_last_client : 0 dcache 1 icache
5242	bool update_last_client;
5243	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5244	{
5245	if(r_icache_cc_send_req.read()) // request from icache
5246	update_last_client = 1; // update last client to icache
5247	}
5248	else // last client was icache
5249	{
5250	if(r_dcache_cc_send_req.read()) // request from dcache
5251	update_last_client = 0; // update last client to dcache
5252	}
5253	r_cc_send_last_client = update_last_client;
5254
5255	// if there is an actual request
5256	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5257	{
5258	// test if the new client is dcache and has a cleanup request
5259	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5260	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5261	// test if the new client is dcache and has a multi acknowledgement request
5262	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5263	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5264	// test if the new client is icache and has a cleanup request
5265	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5266	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5267	// test if the new client is icache and has a multi acknowledgement request
5268	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5269	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5270	}
5271	break;
5272	}
5273	///////////////////////////
5274	case CC_SEND_CLEANUP_1:
5275	{
5276	// wait for the first flit to be consumed
5277	if(p_dspin_out.read.read())
5278	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5279
5280	break;
5281	}
5282	///////////////////////////
5283	case CC_SEND_CLEANUP_2:
5284	{
5285	assert( p_dspin_out.read.read() and
5286	"The interconnect should accept the second cleanup flit instantly" );
5287
5288	// wait for the second flit to be consumed
5289	if(p_dspin_out.read.read())
5290	{
5291	if(r_cc_send_last_client.read() == 0) // dcache active request
5292	r_dcache_cc_send_req = false; // reset dcache request
5293	else // icache active request
5294	r_icache_cc_send_req = false; // reset icache request
5295
5296	// go back to idle state
5297	r_cc_send_fsm = CC_SEND_IDLE;
5298	}
5299	break;
5300	}
5301	///////////////////////////
5302	case CC_SEND_MULTI_ACK:
5303	{
5304	// wait for the flit to be consumed
5305	if(p_dspin_out.read.read())
5306	{
5307	if(r_cc_send_last_client.read() == 0) // dcache active request
5308	r_dcache_cc_send_req = false; // reset dcache request
5309	else // icache active request
5310	r_icache_cc_send_req = false; // reset icache request
5311	// go back to idle state
5312	r_cc_send_fsm = CC_SEND_IDLE;
5313	}
5314	break;
5315	}
5316	} // end switch CC_SEND FSM
5317
5318	///////////////////////////////////////////////////////////////////////////////
5319	// C_RECEIVE FSM
5320	// This FSM receive all coherence packets on a DSPIN40 port.
5321	// There is 4 packet types:
5322	// - CC_DATA_INVAL : DCACHE invalidate request
5323	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5324	// - CC_INST_INVAL : ICACHE invalidate request
5325	// - CC_INST_UPDT : ICACHE update request (multi-words)
5326	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5327	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5328	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5329	//////////////////////////////////////////////////////////////////////////////
5330	switch( r_cc_receive_fsm.read() )
5331	{
5332	/////////////////////
5333	case CC_RECEIVE_IDLE:
5334	{
5335	// a coherence request has arrived
5336	if(p_dspin_in.write.read())
5337	{
5338	// initialize dspin received data
5339	uint64_t receive_data = p_dspin_in.data.read();
5340	// initialize coherence packet type
5341	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5342	// initialize data/ins flip_flop (0 data / 1 ins)
5343	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5344	// test for a broadcast
5345	if(DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5346	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5347	// test for a CLACK
5348	else if(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK)
5349	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5350	// test for a multi updt
5351	else if((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5352	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5353	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5354	// test for a multi inval
5355	else
5356	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5357	}
5358	break;
5359	}
5360	//////////////////////
5361	case CC_RECEIVE_CLACK:
5362	{
5363	// initialize dspin received data
5364	uint64_t receive_data = p_dspin_in.data.read();
5365
5366	// for data CLACK, wait for dcache to take the request
5367	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5368	{
5369	// request dcache to handle the CLACK
5370	r_cc_receive_dcache_req = true;
5371	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET);
5372	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY);
5373	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5374	// get back to idle state
5375	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5376	break;
5377	}
5378	// for ins CLACK, wait for icache to take the request
5379	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5380	{
5381	// request icache to handle the CLACK
5382	r_cc_receive_icache_req = true;
5383	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET);
5384	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY);
5385	r_cc_receive_icache_type = CC_TYPE_CLACK;
5386	// get back to idle state
5387	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5388	break;
5389	}
5390	// keep waiting for the correct cache to accept the request
5391	break;
5392	}
5393	///////////////////////////////
5394	case CC_RECEIVE_BRDCAST_HEADER:
5395	{
5396	// no actual data in the HEADER, just skip to second flit
5397	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5398	break;
5399	}
5400	//////////////////////////////
5401	case CC_RECEIVE_BRDCAST_NLINE:
5402	{
5403	// initialize dspin received data
5404	uint64_t receive_data = p_dspin_in.data.read();
5405	// wait for both dcache and icache to take the request
5406	// TODO maybe we need to wait for both only to leave the state, but
5407	// not to actually post a request to an available cache => need a
5408	// flip_flop to check that ?
5409	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5410	{
5411	// request dcache to handle the BROADCAST
5412	r_cc_receive_dcache_req = true;
5413	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5414	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5415	// request icache to handle the BROADCAST
5416	r_cc_receive_icache_req = true;
5417	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5418	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5419	// get back to idle state
5420	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5421	break;
5422	}
5423	// keep waiting for the caches to accept the request
5424	break;
5425	}
5426	/////////////////////////////
5427	case CC_RECEIVE_INVAL_HEADER:
5428	{
5429	// sample updt tab index in the HEADER, than skip to second flit
5430	uint64_t receive_data = p_dspin_in.data.read();
5431	// for data INVAL, wait for dcache to take the request
5432	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5433	{
5434	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5435	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5436	break;
5437	}
5438	// for ins INVAL, wait for icache to take the request
5439	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5440	{
5441	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5442	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5443	break;
5444	}
5445	// keep waiting for the correct cache to accept the request
5446	break;
5447	}
5448	////////////////////////////
5449	case CC_RECEIVE_INVAL_NLINE:
5450	{
5451	// sample nline in the second flit
5452	uint64_t receive_data = p_dspin_in.data.read();
5453	// for data INVAL, wait for dcache to take the request
5454	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5455	{
5456	// request dcache to handle the INVAL
5457	r_cc_receive_dcache_req = true;
5458	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5459	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5460	// get back to idle state
5461	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5462	break;
5463	}
5464	// for ins INVAL, wait for icache to take the request
5465	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5466	{
5467	// request icache to handle the INVAL
5468	r_cc_receive_icache_req = true;
5469	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5470	r_cc_receive_icache_type = CC_TYPE_INVAL;
5471	// get back to idle state
5472	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5473	break;
5474	}
5475	// we should never get there
5476	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5477	}
5478	////////////////////////////
5479	case CC_RECEIVE_UPDT_HEADER:
5480	{
5481	// sample updt tab index in the HEADER, than skip to second flit
5482	uint64_t receive_data = p_dspin_in.data.read();
5483	// for data INVAL, wait for dcache to take the request and fifo to
5484	// be empty
5485	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5486	{
5487	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5488	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5489	break;
5490	}
5491	// for ins INVAL, wait for icache to take the request and fifo to be
5492	// empty
5493	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5494	{
5495	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5496	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5497	break;
5498	}
5499	// keep waiting for the correct cache to accept the request
5500	break;
5501	}
5502	///////////////////////////
5503	case CC_RECEIVE_UPDT_NLINE:
5504	{
5505	// sample nline and word index in the second flit
5506	uint64_t receive_data = p_dspin_in.data.read();
5507	// for data INVAL, wait for dcache to take the request and fifo to
5508	// be empty
5509	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5510	{
5511	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5512	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5513	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5514	// get back to idle state
5515	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5516	break;
5517	}
5518	// for ins INVAL, wait for icache to take the request and fifo to be
5519	// empty
5520	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5521	{
5522	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5523	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5524	r_cc_receive_icache_type = CC_TYPE_UPDT;
5525	// get back to idle state
5526	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5527	break;
5528	}
5529	// we should never get there
5530	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5531	break;
5532	}
5533	//////////////////////////
5534	case CC_RECEIVE_UPDT_DATA:
5535	{
5536	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5537	r_cc_receive_dcache_req = true;
5538	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5539	r_cc_receive_icache_req = true;
5540
5541	// sample data, be and eop
5542	uint64_t receive_data = p_dspin_in.data.read();
5543	// wait for the fifo
5544	if (r_cc_receive_updt_fifo_be.wok())
5545	{
5546	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5547	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5548	// sample eop to test for state exit
5549	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5550	cc_receive_updt_fifo_eop = flit_eop;
5551	cc_receive_updt_fifo_put = true;
5552	if(flit_eop)
5553	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5554	}
5555	break;
5556	}
5557	} // end switch CC_RECEIVE FSM
5558
5559	///////////////// Response FIFOs update //////////////////////
5560	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5561	vci_rsp_fifo_icache_put,
5562	vci_rsp_fifo_icache_data);
5563
5564	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5565	vci_rsp_fifo_dcache_put,
5566	vci_rsp_fifo_dcache_data);
5567	///////////////// updt FIFO update //////////////////////
5568	//TODO check this
5569	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5570	cc_receive_updt_fifo_put,
5571	cc_receive_updt_fifo_be);
5572	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5573	cc_receive_updt_fifo_put,
5574	cc_receive_updt_fifo_data);
5575	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5576	cc_receive_updt_fifo_put,
5577	cc_receive_updt_fifo_eop);
5578
5579	} // end transition()
5580
5581	///////////////////////
5582	tmpl(void)::genMoore()
5583	///////////////////////
5584	{
5585
5586	// VCI initiator command on the direct network
5587	// it depends on the CMD FSM state
5588
5589	p_vci_ini_d.pktid = 0;
5590	p_vci_ini_d.srcid = m_srcid_d;
5591	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5592	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5593	p_vci_ini_d.wrap = false;
5594	p_vci_ini_d.clen = 0;
5595	p_vci_ini_d.cfixed = false;
5596
5597	switch ( r_vci_cmd_fsm.read() ) {
5598
5599	case CMD_IDLE:
5600	p_vci_ini_d.cmdval = false;
5601	p_vci_ini_d.address = 0;
5602	p_vci_ini_d.wdata = 0;
5603	p_vci_ini_d.be = 0;
5604	p_vci_ini_d.trdid = 0;
5605	p_vci_ini_d.pktid = 0;
5606	p_vci_ini_d.plen = 0;
5607	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5608	p_vci_ini_d.eop = false;
5609	break;
5610
5611	case CMD_INS_MISS:
5612	p_vci_ini_d.cmdval = true;
5613	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5614	p_vci_ini_d.wdata = 0;
5615	p_vci_ini_d.be = 0xF;
5616	p_vci_ini_d.trdid = 0;
5617	p_vci_ini_d.pktid = TYPE_READ_INS_MISS;
5618	p_vci_ini_d.plen = m_icache_words<<2;
5619	p_vci_ini_d.cmd = vci_param::CMD_READ;
5620	p_vci_ini_d.eop = true;
5621	break;
5622
5623	case CMD_INS_UNC:
5624	p_vci_ini_d.cmdval = true;
5625	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
5626	p_vci_ini_d.wdata = 0;
5627	p_vci_ini_d.be = 0xF;
5628	p_vci_ini_d.trdid = 0;
5629	p_vci_ini_d.pktid = TYPE_READ_INS_UNC;
5630	p_vci_ini_d.plen = 4;
5631	p_vci_ini_d.cmd = vci_param::CMD_READ;
5632	p_vci_ini_d.eop = true;
5633	break;
5634
5635	case CMD_DATA_MISS:
5636	p_vci_ini_d.cmdval = true;
5637	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5638	p_vci_ini_d.wdata = 0;
5639	p_vci_ini_d.be = 0xF;
5640	p_vci_ini_d.trdid = 0;
5641	p_vci_ini_d.pktid = TYPE_READ_DATA_MISS;
5642	p_vci_ini_d.plen = m_dcache_words << 2;
5643	p_vci_ini_d.cmd = vci_param::CMD_READ;
5644	p_vci_ini_d.eop = true;
5645	break;
5646
5647	case CMD_DATA_UNC:
5648	p_vci_ini_d.cmdval = true;
5649	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5650	p_vci_ini_d.wdata = 0;
5651	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
5652	p_vci_ini_d.trdid = 0;
5653	p_vci_ini_d.pktid = TYPE_READ_DATA_UNC;
5654	p_vci_ini_d.plen = 4;
5655	p_vci_ini_d.cmd = vci_param::CMD_READ;
5656	p_vci_ini_d.eop = true;
5657	break;
5658
5659	case CMD_DATA_WRITE:
5660	p_vci_ini_d.cmdval = true;
5661	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5662	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5663	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5664	p_vci_ini_d.trdid = r_wbuf.getIndex();
5665	p_vci_ini_d.pktid = TYPE_WRITE;
5666	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5667	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
5668	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5669	break;
5670
5671	case CMD_DATA_LL:
5672	p_vci_ini_d.cmdval = true;
5673	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5674	p_vci_ini_d.wdata = 0;
5675	p_vci_ini_d.be = 0xF;
5676	p_vci_ini_d.trdid = 0;
5677	p_vci_ini_d.pktid = TYPE_LL;
5678	p_vci_ini_d.plen = 8;
5679	p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
5680	p_vci_ini_d.eop = true;
5681	break;
5682
5683	case CMD_DATA_SC:
5684	p_vci_ini_d.cmdval = true;
5685	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5686	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_llsc_key.read();
5687	else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
5688	p_vci_ini_d.be = 0xF;
5689	p_vci_ini_d.trdid = 0;
5690	p_vci_ini_d.pktid = TYPE_SC;
5691	p_vci_ini_d.plen = 8;
5692	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5693	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5694	break;
5695
5696	case CMD_DATA_CAS:
5697	p_vci_ini_d.cmdval = true;
5698	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5699	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
5700	else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
5701	p_vci_ini_d.be = 0xF;
5702	p_vci_ini_d.trdid = 0;
5703	p_vci_ini_d.pktid = TYPE_CAS;
5704	p_vci_ini_d.plen = 8;
5705	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5706	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5707	break;
5708	} // end switch r_vci_cmd_fsm
5709
5710	// VCI initiator response on the direct network
5711	// it depends on the VCI RSP state
5712
5713	switch (r_vci_rsp_fsm.read() )
5714	{
5715	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
5716	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5717	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5718	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5719	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5720	case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5721	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
5722	} // end switch r_vci_rsp_fsm
5723
5724	/////////////////
5725	// CC_SEND FSM //
5726	/////////////////
5727	uint64_t dspin_send_data = 0;
5728	switch ( r_cc_send_fsm.read() )
5729	{
5730	///////////////////////////
5731	case CC_SEND_IDLE:
5732	{
5733	p_dspin_out.write = false;
5734	break;
5735	}
5736	///////////////////////////
5737	case CC_SEND_CLEANUP_1:
5738	{
5739	// initialize dspin send data
5740	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP);
5741	DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID);
5742	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5743	// dcache active request
5744	if(r_cc_send_last_client.read() == 0)
5745	{
5746	// compute global id
5747	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5748	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5749	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5750
5751	DspinDhccpParam::dspin_set(dspin_send_data,
5752	global_id,
5753	DspinDhccpParam::CLEANUP_DEST);
5754
5755	DspinDhccpParam::dspin_set(dspin_send_data,
5756	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5757	DspinDhccpParam::CLEANUP_NLINE_MSB);
5758
5759	DspinDhccpParam::dspin_set(dspin_send_data,
5760	r_dcache_cc_send_way.read(),
5761	DspinDhccpParam::CLEANUP_WAY_INDEX);
5762
5763	DspinDhccpParam::dspin_set(dspin_send_data,
5764	DspinDhccpParam::TYPE_CLEANUP_DATA,
5765	DspinDhccpParam::FROM_L1_TYPE);
5766	}
5767	// icache active request
5768	else
5769	{
5770	// compute global id
5771	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5772	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5773	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5774
5775	DspinDhccpParam::dspin_set(dspin_send_data,
5776	global_id,
5777	DspinDhccpParam::CLEANUP_DEST);
5778
5779	DspinDhccpParam::dspin_set(dspin_send_data,
5780	r_icache_cc_send_nline.read() & 0x300000000ULL,
5781	DspinDhccpParam::CLEANUP_NLINE_MSB);
5782
5783	DspinDhccpParam::dspin_set(dspin_send_data,
5784	r_icache_cc_send_way.read(),
5785	DspinDhccpParam::CLEANUP_WAY_INDEX);
5786
5787	DspinDhccpParam::dspin_set(dspin_send_data,
5788	DspinDhccpParam::TYPE_CLEANUP_INST,
5789	DspinDhccpParam::FROM_L1_TYPE);
5790	}
5791	// send flit
5792	p_dspin_out.data = dspin_send_data;
5793	p_dspin_out.write = true;
5794	break;
5795	}
5796	///////////////////////////
5797	case CC_SEND_CLEANUP_2:
5798	{
5799	// initialize dspin send data
5800	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5801	// dcache active request
5802	if(r_cc_send_last_client.read() == 0)
5803	{
5804	DspinDhccpParam::dspin_set(dspin_send_data,
5805	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5806	DspinDhccpParam::CLEANUP_NLINE_LSB);
5807	}
5808	// icache active request
5809	else
5810	{
5811	DspinDhccpParam::dspin_set(dspin_send_data,
5812	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5813	DspinDhccpParam::CLEANUP_NLINE_LSB);
5814	}
5815	// send flit
5816	p_dspin_out.data = dspin_send_data;
5817	p_dspin_out.write = true;
5818	break;
5819	}
5820	///////////////////////////
5821	case CC_SEND_MULTI_ACK:
5822	{
5823	// initialize dspin send data
5824	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5825	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5826	DspinDhccpParam::dspin_set(dspin_send_data,
5827	DspinDhccpParam::TYPE_MULTI_ACK,
5828	DspinDhccpParam::FROM_L1_TYPE);
5829	// dcache active request
5830	if(r_cc_send_last_client.read() == 0)
5831	{
5832	// compute global id
5833	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5834	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5835	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5836
5837	DspinDhccpParam::dspin_set(dspin_send_data,
5838	global_id,
5839	DspinDhccpParam::MULTI_ACK_DEST);
5840
5841	DspinDhccpParam::dspin_set(dspin_send_data,
5842	r_dcache_cc_send_updt_tab_idx.read(),
5843	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5844	}
5845	// icache active request
5846	else
5847	{
5848	// compute global id
5849	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5850	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5851	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5852
5853	DspinDhccpParam::dspin_set(dspin_send_data,
5854	global_id,
5855	DspinDhccpParam::MULTI_ACK_DEST);
5856
5857	DspinDhccpParam::dspin_set(dspin_send_data,
5858	r_icache_cc_send_updt_tab_idx.read(),
5859	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5860	}
5861	// send flit
5862	p_dspin_out.data = dspin_send_data;
5863	p_dspin_out.write = true;
5864	break;
5865	}
5866	} // end switch CC_SEND FSM
5867
5868	////////////////////
5869	// CC_RECEIVE FSM //
5870	////////////////////
5871	switch( r_cc_receive_fsm.read() )
5872	{
5873	/////////////////////
5874	case CC_RECEIVE_IDLE:
5875	{
5876	p_dspin_in.read = false;
5877	break;
5878	}
5879	//////////////////////
5880	case CC_RECEIVE_CLACK:
5881	{
5882	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5883	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5884	p_dspin_in.read = true;
5885	else
5886	p_dspin_in.read = false;
5887	break;
5888	}
5889	///////////////////////////////
5890	case CC_RECEIVE_BRDCAST_HEADER:
5891	{
5892	p_dspin_in.read = true;
5893	break;
5894	}
5895	//////////////////////////////
5896	case CC_RECEIVE_BRDCAST_NLINE:
5897	{
5898	// TODO maybe we need to wait for both only to leave the state, but
5899	// not to actually post a request to an available cache => need a
5900	// flip_flop to check that ?
5901	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5902	p_dspin_in.read = true;
5903	else
5904	p_dspin_in.read = false;
5905	break;
5906	}
5907	/////////////////////////////
5908	case CC_RECEIVE_INVAL_HEADER:
5909	{
5910	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5911	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5912	p_dspin_in.read = true;
5913	else
5914	p_dspin_in.read = false;
5915	break;
5916	}
5917	////////////////////////////
5918	case CC_RECEIVE_INVAL_NLINE:
5919	{
5920	p_dspin_in.read = true;
5921	break;
5922	}
5923	////////////////////////////
5924	case CC_RECEIVE_UPDT_HEADER:
5925	{
5926	if (((r_cc_receive_data_ins.read() == 0) and
5927	not (r_cc_receive_dcache_req.read()) and
5928	r_cc_receive_updt_fifo_be.empty())
5929	or
5930	((r_cc_receive_data_ins.read() == 1) and
5931	not (r_cc_receive_icache_req.read()) and
5932	r_cc_receive_updt_fifo_be.empty()))
5933	p_dspin_in.read = true;
5934	else
5935	p_dspin_in.read = false;
5936	break;
5937	}
5938	///////////////////////////
5939	case CC_RECEIVE_UPDT_NLINE:
5940	{
5941	if (((r_cc_receive_data_ins.read() == 0) and
5942	not (r_cc_receive_dcache_req.read()) and
5943	r_cc_receive_updt_fifo_be.empty())
5944	or
5945	((r_cc_receive_data_ins.read() == 1) and
5946	not (r_cc_receive_icache_req.read()) and
5947	r_cc_receive_updt_fifo_be.empty()))
5948	p_dspin_in.read = true;
5949	else
5950	p_dspin_in.read = false;
5951	break;
5952	}
5953	//////////////////////////
5954	case CC_RECEIVE_UPDT_DATA:
5955	{
5956	if (r_cc_receive_updt_fifo_be.wok())
5957	p_dspin_in.read = true;
5958	else
5959	p_dspin_in.read = false;
5960	break;
5961	}
5962	} // end switch CC_RECEIVE FSM
5963
5964	} // end genMoore
5965
5966	}}
5967
5968	// Local Variables:
5969	// tab-width: 4
5970	// c-basic-offset: 4
5971	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5972	// indent-tabs-mode: nil
5973	// End:
5974
5975	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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