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source: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper.cpp @ 325

Last change on this file since 325 was 325, checked in by joannou, 11 years ago

bugfix in vci_cc_vcache_wrapper_dspin_coherence :

consume fifo in ICACHE_CC_UPDT for last flit
fixed nline value for tlb accesses in DCACHE_CC_CHECK sub fsm
added a break after the jump to the TLB_SCAN sub fsm in DCACHE_CC_UPDT

File size: 227.6 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using soclib::common::uint32_log2;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	int proc_id,
170	const soclib::common::MappingTable &mtd,
171	const soclib::common::MappingTable &mtc,
172	const soclib::common::IntTab &initiator_index_d,
173	const soclib::common::IntTab &initiator_index_c,
174	const soclib::common::IntTab &target_index_c,
175	size_t itlb_ways,
176	size_t itlb_sets,
177	size_t dtlb_ways,
178	size_t dtlb_sets,
179	size_t icache_ways,
180	size_t icache_sets,
181	size_t icache_words,
182	size_t dcache_ways,
183	size_t dcache_sets,
184	size_t dcache_words,
185	size_t wbuf_nlines,
186	size_t wbuf_nwords,
187	size_t x_width,
188	size_t y_width,
189	uint32_t memory_cache_local_id,
190	uint32_t max_frozen_cycles,
191	uint32_t debug_start_cycle,
192	bool debug_ok)
193	: soclib::caba::BaseModule(name),
194
195	p_clk("clk"),
196	p_resetn("resetn"),
197	p_vci_ini_d("vci_ini_d"),
198	p_dspin_in("dspin_in"),
199	p_dspin_out("dspin_out"),
200
201	m_cacheability_table(mtd.getCacheabilityTable()),
202	m_segment(mtc.getSegment(target_index_c)),
203	m_srcid_d(mtd.indexForId(initiator_index_d)),
204	m_srcid_c(mtc.indexForId(initiator_index_c)),
205
206	m_itlb_ways(itlb_ways),
207	m_itlb_sets(itlb_sets),
208
209	m_dtlb_ways(dtlb_ways),
210	m_dtlb_sets(dtlb_sets),
211
212	m_icache_ways(icache_ways),
213	m_icache_sets(icache_sets),
214	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
215	m_icache_words(icache_words),
216
217	m_dcache_ways(dcache_ways),
218	m_dcache_sets(dcache_sets),
219	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
220	m_dcache_words(dcache_words),
221
222	m_x_width(x_width),
223	m_y_width(y_width),
224
225	m_memory_cache_local_id(memory_cache_local_id),
226	m_proc_id(proc_id),
227	m_max_frozen_cycles(max_frozen_cycles),
228	m_paddr_nbits(vci_param::N),
229
230	m_debug_start_cycle(debug_start_cycle),
231	m_debug_ok(debug_ok),
232
233	r_mmu_ptpr("r_mmu_ptpr"),
234	r_mmu_mode("r_mmu_mode"),
235	r_mmu_word_lo("r_mmu_word_lo"),
236	r_mmu_word_hi("r_mmu_word_hi"),
237	r_mmu_ibvar("r_mmu_ibvar"),
238	r_mmu_dbvar("r_mmu_dbvar"),
239	r_mmu_ietr("r_mmu_ietr"),
240	r_mmu_detr("r_mmu_detr"),
241
242	r_icache_fsm("r_icache_fsm"),
243	r_icache_fsm_save("r_icache_fsm_save"),
244	r_icache_vci_paddr("r_icache_vci_paddr"),
245	r_icache_vaddr_save("r_icache_vaddr_save"),
246
247	r_icache_miss_way("r_icache_miss_way"),
248	r_icache_miss_set("r_icache_miss_set"),
249	r_icache_miss_word("r_icache_miss_word"),
250	r_icache_miss_inval("r_icache_miss_inval"),
251	r_icache_miss_clack("r_icache_miss_clack"),
252
253	r_icache_cc_way("r_icache_cc_way"),
254	r_icache_cc_set("r_icache_cc_set"),
255	r_icache_cc_word("r_icache_cc_word"),
256	r_icache_cc_need_write("r_icache_cc_need_write"),
257
258	r_icache_flush_count("r_icache_flush_count"),
259
260	r_icache_miss_req("r_icache_miss_req"),
261	r_icache_unc_req("r_icache_unc_req"),
262
263	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
264	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
265
266	r_icache_cc_send_req("r_icache_cc_send_req"),
267	r_icache_cc_send_type("r_icache_cc_send_type"),
268	r_icache_cc_send_nline("r_icache_cc_send_nline"),
269	r_icache_cc_send_way("r_icache_cc_send_way"),
270	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
271
272	r_dcache_fsm("r_dcache_fsm"),
273	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
274	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
275
276	r_dcache_wbuf_req("r_dcache_wbuf_req"),
277	r_dcache_updt_req("r_dcache_updt_req"),
278	r_dcache_save_vaddr("r_dcache_save_vaddr"),
279	r_dcache_save_wdata("r_dcache_save_wdata"),
280	r_dcache_save_be("r_dcache_save_be"),
281	r_dcache_save_paddr("r_dcache_save_paddr"),
282	r_dcache_save_cacheable("r_dcache_save_cacheable"),
283	r_dcache_save_cache_way("r_dcache_save_cache_way"),
284	r_dcache_save_cache_set("r_dcache_save_cache_set"),
285	r_dcache_save_cache_word("r_dcache_save_cache_word"),
286
287	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
288	r_dcache_dirty_way("r_dcache_dirty_way"),
289	r_dcache_dirty_set("r_dcache_dirty_set"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
296	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
297	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
298	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
299	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
300	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
301
302	r_dcache_xtn_way("r_dcache_xtn_way"),
303	r_dcache_xtn_set("r_dcache_xtn_set"),
304
305	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
306
307	r_dcache_miss_type("r_dcache_miss_type"),
308	r_dcache_miss_word("r_dcache_miss_word"),
309	r_dcache_miss_way("r_dcache_miss_way"),
310	r_dcache_miss_set("r_dcache_miss_set"),
311	r_dcache_miss_inval("r_dcache_miss_inval"),
312
313	r_dcache_cc_way("r_dcache_cc_way"),
314	r_dcache_cc_set("r_dcache_cc_set"),
315	r_dcache_cc_word("r_dcache_cc_word"),
316	r_dcache_cc_need_write("r_dcache_cc_need_write"),
317
318	r_dcache_flush_count("r_dcache_flush_count"),
319
320	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
321
322	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
323	r_dcache_tlb_ins("r_dcache_tlb_ins"),
324	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
325	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
326	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
327	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
328	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
329	r_dcache_tlb_way("r_dcache_tlb_way"),
330	r_dcache_tlb_set("r_dcache_tlb_set"),
331
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
334
335	r_dcache_xtn_req("r_dcache_xtn_req"),
336	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
337
338	r_dcache_cc_send_req("r_dcache_cc_send_req"),
339	r_dcache_cc_send_type("r_dcache_cc_send_type"),
340	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
341	r_dcache_cc_send_way("r_dcache_cc_send_way"),
342	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
343
344	r_vci_cmd_fsm("r_vci_cmd_fsm"),
345	r_vci_cmd_min("r_vci_cmd_min"),
346	r_vci_cmd_max("r_vci_cmd_max"),
347	r_vci_cmd_cpt("r_vci_cmd_cpt"),
348	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
349
350	r_vci_rsp_fsm("r_vci_rsp_fsm"),
351	r_vci_rsp_cpt("r_vci_rsp_cpt"),
352	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
353	r_vci_rsp_data_error("r_vci_rsp_data_error"),
354	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
355	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
356
357	r_cc_send_fsm("r_cc_send_fsm"),
358	r_cc_send_last_client("r_cc_send_last_client"),
359
360	r_cc_receive_fsm("r_cc_receive_fsm"),
361	r_cc_receive_data_ins("r_cc_receive_data_ins"),
362	r_cc_receive_word_idx("r_cc_receive_word_idx"),
363	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
364	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
365	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
366
367	r_cc_receive_icache_req("r_cc_receive_icache_req"),
368	r_cc_receive_icache_type("r_cc_receive_icache_type"),
369	r_cc_receive_icache_way("r_cc_receive_icache_way"),
370	r_cc_receive_icache_set("r_cc_receive_icache_set"),
371	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
372	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
373
374	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
375	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
376	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
377	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
378	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
379	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
380
381	r_iss(this->name(), proc_id),
382	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
383	r_icache("icache", icache_ways, icache_sets, icache_words),
384	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
385	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
386	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
387	{
388	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
389	"Need more PLEN bits.");
390
391	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
392	"Need more TRDID bits.");
393
394	assert( (icache_words == dcache_words) and
395	"icache_words and dcache_words parameters must be equal");
396
397	assert( (itlb_sets == dtlb_sets) and
398	"itlb_sets and dtlb_sets parameters must be etqual");
399
400	assert( (itlb_ways == dtlb_ways) and
401	"itlb_ways and dtlb_ways parameters must be etqual");
402
403	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
404	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
405	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
406	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
407	(uint32_log2(m_icache_words<<2));
408
409	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
410
411	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
412	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
413
414	SC_METHOD(transition);
415	dont_initialize();
416	sensitive << p_clk.pos();
417
418	SC_METHOD(genMoore);
419	dont_initialize();
420	sensitive << p_clk.neg();
421
422	typename iss_t::CacheInfo cache_info;
423	cache_info.has_mmu = true;
424	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
425	cache_info.icache_assoc = icache_ways;
426	cache_info.icache_n_lines = icache_sets;
427	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
428	cache_info.dcache_assoc = dcache_ways;
429	cache_info.dcache_n_lines = dcache_sets;
430	r_iss.setCacheInfo(cache_info);
431	}
432
433	/////////////////////////////////////
434	tmpl(/**/)::~VciCcVCacheWrapper()
435	/////////////////////////////////////
436	{
437	delete [] r_dcache_in_tlb;
438	delete [] r_dcache_contains_ptd;
439	}
440
441	////////////////////////
442	tmpl(void)::print_cpi()
443	////////////////////////
444	{
445	std::cout << name() << " CPI = "
446	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
447	}
448
449	////////////////////////////////////
450	tmpl(void)::print_trace(size_t mode)
451	////////////////////////////////////
452	{
453	// b0 : write buffer trace
454	// b1 : write buffer verbose
455	// b2 : dcache trace
456	// b3 : icache trace
457	// b4 : dtlb trace
458	// b5 : itlb trace
459
460	std::cout << std::dec << "PROC " << name() << std::endl;
461
462	std::cout << " " << m_ireq << std::endl;
463	std::cout << " " << m_irsp << std::endl;
464	std::cout << " " << m_dreq << std::endl;
465	std::cout << " " << m_drsp << std::endl;
466
467	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
468	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
469	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
470	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
471	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
472	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
473	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
474	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
475	std::cout << std::endl;
476
477	if(mode & 0x01)
478	{
479	r_wbuf.printTrace((mode>>1)&1);
480	}
481	if(mode & 0x04)
482	{
483	std::cout << " Data Cache" << std::endl;
484	r_dcache.printTrace();
485	}
486	if(mode & 0x08)
487	{
488	std::cout << " Instruction Cache" << std::endl;
489	r_icache.printTrace();
490	}
491	if(mode & 0x10)
492	{
493	std::cout << " Data TLB" << std::endl;
494	r_dtlb.printTrace();
495	}
496	if(mode & 0x20)
497	{
498	std::cout << " Instruction TLB" << std::endl;
499	r_itlb.printTrace();
500	}
501	}
502
503	//////////////////////////////////////////
504	tmpl(void)::cache_monitor( paddr_t addr )
505	//////////////////////////////////////////
506	{
507	size_t cache_way;
508	size_t cache_set;
509	size_t cache_word;
510	uint32_t cache_rdata;
511	bool cache_hit = r_dcache.read_neutral( addr,
512	&cache_rdata,
513	&cache_way,
514	&cache_set,
515	&cache_word );
516	bool icache_hit = r_icache.read_neutral( addr,
517	&cache_rdata,
518	&cache_way,
519	&cache_set,
520	&cache_word );
521	if ( cache_hit != m_debug_previous_hit )
522	{
523	std::cout << "PROC " << name()
524	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
525	<< " for adresse " << std::hex << addr
526	<< " / HIT = " << std::dec << cache_hit << std::endl;
527	m_debug_previous_hit = cache_hit;
528	}
529	if ( icache_hit != m_idebug_previous_hit )
530	{
531	std::cout << "PROC " << name()
532	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
533	<< " for adresse " << std::hex << addr
534	<< " / HIT = " << icache_hit << std::endl;
535	m_idebug_previous_hit = icache_hit;
536	}
537	}
538
539	/*
540	////////////////////////
541	tmpl(void)::print_stats()
542	////////////////////////
543	{
544	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
545	std::cout << name() << std::endl
546	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
547	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
548	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
549	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
550	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
551	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
552	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
553	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
554	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
555	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
556	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
557	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
558	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
559	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
560	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
561	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
563	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
564	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
565	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
566	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
567	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
568	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
569	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
570	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
571	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
572	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
573	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
574	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
575	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
576	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
577	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
578	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
579	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
580	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
581	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
583	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
584	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
585	}
586
587	////////////////////////
588	tmpl(void)::clear_stats()
589	////////////////////////
590	{
591	m_cpt_dcache_data_read = 0;
592	m_cpt_dcache_data_write = 0;
593	m_cpt_dcache_dir_read = 0;
594	m_cpt_dcache_dir_write = 0;
595	m_cpt_icache_data_read = 0;
596	m_cpt_icache_data_write = 0;
597	m_cpt_icache_dir_read = 0;
598	m_cpt_icache_dir_write = 0;
599
600	m_cpt_frz_cycles = 0;
601	m_cpt_dcache_frz_cycles = 0;
602	m_cpt_total_cycles = 0;
603
604	m_cpt_read = 0;
605	m_cpt_write = 0;
606	m_cpt_data_miss = 0;
607	m_cpt_ins_miss = 0;
608	m_cpt_unc_read = 0;
609	m_cpt_write_cached = 0;
610	m_cpt_ins_read = 0;
611
612	m_cost_write_frz = 0;
613	m_cost_data_miss_frz = 0;
614	m_cost_unc_read_frz = 0;
615	m_cost_ins_miss_frz = 0;
616
617	m_cpt_imiss_transaction = 0;
618	m_cpt_dmiss_transaction = 0;
619	m_cpt_unc_transaction = 0;
620	m_cpt_write_transaction = 0;
621	m_cpt_icache_unc_transaction = 0;
622
623	m_cost_imiss_transaction = 0;
624	m_cost_dmiss_transaction = 0;
625	m_cost_unc_transaction = 0;
626	m_cost_write_transaction = 0;
627	m_cost_icache_unc_transaction = 0;
628	m_length_write_transaction = 0;
629
630	m_cpt_ins_tlb_read = 0;
631	m_cpt_ins_tlb_miss = 0;
632	m_cpt_ins_tlb_update_acc = 0;
633
634	m_cpt_data_tlb_read = 0;
635	m_cpt_data_tlb_miss = 0;
636	m_cpt_data_tlb_update_acc = 0;
637	m_cpt_data_tlb_update_dirty = 0;
638	m_cpt_ins_tlb_hit_dcache = 0;
639	m_cpt_data_tlb_hit_dcache = 0;
640	m_cpt_ins_tlb_occup_cache = 0;
641	m_cpt_data_tlb_occup_cache = 0;
642
643	m_cost_ins_tlb_miss_frz = 0;
644	m_cost_data_tlb_miss_frz = 0;
645	m_cost_ins_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_acc_frz = 0;
647	m_cost_data_tlb_update_dirty_frz = 0;
648	m_cost_ins_tlb_occup_cache_frz = 0;
649	m_cost_data_tlb_occup_cache_frz = 0;
650
651	m_cpt_itlbmiss_transaction = 0;
652	m_cpt_itlb_ll_transaction = 0;
653	m_cpt_itlb_sc_transaction = 0;
654	m_cpt_dtlbmiss_transaction = 0;
655	m_cpt_dtlb_ll_transaction = 0;
656	m_cpt_dtlb_sc_transaction = 0;
657	m_cpt_dtlb_ll_dirty_transaction = 0;
658	m_cpt_dtlb_sc_dirty_transaction = 0;
659
660	m_cost_itlbmiss_transaction = 0;
661	m_cost_itlb_ll_transaction = 0;
662	m_cost_itlb_sc_transaction = 0;
663	m_cost_dtlbmiss_transaction = 0;
664	m_cost_dtlb_ll_transaction = 0;
665	m_cost_dtlb_sc_transaction = 0;
666	m_cost_dtlb_ll_dirty_transaction = 0;
667	m_cost_dtlb_sc_dirty_transaction = 0;
668
669	m_cpt_cc_update_data = 0;
670	m_cpt_cc_inval_ins = 0;
671	m_cpt_cc_inval_data = 0;
672	m_cpt_cc_broadcast = 0;
673
674	m_cost_updt_data_frz = 0;
675	m_cost_inval_ins_frz = 0;
676	m_cost_inval_data_frz = 0;
677	m_cost_broadcast_frz = 0;
678
679	m_cpt_cc_cleanup_data = 0;
680	m_cpt_cc_cleanup_ins = 0;
681	}
682
683	*/
684
685	/////////////////////////
686	tmpl(void)::transition()
687	/////////////////////////
688	{
689	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
690	if ( not p_resetn.read() )
691	{
692	r_iss.reset();
693	r_wbuf.reset();
694	r_icache.reset();
695	r_dcache.reset();
696	r_itlb.reset();
697	r_dtlb.reset();
698
699	r_dcache_fsm = DCACHE_IDLE;
700	r_icache_fsm = ICACHE_IDLE;
701	r_vci_cmd_fsm = CMD_IDLE;
702	r_vci_rsp_fsm = RSP_IDLE;
703	r_cc_receive_fsm = CC_RECEIVE_IDLE;
704	r_cc_send_fsm = CC_SEND_IDLE;
705
706	// reset dcache directory extension
707	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
708	{
709	r_dcache_in_tlb[i] = false;
710	r_dcache_contains_ptd[i] = false;
711	}
712
713	// Response FIFOs and cleanup buffer
714	r_vci_rsp_fifo_icache.init();
715	r_vci_rsp_fifo_dcache.init();
716
717	// ICACHE & DCACHE activated
718	r_mmu_mode = 0x3;
719
720	// No request from ICACHE FSM to CMD FSM
721	r_icache_miss_req = false;
722	r_icache_unc_req = false;
723
724	// No request from ICACHE_FSM to DCACHE FSM
725	r_icache_tlb_miss_req = false;
726
727	// No request from ICACHE_FSM to CC_SEND FSM
728	r_icache_cc_send_req = false;
729
730	// No pending write in pipeline
731	r_dcache_wbuf_req = false;
732	r_dcache_updt_req = false;
733
734	// No request from DCACHE_FSM to CMD_FSM
735	r_dcache_vci_miss_req = false;
736	r_dcache_vci_unc_req = false;
737	r_dcache_vci_cas_req = false;
738	r_dcache_vci_ll_req = false;
739	r_dcache_vci_sc_req = false;
740
741	// No uncacheable write pending
742	r_dcache_pending_unc_write = false;
743
744	// No processor XTN request pending
745	r_dcache_xtn_req = false;
746
747	// No request from DCACHE FSM to CC_SEND FSM
748	r_dcache_cc_send_req = false;
749
750	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
751	r_cc_receive_icache_req = false;
752	r_cc_receive_dcache_req = false;
753
754	// last cc_send client was dcache
755	r_cc_send_last_client = false;
756
757	// No pending cleanup after a replacement
758	r_icache_miss_clack = false;
759	r_dcache_miss_clack = false;
760
761	// No signalisation of a coherence request matching a pending miss
762	r_icache_miss_inval = false;
763	r_dcache_miss_inval = false;
764
765	// No signalisation of errors
766	r_vci_rsp_ins_error = false;
767	r_vci_rsp_data_error = false;
768
769	// Debug variables
770	m_debug_previous_hit = false;
771	m_idebug_previous_hit = false;
772	m_debug_dcache_fsm = false;
773	m_debug_icache_fsm = false;
774
775	// activity counters
776	m_cpt_dcache_data_read = 0;
777	m_cpt_dcache_data_write = 0;
778	m_cpt_dcache_dir_read = 0;
779	m_cpt_dcache_dir_write = 0;
780	m_cpt_icache_data_read = 0;
781	m_cpt_icache_data_write = 0;
782	m_cpt_icache_dir_read = 0;
783	m_cpt_icache_dir_write = 0;
784
785	m_cpt_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787	m_cpt_stop_simulation = 0;
788
789	m_cpt_data_miss = 0;
790	m_cpt_ins_miss = 0;
791	m_cpt_unc_read = 0;
792	m_cpt_write_cached = 0;
793	m_cpt_ins_read = 0;
794
795	m_cost_write_frz = 0;
796	m_cost_data_miss_frz = 0;
797	m_cost_unc_read_frz = 0;
798	m_cost_ins_miss_frz = 0;
799
800	m_cpt_imiss_transaction = 0;
801	m_cpt_dmiss_transaction = 0;
802	m_cpt_unc_transaction = 0;
803	m_cpt_write_transaction = 0;
804	m_cpt_icache_unc_transaction = 0;
805
806	m_cost_imiss_transaction = 0;
807	m_cost_dmiss_transaction = 0;
808	m_cost_unc_transaction = 0;
809	m_cost_write_transaction = 0;
810	m_cost_icache_unc_transaction = 0;
811	m_length_write_transaction = 0;
812
813	m_cpt_ins_tlb_read = 0;
814	m_cpt_ins_tlb_miss = 0;
815	m_cpt_ins_tlb_update_acc = 0;
816
817	m_cpt_data_tlb_read = 0;
818	m_cpt_data_tlb_miss = 0;
819	m_cpt_data_tlb_update_acc = 0;
820	m_cpt_data_tlb_update_dirty = 0;
821	m_cpt_ins_tlb_hit_dcache = 0;
822	m_cpt_data_tlb_hit_dcache = 0;
823	m_cpt_ins_tlb_occup_cache = 0;
824	m_cpt_data_tlb_occup_cache = 0;
825
826	m_cost_ins_tlb_miss_frz = 0;
827	m_cost_data_tlb_miss_frz = 0;
828	m_cost_ins_tlb_update_acc_frz = 0;
829	m_cost_data_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_dirty_frz = 0;
831	m_cost_ins_tlb_occup_cache_frz = 0;
832	m_cost_data_tlb_occup_cache_frz = 0;
833
834	m_cpt_ins_tlb_inval = 0;
835	m_cpt_data_tlb_inval = 0;
836	m_cost_ins_tlb_inval_frz = 0;
837	m_cost_data_tlb_inval_frz = 0;
838
839	m_cpt_cc_broadcast = 0;
840
841	m_cost_updt_data_frz = 0;
842	m_cost_inval_ins_frz = 0;
843	m_cost_inval_data_frz = 0;
844	m_cost_broadcast_frz = 0;
845
846	m_cpt_cc_cleanup_data = 0;
847	m_cpt_cc_cleanup_ins = 0;
848
849	m_cpt_itlbmiss_transaction = 0;
850	m_cpt_itlb_ll_transaction = 0;
851	m_cpt_itlb_sc_transaction = 0;
852	m_cpt_dtlbmiss_transaction = 0;
853	m_cpt_dtlb_ll_transaction = 0;
854	m_cpt_dtlb_sc_transaction = 0;
855	m_cpt_dtlb_ll_dirty_transaction = 0;
856	m_cpt_dtlb_sc_dirty_transaction = 0;
857
858	m_cost_itlbmiss_transaction = 0;
859	m_cost_itlb_ll_transaction = 0;
860	m_cost_itlb_sc_transaction = 0;
861	m_cost_dtlbmiss_transaction = 0;
862	m_cost_dtlb_ll_transaction = 0;
863	m_cost_dtlb_sc_transaction = 0;
864	m_cost_dtlb_ll_dirty_transaction = 0;
865	m_cost_dtlb_sc_dirty_transaction = 0;
866	/*
867	m_cpt_dcache_frz_cycles = 0;
868	m_cpt_read = 0;
869	m_cpt_write = 0;
870	m_cpt_cc_update_data = 0;
871	m_cpt_cc_inval_ins = 0;
872	m_cpt_cc_inval_data = 0;
873	*/
874
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
878	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
879
880	// init the llsc reservation buffer
881	r_dcache_llsc_valid = false;
882
883	return;
884	}
885
886	// Response FIFOs default values
887	bool vci_rsp_fifo_icache_get = false;
888	bool vci_rsp_fifo_icache_put = false;
889	uint32_t vci_rsp_fifo_icache_data = 0;
890
891	bool vci_rsp_fifo_dcache_get = false;
892	bool vci_rsp_fifo_dcache_put = false;
893	uint32_t vci_rsp_fifo_dcache_data = 0;
894
895	// updt fifo
896	bool cc_receive_updt_fifo_get = false;
897	bool cc_receive_updt_fifo_put = false;
898	uint32_t cc_receive_updt_fifo_be = 0;
899	uint32_t cc_receive_updt_fifo_data = 0;
900	bool cc_receive_updt_fifo_eop = false;
901
902	#ifdef INSTRUMENTATION
903	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
904	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
905	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
906	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
907	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
908	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
909	#endif
910
911	m_cpt_total_cycles++;
912
913	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
914	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
915
916	/////////////////////////////////////////////////////////////////////
917	// Get data and instruction requests from processor
918	///////////////////////////////////////////////////////////////////////
919
920	r_iss.getRequests(m_ireq, m_dreq);
921
922	////////////////////////////////////////////////////////////////////////////////////
923	// ICACHE_FSM
924	//
925	// 1/ Coherence operations
926	// They are handled as interrupts generated by the CC_RECEIVE FSM.
927	// - There is a coherence request when r_tgt_icache_req is set.
928	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
929	// - There is a cleanup ack request when r_cleanup_icache_req is set.
930	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
931	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
932	// - For both types of requests, actions associated to the pre-empted state
933	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
934	// or CC_CLACK) to execute the requested coherence operation, and returns
935	// to the pre-empted state.
936	//
937	// 2/ Processor requests
938	// They are taken in IDLE state only. In case of cache miss, or uncacheable
939	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
940	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
941	// flip-flops are reset when the transaction starts.
942	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
943	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
944	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
945	// The availability of the missing cache line is signaled by the response fifo,
946	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
947	// and ICACHE_MISS_DIR_UPDT states.
948	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
949	// to wait the response from the RSP FSM, through the response fifo.
950	// The missing instruction is directly returned to processor in this state.
951	//
952	// 3/ TLB miss
953	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
954	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
955	// register, and goes to the ICACHE_TLB_WAIT state.
956	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
957	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
958	// to signal the completion.
959	//
960	// 4/ XTN requests
961	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
962	// using the r_dcache_xtn_req flip-flop.
963	// The request opcode and the address to be invalidated are transmitted
964	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
965	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
966	// is completed.
967	//
968	// 5/ Error Handling
969	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
970	// in a cache miss or uncacheable read VCI transaction. Nothing is written
971	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
972	////////////////////////////////////////////////////////////////////////////////////////
973
974	// default value for m_irsp
975	m_irsp.valid = false;
976	m_irsp.error = false;
977	m_irsp.instruction = 0;
978
979	switch( r_icache_fsm.read() )
980	{
981	/////////////////
982	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
983	// and coherence requests with a fixed priority:
984	// 1/ Coherence requests => ICACHE_CC_CHECK
985	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
986	// 3/ tlb miss => ICACHE_TLB_WAIT
987	// 4/ cacheable read miss => ICACHE_MISS_SELECT
988	// 5/ uncacheable read miss => ICACHE_UNC_REQ
989	{
990	// coherence interrupt
991	if ( r_cc_receive_icache_req.read() )
992	{
993	r_icache_fsm = ICACHE_CC_CHECK;
994	r_icache_fsm_save = r_icache_fsm.read();
995	break;
996	}
997
998	// XTN requests sent by DCACHE FSM
999	// These request are not executed in this IDLE state, because
1000	// they require access to icache or itlb, that are already accessed
1001	if ( r_dcache_xtn_req.read() )
1002	{
1003	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1004	{
1005	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1006	}
1007	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1008	{
1009	r_icache_flush_count = 0;
1010	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1011	}
1012	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1013	{
1014	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1015	}
1016	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1017	{
1018	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1019	}
1020	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1021	{
1022	if (sizeof(paddr_t) <= 32)
1023	{
1024	assert(r_mmu_word_hi.read() == 0 &&
1025	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1026	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1027	}
1028	else
1029	{
1030	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1031	(paddr_t)r_mmu_word_lo.read();
1032	}
1033	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1034	}
1035	else
1036	{
1037	assert( false and
1038	"undefined XTN request received by ICACHE FSM");
1039	}
1040	break;
1041	} // end if xtn_req
1042
1043	// processor request
1044	if ( m_ireq.valid )
1045	{
1046	bool cacheable;
1047	paddr_t paddr;
1048	bool tlb_hit = false;
1049	pte_info_t tlb_flags;
1050	size_t tlb_way;
1051	size_t tlb_set;
1052	paddr_t tlb_nline;
1053	uint32_t cache_inst = 0;
1054	size_t cache_way;
1055	size_t cache_set;
1056	size_t cache_word;
1057	int cache_state = CACHE_SLOT_STATE_EMPTY;
1058
1059	// We register processor request
1060	r_icache_vaddr_save = m_ireq.addr;
1061
1062	// sytematic itlb access (if activated)
1063	if ( r_mmu_mode.read() & INS_TLB_MASK )
1064	{
1065
1066	#ifdef INSTRUMENTATION
1067	m_cpt_itlb_read++;
1068	#endif
1069	tlb_hit = r_itlb.translate( m_ireq.addr,
1070	&paddr,
1071	&tlb_flags,
1072	&tlb_nline, // unused
1073	&tlb_way, // unused
1074	&tlb_set ); // unused
1075	}
1076	else
1077	{
1078	paddr = (paddr_t)m_ireq.addr;
1079	}
1080
1081	// systematic icache access (if activated)
1082	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1083	{
1084
1085
1086	#ifdef INSTRUMENTATION
1087	m_cpt_icache_data_read++;
1088	m_cpt_icache_dir_read++;
1089	#endif
1090	r_icache.read( paddr,
1091	&cache_inst,
1092	&cache_way,
1093	&cache_set,
1094	&cache_word,
1095	&cache_state );
1096	}
1097
1098	// We compute cacheability and check access rights:
1099	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1100	// and the access rights are defined by the U and X bits in the PTE.
1101	// - If MMU not activated : cacheability is defined by the segment table,
1102	// and there is no access rights checking
1103
1104	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1105	{
1106	// cacheability
1107	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1108	else cacheable = m_cacheability_table[m_ireq.addr];
1109	}
1110	else // itlb activated
1111	{
1112	if ( tlb_hit ) // ITLB hit
1113	{
1114	// cacheability
1115	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1116	else cacheable = tlb_flags.c;
1117
1118	// access rights checking
1119	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1120	{
1121	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1122	r_mmu_ibvar = m_ireq.addr;
1123	m_irsp.valid = true;
1124	m_irsp.error = true;
1125	m_irsp.instruction = 0;
1126	break;
1127	}
1128	else if ( not tlb_flags.x )
1129	{
1130	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1131	r_mmu_ibvar = m_ireq.addr;
1132	m_irsp.valid = true;
1133	m_irsp.error = true;
1134	m_irsp.instruction = 0;
1135	break;
1136	}
1137	}
1138	else // ITLB miss
1139	{
1140
1141	#ifdef INSTRUMENTATION
1142	m_cpt_itlb_miss++;
1143	#endif
1144	r_icache_fsm = ICACHE_TLB_WAIT;
1145	r_icache_tlb_miss_req = true;
1146	break;
1147	}
1148	} // end if itlb activated
1149
1150	// physical address registration
1151	r_icache_vci_paddr = paddr;
1152
1153	// Finally, we send the response to processor, and compute next state
1154	if ( cacheable )
1155	{
1156	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1157	{
1158
1159	#ifdef INSTRUMENTATION
1160	m_cpt_icache_miss++;
1161	#endif
1162	// we request a VCI transaction
1163	r_icache_fsm = ICACHE_MISS_SELECT;
1164	r_icache_miss_req = true;
1165	}
1166	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1167	{
1168	// stalled until cleanup is acknowledged
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	else // cache hit
1172	{
1173
1174	#ifdef INSTRUMENTATION
1175	m_cpt_ins_read++;
1176	#endif
1177	// return instruction to processor
1178	m_irsp.valid = true;
1179	m_irsp.instruction = cache_inst;
1180	r_icache_fsm = ICACHE_IDLE;
1181	}
1182	}
1183	else // non cacheable read
1184	{
1185	r_icache_unc_req = true;
1186	r_icache_fsm = ICACHE_UNC_WAIT;
1187	}
1188	} // end if m_ireq.valid
1189	break;
1190	}
1191	/////////////////////
1192	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1193	// the itlb is udated by the DCACHE FSM, as well as the
1194	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1195	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1196	// reset the r_icache_tlb_miss_req flip-flop
1197	// external coherence request are accepted in this state.
1198	{
1199	// coherence interrupt
1200	if ( r_cc_receive_icache_req.read() )
1201	{
1202	r_icache_fsm = ICACHE_CC_CHECK;
1203	r_icache_fsm_save = r_icache_fsm.read();
1204	break;
1205	}
1206
1207	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1208
1209	// DCACHE FSM signals response by reseting the request flip-flop
1210	if ( not r_icache_tlb_miss_req.read() )
1211	{
1212	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1213	{
1214	r_icache_tlb_rsp_error = false;
1215	m_irsp.error = true;
1216	m_irsp.valid = true;
1217	r_icache_fsm = ICACHE_IDLE;
1218	}
1219	else // tlb updated : return to IDLE state
1220	{
1221	r_icache_fsm = ICACHE_IDLE;
1222	}
1223	}
1224	break;
1225	}
1226	//////////////////////////
1227	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1228	{
1229	r_itlb.flush();
1230	r_dcache_xtn_req = false;
1231	r_icache_fsm = ICACHE_IDLE;
1232	break;
1233	}
1234	////////////////////////////
1235	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1236	// r_icache_flush_count as a slot counter,
1237	// looping in this state until all slots are visited.
1238	// It can require two cycles per slot:
1239	// We test here the slot state, and make the actual inval
1240	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1241	// A cleanup request is generated for each valid line
1242	{
1243	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1244	{
1245	int state;
1246	uint32_t tag;
1247	size_t way = r_icache_flush_count.read()/m_icache_sets;
1248	size_t set = r_icache_flush_count.read()%m_icache_sets;
1249
1250	#ifdef INSTRUMENTATION
1251	m_cpt_icache_dir_read++;
1252	#endif
1253	r_icache.read_dir( way,
1254	set,
1255	&tag,
1256	&state );
1257
1258	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1259	{
1260	// request cleanup
1261	r_icache_cc_send_req = true;
1262	r_icache_cc_send_nline = tag * m_icache_sets;
1263	r_icache_cc_send_way = way;
1264	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1265
1266	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1267	r_icache_miss_way = way;
1268	r_icache_miss_set = set;
1269	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1270	}
1271	else if ( r_icache_flush_count.read() ==
1272	(m_icache_sets*m_icache_ways - 1) ) // last slot
1273	{
1274	r_dcache_xtn_req = false;
1275	m_drsp.valid = true;
1276	r_icache_fsm = ICACHE_IDLE;
1277	}
1278
1279	// saturation counter, to have the same last slot condition
1280	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1281	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1282	{
1283	r_icache_flush_count = r_icache_flush_count.read() + 1;
1284	}
1285	}
1286	break;
1287	}
1288	///////////////////////////////
1289	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1290	{
1291	size_t way = r_icache_miss_way.read();
1292	size_t set = r_icache_miss_set.read();
1293
1294	#ifdef INSTRUMENTATION
1295	m_cpt_icache_dir_write++;
1296	#endif
1297
1298	r_icache.write_dir( 0,
1299	way,
1300	set,
1301	CACHE_SLOT_STATE_ZOMBI );
1302
1303	if ( r_icache_flush_count.read() ==
1304	(m_icache_sets*m_icache_ways - 1) ) // last slot
1305	{
1306	r_dcache_xtn_req = false;
1307	m_drsp.valid = true;
1308	r_icache_fsm = ICACHE_IDLE;
1309	}
1310	else
1311	{
1312	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1313	}
1314	break;
1315	}
1316
1317	//////////////////////////
1318	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1319	// stored in the r_dcache_save_wdata register
1320	{
1321	r_itlb.inval(r_dcache_save_wdata.read());
1322	r_dcache_xtn_req = false;
1323	r_icache_fsm = ICACHE_IDLE;
1324	break;
1325	}
1326	///////////////////////////////
1327	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1328	// requires 3 cycles (in case of hit on itlb and icache).
1329	// In this state, access TLB to translate virtual address
1330	// stored in the r_dcache_save_wdata register.
1331	{
1332	paddr_t paddr;
1333	bool hit;
1334
1335	// read physical address in TLB when MMU activated
1336	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1337	{
1338
1339	#ifdef INSTRUMENTATION
1340	m_cpt_itlb_read++;
1341	#endif
1342	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1343	&paddr);
1344	}
1345	else // itlb not activated
1346	{
1347	paddr = (paddr_t)r_dcache_save_wdata.read();
1348	hit = true;
1349	}
1350
1351	if ( hit ) // continue the selective inval process
1352	{
1353	r_icache_vci_paddr = paddr;
1354	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1355	}
1356	else // miss : send a request to DCACHE FSM
1357	{
1358
1359	#ifdef INSTRUMENTATION
1360	m_cpt_itlb_miss++;
1361	#endif
1362	r_icache_tlb_miss_req = true;
1363	r_icache_vaddr_save = r_dcache_save_wdata.read();
1364	r_icache_fsm = ICACHE_TLB_WAIT;
1365	}
1366	break;
1367	}
1368	///////////////////////////////
1369	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1370	// require 2 cycles. In this state, we read directory
1371	// with address stored in r_icache_vci_paddr register.
1372	{
1373	int state;
1374	size_t way;
1375	size_t set;
1376	size_t word;
1377
1378	#ifdef INSTRUMENTATION
1379	m_cpt_icache_dir_read++;
1380	#endif
1381	r_icache.read_dir(r_icache_vci_paddr.read(),
1382	&state,
1383	&way,
1384	&set,
1385	&word);
1386
1387	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1388	{
1389	r_icache_miss_way = way;
1390	r_icache_miss_set = set;
1391	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1392	}
1393	else // miss : acknowlege the XTN request and return
1394	{
1395	r_dcache_xtn_req = false;
1396	r_icache_fsm = ICACHE_IDLE;
1397	}
1398	break;
1399	}
1400	///////////////////////////////
1401	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1402	{
1403	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1404	{
1405
1406	#ifdef INSTRUMENTATION
1407	m_cpt_icache_dir_write++;
1408	#endif
1409	r_icache.write_dir( 0,
1410	r_icache_miss_way.read(),
1411	r_icache_miss_set.read(),
1412	CACHE_SLOT_STATE_ZOMBI );
1413
1414	// request cleanup
1415	r_icache_cc_send_req = true;
1416	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1417	r_icache_cc_send_way = r_icache_miss_way.read();
1418	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1419
1420	// acknowledge the XTN request and return
1421	r_dcache_xtn_req = false;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424	break;
1425	}
1426	////////////////////////
1427	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1428	// if previous cleanup has been sent.
1429	// Waiting in this state if no slot available.
1430	// Set the r_icache_cleanup_req flip-flop
1431	// and the r_icache_miss_clack flip-flop,
1432	// when a cleanup is required
1433	{
1434	if (m_ireq.valid) m_cost_ins_miss_frz++;
1435
1436	// coherence interrupt
1437	if ( r_cc_receive_icache_req.read() )
1438	{
1439	r_icache_fsm = ICACHE_CC_CHECK;
1440	r_icache_fsm_save = r_icache_fsm.read();
1441	break;
1442	}
1443
1444	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1445	{
1446	bool found;
1447	bool cleanup;
1448	size_t way;
1449	size_t set;
1450	paddr_t victim;
1451
1452	#ifdef INSTRUMENTATION
1453	m_cpt_icache_dir_read++;
1454	#endif
1455	r_icache.read_select(r_icache_vci_paddr.read(),
1456	&victim,
1457	&way,
1458	&set,
1459	&found,
1460	&cleanup );
1461	if ( found )
1462	{
1463	r_icache_miss_way = way;
1464	r_icache_miss_set = set;
1465
1466	if ( cleanup )
1467	{
1468	r_icache_fsm = ICACHE_MISS_CLEAN;
1469	r_icache_miss_clack = true;
1470	// request cleanup
1471	r_icache_cc_send_req = true;
1472	r_icache_cc_send_nline = victim;
1473	r_icache_cc_send_way = way;
1474	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1475	}
1476	else
1477	{
1478	r_icache_fsm = ICACHE_MISS_WAIT;
1479	}
1480
1481	#if DEBUG_ICACHE
1482	if ( m_debug_dcache_fsm )
1483	{
1484	std::cout << " <PROC " << name()
1485	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1486	<< " / WAY = " << way
1487	<< " / SET = " << set;
1488	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1489	else std::cout << std::endl;
1490	}
1491	#endif
1492	}
1493	}
1494	break;
1495	}
1496	///////////////////////
1497	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1498	{
1499	if (m_ireq.valid) m_cost_ins_miss_frz++;
1500
1501	// coherence interrupt
1502	if ( r_cc_receive_icache_req.read() )
1503	{
1504	r_icache_fsm = ICACHE_CC_CHECK;
1505	r_icache_fsm_save = r_icache_fsm.read();
1506	break;
1507	}
1508
1509	#ifdef INSTRUMENTATION
1510	m_cpt_icache_dir_write++;
1511	#endif
1512	r_icache.write_dir( 0,
1513	r_icache_miss_way.read(),
1514	r_icache_miss_set.read(),
1515	CACHE_SLOT_STATE_ZOMBI);
1516	#if DEBUG_ICACHE
1517	if ( m_debug_dcache_fsm )
1518	{
1519	std::cout << " <PROC " << name()
1520	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1521	<< " / WAY = " << r_icache_miss_way.read()
1522	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1523	}
1524	#endif
1525
1526	r_icache_fsm = ICACHE_MISS_WAIT;
1527	break;
1528	}
1529	//////////////////////
1530	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1531	{
1532	if (m_ireq.valid) m_cost_ins_miss_frz++;
1533
1534	// coherence interrupt
1535	if ( r_cc_receive_icache_req.read() )
1536	{
1537	r_icache_fsm = ICACHE_CC_CHECK;
1538	r_icache_fsm_save = r_icache_fsm.read();
1539	break;
1540	}
1541
1542	if ( r_vci_rsp_ins_error.read() ) // bus error
1543	{
1544	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1545	r_mmu_ibvar = r_icache_vaddr_save.read();
1546	m_irsp.valid = true;
1547	m_irsp.error = true;
1548	r_vci_rsp_ins_error = false;
1549	r_icache_fsm = ICACHE_IDLE;
1550	}
1551	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1552	{
1553	r_icache_miss_word = 0;
1554	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1555	}
1556	break;
1557	}
1558	///////////////////////////
1559	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1560	{
1561	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1562
1563	// coherence interrupt
1564	if ( r_cc_receive_icache_req.read() )
1565	{
1566	r_icache_fsm = ICACHE_CC_CHECK;
1567	r_icache_fsm_save = r_icache_fsm.read();
1568	break;
1569	}
1570
1571	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1572	{
1573
1574	#ifdef INSTRUMENTATION
1575	m_cpt_icache_data_write++;
1576	#endif
1577	r_icache.write( r_icache_miss_way.read(),
1578	r_icache_miss_set.read(),
1579	r_icache_miss_word.read(),
1580	r_vci_rsp_fifo_icache.read() );
1581	#if DEBUG_ICACHE
1582	if ( m_debug_icache_fsm )
1583	{
1584	std::cout << " <PROC " << name()
1585	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1586	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1587	<< " WAY = " << r_icache_miss_way.read()
1588	<< " SET = " << r_icache_miss_set.read()
1589	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1590	}
1591	#endif
1592	vci_rsp_fifo_icache_get = true;
1593	r_icache_miss_word = r_icache_miss_word.read() + 1;
1594
1595	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1596	{
1597	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1598	}
1599	}
1600	break;
1601	}
1602	//////////////////////////
1603	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1604	// and the cleanup ack has not been received,
1605	// as indicated by r_icache_miss_clack.
1606	// - If no matching coherence request (r_icache_miss_inval)
1607	// switch directory slot to VALID state.
1608	// - If matching coherence request, switch directory slot
1609	// to ZOMBI state, and send a cleanup request.
1610	{
1611	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1612
1613	// coherence interrupt
1614	if ( r_cc_receive_icache_req.read() )
1615	{
1616	r_icache_fsm = ICACHE_CC_CHECK;
1617	r_icache_fsm_save = r_icache_fsm.read();
1618	break;
1619	}
1620
1621	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1622	{
1623	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1624	{
1625	if ( not r_icache_cc_send_req.read() )
1626	{
1627	r_icache_miss_inval = false;
1628	// request cleanup
1629	r_icache_cc_send_req = true;
1630	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1631	r_icache_cc_send_way = r_icache_miss_way.read();
1632	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1633
1634	#ifdef INSTRUMENTATION
1635	m_cpt_icache_dir_write++;
1636	#endif
1637	r_icache.write_dir( r_icache_vci_paddr.read(),
1638	r_icache_miss_way.read(),
1639	r_icache_miss_set.read(),
1640	CACHE_SLOT_STATE_ZOMBI );
1641	#if DEBUG_ICACHE
1642	if ( m_debug_icache_fsm )
1643	{
1644	std::cout << " <PROC " << name()
1645	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1646	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1647	<< " WAY = " << std::dec << r_icache_miss_way.read()
1648	<< " SET = " << r_icache_miss_set.read() << std::endl;
1649	}
1650	#endif
1651	}
1652	}
1653	else // Switch slot to VALID state
1654	{
1655
1656	#ifdef INSTRUMENTATION
1657	m_cpt_icache_dir_write++;
1658	#endif
1659	r_icache.write_dir( r_icache_vci_paddr.read(),
1660	r_icache_miss_way.read(),
1661	r_icache_miss_set.read(),
1662	CACHE_SLOT_STATE_VALID );
1663	#if DEBUG_ICACHE
1664	if ( m_debug_icache_fsm )
1665	{
1666	std::cout << " <PROC " << name()
1667	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1668	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1669	<< " WAY = " << std::dec << r_icache_miss_way.read()
1670	<< " SET = " << r_icache_miss_set.read() << std::endl;
1671	}
1672	#endif
1673	}
1674
1675	r_icache_fsm = ICACHE_IDLE;
1676	}
1677	break;
1678	}
1679	////////////////////
1680	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1681	{
1682	// coherence interrupt
1683	if ( r_cc_receive_icache_req.read() )
1684	{
1685	r_icache_fsm = ICACHE_CC_CHECK;
1686	r_icache_fsm_save = r_icache_fsm.read();
1687	break;
1688	}
1689
1690	if ( r_vci_rsp_ins_error.read() ) // bus error
1691	{
1692	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1693	r_mmu_ibvar = m_ireq.addr;
1694	r_vci_rsp_ins_error = false;
1695	m_irsp.valid = true;
1696	m_irsp.error = true;
1697	r_icache_fsm = ICACHE_IDLE;
1698	}
1699	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1700	{
1701	vci_rsp_fifo_icache_get = true;
1702	r_icache_fsm = ICACHE_IDLE;
1703	if ( m_ireq.valid and
1704	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1705	{
1706	m_irsp.valid = true;
1707	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1708	}
1709	}
1710	break;
1711	}
1712	/////////////////////
1713	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1714	// handling coherence requests.
1715	// if there is a matching pending miss, it is
1716	// signaled in the r_icache_miss_inval flip-flop.
1717	// The return state is defined in r_icache_fsm_save.
1718	{
1719	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1720	paddr_t mask = ~((m_icache_words<<2)-1);
1721
1722	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1723	// We switch the directory slot to EMPTY state
1724	// and reset r_icache_miss_clack if the cleanup ack
1725	// is matching a pending miss
1726	{
1727
1728	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1729
1730	#ifdef INSTRUMENTATION
1731	m_cpt_icache_dir_write++;
1732	#endif
1733	r_icache.write_dir( 0,
1734	r_cc_receive_icache_way.read(),
1735	r_cc_receive_icache_set.read(),
1736	CACHE_SLOT_STATE_EMPTY);
1737
1738	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1739	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1740	r_icache_miss_clack = false;
1741
1742	r_icache_fsm = r_icache_fsm_save.read() ;
1743	r_cc_receive_icache_req = false;
1744
1745	#if DEBUG_ICACHE
1746	if ( m_debug_icache_fsm )
1747	{
1748	std::cout << " <PROC " << name()
1749	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1750	<< " set = " << r_cc_receive_icache_set.read()
1751	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1752	}
1753	#endif
1754	}
1755	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1756	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1757	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1758	{
1759	// signaling the matching
1760	r_icache_miss_inval = true;
1761
1762	// in case of update, go to CC_UPDT
1763	// JUST TO POP THE FIFO
1764	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1765	{
1766	r_icache_fsm = ICACHE_CC_UPDT;
1767	r_icache_cc_word = r_cc_receive_word_idx.read();
1768	// just pop the fifo , don't write in icache
1769	r_icache_cc_need_write = false;
1770	}
1771	// the request is dealt with
1772	else
1773	{
1774	r_cc_receive_icache_req = false;
1775	r_icache_fsm = r_icache_fsm_save.read();
1776	}
1777	#if DEBUG_ICACHE
1778	if ( m_debug_icache_fsm )
1779	{
1780	std::cout << " <PROC " << name()
1781	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1782	<< " PADDR = " << std::hex << paddr << std::endl;
1783	}
1784	#endif
1785	}
1786	else // no match
1787	{
1788	int state;
1789	size_t way;
1790	size_t set;
1791	size_t word;
1792
1793	#ifdef INSTRUMENTATION
1794	m_cpt_icache_dir_read++;
1795	#endif
1796	r_icache.read_dir(paddr,
1797	&state,
1798	&way,
1799	&set,
1800	&word);
1801
1802	r_icache_cc_way = way;
1803	r_icache_cc_set = set;
1804
1805	if ( state == CACHE_SLOT_STATE_VALID) // hit
1806	{
1807	// need to update the cache state
1808	r_icache_cc_need_write = true;
1809	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1810	{
1811	r_icache_fsm = ICACHE_CC_UPDT;
1812	r_icache_cc_word = r_cc_receive_word_idx.read();
1813	}
1814	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1815	{
1816	r_icache_fsm = ICACHE_CC_INVAL;
1817	}
1818	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1819	{
1820	r_icache_fsm = ICACHE_CC_BROADCAST;
1821	}
1822	}
1823	else // miss
1824	{
1825	// multicast acknowledgement required in case of update
1826	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1827	{
1828	r_icache_fsm = ICACHE_CC_UPDT;
1829	r_icache_cc_word = r_cc_receive_word_idx.read();
1830	// just pop the fifo , don't write in icache
1831	r_icache_cc_need_write = false;
1832	}
1833	else // No response needed
1834	{
1835	r_cc_receive_icache_req = false;
1836	r_icache_fsm = r_icache_fsm_save.read();
1837	}
1838	}
1839	}
1840	break;
1841	}
1842	/////////////////////
1843	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1844	{
1845
1846	#if DEBUG_ICACHE
1847	if ( m_debug_icache_fsm )
1848	{
1849	std::cout << " <PROC " << name()
1850	<< " ICACHE_CC_INVAL> slot returns to empty state"
1851	<< " set = " << r_icache_cc_set.read()
1852	<< " / way = " << r_icache_cc_way.read() << std::endl;
1853	}
1854	#endif
1855
1856	#ifdef INSTRUMENTATION
1857	m_cpt_icache_dir_read++;
1858	#endif
1859	if (r_icache_cc_need_write.read())
1860	{
1861	r_icache.write_dir( 0,
1862	r_icache_cc_way.read(),
1863	r_icache_cc_set.read(),
1864	CACHE_SLOT_STATE_EMPTY );
1865	// no need to write in the cache anymore
1866	r_icache_cc_need_write = false;
1867	}
1868
1869	// multicast acknowledgement
1870	// send a request to cc_send_fsm
1871	if(not r_icache_cc_send_req.read()) // cc_send is available
1872	{
1873	// coherence request completed
1874	r_cc_receive_icache_req = false;
1875	// request multicast acknowledgement
1876	r_icache_cc_send_req = true;
1877	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1878	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1879
1880	r_icache_fsm = r_icache_fsm_save.read();
1881	}
1882	//else wait for previous cc_send request to be sent
1883	break;
1884	}
1885	////////////////////
1886	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1887	{
1888
1889	#if DEBUG_ICACHE
1890	if ( m_debug_icache_fsm )
1891	{
1892	std::cout << " <PROC " << name()
1893	<< " ICACHE_CC_UPDT> Write one word "
1894	<< " set = " << r_icache_cc_set.read()
1895	<< " / way = " << r_icache_cc_way.read()
1896	<< " / word = " << r_icache_cc_word.read() << std::endl;
1897	}
1898	#endif
1899
1900	#ifdef INSTRUMENTATION
1901	m_cpt_icache_data_write++;
1902	#endif
1903	size_t word = r_icache_cc_word.read();
1904	size_t way = r_icache_cc_way.read();
1905	size_t set = r_icache_cc_set.read();
1906
1907	if (r_cc_receive_updt_fifo_be.rok())
1908	{
1909	if (r_icache_cc_need_write.read())
1910	{
1911	r_icache.write( way,
1912	set,
1913	word,
1914	r_cc_receive_updt_fifo_data.read(),
1915	r_cc_receive_updt_fifo_be.read() );
1916
1917	r_icache_cc_word = word+1;
1918	}
1919	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1920	{
1921	// no need to write in the cache anymore
1922	r_icache_cc_need_write = false;
1923	// wait to send a request to cc_send_fsm
1924	if(not r_icache_cc_send_req.read()) // cc_send is available
1925	{
1926	//consume last flit
1927	cc_receive_updt_fifo_get = true;
1928	// coherence request completed
1929	r_cc_receive_icache_req = false;
1930	// request multicast acknowledgement
1931	r_icache_cc_send_req = true;
1932	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1933	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1934
1935	r_icache_fsm = r_icache_fsm_save.read();
1936	}
1937	}
1938	else
1939	{
1940	//consume fifo if not eop
1941	cc_receive_updt_fifo_get = true;
1942	}
1943	}
1944	break;
1945	}
1946	/////////////////////////
1947	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1948	// and request a cleanup
1949	{
1950
1951	#if DEBUG_ICACHE
1952	if ( m_debug_icache_fsm )
1953	{
1954	std::cout << " <PROC " << name()
1955	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1956	<< " set = " << r_icache_cc_set.read()
1957	<< " / way = " << r_icache_cc_way.read() << std::endl;
1958	}
1959	#endif
1960
1961	#ifdef INSTRUMENTATION
1962	m_cpt_icache_dir_write++;
1963	#endif
1964	if (r_icache_cc_need_write.read())
1965	{
1966	r_icache.write_dir( 0,
1967	r_icache_cc_way.read(),
1968	r_icache_cc_set.read(),
1969	CACHE_SLOT_STATE_ZOMBI );
1970	// no need to write in the cache anymore
1971	r_icache_cc_need_write = false;
1972	}
1973
1974	// cleanup
1975	// send a request to cc_send_fsm
1976	if(not r_icache_cc_send_req.read()) // cc_send is available
1977	{
1978	// coherence request completed
1979	r_cc_receive_icache_req = false;
1980	// request cleanup
1981	r_icache_cc_send_req = true;
1982	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1983	r_icache_cc_send_way = r_icache_cc_way.read();
1984	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1985
1986	r_icache_fsm = r_icache_fsm_save.read();
1987	}
1988	//else wait for previous cc_send request to be sent
1989	break;
1990	}
1991	} // end switch r_icache_fsm
1992
1993	////////////////////////////////////////////////////////////////////////////////////
1994	// DCACHE FSM
1995	//
1996	// 1/ Coherence operations
1997	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1998	// - There is a coherence request when r_tgt_dcache_req is set.
1999	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2000	// and SC_WAIT states.
2001	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2002	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2003	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2004	// - For both types of requests, actions associated to the pre-empted state
2005	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2006	// or CC_CLACK) to execute the requested coherence operation, and returns
2007	// to the pre-empted state.
2008	//
2009	// 2/ TLB miss
2010	// The page tables are generally cacheable.
2011	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2012	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2013	// this sub-fsm implement the table-walk...
2014	//
2015	// 3/ processor requests
2016	// Processor requests are taken in IDLE state only.
2017	// The IDLE state implements a two stages pipe-line to handle write bursts:
2018	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2019	// - The registration in wbuf and the dcache update is done in stage P1
2020	// (if the processor request is a write).
2021	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2022	// the operations that must be done in P1 stage, and the access type
2023	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2024	// READ requests are delayed if a cache update is requested.
2025	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2026	// that is done (before handling the processor request) by a dedicated sub-fsm.
2027	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2028	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2029	//
2030	// 4/ Atomic instructions LL/SC
2031	// The LL/SC address are non cacheable (systematic access to memory).
2032	// The llsc buffer contains a registration for an active LL/SC operation
2033	// (with an address, a registration key, an aging counter and a valid bit).
2034	// - LL requests from the processor are transmitted as a one flit VCI command
2035	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2036	// be 8 as the response is 2 flits long (data and registration key)
2037	// - SC requests from the processor are systematically transmitted to the
2038	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2039	// as PKTID value). The first flit contains the registration key, the second
2040	// flit contains the data to write in case of success.
2041	// The cache is not updated, as this is done in case of success by the
2042	// coherence transaction.
2043	//
2044	// 5/ Non cacheable access:
2045	// This component implement a strong order between non cacheable access
2046	// (read or write) : A new non cacheable VCI transaction starts only when
2047	// the previous non cacheable transaction is completed. Both cacheable and
2048	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2049	// a non cacheable write transaction posted in the write buffer by setting the
2050	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2051	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2052	// pending non cacheable write transaction completes).
2053	//
2054	// 6/ Error handling:
2055	// When the MMU is not activated, Read Bus Errors are synchronous events,
2056	// but Write Bus Errors are asynchronous events (processor is not frozen).
2057	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2058	// r_vci_rsp_data_error flip-flop, without writing any data in the
2059	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2060	// by the DCACHE FSM.
2061	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2062	// the asynchronous error using the setWriteBerr() method.
2063	// When the MMU is activated bus error are rare events, as the MMU
2064	// checks the physical address before the VCI transaction starts.
2065	////////////////////////////////////////////////////////////////////////////////////////
2066
2067	// default value for m_drsp
2068	m_drsp.valid = false;
2069	m_drsp.error = false;
2070	m_drsp.rdata = 0;
2071
2072	switch ( r_dcache_fsm.read() )
2073	{
2074	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2075	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2076	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2077	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2078	// 4) XTN request (processor) => DCACHE_XTN_*
2079	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2080	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2081	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2082	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2083	// 9) LL access (processor) => DCACHE_LL_WAIT
2084	// 10) SC access (processor) => DCACHE_SC_WAIT
2085	//
2086	// There is a fixed priority to handle requests to DCACHE:
2087	// 1/ the ITLB/DTLB invalidate requests
2088	// 2/ the coherence requests,
2089	// 3/ the processor requests (including DTLB miss),
2090	// 4/ the ITLB miss requests,
2091	// The address space processor request are handled as follows:
2092	// - WRITE request is blocked if the Dirty bit mus be set.
2093	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2094	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2095	// - READ request generate a simultaneouss access to DCACHE.DATA
2096	// and DCACHE.DIR, but is delayed if DCACHE update required.
2097	//
2098	// There is 4 configurations defining the access type to
2099	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2100	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2101	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2102	// 0 / 0 / NOP / NOP / NOP /
2103	// 0 / 1 / NOP / NOP / WRITE /
2104	// 1 / 0 / READ / READ / NOP /
2105	// 1 / 1 / READ / READ / WRITE /
2106	// Those two registers are set at each cycle from the 3 signals
2107	// updt_request, wbuf_request, wbuf_write_miss.
2108	{
2109	paddr_t paddr; // physical address
2110	pte_info_t tlb_flags;
2111	size_t tlb_way;
2112	size_t tlb_set;
2113	paddr_t tlb_nline;
2114	size_t cache_way;
2115	size_t cache_set;
2116	size_t cache_word;
2117	uint32_t cache_rdata = 0;
2118	bool tlb_hit = false;
2119	int cache_state = CACHE_SLOT_STATE_EMPTY;
2120
2121	bool tlb_inval_required = false; // request TLB inval after cache update
2122	bool wbuf_write_miss = false; // miss a WBUF write request
2123	bool updt_request = false; // request DCACHE update in P1 stage
2124	bool wbuf_request = false; // request WBUF write in P1 stage
2125
2126	// physical address computation : systematic DTLB access if activated)
2127	if ( m_dreq.valid )
2128	{
2129	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2130	{
2131	tlb_hit = r_dtlb.translate( m_dreq.addr,
2132	&paddr,
2133	&tlb_flags,
2134	&tlb_nline,
2135	&tlb_way,
2136	&tlb_set );
2137	#ifdef INSTRUMENTATION
2138	m_cpt_dtlb_read++;
2139	#endif
2140	}
2141	else // identity mapping
2142	{
2143	paddr = (paddr_t)m_dreq.addr;
2144	}
2145	} // end physical address computation
2146
2147	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2148	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2149	{
2150	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2151	{
2152	r_dcache.read_dir( paddr,
2153	&cache_state,
2154	&cache_way,
2155	&cache_set,
2156	&cache_word );
2157
2158	r_dcache.write( r_dcache_save_cache_way.read(),
2159	r_dcache_save_cache_set.read(),
2160	r_dcache_save_cache_word.read(),
2161	r_dcache_save_wdata.read(),
2162	r_dcache_save_be.read() );
2163	#ifdef INSTRUMENTATION
2164	m_cpt_dcache_dir_read++;
2165	m_cpt_dcache_data_write++;
2166	#endif
2167	}
2168	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2169	{
2170	r_dcache.read( paddr,
2171	&cache_rdata,
2172	&cache_way,
2173	&cache_set,
2174	&cache_word,
2175	&cache_state );
2176	#ifdef INSTRUMENTATION
2177	m_cpt_dcache_dir_read++;
2178	m_cpt_dcache_data_read++;
2179	#endif
2180	}
2181	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2182	{
2183	r_dcache.write( r_dcache_save_cache_way.read(),
2184	r_dcache_save_cache_set.read(),
2185	r_dcache_save_cache_word.read(),
2186	r_dcache_save_wdata.read(),
2187	r_dcache_save_be.read() );
2188	#ifdef INSTRUMENTATION
2189	m_cpt_dcache_data_write++;
2190	#endif
2191	}
2192	} // end dcache access
2193
2194	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2195	if ( r_dcache_updt_req.read() )
2196	{
2197	size_t way = r_dcache_save_cache_way.read();
2198	size_t set = r_dcache_save_cache_set.read();
2199
2200	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2201	{
2202	tlb_inval_required = true;
2203	r_dcache_tlb_inval_set = 0;
2204	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2205	(uint32_log2(m_dcache_words<<2));
2206	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2207	}
2208	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2209	{
2210	r_itlb.reset();
2211	r_dtlb.reset();
2212	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2213	}
2214
2215	#if DEBUG_DCACHE
2216	if ( m_debug_dcache_fsm )
2217	{
2218	std::cout << " <PROC " << name()
2219	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2220	<< " / WAY = " << r_dcache_save_cache_way.read()
2221	<< " / SET = " << r_dcache_save_cache_set.read()
2222	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2223	<< " / DATA = " << r_dcache_save_wdata.read()
2224	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2225	}
2226	#endif
2227	} // end test TLB inval
2228
2229	// Try WBUF update in P1 stage
2230	// Miss if the write request is non cacheable, and there is a pending
2231	// non cacheable write, or if the write buffer is full.
2232	if ( r_dcache_wbuf_req.read() )
2233	{
2234	// miss if write not cacheable, and previous non cacheable write registered
2235	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2236	{
2237	wbuf_write_miss = true;
2238	}
2239	else // try a registration into write buffer
2240	{
2241	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2242	r_dcache_save_be.read(),
2243	r_dcache_save_wdata.read(),
2244	r_dcache_save_cacheable.read() );
2245	#ifdef INSTRUMENTATION
2246	m_cpt_wbuf_write++;
2247	#endif
2248	if ( not wok ) // miss if write buffer full
2249	{
2250	wbuf_write_miss = true;
2251	}
2252	else // update the write_buffer state extension
2253	{
2254	if(not r_dcache_pending_unc_write.read())
2255	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2256	}
2257	}
2258	} // end WBUF update
2259
2260	// Computing the response to processor,
2261	// and the next value for r_dcache_fsm
2262
2263	// itlb/dtlb invalidation self-request
2264	if ( tlb_inval_required )
2265	{
2266	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2267	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2268	}
2269
2270	// coherence request (from CC_RECEIVE FSM)
2271	else if ( r_cc_receive_dcache_req.read() )
2272	{
2273	r_dcache_fsm = DCACHE_CC_CHECK;
2274	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2275	}
2276
2277	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2278	// we don't take the processor request, and registers
2279	// are frozen in case of wbuf_write_miss
2280	else if ( m_dreq.valid and not wbuf_write_miss )
2281	{
2282	// register processor request and DCACHE response
2283	r_dcache_save_vaddr = m_dreq.addr;
2284	r_dcache_save_be = m_dreq.be;
2285	r_dcache_save_wdata = m_dreq.wdata;
2286	r_dcache_save_paddr = paddr;
2287	r_dcache_save_cache_way = cache_way;
2288	r_dcache_save_cache_set = cache_set;
2289	r_dcache_save_cache_word = cache_word;
2290
2291	// READ XTN requests from processor
2292	// They are executed in this DCACHE_IDLE state.
2293	// The processor must not be in user mode
2294	if (m_dreq.type == iss_t::XTN_READ)
2295	{
2296	int xtn_opcode = (int)m_dreq.addr/4;
2297
2298	// checking processor mode:
2299	if (m_dreq.mode == iss_t::MODE_USER)
2300	{
2301	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2302	r_mmu_dbvar = m_dreq.addr;
2303	m_drsp.valid = true;
2304	m_drsp.error = true;
2305	m_drsp.rdata = 0;
2306	r_dcache_fsm = DCACHE_IDLE;
2307	}
2308	else
2309	{
2310	switch( xtn_opcode )
2311	{
2312	case iss_t::XTN_INS_ERROR_TYPE:
2313	m_drsp.rdata = r_mmu_ietr.read();
2314	m_drsp.valid = true;
2315	m_drsp.error = false;
2316	break;
2317
2318	case iss_t::XTN_DATA_ERROR_TYPE:
2319	m_drsp.rdata = r_mmu_detr.read();
2320	m_drsp.valid = true;
2321	m_drsp.error = false;
2322	break;
2323
2324	case iss_t::XTN_INS_BAD_VADDR:
2325	m_drsp.rdata = r_mmu_ibvar.read();
2326	m_drsp.valid = true;
2327	m_drsp.error = false;
2328	break;
2329
2330	case iss_t::XTN_DATA_BAD_VADDR:
2331	m_drsp.rdata = r_mmu_dbvar.read();
2332	m_drsp.valid = true;
2333	m_drsp.error = false;
2334	break;
2335
2336	case iss_t::XTN_PTPR:
2337	m_drsp.rdata = r_mmu_ptpr.read();
2338	m_drsp.valid = true;
2339	m_drsp.error = false;
2340	break;
2341
2342	case iss_t::XTN_TLB_MODE:
2343	m_drsp.rdata = r_mmu_mode.read();
2344	m_drsp.valid = true;
2345	m_drsp.error = false;
2346	break;
2347
2348	case iss_t::XTN_MMU_PARAMS:
2349	m_drsp.rdata = r_mmu_params;
2350	m_drsp.valid = true;
2351	m_drsp.error = false;
2352	break;
2353
2354	case iss_t::XTN_MMU_RELEASE:
2355	m_drsp.rdata = r_mmu_release;
2356	m_drsp.valid = true;
2357	m_drsp.error = false;
2358	break;
2359
2360	case iss_t::XTN_MMU_WORD_LO:
2361	m_drsp.rdata = r_mmu_word_lo.read();
2362	m_drsp.valid = true;
2363	m_drsp.error = false;
2364	break;
2365
2366	case iss_t::XTN_MMU_WORD_HI:
2367	m_drsp.rdata = r_mmu_word_hi.read();
2368	m_drsp.valid = true;
2369	m_drsp.error = false;
2370	break;
2371
2372	default:
2373	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2374	r_mmu_dbvar = m_dreq.addr;
2375	m_drsp.valid = true;
2376	m_drsp.error = true;
2377	m_drsp.rdata = 0;
2378	break;
2379	} // end switch xtn_opcode
2380	} // end else
2381	} // end if XTN_READ
2382
2383	// Handling WRITE XTN requests from processor.
2384	// They are not executed in this DCACHE_IDLE state
2385	// if they require access to the caches or the TLBs
2386	// that are already accessed.
2387	// Caches can be invalidated or flushed in user mode,
2388	// and the sync instruction can be executed in user mode
2389	else if (m_dreq.type == iss_t::XTN_WRITE)
2390	{
2391	int xtn_opcode = (int)m_dreq.addr/4;
2392	r_dcache_xtn_opcode = xtn_opcode;
2393
2394	// checking processor mode:
2395	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2396	(xtn_opcode != iss_t:: XTN_SYNC) &&
2397	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2398	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2399	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2400	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2401	{
2402	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2403	r_mmu_dbvar = m_dreq.addr;
2404	m_drsp.valid = true;
2405	m_drsp.error = true;
2406	m_drsp.rdata = 0;
2407	r_dcache_fsm = DCACHE_IDLE;
2408	}
2409	else
2410	{
2411	switch( xtn_opcode )
2412	{
2413	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2414	r_dcache_xtn_req = true;
2415	r_dcache_fsm = DCACHE_XTN_SWITCH;
2416	break;
2417
2418	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2419	r_mmu_mode = m_dreq.wdata;
2420	m_drsp.valid = true;
2421	r_dcache_fsm = DCACHE_IDLE;
2422	break;
2423
2424	case iss_t::XTN_DTLB_INVAL: // dtlb access
2425	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2426	break;
2427
2428	case iss_t::XTN_ITLB_INVAL: // itlb access
2429	r_dcache_xtn_req = true;
2430	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2431	break;
2432
2433	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2434	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2435	break;
2436
2437	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2438	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2439	if (sizeof(paddr_t) <= 32)
2440	{
2441	assert(r_mmu_word_hi.read() == 0 &&
2442	"high bits should be 0 for 32bit paddr");
2443	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2444	}
2445	else
2446	{
2447	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2448	(paddr_t)r_mmu_word_lo.read();
2449	}
2450	break;
2451
2452	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2453	r_dcache_flush_count = 0;
2454	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2455	break;
2456
2457	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2458	r_dcache_xtn_req = true;
2459	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2460	break;
2461
2462	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2463	r_dcache_xtn_req = true;
2464	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2465	break;
2466
2467	case iss_t::XTN_ICACHE_FLUSH: // icache access
2468	r_dcache_xtn_req = true;
2469	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2470	break;
2471
2472	case iss_t::XTN_SYNC: // wait until write buffer empty
2473	r_dcache_fsm = DCACHE_XTN_SYNC;
2474	break;
2475
2476	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2477	r_mmu_word_lo = m_dreq.wdata;
2478	m_drsp.valid = true;
2479	r_dcache_fsm = DCACHE_IDLE;
2480	break;
2481
2482	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2483	r_mmu_word_hi = m_dreq.wdata;
2484	m_drsp.valid = true;
2485	r_dcache_fsm = DCACHE_IDLE;
2486	break;
2487
2488	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2489	r_dcache_llsc_valid = false;
2490	m_drsp.valid = true;
2491	r_dcache_fsm = DCACHE_IDLE;
2492	break;
2493
2494	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2495	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2496	m_drsp.valid = true;
2497	r_dcache_fsm = DCACHE_IDLE;
2498	break;
2499
2500	default:
2501	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2502	r_mmu_dbvar = m_dreq.addr;
2503	m_drsp.valid = true;
2504	m_drsp.error = true;
2505	r_dcache_fsm = DCACHE_IDLE;
2506	break;
2507	} // end switch xtn_opcode
2508	} // end else
2509	} // end if XTN_WRITE
2510
2511	// Handling processor requests to address space (READ/WRITE/LL/SC)
2512	// The dtlb and dcache can be activated or not.
2513	// We compute the cacheability, and check processor request validity:
2514	// - If DTLB not activated : cacheability is defined by the segment table,
2515	// and there is no access rights checking.
2516	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2517	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2518	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2519	else
2520	{
2521	bool valid_req;
2522	bool cacheable;
2523
2524	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2525	{
2526	valid_req = true;
2527
2528	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2529	else cacheable = m_cacheability_table[m_dreq.addr];
2530	}
2531	else // dtlb activated
2532	{
2533	if ( tlb_hit ) // tlb hit
2534	{
2535	// cacheability
2536	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2537	else cacheable = tlb_flags.c;
2538
2539	// access rights checking
2540	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2541	{
2542	if ( (m_dreq.type == iss_t::DATA_READ) or
2543	(m_dreq.type == iss_t::DATA_LL) )
2544	{
2545	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2546	}
2547	else
2548	{
2549	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2550	}
2551	valid_req = false;
2552	r_mmu_dbvar = m_dreq.addr;
2553	m_drsp.valid = true;
2554	m_drsp.error = true;
2555	m_drsp.rdata = 0;
2556	#if DEBUG_DCACHE
2557	if ( m_debug_dcache_fsm )
2558	{
2559	std::cout << " <PROC " << name()
2560	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2561	}
2562	#endif
2563	}
2564	else if ( not tlb_flags.w and
2565	((m_dreq.type == iss_t::DATA_WRITE) or
2566	(m_dreq.type == iss_t::DATA_SC)) )
2567	{
2568	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2569	valid_req = false;
2570	r_mmu_dbvar = m_dreq.addr;
2571	m_drsp.valid = true;
2572	m_drsp.error = true;
2573	m_drsp.rdata = 0;
2574	#if DEBUG_DCACHE
2575	if ( m_debug_dcache_fsm )
2576	{
2577	std::cout << " <PROC " << name()
2578	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2579	}
2580	#endif
2581	}
2582	else
2583	{
2584	valid_req = true;
2585	}
2586	}
2587	else // tlb miss
2588	{
2589	valid_req = false;
2590	r_dcache_tlb_vaddr = m_dreq.addr;
2591	r_dcache_tlb_ins = false;
2592	r_dcache_fsm = DCACHE_TLB_MISS;
2593	}
2594	} // end DTLB activated
2595
2596	if ( valid_req ) // processor request is valid after TLB check
2597	{
2598	r_dcache_save_cacheable = cacheable;
2599
2600	// READ request
2601	// The read requests are taken only if there is no cache update.
2602	// We request a VCI transaction to CMD FSM if miss or uncachable
2603	if ( ((m_dreq.type == iss_t::DATA_READ))
2604	and not r_dcache_updt_req.read() )
2605	{
2606	if ( cacheable ) // cacheable read
2607	{
2608	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2609	{
2610	#ifdef INSTRUMENTATION
2611	m_cpt_dcache_miss++;
2612	#endif
2613	// request a VCI DMISS transaction
2614	r_dcache_vci_paddr = paddr;
2615	r_dcache_vci_miss_req = true;
2616	r_dcache_miss_type = PROC_MISS;
2617	r_dcache_fsm = DCACHE_MISS_SELECT;
2618	#if DEBUG_DCACHE
2619	if ( m_debug_dcache_fsm )
2620	{
2621	std::cout << " <PROC " << name()
2622	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2623	}
2624	#endif
2625	}
2626	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2627	{
2628	// stalled until cleanup is acknowledged
2629	r_dcache_fsm = DCACHE_IDLE;
2630	}
2631	else // cache hit
2632	{
2633	#ifdef INSTRUMENTATION
2634	m_cpt_data_read++;
2635	#endif
2636	// returns data to processor
2637	m_drsp.valid = true;
2638	m_drsp.error = false;
2639	m_drsp.rdata = cache_rdata;
2640	#if DEBUG_DCACHE
2641	if ( m_debug_dcache_fsm )
2642	{
2643	std::cout << " <PROC " << name()
2644	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2645	}
2646	#endif
2647	}
2648	}
2649	else // uncacheable read
2650	{
2651	r_dcache_vci_paddr = paddr;
2652	r_dcache_vci_unc_be = m_dreq.be;
2653	r_dcache_vci_unc_req = true;
2654	r_dcache_fsm = DCACHE_UNC_WAIT;
2655	#if DEBUG_DCACHE
2656	if ( m_debug_dcache_fsm )
2657	{
2658	std::cout << " <PROC " << name()
2659	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2660	}
2661	#endif
2662	}
2663	} // end READ
2664
2665	// LL request (non cachable)
2666	// We request a VCI LL transaction to CMD FSM and register
2667	// the LL/SC operation in llsc buffer.
2668	else if (m_dreq.type == iss_t::DATA_LL)
2669	{
2670	// register paddr in LLSC buffer
2671	r_dcache_llsc_paddr = paddr;
2672	r_dcache_llsc_count = LLSC_TIMEOUT;
2673	r_dcache_llsc_valid = true;
2674
2675	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2676	r_dcache_vci_ll_req = true;
2677	r_dcache_vci_paddr = paddr;
2678	r_dcache_ll_rsp_count = 0;
2679	r_dcache_fsm = DCACHE_LL_WAIT;
2680
2681	}// end LL
2682
2683	// WRITE request:
2684	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2685	// the processor and set the Dirty bit before handling the write request,
2686	// going to the DCACHE_DIRTY_GT_PTE state.
2687	// If we don't need to set the Dirty bit, we can acknowledge
2688	// the processor request, as the write arguments (including the
2689	// physical address) are registered in r_dcache_save registers,
2690	// and the write will be done in the P1 pipeline stage.
2691	else if ( m_dreq.type == iss_t::DATA_WRITE )
2692	{
2693	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2694	and not tlb_flags.d ) // Dirty bit must be set
2695	{
2696	// The PTE physical address is obtained from the nline value (dtlb),
2697	// and from the virtual address (word index)
2698	if ( tlb_flags.b ) // PTE1
2699	{
2700	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2701	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2702	}
2703	else // PTE2
2704	{
2705	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2706	(paddr_t)((m_dreq.addr>>9) & 0x38);
2707	}
2708	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2709	}
2710	else // Write request accepted
2711	{
2712	#ifdef INSTRUMENTATION
2713	m_cpt_data_write++;
2714	#endif
2715	// cleaning llsc buffer if address matching
2716	if ( paddr == r_dcache_llsc_paddr.read() )
2717	r_dcache_llsc_valid = false;
2718
2719	// response to processor
2720	m_drsp.valid = true;
2721
2722	// activating P1 stage
2723	wbuf_request = true;
2724	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2725	}
2726	} // end WRITE
2727
2728	// SC request:
2729	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2730	// the processor and set the Dirty bit before handling the write request,
2731	// going to the DCACHE_DIRTY_GT_PTE state.
2732	// If we don't need to set the Dirty bit, we test the llsc buffer:
2733	// If failure, we send a negative response to processor.
2734	// If success, we request a SC transaction to CMD FSM and go
2735	// to DCACHE_SC_WAIT state.
2736	// We don't check a possible write hit in dcache, as the cache update
2737	// is done by the coherence transaction induced by the SC...
2738	else if ( m_dreq.type == iss_t::DATA_SC )
2739	{
2740	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2741	and not tlb_flags.d ) // Dirty bit must be set
2742	{
2743	// The PTE physical address is obtained from the nline value (dtlb),
2744	// and the word index (virtual address)
2745	if ( tlb_flags.b ) // PTE1
2746	{
2747	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2748	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2749	}
2750	else // PTE2
2751	{
2752	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2753	(paddr_t)((m_dreq.addr>>9) & 0x38);
2754	}
2755	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2756	m_drsp.valid = false;
2757	m_drsp.error = false;
2758	m_drsp.rdata = 0;
2759	}
2760	else // SC request accepted
2761	{
2762	#ifdef INSTRUMENTATION
2763	m_cpt_data_sc++;
2764	#endif
2765	// checking local success
2766	if( r_dcache_llsc_valid.read() and
2767	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2768	{
2769	// request an SC CMD and go to DCACHE_SC_WAIT state
2770	r_dcache_vci_paddr = paddr;
2771	r_dcache_vci_sc_req = true;
2772	r_dcache_vci_sc_data = m_dreq.wdata;
2773	r_dcache_fsm = DCACHE_SC_WAIT;
2774	}
2775	else // local fail
2776	{
2777	m_drsp.valid = true;
2778	m_drsp.error = false;
2779	m_drsp.rdata = 0x1;
2780	}
2781	}
2782	} // end SC
2783	} // end valid_req
2784	} // end if read/write/ll/sc request
2785	} // end processor request
2786
2787	// itlb miss request
2788	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2789	{
2790	r_dcache_tlb_ins = true;
2791	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2792	r_dcache_fsm = DCACHE_TLB_MISS;
2793	}
2794
2795	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2796	r_dcache_updt_req = updt_request;
2797	r_dcache_wbuf_req = wbuf_request or
2798	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2799	break;
2800	}
2801	/////////////////////
2802	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2803	// Input arguments are:
2804	// - r_dcache_tlb_vaddr
2805	// - r_dcache_tlb_ins (true when itlb miss)
2806	// The sub-fsm access the dcache to find the missing TLB entry,
2807	// and activates the cache miss procedure in case of miss.
2808	// It bypass the first level page table access if possible.
2809	// It uses atomic access to update the R/L access bits
2810	// in the page table if required.
2811	// It directly updates the itlb or dtlb, and writes into the
2812	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2813	{
2814	uint32_t ptba = 0;
2815	bool bypass;
2816	paddr_t pte_paddr;
2817
2818	// evaluate bypass in order to skip first level page table access
2819	if ( r_dcache_tlb_ins.read() ) // itlb miss
2820	{
2821	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2822	}
2823	else // dtlb miss
2824	{
2825	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2826	}
2827
2828	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2829	{
2830	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2831	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2832	r_dcache_tlb_paddr = pte_paddr;
2833	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2834	}
2835	else // Try to read PTE2 in dcache
2836	{
2837	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2838	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2839	r_dcache_tlb_paddr = pte_paddr;
2840	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2841	}
2842
2843	#if DEBUG_DCACHE
2844	if ( m_debug_dcache_fsm )
2845	{
2846	if ( r_dcache_tlb_ins.read() )
2847	{
2848	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2849	}
2850	else
2851	{
2852	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2853	}
2854	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2855	<< " / BYPASS = " << bypass
2856	<< " / PTE_ADR = " << pte_paddr << std::endl;
2857	}
2858	#endif
2859
2860	break;
2861	}
2862	/////////////////////////
2863	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2864	{
2865	uint32_t entry;
2866	size_t way;
2867	size_t set;
2868	size_t word;
2869
2870	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2871	&entry,
2872	&way,
2873	&set,
2874	&word );
2875	#ifdef INSTRUMENTATION
2876	m_cpt_dcache_data_read++;
2877	m_cpt_dcache_dir_read++;
2878	#endif
2879	if ( hit ) // hit in dcache
2880	{
2881	if ( not (entry & PTE_V_MASK) ) // unmapped
2882	{
2883	if ( r_dcache_tlb_ins.read() )
2884	{
2885	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2886	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2887	r_icache_tlb_miss_req = false;
2888	r_icache_tlb_rsp_error = true;
2889	}
2890	else
2891	{
2892	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2893	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2894	m_drsp.valid = true;
2895	m_drsp.error = true;
2896	}
2897	r_dcache_fsm = DCACHE_IDLE;
2898
2899	#if DEBUG_DCACHE
2900	if ( m_debug_dcache_fsm )
2901	{
2902	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2903	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2904	<< std::dec << " / way = " << way
2905	<< std::dec << " / set = " << set
2906	<< std::dec << " / word = " << word
2907	<< std::hex << " / PTE1 = " << entry << std::endl;
2908	}
2909	#endif
2910
2911	}
2912	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2913	{
2914	// mark the cache line ac containing a PTD
2915	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2916
2917	// register bypass
2918	if ( r_dcache_tlb_ins.read() ) // itlb
2919	{
2920	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2921	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2922	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2923	}
2924	else // dtlb
2925	{
2926	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2927	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2928	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2929	}
2930	r_dcache_tlb_paddr =
2931	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2932	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2933	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2934
2935	#if DEBUG_DCACHE
2936	if ( m_debug_dcache_fsm )
2937	{
2938	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2939	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2940	<< std::dec << " / way = " << way
2941	<< std::dec << " / set = " << set
2942	<< std::dec << " / word = " << word
2943	<< std::hex << " / PTD = " << entry << std::endl;
2944	}
2945	#endif
2946	}
2947	else // PTE1 : we must update the TLB
2948	{
2949	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2950	r_dcache_tlb_pte_flags = entry;
2951	r_dcache_tlb_cache_way = way;
2952	r_dcache_tlb_cache_set = set;
2953	r_dcache_tlb_cache_word = word;
2954	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2955
2956	#if DEBUG_DCACHE
2957	if ( m_debug_dcache_fsm )
2958	{
2959	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2960	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2961	<< std::dec << " / way = " << way
2962	<< std::dec << " / set = " << set
2963	<< std::dec << " / word = " << word
2964	<< std::hex << " / PTE1 = " << entry << std::endl;
2965	}
2966	#endif
2967	}
2968	}
2969	else // we must load the missing cache line in dcache
2970	{
2971	r_dcache_vci_miss_req = true;
2972	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2973	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2974	r_dcache_miss_type = PTE1_MISS;
2975	r_dcache_fsm = DCACHE_MISS_SELECT;
2976
2977	#if DEBUG_DCACHE
2978	if ( m_debug_dcache_fsm )
2979	{
2980	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2981	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2982	}
2983	#endif
2984	}
2985	break;
2986	}
2987	////////////////////////////
2988	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2989	{
2990	size_t way;
2991	size_t set;
2992
2993	if ( r_dcache_tlb_ins.read() )
2994	{
2995	r_itlb.select( r_dcache_tlb_vaddr.read(),
2996	true, // PTE1
2997	&way,
2998	&set );
2999	#ifdef INSTRUMENTATION
3000	m_cpt_itlb_read++;
3001	#endif
3002	}
3003	else
3004	{
3005	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3006	true, // PTE1
3007	&way,
3008	&set );
3009	#ifdef INSTRUMENTATION
3010	m_cpt_dtlb_read++;
3011	#endif
3012	}
3013	r_dcache_tlb_way = way;
3014	r_dcache_tlb_set = set;
3015	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3016
3017	#if DEBUG_DCACHE
3018	if ( m_debug_dcache_fsm )
3019	{
3020	if ( r_dcache_tlb_ins.read() )
3021	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3022	else
3023	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3024	std::cout << " way = " << std::dec << way
3025	<< " / set = " << set << std::endl;
3026	}
3027	#endif
3028	break;
3029	}
3030	//////////////////////////
3031	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3032	// - if L/R bit already set, exit the sub-fsm.
3033	// - if not, we update the page table but we dont write
3034	// neither in DCACHE, nor in TLB, as this will be done by
3035	// the coherence mechanism.
3036	{
3037	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3038	uint32_t pte = r_dcache_tlb_pte_flags.read();
3039	bool pt_updt = false;
3040	bool local = true;
3041
3042	// We should compute the access locality:
3043	// The PPN MSB bits define the destination cluster index.
3044	// The m_srcid_d MSB bits define the source cluster index.
3045	// The number of bits to compare depends on the number of clusters,
3046	// and can be obtained in the mapping table.
3047	// As long as this computation is not done, all access are local.
3048
3049	if ( local ) // local access
3050	{
3051	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3052	{
3053	pt_updt = true;
3054	r_dcache_vci_cas_old = pte;
3055	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3056	pte = pte \| PTE_L_MASK;
3057	r_dcache_tlb_pte_flags = pte;
3058	}
3059	}
3060	else // remote access
3061	{
3062	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3063	{
3064	pt_updt = true;
3065	r_dcache_vci_cas_old = pte;
3066	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3067	pte = pte \| PTE_R_MASK;
3068	r_dcache_tlb_pte_flags = pte;
3069	}
3070	}
3071
3072	if ( not pt_updt ) // update TLB and return
3073	{
3074	if ( r_dcache_tlb_ins.read() )
3075	{
3076	r_itlb.write( true, // 2M page
3077	pte,
3078	0, // argument unused for a PTE1
3079	r_dcache_tlb_vaddr.read(),
3080	r_dcache_tlb_way.read(),
3081	r_dcache_tlb_set.read(),
3082	nline );
3083	#ifdef INSTRUMENTATION
3084	m_cpt_itlb_write++;
3085	#endif
3086
3087	#if DEBUG_DCACHE
3088	if ( m_debug_dcache_fsm )
3089	{
3090	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3091	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3092	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3093	r_itlb.printTrace();
3094	}
3095	#endif
3096	}
3097	else
3098	{
3099	r_dtlb.write( true, // 2M page
3100	pte,
3101	0, // argument unused for a PTE1
3102	r_dcache_tlb_vaddr.read(),
3103	r_dcache_tlb_way.read(),
3104	r_dcache_tlb_set.read(),
3105	nline );
3106	#ifdef INSTRUMENTATION
3107	m_cpt_dtlb_write++;
3108	#endif
3109
3110	#if DEBUG_DCACHE
3111	if ( m_debug_dcache_fsm )
3112	{
3113	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3114	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3115	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3116	r_dtlb.printTrace();
3117	}
3118	#endif
3119	}
3120	r_dcache_fsm = DCACHE_TLB_RETURN;
3121	}
3122	else // update page table but not TLB
3123	{
3124	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3125
3126	#if DEBUG_DCACHE
3127	if ( m_debug_dcache_fsm )
3128	{
3129	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3130	<< std::endl;
3131	}
3132	#endif
3133	}
3134	break;
3135	}
3136	/////////////////////////
3137	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3138	{
3139	uint32_t pte_flags;
3140	uint32_t pte_ppn;
3141	size_t way;
3142	size_t set;
3143	size_t word;
3144
3145	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3146	&pte_flags,
3147	&pte_ppn,
3148	&way,
3149	&set,
3150	&word );
3151	#ifdef INSTRUMENTATION
3152	m_cpt_dcache_data_read++;
3153	m_cpt_dcache_dir_read++;
3154	#endif
3155	if ( hit ) // request hits in dcache
3156	{
3157	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3158	{
3159	if ( r_dcache_tlb_ins.read() )
3160	{
3161	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3162	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3163	r_icache_tlb_miss_req = false;
3164	r_icache_tlb_rsp_error = true;
3165	}
3166	else
3167	{
3168	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3169	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3170	m_drsp.valid = true;
3171	m_drsp.error = true;
3172	}
3173	r_dcache_fsm = DCACHE_IDLE;
3174
3175	#if DEBUG_DCACHE
3176	if ( m_debug_dcache_fsm )
3177	{
3178	std::cout << " <PROC " << name()
3179	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3180	<< " PTE_FLAGS = " << std::hex << pte_flags
3181	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3182	}
3183	#endif
3184	}
3185	else // mapped : we must update the TLB
3186	{
3187	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3188	r_dcache_tlb_pte_flags = pte_flags;
3189	r_dcache_tlb_pte_ppn = pte_ppn;
3190	r_dcache_tlb_cache_way = way;
3191	r_dcache_tlb_cache_set = set;
3192	r_dcache_tlb_cache_word = word;
3193	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3194
3195	#if DEBUG_DCACHE
3196	if ( m_debug_dcache_fsm )
3197	{
3198	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3199	<< " PTE_FLAGS = " << std::hex << pte_flags
3200	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3201	}
3202	#endif
3203	}
3204	}
3205	else // we must load the missing cache line in dcache
3206	{
3207	r_dcache_fsm = DCACHE_MISS_SELECT;
3208	r_dcache_vci_miss_req = true;
3209	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3210	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3211	r_dcache_miss_type = PTE2_MISS;
3212
3213	#if DEBUG_DCACHE
3214	if ( m_debug_dcache_fsm )
3215	{
3216	std::cout << " <PROC " << name()
3217	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3218	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3219	}
3220	#endif
3221	}
3222	break;
3223	}
3224	////////////////////////////
3225	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3226	{
3227	size_t way;
3228	size_t set;
3229
3230	if ( r_dcache_tlb_ins.read() )
3231	{
3232	r_itlb.select( r_dcache_tlb_vaddr.read(),
3233	false, // PTE2
3234	&way,
3235	&set );
3236	#ifdef INSTRUMENTATION
3237	m_cpt_itlb_read++;
3238	#endif
3239	}
3240	else
3241	{
3242	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3243	false, // PTE2
3244	&way,
3245	&set );
3246	#ifdef INSTRUMENTATION
3247	m_cpt_dtlb_read++;
3248	#endif
3249	}
3250
3251	#if DEBUG_DCACHE
3252	if ( m_debug_dcache_fsm )
3253	{
3254	if ( r_dcache_tlb_ins.read() )
3255	std::cout << " <PROC " << name()
3256	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3257	else
3258	std::cout << " <PROC " << name()
3259	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3260	std::cout << " way = " << std::dec << way
3261	<< " / set = " << set << std::endl;
3262	}
3263	#endif
3264	r_dcache_tlb_way = way;
3265	r_dcache_tlb_set = set;
3266	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3267	break;
3268	}
3269	//////////////////////////
3270	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3271	// - if L/R bit already set, exit the sub-fsm.
3272	// - if not, we update the page table but we dont write
3273	// neither in DCACHE, nor in TLB, as this will be done by
3274	// the coherence mechanism.
3275	{
3276	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3277	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3278	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3279	bool pt_updt = false;
3280	bool local = true;
3281
3282	// We should compute the access locality:
3283	// The PPN MSB bits define the destination cluster index.
3284	// The m_srcid_d MSB bits define the source cluster index.
3285	// The number of bits to compare depends on the number of clusters,
3286	// and can be obtained in the mapping table.
3287	// As long as this computation is not done, all access are local.
3288
3289	if ( local ) // local access
3290	{
3291	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3292	{
3293	pt_updt = true;
3294	r_dcache_vci_cas_old = pte_flags;
3295	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3296	pte_flags = pte_flags \| PTE_L_MASK;
3297	r_dcache_tlb_pte_flags = pte_flags;
3298	}
3299	}
3300	else // remote access
3301	{
3302	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3303	{
3304	pt_updt = true;
3305	r_dcache_vci_cas_old = pte_flags;
3306	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3307	pte_flags = pte_flags \| PTE_R_MASK;
3308	r_dcache_tlb_pte_flags = pte_flags;
3309	}
3310	}
3311
3312	if ( not pt_updt ) // update TLB
3313	{
3314	if ( r_dcache_tlb_ins.read() )
3315	{
3316	r_itlb.write( false, // 4K page
3317	pte_flags,
3318	pte_ppn,
3319	r_dcache_tlb_vaddr.read(),
3320	r_dcache_tlb_way.read(),
3321	r_dcache_tlb_set.read(),
3322	nline );
3323	#ifdef INSTRUMENTATION
3324	m_cpt_itlb_write++;
3325	#endif
3326
3327	#if DEBUG_DCACHE
3328	if ( m_debug_dcache_fsm )
3329	{
3330	std::cout << " <PROC " << name()
3331	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3332	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3333	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3334	r_itlb.printTrace();
3335	}
3336	#endif
3337	}
3338	else
3339	{
3340	r_dtlb.write( false, // 4K page
3341	pte_flags,
3342	pte_ppn,
3343	r_dcache_tlb_vaddr.read(),
3344	r_dcache_tlb_way.read(),
3345	r_dcache_tlb_set.read(),
3346	nline );
3347	#ifdef INSTRUMENTATION
3348	m_cpt_dtlb_write++;
3349	#endif
3350
3351	#if DEBUG_DCACHE
3352	if ( m_debug_dcache_fsm )
3353	{
3354	std::cout << " <PROC " << name()
3355	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3356	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3357	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3358	r_dtlb.printTrace();
3359	}
3360	#endif
3361
3362	}
3363	r_dcache_fsm = DCACHE_TLB_RETURN;
3364	}
3365	else // update page table but not TLB
3366	{
3367	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3368
3369	#if DEBUG_DCACHE
3370	if ( m_debug_dcache_fsm )
3371	{
3372	std::cout << " <PROC " << name()
3373	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3374	}
3375	#endif
3376	}
3377	break;
3378	}
3379	////////////////////////
3380	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3381	{
3382	#if DEBUG_DCACHE
3383	if ( m_debug_dcache_fsm )
3384	{
3385	std::cout << " <PROC " << name()
3386	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3387	}
3388	#endif
3389	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3390	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3391
3392	// checking llsc reservation buffer
3393	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3394	r_dcache_llsc_valid = false;
3395
3396	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3397	r_dcache_vci_cas_req = true;
3398	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3399	break;
3400	}
3401	////////////////////////
3402	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3403	// We consume the response in rsp FIFO,
3404	// and exit the sub-fsm, but we don't
3405	// analyse the response, because we don't
3406	// care if the L/R bit update is not done.
3407	// We must take the coherence requests because
3408	// there is a risk of dead-lock
3409
3410	{
3411	// coherence request (from CC_RECEIVE FSM)
3412	if ( r_cc_receive_dcache_req.read() )
3413	{
3414	r_dcache_fsm = DCACHE_CC_CHECK;
3415	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3416	break;
3417	}
3418
3419	if ( r_vci_rsp_data_error.read() ) // bus error
3420	{
3421	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3422	std::cout << "This should not happen in this state" << std::endl;
3423	exit(0);
3424	}
3425	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3426	{
3427	#if DEBUG_DCACHE
3428	if ( m_debug_dcache_fsm )
3429	{
3430	std::cout << " <PROC " << name()
3431	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3432	}
3433	#endif
3434	vci_rsp_fifo_dcache_get = true;
3435	r_dcache_fsm = DCACHE_TLB_RETURN;
3436	}
3437	break;
3438	}
3439	///////////////////////
3440	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3441	{
3442	#if DEBUG_DCACHE
3443	if ( m_debug_dcache_fsm )
3444	{
3445	std::cout << " <PROC " << name()
3446	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3447	}
3448	#endif
3449	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3450	r_dcache_fsm = DCACHE_IDLE;
3451	break;
3452	}
3453	///////////////////////
3454	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3455	// and both itlb and dtlb must be flushed.
3456	// Caution : the itlb miss requests must be taken
3457	// to avoid dead-lock in case of simultaneous ITLB miss
3458	{
3459	// itlb miss request
3460	if ( r_icache_tlb_miss_req.read() )
3461	{
3462	r_dcache_tlb_ins = true;
3463	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3464	r_dcache_fsm = DCACHE_TLB_MISS;
3465	break;
3466	}
3467
3468	if ( not r_dcache_xtn_req.read() )
3469	{
3470	r_dtlb.flush();
3471	r_mmu_ptpr = m_dreq.wdata;
3472	r_dcache_fsm = DCACHE_IDLE;
3473	m_drsp.valid = true;
3474	}
3475	break;
3476	}
3477	/////////////////////
3478	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3479	// The coherence request must be taken
3480	// as there is a risk of dead-lock
3481	{
3482	// coherence request (from CC_RECEIVE FSM)
3483	if ( r_cc_receive_dcache_req.read() )
3484	{
3485	r_dcache_fsm = DCACHE_CC_CHECK;
3486	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3487	}
3488
3489	if ( r_wbuf.empty() )
3490	{
3491	m_drsp.valid = true;
3492	r_dcache_fsm = DCACHE_IDLE;
3493	}
3494	break;
3495	}
3496	////////////////////////
3497	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3498	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3499	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3500	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3501	// and because it can exist a simultaneous ITLB miss
3502	{
3503	// coherence request (from CC_RECEIVE FSM)
3504	if ( r_cc_receive_dcache_req.read() )
3505	{
3506	r_dcache_fsm = DCACHE_CC_CHECK;
3507	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3508	break;
3509	}
3510
3511	// itlb miss request
3512	if ( r_icache_tlb_miss_req.read() )
3513	{
3514	r_dcache_tlb_ins = true;
3515	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3516	r_dcache_fsm = DCACHE_TLB_MISS;
3517	break;
3518	}
3519
3520	// test if XTN request to icache completed
3521	if ( not r_dcache_xtn_req.read() )
3522	{
3523	r_dcache_fsm = DCACHE_IDLE;
3524	m_drsp.valid = true;
3525	}
3526	break;
3527	}
3528	/////////////////////////
3529	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3530	// r_dcache_flush_count as a slot counter,
3531	// looping in this state until all slots have been visited.
3532	// It can require two cycles per slot:
3533	// We test here the slot state, and make the actual inval
3534	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3535	// A cleanup request is generated for each valid line.
3536	// returns to IDLE and flush TLBs when last slot
3537	{
3538	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3539	{
3540	int state;
3541	uint32_t tag;
3542	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3543	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3544
3545	#ifdef INSTRUMENTATION
3546	m_cpt_dcache_dir_read++;
3547	#endif
3548	r_dcache.read_dir( way,
3549	set,
3550	&tag,
3551	&state );
3552
3553	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3554	{
3555	// request cleanup
3556	r_dcache_cc_send_req = true;
3557	r_dcache_cc_send_nline = tag * m_dcache_sets;
3558	r_dcache_cc_send_way = way;
3559	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3560
3561	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3562	r_dcache_miss_way = way;
3563	r_dcache_miss_set = set;
3564	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3565	}
3566	else if ( r_dcache_flush_count.read() ==
3567	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3568	{
3569	r_dtlb.reset();
3570	r_itlb.reset();
3571	r_dcache_fsm = DCACHE_IDLE;
3572	m_drsp.valid = true;
3573	}
3574
3575	// saturation counter
3576	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3577	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3578	}
3579	break;
3580	}
3581	////////////////////////////
3582	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3583	// and reset directory extension.
3584	// returns to IDLE and flush TLBs when last slot
3585	{
3586	size_t way = r_dcache_miss_way.read();
3587	size_t set = r_dcache_miss_set.read();
3588
3589	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3590	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3591
3592	#ifdef INSTRUMENTATION
3593	m_cpt_dcache_dir_write++;
3594	#endif
3595	r_dcache.write_dir( 0,
3596	way,
3597	set,
3598	CACHE_SLOT_STATE_ZOMBI );
3599
3600	if ( r_dcache_flush_count.read() ==
3601	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3602	{
3603	r_dtlb.reset();
3604	r_itlb.reset();
3605	r_dcache_fsm = DCACHE_IDLE;
3606	m_drsp.valid = true;
3607	}
3608	else
3609	{
3610	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3611	}
3612	break;
3613	}
3614	/////////////////////////
3615	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3616	{
3617	r_dtlb.inval(r_dcache_save_wdata.read());
3618	r_dcache_fsm = DCACHE_IDLE;
3619	m_drsp.valid = true;
3620	break;
3621	}
3622	////////////////////////////
3623	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3624	// requires 3 cycles: access tlb, read cache, inval cache
3625	// we compute the physical address in this state
3626	{
3627	paddr_t paddr;
3628	bool hit;
3629
3630	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3631	{
3632
3633	#ifdef INSTRUMENTATION
3634	m_cpt_dtlb_read++;
3635	#endif
3636	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3637	&paddr );
3638	}
3639	else // dtlb not activated
3640	{
3641	paddr = (paddr_t)r_dcache_save_wdata.read();
3642	hit = true;
3643	}
3644
3645	if ( hit ) // tlb hit
3646	{
3647	r_dcache_save_paddr = paddr;
3648	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3649	}
3650	else // tlb miss
3651	{
3652
3653	#ifdef INSTRUMENTATION
3654	m_cpt_dtlb_miss++;
3655	#endif
3656	r_dcache_tlb_ins = false; // dtlb
3657	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3658	r_dcache_fsm = DCACHE_TLB_MISS;
3659	}
3660
3661	#if DEBUG_DCACHE
3662	if ( m_debug_dcache_fsm )
3663	{
3664	std::cout << " <PROC " << name()
3665	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3666	<< " / VADDR = " << r_dcache_save_wdata.read()
3667	<< " / PADDR = " << paddr << std::endl;
3668	}
3669	#endif
3670
3671	break;
3672	}
3673	////////////////////////////
3674	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3675	// requires 2 cycles: read cache / inval cache
3676	// In this state we read dcache.
3677	{
3678	size_t way;
3679	size_t set;
3680	size_t word;
3681	int state;
3682
3683	#ifdef INSTRUMENTATION
3684	m_cpt_dcache_dir_read++;
3685	#endif
3686	r_dcache.read_dir( r_dcache_save_paddr.read(),
3687	&state,
3688	&way,
3689	&set,
3690	&word );
3691
3692	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3693	{
3694	r_dcache_xtn_way = way;
3695	r_dcache_xtn_set = set;
3696	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3697	}
3698	else // miss : nothing to do
3699	{
3700	r_dcache_fsm = DCACHE_IDLE;
3701	m_drsp.valid = true;
3702	}
3703
3704	#if DEBUG_DCACHE
3705	if ( m_debug_dcache_fsm )
3706	{
3707	std::cout << " <PROC " << name()
3708	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3709	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3710	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3711	<< " / SET = " << set
3712	<< " / WAY = " << way << std::endl;
3713	}
3714	#endif
3715	break;
3716	}
3717	////////////////////////////
3718	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3719	// Blocked if previous cleanup not completed
3720	// Test if itlb or dtlb inval is required
3721	{
3722	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3723	{
3724	size_t way = r_dcache_xtn_way.read();
3725	size_t set = r_dcache_xtn_set.read();
3726	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3727
3728	#ifdef INSTRUMENTATION
3729	m_cpt_dcache_dir_write++;
3730	#endif
3731	r_dcache.write_dir( 0,
3732	way,
3733	set,
3734	CACHE_SLOT_STATE_EMPTY );
3735
3736	// request cleanup
3737	r_dcache_cc_send_req = true;
3738	r_dcache_cc_send_nline = nline;
3739	r_dcache_cc_send_way = way;
3740	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3741
3742	// possible itlb & dtlb invalidate
3743	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3744	{
3745	r_dcache_tlb_inval_line = nline;
3746	r_dcache_tlb_inval_set = 0;
3747	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3748	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3749	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3750	}
3751	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3752	{
3753	r_itlb.reset();
3754	r_dtlb.reset();
3755	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3756	r_dcache_fsm = DCACHE_IDLE;
3757	m_drsp.valid = true;
3758	}
3759	else
3760	{
3761	r_dcache_fsm = DCACHE_IDLE;
3762	m_drsp.valid = true;
3763	}
3764
3765	#if DEBUG_DCACHE
3766	if ( m_debug_dcache_fsm )
3767	{
3768	std::cout << " <PROC " << name()
3769	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3770	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3771	}
3772	#endif
3773	}
3774	break;
3775	}
3776	//////////////////////////////
3777	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3778	{
3779	r_dcache_fsm = DCACHE_IDLE;
3780	m_drsp.valid = true;
3781	break;
3782	}
3783	////////////////////////
3784	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3785	// if previous cleanup has been sent.
3786	// Waiting in this state if no slot available
3787	// Set the r_dcache_cleanup_req flip-flop
3788	// and the r_dcache_miss_clack flip-flop
3789	// when a cleanup is required
3790	{
3791	if ( m_dreq.valid) m_cost_data_miss_frz++;
3792
3793	// coherence request (from CC_RECEIVE FSM)
3794	if ( r_cc_receive_dcache_req.read() )
3795	{
3796	r_dcache_fsm = DCACHE_CC_CHECK;
3797	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3798	break;
3799	}
3800
3801	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3802	{
3803	bool found;
3804	bool cleanup;
3805	size_t way;
3806	size_t set;
3807	paddr_t victim;
3808
3809	#ifdef INSTRUMENTATION
3810	m_cpt_dcache_dir_read++;
3811	#endif
3812	r_dcache.read_select( r_dcache_save_paddr.read(),
3813	&victim,
3814	&way,
3815	&set,
3816	&found,
3817	&cleanup );
3818	if ( found )
3819	{
3820	r_dcache_miss_way = way;
3821	r_dcache_miss_set = set;
3822
3823	if ( cleanup )
3824	{
3825	r_dcache_miss_clack = true;
3826	r_dcache_fsm = DCACHE_MISS_CLEAN;
3827	// request cleanup
3828	r_dcache_cc_send_req = true;
3829	r_dcache_cc_send_nline = victim;
3830	r_dcache_cc_send_way = way;
3831	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3832	}
3833	else
3834	{
3835	r_dcache_fsm = DCACHE_MISS_WAIT;
3836	}
3837
3838	#if DEBUG_DCACHE
3839	if ( m_debug_dcache_fsm )
3840	{
3841	std::cout << " <PROC " << name()
3842	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3843	<< " / WAY = " << way
3844	<< " / SET = " << set
3845	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3846	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3847	else std::cout << std::endl;
3848	}
3849	#endif
3850	} // end found
3851	}
3852	break;
3853	}
3854	///////////////////////
3855	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3856	// and possibly request itlb or dtlb invalidate
3857	{
3858	if ( m_dreq.valid) m_cost_data_miss_frz++;
3859
3860	// coherence request (from CC_RECEIVE FSM)
3861	if ( r_cc_receive_dcache_req.read() )
3862	{
3863	r_dcache_fsm = DCACHE_CC_CHECK;
3864	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3865	break;
3866	}
3867
3868	size_t way = r_dcache_miss_way.read();
3869	size_t set = r_dcache_miss_set.read();
3870	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3871
3872	#ifdef INSTRUMENTATION
3873	m_cpt_dcache_dir_read++;
3874	#endif
3875	r_dcache.write_dir( 0,
3876	way,
3877	set,
3878	CACHE_SLOT_STATE_ZOMBI );
3879	#if DEBUG_DCACHE
3880	if ( m_debug_dcache_fsm )
3881	{
3882	std::cout << " <PROC " << name()
3883	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3884	<< " / way = " << way
3885	<< " / set = " << set << std::endl;
3886	}
3887	#endif
3888	// if selective itlb & dtlb invalidate are required
3889	// the miss response is not handled before invalidate completed
3890	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3891	{
3892	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3893	r_dcache_tlb_inval_line = nline;
3894	r_dcache_tlb_inval_set = 0;
3895	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3896	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3897	}
3898	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3899	{
3900	r_itlb.reset();
3901	r_dtlb.reset();
3902	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3903	r_dcache_fsm = DCACHE_MISS_WAIT;
3904	}
3905	else
3906	{
3907	r_dcache_fsm = DCACHE_MISS_WAIT;
3908	}
3909	break;
3910	}
3911	//////////////////////
3912	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3913	// This state is in charge of error signaling
3914	// There is 5 types of error depending on the requester
3915	{
3916	if ( m_dreq.valid) m_cost_data_miss_frz++;
3917
3918	// coherence request (from CC_RECEIVE FSM)
3919	if ( r_cc_receive_dcache_req.read() )
3920	{
3921	r_dcache_fsm = DCACHE_CC_CHECK;
3922	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3923	break;
3924	}
3925
3926	if ( r_vci_rsp_data_error.read() ) // bus error
3927	{
3928	switch ( r_dcache_miss_type.read() )
3929	{
3930	case PROC_MISS:
3931	{
3932	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3933	r_mmu_dbvar = r_dcache_save_vaddr.read();
3934	m_drsp.valid = true;
3935	m_drsp.error = true;
3936	r_dcache_fsm = DCACHE_IDLE;
3937	break;
3938	}
3939	case PTE1_MISS:
3940	{
3941	if ( r_dcache_tlb_ins.read() )
3942	{
3943	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3944	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3945	r_icache_tlb_miss_req = false;
3946	r_icache_tlb_rsp_error = true;
3947	}
3948	else
3949	{
3950	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3951	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3952	m_drsp.valid = true;
3953	m_drsp.error = true;
3954	}
3955	r_dcache_fsm = DCACHE_IDLE;
3956	break;
3957	}
3958	case PTE2_MISS:
3959	{
3960	if ( r_dcache_tlb_ins.read() )
3961	{
3962	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3963	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3964	r_icache_tlb_miss_req = false;
3965	r_icache_tlb_rsp_error = true;
3966	}
3967	else
3968	{
3969	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3970	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3971	m_drsp.valid = true;
3972	m_drsp.error = true;
3973	}
3974	r_dcache_fsm = DCACHE_IDLE;
3975	break;
3976	}
3977	} // end switch type
3978	r_vci_rsp_data_error = false;
3979	}
3980	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3981	{
3982	r_dcache_miss_word = 0;
3983	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3984	}
3985	break;
3986	}
3987	//////////////////////////
3988	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3989	{
3990	if ( m_dreq.valid) m_cost_data_miss_frz++;
3991
3992	// coherence request (from CC_RECEIVE FSM)
3993	if ( r_cc_receive_dcache_req.read() )
3994	{
3995	r_dcache_fsm = DCACHE_CC_CHECK;
3996	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3997	break;
3998	}
3999
4000	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4001	{
4002	#ifdef INSTRUMENTATION
4003	m_cpt_dcache_data_write++;
4004	#endif
4005	r_dcache.write( r_dcache_miss_way.read(),
4006	r_dcache_miss_set.read(),
4007	r_dcache_miss_word.read(),
4008	r_vci_rsp_fifo_dcache.read() );
4009	#if DEBUG_DCACHE
4010	if ( m_debug_dcache_fsm )
4011	{
4012	std::cout << " <PROC " << name()
4013	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4014	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4015	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4016	<< " / SET = " << r_dcache_miss_set.read()
4017	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4018	}
4019	#endif
4020	vci_rsp_fifo_dcache_get = true;
4021	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4022
4023	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4024	{
4025	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4026	}
4027	}
4028	break;
4029	}
4030	//////////////////////////
4031	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4032	// and the cleanup ack has not been received,
4033	// as indicated by the r_dcache_miss clack.
4034	// - If no matching coherence request (r_dcache_inval_miss)
4035	// switch directory slot to VALID state.
4036	// - If matching coherence request, switch directory slot
4037	// to ZOMBI state, and send a cleanup request.
4038	{
4039	if ( m_dreq.valid) m_cost_data_miss_frz++;
4040
4041	// coherence request (from CC_RECEIVE FSM)
4042	if ( r_cc_receive_dcache_req.read() )
4043	{
4044	r_dcache_fsm = DCACHE_CC_CHECK;
4045	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4046	break;
4047	}
4048
4049	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4050	{
4051	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4052	{
4053	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4054	{
4055	r_dcache_miss_inval = false;
4056	// request cleanup
4057	r_dcache_cc_send_req = true;
4058	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4059	r_dcache_cc_send_way = r_dcache_miss_way.read();
4060	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4061
4062	#ifdef INSTRUMENTATION
4063	m_cpt_dcache_dir_write++;
4064	#endif
4065	r_dcache.write_dir( r_dcache_save_paddr.read(),
4066	r_dcache_miss_way.read(),
4067	r_dcache_miss_set.read(),
4068	CACHE_SLOT_STATE_ZOMBI );
4069	#if DEBUG_DCACHE
4070	if ( m_debug_dcache_fsm )
4071	{
4072	std::cout << " <PROC " << name()
4073	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4074	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4075	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4076	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4077	}
4078	#endif
4079	}
4080	}
4081	else // switch slot to VALID state
4082	{
4083
4084	#ifdef INSTRUMENTATION
4085	m_cpt_dcache_dir_write++;
4086	#endif
4087	r_dcache.write_dir( r_dcache_save_paddr.read(),
4088	r_dcache_miss_way.read(),
4089	r_dcache_miss_set.read(),
4090	CACHE_SLOT_STATE_VALID );
4091
4092	#if DEBUG_DCACHE
4093	if ( m_debug_dcache_fsm )
4094	{
4095	std::cout << " <PROC " << name()
4096	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4097	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4098	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4099	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4100
4101	r_dcache.printTrace();
4102
4103
4104	}
4105	#endif
4106	// reset directory extension
4107	size_t way = r_dcache_miss_way.read();
4108	size_t set = r_dcache_miss_set.read();
4109	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4110	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4111	}
4112
4113	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4114	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4115	else r_dcache_fsm = DCACHE_IDLE;
4116	}
4117	break;
4118	}
4119	/////////////////////
4120	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4121	{
4122	// coherence request (from CC_RECEIVE FSM)
4123	if ( r_cc_receive_dcache_req.read() )
4124	{
4125	r_dcache_fsm = DCACHE_CC_CHECK;
4126	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4127	break;
4128	}
4129
4130	if ( r_vci_rsp_data_error.read() ) // bus error
4131	{
4132	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4133	r_mmu_dbvar = m_dreq.addr;
4134	r_vci_rsp_data_error = false;
4135	m_drsp.error = true;
4136	m_drsp.valid = true;
4137	r_dcache_fsm = DCACHE_IDLE;
4138	break;
4139	}
4140	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4141	{
4142	// consume data
4143	vci_rsp_fifo_dcache_get = true;
4144	r_dcache_fsm = DCACHE_IDLE;
4145
4146	// acknowledge the processor request if it has not been modified
4147	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4148	{
4149	m_drsp.valid = true;
4150	m_drsp.error = false;
4151	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4152	}
4153	}
4154	break;
4155	}
4156	/////////////////////
4157	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4158	{
4159	// coherence request (from CC_RECEIVE FSM)
4160	if ( r_cc_receive_dcache_req.read() )
4161	{
4162	r_dcache_fsm = DCACHE_CC_CHECK;
4163	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4164	break;
4165	}
4166
4167	if ( r_vci_rsp_data_error.read() ) // bus error
4168	{
4169	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4170	r_mmu_dbvar = m_dreq.addr;
4171	r_vci_rsp_data_error = false;
4172	m_drsp.error = true;
4173	m_drsp.valid = true;
4174	r_dcache_fsm = DCACHE_IDLE;
4175	break;
4176	}
4177	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4178	{
4179	// consume data
4180	vci_rsp_fifo_dcache_get = true;
4181
4182	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4183	{
4184	// set key value in llsc reservation buffer
4185	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4186	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4187	}
4188	else // last flit
4189	{
4190	// acknowledge the processor request if it has not been modified
4191	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4192	{
4193	m_drsp.valid = true;
4194	m_drsp.error = false;
4195	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4196	}
4197	r_dcache_fsm = DCACHE_IDLE;
4198	}
4199	}
4200	break;
4201	}
4202	////////////////////
4203	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4204	{
4205	// coherence request (from CC_RECEIVE FSM)
4206	if ( r_cc_receive_dcache_req.read() )
4207	{
4208	r_dcache_fsm = DCACHE_CC_CHECK;
4209	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4210	break;
4211	}
4212
4213	if ( r_vci_rsp_data_error.read() ) // bus error
4214	{
4215	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4216	r_mmu_dbvar = m_dreq.addr;
4217	r_vci_rsp_data_error = false;
4218	m_drsp.error = true;
4219	m_drsp.valid = true;
4220	r_dcache_fsm = DCACHE_IDLE;
4221	break;
4222	}
4223	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4224	{
4225	// consume response
4226	vci_rsp_fifo_dcache_get = true;
4227	m_drsp.valid = true;
4228	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4229	r_dcache_fsm = DCACHE_IDLE;
4230	}
4231	break;
4232	}
4233	//////////////////////////
4234	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4235	// before handling a processor WRITE or SC request
4236	// Input argument is r_dcache_dirty_paddr
4237	// In this first state, we get PTE value in dcache
4238	// and post a CAS request to CMD FSM
4239	{
4240	// get PTE in dcache
4241	uint32_t pte;
4242	size_t way;
4243	size_t set;
4244	size_t word; // unused
4245	int state;
4246
4247	#ifdef INSTRUMENTATION
4248	m_cpt_dcache_data_read++;
4249	m_cpt_dcache_dir_read++;
4250	#endif
4251	r_dcache.read( r_dcache_dirty_paddr.read(),
4252	&pte,
4253	&way,
4254	&set,
4255	&word,
4256	&state );
4257
4258	assert( (state == CACHE_SLOT_STATE_VALID) and
4259	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4260
4261	// request CAS transaction to CMD_FSM
4262	r_dcache_dirty_way = way;
4263	r_dcache_dirty_set = set;
4264
4265	// check llsc reservation buffer
4266	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4267	r_dcache_llsc_valid = false;
4268
4269	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4270	r_dcache_vci_cas_req = true;
4271	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4272	r_dcache_vci_cas_old = pte;
4273	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4274	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4275
4276	#if DEBUG_DCACHE
4277	if ( m_debug_dcache_fsm )
4278	{
4279	std::cout << " <PROC " << name()
4280	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4281	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4282	<< " / PTE_VALUE = " << pte << std::dec
4283	<< " / SET = " << set
4284	<< " / WAY = " << way << std::endl;
4285	}
4286	#endif
4287	break;
4288	}
4289	///////////////////////
4290	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4291	// and return to IDLE state when response is received.
4292	// we don't care if the CAS is a failure:
4293	// - if the CAS is a success, the coherence mechanism
4294	// updates the local copy.
4295	// - if the CAS is a failure, we just retry the write.
4296	{
4297	// coherence request (from CC_RECEIVE FSM)
4298	if ( r_cc_receive_dcache_req.read() )
4299	{
4300	r_dcache_fsm = DCACHE_CC_CHECK;
4301	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4302	break;
4303	}
4304
4305	if ( r_vci_rsp_data_error.read() ) // bus error
4306	{
4307	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4308	std::cout << "This should not happen in this state" << std::endl;
4309	exit(0);
4310	}
4311	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4312	{
4313	vci_rsp_fifo_dcache_get = true;
4314	r_dcache_fsm = DCACHE_IDLE;
4315
4316	#if DEBUG_DCACHE
4317	if ( m_debug_dcache_fsm )
4318	{
4319	std::cout << " <PROC " << name()
4320	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4321	}
4322	#endif
4323	}
4324	break;
4325	}
4326	/////////////////////
4327	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4328	// handling coherence requests for DCACHE.
4329	// If there is a matching pending miss on the modified cache
4330	// line this is signaled in the r_dcache_miss inval flip-flop.
4331	// If the updated (or invalidated) cache line has copies in TLBs
4332	// these TLB copies are invalidated.
4333	// The return state is defined in r_dcache_fsm_cc_save
4334	{
4335	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4336	paddr_t mask = ~((m_dcache_words<<2)-1);
4337
4338
4339	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4340	// We switch the directory slot to EMPTY state
4341	// and reset r_icache_miss_clack if the cleanup ack
4342	// is matching a pending miss.
4343	{
4344
4345	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4346
4347	#ifdef INSTRUMENTATION
4348	m_cpt_dcache_dir_write++;
4349	#endif
4350	r_dcache.write_dir( 0,
4351	r_cc_receive_dcache_way.read(),
4352	r_cc_receive_dcache_set.read(),
4353	CACHE_SLOT_STATE_EMPTY);
4354
4355	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4356	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4357	r_dcache_miss_clack = false;
4358
4359	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4360	r_cc_receive_dcache_req = false;
4361	#if DEBUG_DCACHE
4362	if ( m_debug_dcache_fsm )
4363	{
4364	std::cout << " <PROC " << name()
4365	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4366	<< " set = " << r_cc_receive_dcache_set.read()
4367	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4368	}
4369	#endif
4370	}
4371	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4372	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4373	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4374	{
4375	// signaling matching
4376	r_dcache_miss_inval = true;
4377
4378	// in case of update, go to CC_UPDT
4379	// JUST TO POP THE FIFO
4380	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4381	{
4382	r_dcache_fsm = DCACHE_CC_UPDT;
4383	r_dcache_cc_word = r_cc_receive_word_idx.read();
4384	// just pop the fifo , don't write in icache
4385	r_dcache_cc_need_write = false;
4386	}
4387	// the request is dealt with
4388	else
4389	{
4390	r_cc_receive_dcache_req = false;
4391	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4392	}
4393
4394	#if DEBUG_DCACHE
4395	if ( m_debug_dcache_fsm )
4396	{
4397	std::cout << " <PROC " << name()
4398	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4399	<< " PADDR = " << std::hex << paddr << std::endl;
4400	}
4401	#endif
4402
4403	}
4404	else // no match
4405	{
4406	int state;
4407	size_t way;
4408	size_t set;
4409	size_t word;
4410
4411	#ifdef INSTRUMENTATION
4412	m_cpt_dcache_dir_read++;
4413	#endif
4414	r_dcache.read_dir( paddr,
4415	&state,
4416	&way,
4417	&set,
4418	&word ); // unused
4419
4420	r_dcache_cc_way = way;
4421	r_dcache_cc_set = set;
4422
4423	if ( state == CACHE_SLOT_STATE_VALID) // hit
4424	{
4425	// need to update the cache state
4426	r_dcache_cc_need_write = true;
4427	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4428	{
4429	r_dcache_fsm = DCACHE_CC_UPDT;
4430	r_dcache_cc_word = r_cc_receive_word_idx.read();
4431	}
4432	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4433	{
4434	r_dcache_fsm = DCACHE_CC_INVAL;
4435	}
4436	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4437	{
4438	r_dcache_fsm = DCACHE_CC_BROADCAST;
4439	}
4440	}
4441	else // miss
4442	{
4443	// multicast acknowledgement required in case of update
4444	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4445	{
4446	r_dcache_fsm = DCACHE_CC_UPDT;
4447	r_dcache_cc_word = r_cc_receive_word_idx.read();
4448	// just pop the fifo , don't write in icache
4449	r_dcache_cc_need_write = false;
4450	}
4451	else // No response needed
4452	{
4453	r_cc_receive_dcache_req = false;
4454	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4455	}
4456	}
4457
4458	#if DEBUG_DCACHE
4459	if ( m_debug_dcache_fsm )
4460	{
4461	std::cout << " <PROC " << name()
4462	<< " DCACHE_CC_CHECK> Coherence request received:"
4463	<< " PADDR = " << std::hex << paddr
4464	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4465	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4466	}
4467	#endif
4468	}
4469	break;
4470	}
4471	/////////////////////
4472	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4473	// after possible invalidation of copies in TLBs
4474	{
4475	size_t way = r_dcache_cc_way.read();
4476	size_t set = r_dcache_cc_set.read();
4477
4478	if (r_dcache_cc_need_write.read())
4479	{
4480	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4481	{
4482	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4483	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4484	r_dcache_tlb_inval_set = 0;
4485	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4486	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4487	break;
4488	}
4489	else
4490	{
4491	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4492	{
4493	r_itlb.reset();
4494	r_dtlb.reset();
4495	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4496
4497	#if DEBUG_DCACHE
4498	if ( m_debug_dcache_fsm )
4499	{
4500	std::cout << " <PROC " << name()
4501	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4502	}
4503	#endif
4504	}
4505
4506	r_dcache.write_dir( 0,
4507	way,
4508	set,
4509	CACHE_SLOT_STATE_EMPTY );
4510
4511	r_dcache_cc_need_write = false;
4512
4513	#if DEBUG_DCACHE
4514	if ( m_debug_dcache_fsm )
4515	{
4516	std::cout << " <PROC " << name()
4517	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4518	<< " / WAY = " << way
4519	<< " / SET = " << set << std::endl;
4520	}
4521	#endif
4522	}
4523	}
4524	// multicast acknowledgement
4525	// send a request to cc_send_fsm
4526	if(not r_dcache_cc_send_req.read()) // cc_send is available
4527	{
4528	// coherence request completed
4529	r_cc_receive_dcache_req = false;
4530	// request multicast acknowledgement
4531	r_dcache_cc_send_req = true;
4532	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4533	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4534
4535	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4536	}
4537	//else wait for previous cc_send request to be sent
4538	break;
4539	}
4540	///////////////////
4541	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4542	// after possible invalidation of copies in TLBs
4543	{
4544	size_t word = r_dcache_cc_word.read();
4545	size_t way = r_dcache_cc_way.read();
4546	size_t set = r_dcache_cc_set.read();
4547
4548	if (r_cc_receive_updt_fifo_be.rok())
4549	{
4550	if (r_dcache_cc_need_write.read())
4551	{
4552	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4553	{
4554	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4555	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4556	r_dcache_tlb_inval_set = 0;
4557	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4558	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4559	break;
4560	}
4561
4562	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4563	{
4564	r_itlb.reset();
4565	r_dtlb.reset();
4566	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4567
4568	#if DEBUG_DCACHE
4569	if ( m_debug_dcache_fsm )
4570	{
4571	std::cout << " <PROC " << name()
4572	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4573	}
4574	#endif
4575	}
4576
4577	#ifdef INSTRUMENTATION
4578	m_cpt_dcache_data_write++;
4579	#endif
4580	r_dcache.write( way,
4581	set,
4582	word,
4583	r_cc_receive_updt_fifo_data.read(),
4584	r_cc_receive_updt_fifo_be.read() );
4585
4586	r_dcache_cc_word = word + 1;
4587
4588	#if DEBUG_DCACHE
4589	if ( m_debug_dcache_fsm )
4590	{
4591	std::cout << " <PROC " << name()
4592	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4593	<< " / WAY = " << way
4594	<< " / SET = " << set
4595	<< " / WORD = " << word
4596	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4597	}
4598	#endif
4599	}
4600
4601	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4602	{
4603	// no need to write in the cache anymore
4604	r_dcache_cc_need_write = false;
4605
4606	// wait to send a request to cc_send_fsm
4607	if(not r_icache_cc_send_req.read())
4608	// cc_send is available
4609	{
4610	//consume last fifo flit if eop and request to cc_send possible
4611	cc_receive_updt_fifo_get = true;
4612
4613	// coherence request completed
4614	r_cc_receive_dcache_req = false;
4615
4616	// request multicast acknowledgement
4617	r_dcache_cc_send_req = true;
4618	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4619	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4620
4621	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4622	}
4623	}
4624	else
4625	{
4626	//consume fifo if not eop
4627	cc_receive_updt_fifo_get = true;
4628	}
4629	}
4630	break;
4631	}
4632	/////////////////////////
4633	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4634	// and request a cleanup, after possible
4635	// invalidation of copies in TLBs
4636	{
4637	size_t way = r_dcache_cc_way.read();
4638	size_t set = r_dcache_cc_set.read();
4639	paddr_t nline = r_cc_receive_dcache_nline.read();
4640
4641	if (r_dcache_cc_need_write.read())
4642	{
4643	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4644	{
4645	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4646	r_dcache_tlb_inval_line = nline;
4647	r_dcache_tlb_inval_set = 0;
4648	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4649	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4650	break;
4651	}
4652	else
4653	{
4654	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4655	{
4656	r_itlb.reset();
4657	r_dtlb.reset();
4658	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4659
4660	#if DEBUG_DCACHE
4661	if ( m_debug_dcache_fsm )
4662	{
4663	std::cout << " <PROC " << name()
4664	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4665	}
4666	#endif
4667	}
4668
4669	#ifdef INSTRUMENTATION
4670	m_cpt_dcache_dir_write++;
4671	#endif
4672	r_dcache.write_dir( 0,
4673	way,
4674	set,
4675	CACHE_SLOT_STATE_ZOMBI );
4676
4677	r_dcache_cc_need_write = false;
4678	#if DEBUG_DCACHE
4679	if ( m_debug_dcache_fsm )
4680	{
4681	std::cout << " <PROC " << name()
4682	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4683	<< " SET = " << set
4684	<< " / WAY = " << way << std::endl;
4685	}
4686	#endif
4687	}
4688	}
4689	// cleanup
4690	// send a request to cc_send_fsm
4691	if(not r_dcache_cc_send_req.read()) // cc_send is available
4692	{
4693	// coherence request completed
4694	r_cc_receive_dcache_req = false;
4695	// request cleanup
4696	r_dcache_cc_send_req = true;
4697	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4698	r_dcache_cc_send_way = r_dcache_cc_way.read();
4699	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4700
4701	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4702	}
4703	//else wait for previous cc_send request to be sent
4704	break;
4705	}
4706	///////////////////////////
4707	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4708	// It makes assumption: m_itlb_sets == m_dtlb_sets
4709	// All ways are handled in parallel.
4710	// We enter this state when a DCACHE line is modified,
4711	// and there is a copy in itlb or dtlb.
4712	// It can be caused by:
4713	// - a coherence inval or updt transaction,
4714	// - a line inval caused by a cache miss
4715	// - a processor XTN inval request,
4716	// - a WRITE hit,
4717	// - a Dirty bit update
4718	// Input arguments are:
4719	// - r_dcache_tlb_inval_line
4720	// - r_dcache_tlb_inval_set
4721	// - r_dcache_fsm_scan_save
4722	{
4723	paddr_t line = r_dcache_tlb_inval_line.read();
4724	size_t set = r_dcache_tlb_inval_set.read();
4725	size_t way;
4726	bool ok;
4727
4728	for ( way = 0 ; way < m_itlb_ways ; way++ )
4729	{
4730	ok = r_itlb.inval( line, way, set );
4731
4732	#if DEBUG_DCACHE
4733	if ( m_debug_dcache_fsm and ok )
4734	{
4735	std::cout << " <PROC " << name()
4736	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4737	<< " line = " << line << std::dec
4738	<< " / set = " << set
4739	<< " / way = " << way << std::endl;
4740	}
4741	#endif
4742	}
4743
4744	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4745	{
4746	ok = r_dtlb.inval( line, way, set );
4747
4748	#if DEBUG_DCACHE
4749	if ( m_debug_dcache_fsm and ok )
4750	{
4751	std::cout << " <PROC " << name()
4752	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4753	<< " line = " << line << std::dec
4754	<< " / set = " << set
4755	<< " / way = " << way << std::endl;
4756	}
4757	#endif
4758	}
4759
4760	// return to the calling state when TLB inval completed
4761	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4762	{
4763	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4764	}
4765	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4766	break;
4767	}
4768	} // end switch r_dcache_fsm
4769
4770	///////////////// wbuf update ///////////////////////////////////////////////////////
4771	r_wbuf.update();
4772
4773	///////////////// llsc update ///////////////////////////////////////////////////////
4774	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4775	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4776
4777	//////////////// test processor frozen //////////////////////////////////////////////
4778	// The simulation exit if the number of consecutive frozen cycles
4779	// is larger than the m_max_frozen_cycles (constructor parameter)
4780	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4781	{
4782	m_cpt_frz_cycles++; // used for instrumentation
4783	m_cpt_stop_simulation++; // used for debug
4784	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4785	{
4786	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4787	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4788	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4789	<< std::endl;
4790	r_iss.dump();
4791	exit(1);
4792	}
4793	}
4794	else
4795	{
4796	m_cpt_stop_simulation = 0;
4797	}
4798
4799	/////////// execute one iss cycle /////////////////////////////////
4800	{
4801	uint32_t it = 0;
4802	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4803	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4804	}
4805
4806	////////////////////////////////////////////////////////////////////////////
4807	// The VCI_CMD FSM controls the following ressources:
4808	// - r_vci_cmd_fsm
4809	// - r_vci_cmd_min
4810	// - r_vci_cmd_max
4811	// - r_vci_cmd_cpt
4812	// - r_vci_cmd_imiss_prio
4813	// - wbuf (reset)
4814	// - r_icache_miss_req (reset)
4815	// - r_icache_unc_req (reset)
4816	// - r_dcache_vci_miss_req (reset)
4817	// - r_dcache_vci_unc_req (reset)
4818	// - r_dcache_vci_ll_req (reset)
4819	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4820	// - r_dcache_vci_cas_req (reset)
4821	//
4822	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4823	// There are 8 request types, with the following priorities :
4824	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4825	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4826	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4827	// 4 - Instruction Uncachable : r_icache_unc_req
4828	// 5 - Data Write : r_wbuf.rok()
4829	// 6 - Data Linked Load : r_dcache_vci_ll_req
4830	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4831	// 8 - Compare And Swap : r_dcache_vci_cas_req
4832	//
4833	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4834	// and the VCI_RSP_FSM are fully desynchronized.
4835	//
4836	// VCI formats:
4837	// According to the VCI advanced specification, all read requests packets
4838	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4839	// are one word packets.
4840	// For write burst packets, all words are in the same cache line,
4841	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4842	// The sc command packet implements actually a compare-and-swap mechanism
4843	// and the packet contains two flits.
4844	////////////////////////////////////////////////////////////////////////////////////
4845
4846	switch ( r_vci_cmd_fsm.read() )
4847	{
4848	//////////////
4849	case CMD_IDLE:
4850	{
4851	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4852	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4853	// to check a possible pending write on the same cache line.
4854	// As there is only one possible access per cycle to write buffer, we implement
4855	// a round-robin priority between DCACHE and ICACHE for this access,
4856	// using the r_vci_cmd_imiss_prio flip-flop.
4857
4858	size_t wbuf_min;
4859	size_t wbuf_max;
4860
4861	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4862	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4863
4864	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4865	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4866
4867	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4868	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4869
4870	bool icache_miss_req = r_icache_miss_req.read() and
4871	( not (r_dcache_vci_miss_req.read() or
4872	r_dcache_vci_ll_req.read() or
4873	r_dcache_vci_unc_req.read())
4874	or r_vci_cmd_imiss_prio.read() ) ;
4875
4876	// 1 - Data Read Miss
4877	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4878	{
4879	r_vci_cmd_fsm = CMD_DATA_MISS;
4880	r_dcache_vci_miss_req = false;
4881	r_vci_cmd_imiss_prio = true;
4882	// m_cpt_dmiss_transaction++;
4883	}
4884	// 2 - Data Read Uncachable
4885	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4886	{
4887	r_vci_cmd_fsm = CMD_DATA_UNC;
4888	r_dcache_vci_unc_req = false;
4889	// m_cpt_dunc_transaction++;
4890	}
4891	// 3 - Data Linked Load
4892	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4893	{
4894	r_dcache_vci_ll_req = false;
4895	r_vci_cmd_fsm = CMD_DATA_LL;
4896	// m_cpt_ll_transaction++;
4897	}
4898	// 4 - Instruction Miss
4899	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4900	{
4901	r_vci_cmd_fsm = CMD_INS_MISS;
4902	r_icache_miss_req = false;
4903	r_vci_cmd_imiss_prio = false;
4904	// m_cpt_imiss_transaction++;
4905	}
4906	// 5 - Instruction Uncachable
4907	else if ( r_icache_unc_req.read() )
4908	{
4909	r_vci_cmd_fsm = CMD_INS_UNC;
4910	r_icache_unc_req = false;
4911	// m_cpt_iunc_transaction++;
4912	}
4913	// 6 - Data Write
4914	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4915	{
4916	r_vci_cmd_fsm = CMD_DATA_WRITE;
4917	r_vci_cmd_cpt = wbuf_min;
4918	r_vci_cmd_min = wbuf_min;
4919	r_vci_cmd_max = wbuf_max;
4920	// m_cpt_write_transaction++;
4921	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4922	}
4923	// 7 - Data Store Conditionnal
4924	else if ( r_dcache_vci_sc_req.read() )
4925	{
4926	r_dcache_vci_sc_req = false;
4927	r_vci_cmd_cpt = 0;
4928	r_vci_cmd_fsm = CMD_DATA_SC;
4929	// m_cpt_sc_transaction++;
4930	}
4931	// 8 - Compare And Swap
4932	else if ( r_dcache_vci_cas_req.read() )
4933	{
4934	r_vci_cmd_fsm = CMD_DATA_CAS;
4935	r_dcache_vci_cas_req = false;
4936	r_vci_cmd_cpt = 0;
4937	// m_cpt_cas_transaction++;
4938	}
4939	break;
4940	}
4941	////////////////////
4942	case CMD_DATA_WRITE:
4943	{
4944	if ( p_vci_ini_d.cmdack.read() )
4945	{
4946	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4947	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4948	{
4949	r_vci_cmd_fsm = CMD_IDLE ;
4950	r_wbuf.sent() ;
4951	}
4952	}
4953	break;
4954	}
4955	/////////////////
4956	case CMD_DATA_SC:
4957	case CMD_DATA_CAS:
4958	{
4959	// The CAS and SC VCI commands contain two flits
4960	if ( p_vci_ini_d.cmdack.read() )
4961	{
4962	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4963	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4964	}
4965	break;
4966	}
4967	//////////////////
4968	case CMD_INS_MISS:
4969	case CMD_INS_UNC:
4970	case CMD_DATA_MISS:
4971	case CMD_DATA_UNC:
4972	case CMD_DATA_LL:
4973	{
4974	// all read VCI commands contain one single flit
4975	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4976	break;
4977	}
4978
4979	} // end switch r_vci_cmd_fsm
4980
4981	//////////////////////////////////////////////////////////////////////////
4982	// The VCI_RSP FSM controls the following ressources:
4983	// - r_vci_rsp_fsm:
4984	// - r_vci_rsp_fifo_icache (push)
4985	// - r_vci_rsp_fifo_dcache (push)
4986	// - r_vci_rsp_data_error (set)
4987	// - r_vci_rsp_ins_error (set)
4988	// - r_vci_rsp_cpt
4989	// - r_dcache_vci_sc_req (reset when SC response recieved)
4990	//
4991	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4992	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4993	// to identify the transactions.
4994	//
4995	// VCI vormat:
4996	// This component checks the response packet length and accepts only
4997	// single word packets for write response packets.
4998	//
4999	// Error handling:
5000	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5001	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5002	// flip_flop and the error is signaled by the DCACHE FSM.
5003	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5004	// flip_flop and the error is signaled by the ICACHE FSM.
5005	// In case of Cleanup Error, the simulation stops with an error message...
5006	//////////////////////////////////////////////////////////////////////////
5007
5008	switch ( r_vci_rsp_fsm.read() )
5009	{
5010	//////////////
5011	case RSP_IDLE:
5012	{
5013	if ( p_vci_ini_d.rspval.read() )
5014	{
5015	r_vci_rsp_cpt = 0;
5016
5017	if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5018	{
5019	r_vci_rsp_fsm = RSP_DATA_UNC;
5020	}
5021	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5022	{
5023	r_vci_rsp_fsm = RSP_DATA_MISS;
5024	}
5025	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5026	{
5027	r_vci_rsp_fsm = RSP_INS_UNC;
5028	}
5029	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5030	{
5031	r_vci_rsp_fsm = RSP_INS_MISS;
5032	}
5033	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE )
5034	{
5035	r_vci_rsp_fsm = RSP_DATA_WRITE;
5036	}
5037	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS )
5038	{
5039	r_vci_rsp_fsm = RSP_DATA_UNC;
5040	}
5041	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL )
5042	{
5043	r_vci_rsp_fsm = RSP_DATA_LL;
5044	}
5045	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC )
5046	{
5047	r_vci_rsp_fsm = RSP_DATA_UNC;
5048	}
5049	else
5050	{
5051	assert(false and "Unexpected VCI response");
5052	}
5053	}
5054	break;
5055	}
5056	//////////////////
5057	case RSP_INS_MISS:
5058	{
5059	if ( p_vci_ini_d.rspval.read() )
5060	{
5061	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5062	{
5063	r_vci_rsp_ins_error = true;
5064	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5065	}
5066	else // no error reported
5067	{
5068	if ( r_vci_rsp_fifo_icache.wok() )
5069	{
5070	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5071	"The VCI response packet for instruction miss is too long" );
5072
5073	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5074	vci_rsp_fifo_icache_put = true,
5075	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5076	if ( p_vci_ini_d.reop.read() )
5077	{
5078	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5079	"The VCI response packet for instruction miss is too short");
5080
5081	r_vci_rsp_fsm = RSP_IDLE;
5082	}
5083	}
5084	}
5085	}
5086	break;
5087	}
5088	/////////////////
5089	case RSP_INS_UNC:
5090	{
5091	if (p_vci_ini_d.rspval.read() )
5092	{
5093	assert( p_vci_ini_d.reop.read() and
5094	"illegal VCI response packet for uncachable instruction");
5095
5096	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5097	{
5098	r_vci_rsp_ins_error = true;
5099	r_vci_rsp_fsm = RSP_IDLE;
5100	}
5101	else // no error reported
5102	{
5103	if ( r_vci_rsp_fifo_icache.wok())
5104	{
5105	vci_rsp_fifo_icache_put = true;
5106	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5107	r_vci_rsp_fsm = RSP_IDLE;
5108	}
5109	}
5110	}
5111	break;
5112	}
5113	///////////////////
5114	case RSP_DATA_MISS:
5115	{
5116	if ( p_vci_ini_d.rspval.read() )
5117	{
5118	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5119	{
5120	r_vci_rsp_data_error = true;
5121	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5122	}
5123	else // no error reported
5124	{
5125	if ( r_vci_rsp_fifo_dcache.wok() )
5126	{
5127	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5128	"The VCI response packet for data miss is too long");
5129
5130	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5131	vci_rsp_fifo_dcache_put = true,
5132	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5133	if ( p_vci_ini_d.reop.read() )
5134	{
5135	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5136	"The VCI response packet for data miss is too short");
5137
5138	r_vci_rsp_fsm = RSP_IDLE;
5139	}
5140	}
5141	}
5142	}
5143	break;
5144	}
5145	//////////////////
5146	case RSP_DATA_UNC:
5147	{
5148	if (p_vci_ini_d.rspval.read() )
5149	{
5150	assert( p_vci_ini_d.reop.read() and
5151	"illegal VCI response packet for uncachable read data");
5152
5153	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5154	{
5155	r_vci_rsp_data_error = true;
5156	r_vci_rsp_fsm = RSP_IDLE;
5157	}
5158	else // no error reported
5159	{
5160	if ( r_vci_rsp_fifo_dcache.wok())
5161	{
5162	vci_rsp_fifo_dcache_put = true;
5163	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5164	r_vci_rsp_fsm = RSP_IDLE;
5165	}
5166	}
5167	}
5168	break;
5169	}
5170	////////////////////
5171	case RSP_DATA_LL:
5172	{
5173	if ( p_vci_ini_d.rspval.read() )
5174	{
5175	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5176	{
5177	r_vci_rsp_data_error = true;
5178	r_vci_rsp_fsm = RSP_IDLE;
5179	}
5180	if (r_vci_rsp_cpt.read() == 0) //first flit
5181	{
5182	if(r_vci_rsp_fifo_dcache.wok())
5183	{
5184	assert(!p_vci_ini_d.reop.read() &&
5185	"illegal VCI response packet for LL");
5186	vci_rsp_fifo_dcache_put = true;
5187	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5188	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5189	}
5190	break;
5191	}
5192	else // last flit
5193	{
5194	if(r_vci_rsp_fifo_dcache.wok())
5195	{
5196	assert(p_vci_ini_d.reop.read() &&
5197	"illegal VCI response packet for LL");
5198	vci_rsp_fifo_dcache_put = true;
5199	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5200	r_vci_rsp_fsm = RSP_IDLE;
5201	}
5202	break;
5203	}
5204	}
5205	break;
5206	}
5207	////////////////////
5208	case RSP_DATA_WRITE:
5209	{
5210	if (p_vci_ini_d.rspval.read())
5211	{
5212	assert( p_vci_ini_d.reop.read() and
5213	"a VCI response packet must contain one flit for a write transaction");
5214
5215	r_vci_rsp_fsm = RSP_IDLE;
5216	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read();
5217	bool cacheable = r_wbuf.completed(wbuf_index);
5218	if ( not cacheable ) r_dcache_pending_unc_write = false;
5219	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5220	}
5221	break;
5222	}
5223	} // end switch r_vci_rsp_fsm
5224
5225	/////////////////////////////////////////////////////////////////////////////////////
5226	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5227	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5228	// and ICACHE FSM) that are served with a round-robin priority.
5229	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5230	// soon as the request has been sent.
5231	/////////////////////////////////////////////////////////////////////////////////////
5232	switch ( r_cc_send_fsm.read() )
5233	{
5234	///////////////////////////
5235	case CC_SEND_IDLE:
5236	{
5237	///////////////////////////////////////////////////////
5238	// handling round robin between icache and dcache : //
5239	// we first check for the last client and listen for //
5240	// a request of the other, then update the client //
5241	///////////////////////////////////////////////////////
5242	// r_cc_send_last_client : 0 dcache 1 icache
5243	bool update_last_client;
5244	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5245	{
5246	if(r_icache_cc_send_req.read()) // request from icache
5247	update_last_client = 1; // update last client to icache
5248	}
5249	else // last client was icache
5250	{
5251	if(r_dcache_cc_send_req.read()) // request from dcache
5252	update_last_client = 0; // update last client to dcache
5253	}
5254	r_cc_send_last_client = update_last_client;
5255
5256	// if there is an actual request
5257	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5258	{
5259	// test if the new client is dcache and has a cleanup request
5260	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5261	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5262	// test if the new client is dcache and has a multi acknowledgement request
5263	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5264	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5265	// test if the new client is icache and has a cleanup request
5266	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5267	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5268	// test if the new client is icache and has a multi acknowledgement request
5269	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5270	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5271	}
5272	break;
5273	}
5274	///////////////////////////
5275	case CC_SEND_CLEANUP_1:
5276	{
5277	// wait for the first flit to be consumed
5278	if(p_dspin_out.read.read())
5279	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5280
5281	break;
5282	}
5283	///////////////////////////
5284	case CC_SEND_CLEANUP_2:
5285	{
5286	assert( p_dspin_out.read.read() and
5287	"The interconnect should accept the second cleanup flit instantly" );
5288
5289	// wait for the second flit to be consumed
5290	if(p_dspin_out.read.read())
5291	{
5292	if(r_cc_send_last_client.read() == 0) // dcache active request
5293	r_dcache_cc_send_req = false; // reset dcache request
5294	else // icache active request
5295	r_icache_cc_send_req = false; // reset icache request
5296
5297	// go back to idle state
5298	r_cc_send_fsm = CC_SEND_IDLE;
5299	}
5300	break;
5301	}
5302	///////////////////////////
5303	case CC_SEND_MULTI_ACK:
5304	{
5305	// wait for the flit to be consumed
5306	if(p_dspin_out.read.read())
5307	{
5308	if(r_cc_send_last_client.read() == 0) // dcache active request
5309	r_dcache_cc_send_req = false; // reset dcache request
5310	else // icache active request
5311	r_icache_cc_send_req = false; // reset icache request
5312	// go back to idle state
5313	r_cc_send_fsm = CC_SEND_IDLE;
5314	}
5315	break;
5316	}
5317	} // end switch CC_SEND FSM
5318
5319	///////////////////////////////////////////////////////////////////////////////
5320	// C_RECEIVE FSM
5321	// This FSM receive all coherence packets on a DSPIN40 port.
5322	// There is 4 packet types:
5323	// - CC_DATA_INVAL : DCACHE invalidate request
5324	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5325	// - CC_INST_INVAL : ICACHE invalidate request
5326	// - CC_INST_UPDT : ICACHE update request (multi-words)
5327	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5328	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5329	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5330	//////////////////////////////////////////////////////////////////////////////
5331	switch( r_cc_receive_fsm.read() )
5332	{
5333	/////////////////////
5334	case CC_RECEIVE_IDLE:
5335	{
5336	// a coherence request has arrived
5337	if (p_dspin_in.write.read())
5338	{
5339	// initialize dspin received data
5340	uint64_t receive_data = p_dspin_in.data.read();
5341	// initialize coherence packet type
5342	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5343	// initialize data/ins flip_flop (0 data / 1 ins)
5344	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5345	// test for a broadcast
5346	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5347	{
5348	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5349	}
5350	// test for a CLACK
5351	else if (receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK)
5352	{
5353	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5354	}
5355	// test for a multi updt
5356	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5357	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5358	{
5359	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5360	}
5361	// test for a multi inval
5362	else
5363	{
5364	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5365	}
5366	}
5367	break;
5368	}
5369	//////////////////////
5370	case CC_RECEIVE_CLACK:
5371	{
5372	// initialize dspin received data
5373	uint64_t receive_data = p_dspin_in.data.read();
5374
5375	// for data CLACK, wait for dcache to take the request
5376	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5377	{
5378	// request dcache to handle the CLACK
5379	r_cc_receive_dcache_req = true;
5380	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5381	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5382	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5383	// get back to idle state
5384	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5385	break;
5386	}
5387	// for ins CLACK, wait for icache to take the request
5388	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5389	{
5390	// request icache to handle the CLACK
5391	r_cc_receive_icache_req = true;
5392	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5393	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5394	r_cc_receive_icache_type = CC_TYPE_CLACK;
5395	// get back to idle state
5396	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5397	break;
5398	}
5399	// keep waiting for the correct cache to accept the request
5400	break;
5401	}
5402	///////////////////////////////
5403	case CC_RECEIVE_BRDCAST_HEADER:
5404	{
5405	// no actual data in the HEADER, just skip to second flit
5406	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5407	break;
5408	}
5409	//////////////////////////////
5410	case CC_RECEIVE_BRDCAST_NLINE:
5411	{
5412	// initialize dspin received data
5413	uint64_t receive_data = p_dspin_in.data.read();
5414	// wait for both dcache and icache to take the request
5415	// TODO maybe we need to wait for both only to leave the state, but
5416	// not to actually post a request to an available cache => need a
5417	// flip_flop to check that ?
5418	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5419	{
5420	// request dcache to handle the BROADCAST
5421	r_cc_receive_dcache_req = true;
5422	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5423	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5424	// request icache to handle the BROADCAST
5425	r_cc_receive_icache_req = true;
5426	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5427	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5428	// get back to idle state
5429	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5430	break;
5431	}
5432	// keep waiting for the caches to accept the request
5433	break;
5434	}
5435	/////////////////////////////
5436	case CC_RECEIVE_INVAL_HEADER:
5437	{
5438	// sample updt tab index in the HEADER, than skip to second flit
5439	uint64_t receive_data = p_dspin_in.data.read();
5440	// for data INVAL, wait for dcache to take the request
5441	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5442	{
5443	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5444	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5445	break;
5446	}
5447	// for ins INVAL, wait for icache to take the request
5448	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5449	{
5450	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5451	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5452	break;
5453	}
5454	// keep waiting for the correct cache to accept the request
5455	break;
5456	}
5457	////////////////////////////
5458	case CC_RECEIVE_INVAL_NLINE:
5459	{
5460	// sample nline in the second flit
5461	uint64_t receive_data = p_dspin_in.data.read();
5462	// for data INVAL, wait for dcache to take the request
5463	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5464	{
5465	// request dcache to handle the INVAL
5466	r_cc_receive_dcache_req = true;
5467	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5468	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5469	// get back to idle state
5470	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5471	break;
5472	}
5473	// for ins INVAL, wait for icache to take the request
5474	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5475	{
5476	// request icache to handle the INVAL
5477	r_cc_receive_icache_req = true;
5478	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5479	r_cc_receive_icache_type = CC_TYPE_INVAL;
5480	// get back to idle state
5481	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5482	break;
5483	}
5484	// we should never get there
5485	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5486	}
5487	////////////////////////////
5488	case CC_RECEIVE_UPDT_HEADER:
5489	{
5490	// sample updt tab index in the HEADER, than skip to second flit
5491	uint64_t receive_data = p_dspin_in.data.read();
5492	// for data INVAL, wait for dcache to take the request and fifo to
5493	// be empty
5494	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5495	{
5496	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5497	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5498	break;
5499	}
5500	// for ins INVAL, wait for icache to take the request and fifo to be
5501	// empty
5502	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5503	{
5504	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5505	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5506	break;
5507	}
5508	// keep waiting for the correct cache to accept the request
5509	break;
5510	}
5511	///////////////////////////
5512	case CC_RECEIVE_UPDT_NLINE:
5513	{
5514	// sample nline and word index in the second flit
5515	uint64_t receive_data = p_dspin_in.data.read();
5516	// for data INVAL, wait for dcache to take the request and fifo to
5517	// be empty
5518	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5519	{
5520	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5521	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5522	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5523	// get back to idle state
5524	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5525	break;
5526	}
5527	// for ins INVAL, wait for icache to take the request and fifo to be
5528	// empty
5529	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5530	{
5531	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5532	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5533	r_cc_receive_icache_type = CC_TYPE_UPDT;
5534	// get back to idle state
5535	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5536	break;
5537	}
5538	// we should never get there
5539	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5540	break;
5541	}
5542	//////////////////////////
5543	case CC_RECEIVE_UPDT_DATA:
5544	{
5545	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5546	r_cc_receive_dcache_req = true;
5547	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5548	r_cc_receive_icache_req = true;
5549
5550	// sample data, be and eop
5551	uint64_t receive_data = p_dspin_in.data.read();
5552	// wait for the fifo
5553	if (r_cc_receive_updt_fifo_be.wok())
5554	{
5555	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5556	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5557	// sample eop to test for state exit
5558	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5559	cc_receive_updt_fifo_eop = flit_eop;
5560	cc_receive_updt_fifo_put = true;
5561	if(flit_eop)
5562	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5563	}
5564	break;
5565	}
5566	} // end switch CC_RECEIVE FSM
5567
5568	///////////////// Response FIFOs update //////////////////////
5569	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5570	vci_rsp_fifo_icache_put,
5571	vci_rsp_fifo_icache_data);
5572
5573	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5574	vci_rsp_fifo_dcache_put,
5575	vci_rsp_fifo_dcache_data);
5576	///////////////// updt FIFO update //////////////////////
5577	//TODO check this
5578	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5579	cc_receive_updt_fifo_put,
5580	cc_receive_updt_fifo_be);
5581	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5582	cc_receive_updt_fifo_put,
5583	cc_receive_updt_fifo_data);
5584	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5585	cc_receive_updt_fifo_put,
5586	cc_receive_updt_fifo_eop);
5587
5588	} // end transition()
5589
5590	///////////////////////
5591	tmpl(void)::genMoore()
5592	///////////////////////
5593	{
5594
5595	// VCI initiator command on the direct network
5596	// it depends on the CMD FSM state
5597
5598	p_vci_ini_d.pktid = 0;
5599	p_vci_ini_d.srcid = m_srcid_d;
5600	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5601	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5602	p_vci_ini_d.wrap = false;
5603	p_vci_ini_d.clen = 0;
5604	p_vci_ini_d.cfixed = false;
5605
5606	switch ( r_vci_cmd_fsm.read() ) {
5607
5608	case CMD_IDLE:
5609	p_vci_ini_d.cmdval = false;
5610	p_vci_ini_d.address = 0;
5611	p_vci_ini_d.wdata = 0;
5612	p_vci_ini_d.be = 0;
5613	p_vci_ini_d.trdid = 0;
5614	p_vci_ini_d.pktid = 0;
5615	p_vci_ini_d.plen = 0;
5616	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5617	p_vci_ini_d.eop = false;
5618	break;
5619
5620	case CMD_INS_MISS:
5621	p_vci_ini_d.cmdval = true;
5622	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5623	p_vci_ini_d.wdata = 0;
5624	p_vci_ini_d.be = 0xF;
5625	p_vci_ini_d.trdid = 0;
5626	p_vci_ini_d.pktid = TYPE_READ_INS_MISS;
5627	p_vci_ini_d.plen = m_icache_words<<2;
5628	p_vci_ini_d.cmd = vci_param::CMD_READ;
5629	p_vci_ini_d.eop = true;
5630	break;
5631
5632	case CMD_INS_UNC:
5633	p_vci_ini_d.cmdval = true;
5634	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
5635	p_vci_ini_d.wdata = 0;
5636	p_vci_ini_d.be = 0xF;
5637	p_vci_ini_d.trdid = 0;
5638	p_vci_ini_d.pktid = TYPE_READ_INS_UNC;
5639	p_vci_ini_d.plen = 4;
5640	p_vci_ini_d.cmd = vci_param::CMD_READ;
5641	p_vci_ini_d.eop = true;
5642	break;
5643
5644	case CMD_DATA_MISS:
5645	p_vci_ini_d.cmdval = true;
5646	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5647	p_vci_ini_d.wdata = 0;
5648	p_vci_ini_d.be = 0xF;
5649	p_vci_ini_d.trdid = 0;
5650	p_vci_ini_d.pktid = TYPE_READ_DATA_MISS;
5651	p_vci_ini_d.plen = m_dcache_words << 2;
5652	p_vci_ini_d.cmd = vci_param::CMD_READ;
5653	p_vci_ini_d.eop = true;
5654	break;
5655
5656	case CMD_DATA_UNC:
5657	p_vci_ini_d.cmdval = true;
5658	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5659	p_vci_ini_d.wdata = 0;
5660	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
5661	p_vci_ini_d.trdid = 0;
5662	p_vci_ini_d.pktid = TYPE_READ_DATA_UNC;
5663	p_vci_ini_d.plen = 4;
5664	p_vci_ini_d.cmd = vci_param::CMD_READ;
5665	p_vci_ini_d.eop = true;
5666	break;
5667
5668	case CMD_DATA_WRITE:
5669	p_vci_ini_d.cmdval = true;
5670	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5671	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5672	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5673	p_vci_ini_d.trdid = r_wbuf.getIndex();
5674	p_vci_ini_d.pktid = TYPE_WRITE;
5675	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5676	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
5677	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5678	break;
5679
5680	case CMD_DATA_LL:
5681	p_vci_ini_d.cmdval = true;
5682	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5683	p_vci_ini_d.wdata = 0;
5684	p_vci_ini_d.be = 0xF;
5685	p_vci_ini_d.trdid = 0;
5686	p_vci_ini_d.pktid = TYPE_LL;
5687	p_vci_ini_d.plen = 8;
5688	p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
5689	p_vci_ini_d.eop = true;
5690	break;
5691
5692	case CMD_DATA_SC:
5693	p_vci_ini_d.cmdval = true;
5694	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5695	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_llsc_key.read();
5696	else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
5697	p_vci_ini_d.be = 0xF;
5698	p_vci_ini_d.trdid = 0;
5699	p_vci_ini_d.pktid = TYPE_SC;
5700	p_vci_ini_d.plen = 8;
5701	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5702	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5703	break;
5704
5705	case CMD_DATA_CAS:
5706	p_vci_ini_d.cmdval = true;
5707	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5708	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
5709	else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
5710	p_vci_ini_d.be = 0xF;
5711	p_vci_ini_d.trdid = 0;
5712	p_vci_ini_d.pktid = TYPE_CAS;
5713	p_vci_ini_d.plen = 8;
5714	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5715	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5716	break;
5717	} // end switch r_vci_cmd_fsm
5718
5719	// VCI initiator response on the direct network
5720	// it depends on the VCI RSP state
5721
5722	switch (r_vci_rsp_fsm.read() )
5723	{
5724	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
5725	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5726	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5727	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5728	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5729	case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5730	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
5731	} // end switch r_vci_rsp_fsm
5732
5733	/////////////////
5734	// CC_SEND FSM //
5735	/////////////////
5736	uint64_t dspin_send_data = 0;
5737	switch ( r_cc_send_fsm.read() )
5738	{
5739	///////////////////////////
5740	case CC_SEND_IDLE:
5741	{
5742	p_dspin_out.write = false;
5743	break;
5744	}
5745	///////////////////////////
5746	case CC_SEND_CLEANUP_1:
5747	{
5748	// initialize dspin send data
5749	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP);
5750	DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID);
5751	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5752	// dcache active request
5753	if(r_cc_send_last_client.read() == 0)
5754	{
5755	// compute global id
5756	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5757	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5758	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5759
5760	DspinDhccpParam::dspin_set(dspin_send_data,
5761	global_id,
5762	DspinDhccpParam::CLEANUP_DEST);
5763
5764	DspinDhccpParam::dspin_set(dspin_send_data,
5765	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5766	DspinDhccpParam::CLEANUP_NLINE_MSB);
5767
5768	DspinDhccpParam::dspin_set(dspin_send_data,
5769	r_dcache_cc_send_way.read(),
5770	DspinDhccpParam::CLEANUP_WAY_INDEX);
5771
5772	DspinDhccpParam::dspin_set(dspin_send_data,
5773	DspinDhccpParam::TYPE_CLEANUP_DATA,
5774	DspinDhccpParam::FROM_L1_TYPE);
5775	}
5776	// icache active request
5777	else
5778	{
5779	// compute global id
5780	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5781	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5782	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5783
5784	DspinDhccpParam::dspin_set(dspin_send_data,
5785	global_id,
5786	DspinDhccpParam::CLEANUP_DEST);
5787
5788	DspinDhccpParam::dspin_set(dspin_send_data,
5789	r_icache_cc_send_nline.read() & 0x300000000ULL,
5790	DspinDhccpParam::CLEANUP_NLINE_MSB);
5791
5792	DspinDhccpParam::dspin_set(dspin_send_data,
5793	r_icache_cc_send_way.read(),
5794	DspinDhccpParam::CLEANUP_WAY_INDEX);
5795
5796	DspinDhccpParam::dspin_set(dspin_send_data,
5797	DspinDhccpParam::TYPE_CLEANUP_INST,
5798	DspinDhccpParam::FROM_L1_TYPE);
5799	}
5800	// send flit
5801	p_dspin_out.data = dspin_send_data;
5802	p_dspin_out.write = true;
5803	break;
5804	}
5805	///////////////////////////
5806	case CC_SEND_CLEANUP_2:
5807	{
5808	// initialize dspin send data
5809	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5810	// dcache active request
5811	if(r_cc_send_last_client.read() == 0)
5812	{
5813	DspinDhccpParam::dspin_set(dspin_send_data,
5814	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5815	DspinDhccpParam::CLEANUP_NLINE_LSB);
5816	}
5817	// icache active request
5818	else
5819	{
5820	DspinDhccpParam::dspin_set(dspin_send_data,
5821	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5822	DspinDhccpParam::CLEANUP_NLINE_LSB);
5823	}
5824	// send flit
5825	p_dspin_out.data = dspin_send_data;
5826	p_dspin_out.write = true;
5827	break;
5828	}
5829	///////////////////////////
5830	case CC_SEND_MULTI_ACK:
5831	{
5832	// initialize dspin send data
5833	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5834	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5835	DspinDhccpParam::dspin_set(dspin_send_data,
5836	DspinDhccpParam::TYPE_MULTI_ACK,
5837	DspinDhccpParam::FROM_L1_TYPE);
5838	// dcache active request
5839	if(r_cc_send_last_client.read() == 0)
5840	{
5841	// compute global id
5842	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5843	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5844	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5845
5846	DspinDhccpParam::dspin_set(dspin_send_data,
5847	global_id,
5848	DspinDhccpParam::MULTI_ACK_DEST);
5849
5850	DspinDhccpParam::dspin_set(dspin_send_data,
5851	r_dcache_cc_send_updt_tab_idx.read(),
5852	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5853	}
5854	// icache active request
5855	else
5856	{
5857	// compute global id
5858	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5859	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5860	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5861
5862	DspinDhccpParam::dspin_set(dspin_send_data,
5863	global_id,
5864	DspinDhccpParam::MULTI_ACK_DEST);
5865
5866	DspinDhccpParam::dspin_set(dspin_send_data,
5867	r_icache_cc_send_updt_tab_idx.read(),
5868	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5869	}
5870	// send flit
5871	p_dspin_out.data = dspin_send_data;
5872	p_dspin_out.write = true;
5873	break;
5874	}
5875	} // end switch CC_SEND FSM
5876
5877	////////////////////
5878	// CC_RECEIVE FSM //
5879	////////////////////
5880	switch( r_cc_receive_fsm.read() )
5881	{
5882	/////////////////////
5883	case CC_RECEIVE_IDLE:
5884	{
5885	p_dspin_in.read = false;
5886	break;
5887	}
5888	//////////////////////
5889	case CC_RECEIVE_CLACK:
5890	{
5891	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5892	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5893	p_dspin_in.read = true;
5894	else
5895	p_dspin_in.read = false;
5896	break;
5897	}
5898	///////////////////////////////
5899	case CC_RECEIVE_BRDCAST_HEADER:
5900	{
5901	p_dspin_in.read = true;
5902	break;
5903	}
5904	//////////////////////////////
5905	case CC_RECEIVE_BRDCAST_NLINE:
5906	{
5907	// TODO maybe we need to wait for both only to leave the state, but
5908	// not to actually post a request to an available cache => need a
5909	// flip_flop to check that ?
5910	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5911	p_dspin_in.read = true;
5912	else
5913	p_dspin_in.read = false;
5914	break;
5915	}
5916	/////////////////////////////
5917	case CC_RECEIVE_INVAL_HEADER:
5918	{
5919	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5920	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5921	p_dspin_in.read = true;
5922	else
5923	p_dspin_in.read = false;
5924	break;
5925	}
5926	////////////////////////////
5927	case CC_RECEIVE_INVAL_NLINE:
5928	{
5929	p_dspin_in.read = true;
5930	break;
5931	}
5932	////////////////////////////
5933	case CC_RECEIVE_UPDT_HEADER:
5934	{
5935	if (((r_cc_receive_data_ins.read() == 0) and
5936	not r_cc_receive_dcache_req.read() and
5937	r_cc_receive_updt_fifo_be.empty())
5938	or
5939	((r_cc_receive_data_ins.read() == 1) and
5940	not r_cc_receive_icache_req.read()) and
5941	r_cc_receive_updt_fifo_be.empty())
5942	p_dspin_in.read = true;
5943	else
5944	p_dspin_in.read = false;
5945	break;
5946	}
5947	///////////////////////////
5948	case CC_RECEIVE_UPDT_NLINE:
5949	{
5950	if (((r_cc_receive_data_ins.read() == 0) and
5951	not (r_cc_receive_dcache_req.read()) and
5952	r_cc_receive_updt_fifo_be.empty())
5953	or
5954	((r_cc_receive_data_ins.read() == 1) and
5955	not (r_cc_receive_icache_req.read()) and
5956	r_cc_receive_updt_fifo_be.empty()))
5957	p_dspin_in.read = true;
5958	else
5959	p_dspin_in.read = false;
5960	break;
5961	}
5962	//////////////////////////
5963	case CC_RECEIVE_UPDT_DATA:
5964	{
5965	if (r_cc_receive_updt_fifo_be.wok())
5966	p_dspin_in.read = true;
5967	else
5968	p_dspin_in.read = false;
5969	break;
5970	}
5971	} // end switch CC_RECEIVE FSM
5972
5973	} // end genMoore
5974
5975	}}
5976
5977	// Local Variables:
5978	// tab-width: 4
5979	// c-basic-offset: 4
5980	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5981	// indent-tabs-mode: nil
5982	// End:
5983
5984	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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