source: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 441

Last change on this file since 441 was 441, checked in by cfuguet, 11 years ago

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt
File size: 41.2 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define IVT_ENTRIES      4      // Number of entries in IVT
57#define HEAP_ENTRIES     1024   // Number of entries in HEAP
58
59namespace soclib {  namespace caba {
60
61  using namespace sc_core;
62
63  template<typename vci_param_int, 
64           typename vci_param_ext,
65           size_t   dspin_in_width,
66           size_t   dspin_out_width>
67    class VciMemCache
68    : public soclib::caba::BaseModule
69    {
70      typedef typename vci_param_int::fast_addr_t  addr_t;
71
72      typedef typename sc_dt::sc_uint<64>          wide_data_t;
73
74      typedef uint32_t data_t;
75      typedef uint32_t tag_t;
76      typedef uint32_t be_t;
77      typedef uint32_t copy_t;
78
79      /* States of the TGT_CMD fsm */
80      enum tgt_cmd_fsm_state_e
81      {
82        TGT_CMD_IDLE,
83        TGT_CMD_ERROR,
84        TGT_CMD_READ,
85        TGT_CMD_WRITE,
86        TGT_CMD_CAS,
87        TGT_CMD_CONFIG
88      };
89
90      /* States of the TGT_RSP fsm */
91      enum tgt_rsp_fsm_state_e
92      {
93        TGT_RSP_CONFIG_IDLE,
94        TGT_RSP_TGT_CMD_IDLE,
95        TGT_RSP_READ_IDLE,
96        TGT_RSP_WRITE_IDLE,
97        TGT_RSP_CAS_IDLE,
98        TGT_RSP_XRAM_IDLE,
99        TGT_RSP_MULTI_ACK_IDLE,
100        TGT_RSP_CLEANUP_IDLE,
101        TGT_RSP_CONFIG,
102        TGT_RSP_TGT_CMD,
103        TGT_RSP_READ,
104        TGT_RSP_WRITE,
105        TGT_RSP_CAS,
106        TGT_RSP_XRAM,
107        TGT_RSP_MULTI_ACK,
108        TGT_RSP_CLEANUP
109      };
110
111      /* States of the DSPIN_TGT fsm */
112      enum cc_receive_fsm_state_e
113      {
114        CC_RECEIVE_IDLE,
115        CC_RECEIVE_CLEANUP,
116        CC_RECEIVE_CLEANUP_EOP,
117        CC_RECEIVE_MULTI_ACK
118      };
119
120      /* States of the CC_SEND fsm */
121      enum cc_send_fsm_state_e
122      {
123        CC_SEND_CONFIG_IDLE,
124        CC_SEND_XRAM_RSP_IDLE,
125        CC_SEND_WRITE_IDLE,
126        CC_SEND_CAS_IDLE,
127        CC_SEND_CLEANUP_IDLE,
128        CC_SEND_CONFIG_INVAL_HEADER,
129        CC_SEND_CONFIG_INVAL_NLINE,
130        CC_SEND_CONFIG_BRDCAST_HEADER,
131        CC_SEND_CONFIG_BRDCAST_NLINE,
132        CC_SEND_CLEANUP_ACK,
133        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
134        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
135        CC_SEND_XRAM_RSP_INVAL_HEADER,
136        CC_SEND_XRAM_RSP_INVAL_NLINE,
137        CC_SEND_WRITE_BRDCAST_HEADER,
138        CC_SEND_WRITE_BRDCAST_NLINE,
139        CC_SEND_WRITE_UPDT_HEADER,
140        CC_SEND_WRITE_UPDT_NLINE,
141        CC_SEND_WRITE_UPDT_DATA,
142        CC_SEND_CAS_BRDCAST_HEADER,
143        CC_SEND_CAS_BRDCAST_NLINE,
144        CC_SEND_CAS_UPDT_HEADER,
145        CC_SEND_CAS_UPDT_NLINE,
146        CC_SEND_CAS_UPDT_DATA,
147        CC_SEND_CAS_UPDT_DATA_HIGH
148      };
149
150      /* States of the MULTI_ACK fsm */
151      enum multi_ack_fsm_state_e
152      {
153        MULTI_ACK_IDLE,
154        MULTI_ACK_UPT_LOCK,
155        MULTI_ACK_UPT_CLEAR,
156        MULTI_ACK_WRITE_RSP,
157        MULTI_ACK_CONFIG_ACK
158      };
159
160      /* States of the CONFIG fsm */
161      enum config_fsm_state_e
162      {
163        CONFIG_IDLE,
164        CONFIG_LOOP,
165        CONFIG_RSP,
166        CONFIG_DIR_REQ,
167        CONFIG_DIR_ACCESS,
168        CONFIG_DIR_IVT_LOCK,
169        CONFIG_BC_SEND,
170        CONFIG_BC_WAIT,
171        CONFIG_INV_SEND,
172        CONFIG_HEAP_REQ,
173        CONFIG_HEAP_SCAN,
174        CONFIG_HEAP_LAST,
175        CONFIG_INV_WAIT
176      };
177
178      /* States of the READ fsm */
179      enum read_fsm_state_e
180      {
181        READ_IDLE,
182        READ_DIR_REQ,
183        READ_DIR_LOCK,
184        READ_DIR_HIT,
185        READ_HEAP_REQ,
186        READ_HEAP_LOCK,
187        READ_HEAP_WRITE,
188        READ_HEAP_ERASE,
189        READ_HEAP_LAST,
190        READ_RSP,
191        READ_TRT_LOCK,
192        READ_TRT_SET,
193        READ_TRT_REQ
194      };
195
196      /* States of the WRITE fsm */
197      enum write_fsm_state_e
198      {
199        WRITE_IDLE,
200        WRITE_NEXT,
201        WRITE_DIR_REQ,
202        WRITE_DIR_LOCK,
203        WRITE_DIR_READ,
204        WRITE_DIR_HIT,
205        WRITE_UPT_LOCK,
206        WRITE_UPT_HEAP_LOCK,
207        WRITE_UPT_REQ,
208        WRITE_UPT_NEXT,
209        WRITE_UPT_DEC,
210        WRITE_RSP,
211        WRITE_MISS_TRT_LOCK,
212        WRITE_MISS_TRT_DATA,
213        WRITE_MISS_TRT_SET,
214        WRITE_MISS_XRAM_REQ,
215        WRITE_BC_TRT_LOCK,
216        WRITE_BC_IVT_LOCK,
217        WRITE_BC_DIR_INVAL,
218        WRITE_BC_CC_SEND,
219        WRITE_BC_XRAM_REQ,
220        WRITE_WAIT
221      };
222
223      /* States of the IXR_RSP fsm */
224      enum ixr_rsp_fsm_state_e
225      {
226        IXR_RSP_IDLE,
227        IXR_RSP_ACK,
228        IXR_RSP_TRT_ERASE,
229        IXR_RSP_TRT_READ
230      };
231
232      /* States of the XRAM_RSP fsm */
233      enum xram_rsp_fsm_state_e
234      {
235        XRAM_RSP_IDLE,
236        XRAM_RSP_TRT_COPY,
237        XRAM_RSP_TRT_DIRTY,
238        XRAM_RSP_DIR_LOCK,
239        XRAM_RSP_DIR_UPDT,
240        XRAM_RSP_DIR_RSP,
241        XRAM_RSP_INVAL_LOCK,
242        XRAM_RSP_INVAL_WAIT,
243        XRAM_RSP_INVAL,
244        XRAM_RSP_WRITE_DIRTY,
245        XRAM_RSP_HEAP_REQ,
246        XRAM_RSP_HEAP_ERASE,
247        XRAM_RSP_HEAP_LAST,
248        XRAM_RSP_ERROR_ERASE,
249        XRAM_RSP_ERROR_RSP
250      };
251
252      /* States of the IXR_CMD fsm */
253      enum ixr_cmd_fsm_state_e
254      {
255        IXR_CMD_READ_IDLE,
256        IXR_CMD_WRITE_IDLE,
257        IXR_CMD_CAS_IDLE,
258        IXR_CMD_XRAM_IDLE,
259        IXR_CMD_READ,
260        IXR_CMD_WRITE,
261        IXR_CMD_CAS,
262        IXR_CMD_XRAM
263      };
264
265      /* States of the CAS fsm */
266      enum cas_fsm_state_e
267      {
268        CAS_IDLE,
269        CAS_DIR_REQ,
270        CAS_DIR_LOCK,
271        CAS_DIR_HIT_READ,
272        CAS_DIR_HIT_COMPARE,
273        CAS_DIR_HIT_WRITE,
274        CAS_UPT_LOCK,
275        CAS_UPT_HEAP_LOCK,
276        CAS_UPT_REQ,
277        CAS_UPT_NEXT,
278        CAS_BC_TRT_LOCK,
279        CAS_BC_IVT_LOCK,
280        CAS_BC_DIR_INVAL,
281        CAS_BC_CC_SEND,
282        CAS_BC_XRAM_REQ,
283        CAS_RSP_FAIL,
284        CAS_RSP_SUCCESS,
285        CAS_MISS_TRT_LOCK,
286        CAS_MISS_TRT_SET,
287        CAS_MISS_XRAM_REQ,
288        CAS_WAIT
289      };
290
291      /* States of the CLEANUP fsm */
292      enum cleanup_fsm_state_e
293      {
294        CLEANUP_IDLE,
295        CLEANUP_GET_NLINE,
296        CLEANUP_DIR_REQ,
297        CLEANUP_DIR_LOCK,
298        CLEANUP_DIR_WRITE,
299        CLEANUP_HEAP_REQ,
300        CLEANUP_HEAP_LOCK,
301        CLEANUP_HEAP_SEARCH,
302        CLEANUP_HEAP_CLEAN,
303        CLEANUP_HEAP_FREE,
304        CLEANUP_IVT_LOCK,
305        CLEANUP_IVT_DECREMENT,
306        CLEANUP_IVT_CLEAR,
307        CLEANUP_WRITE_RSP,
308        CLEANUP_CONFIG_ACK,
309        CLEANUP_SEND_CLACK
310      };
311
312      /* States of the ALLOC_DIR fsm */
313      enum alloc_dir_fsm_state_e
314      {
315        ALLOC_DIR_RESET,
316        ALLOC_DIR_CONFIG,
317        ALLOC_DIR_READ,
318        ALLOC_DIR_WRITE,
319        ALLOC_DIR_CAS,
320        ALLOC_DIR_CLEANUP,
321        ALLOC_DIR_XRAM_RSP
322      };
323
324      /* States of the ALLOC_TRT fsm */
325      enum alloc_trt_fsm_state_e
326      {
327        ALLOC_TRT_READ,
328        ALLOC_TRT_WRITE,
329        ALLOC_TRT_CAS,
330        ALLOC_TRT_XRAM_RSP,
331        ALLOC_TRT_IXR_RSP
332      };
333
334      /* States of the ALLOC_UPT fsm */
335      enum alloc_upt_fsm_state_e
336      {
337        ALLOC_UPT_WRITE,
338        ALLOC_UPT_CAS,
339        ALLOC_UPT_MULTI_ACK
340      };
341
342      /* States of the ALLOC_IVT fsm */
343      enum alloc_ivt_fsm_state_e
344      {
345        ALLOC_IVT_WRITE,
346        ALLOC_IVT_XRAM_RSP,
347        ALLOC_IVT_CLEANUP,
348        ALLOC_IVT_CAS,
349        ALLOC_IVT_CONFIG
350      };
351
352      /* States of the ALLOC_HEAP fsm */
353      enum alloc_heap_fsm_state_e
354      {
355        ALLOC_HEAP_RESET,
356        ALLOC_HEAP_READ,
357        ALLOC_HEAP_WRITE,
358        ALLOC_HEAP_CAS,
359        ALLOC_HEAP_CLEANUP,
360        ALLOC_HEAP_XRAM_RSP,
361        ALLOC_HEAP_CONFIG
362      };
363
364      /* transaction type, pktid field */
365      enum transaction_type_e
366      {
367          // b3 unused
368          // b2 READ / NOT READ
369          // Si READ
370          //  b1 DATA / INS
371          //  b0 UNC / MISS
372          // Si NOT READ
373          //  b1 accÚs table llsc type SW / other
374          //  b2 WRITE/CAS/LL/SC
375          TYPE_READ_DATA_UNC          = 0x0,
376          TYPE_READ_DATA_MISS         = 0x1,
377          TYPE_READ_INS_UNC           = 0x2,
378          TYPE_READ_INS_MISS          = 0x3,
379          TYPE_WRITE                  = 0x4,
380          TYPE_CAS                    = 0x5,
381          TYPE_LL                     = 0x6,
382          TYPE_SC                     = 0x7
383      };
384
385      /* SC return values */
386      enum sc_status_type_e
387      {
388          SC_SUCCESS  =   0x00000000,
389          SC_FAIL     =   0x00000001
390      };
391
392      /* Configuration commands */
393      enum cmd_config_type_e
394      {
395          CMD_CONFIG_INVAL = 0,
396          CMD_CONFIG_SYNC  = 1
397      };
398
399      // debug variables (for each FSM)
400      bool         m_debug;
401      bool         m_debug_previous_hit;
402      size_t       m_debug_previous_count;
403
404      bool         m_monitor_ok;
405      addr_t       m_monitor_base;
406      addr_t       m_monitor_length;
407
408      // instrumentation counters
409      uint32_t     m_cpt_cycles;        // Counter of cycles
410
411      uint32_t     m_cpt_read;          // Number of READ transactions
412      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
413      uint32_t     m_cpt_read_flits;    // number of flits for READs
414      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
415
416      uint32_t     m_cpt_read_miss;     // Number of MISS READ
417
418      uint32_t     m_cpt_write;         // Number of WRITE transactions
419      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
420      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
421      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
422
423      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
424      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
425      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
426      uint32_t     m_cpt_update;        // Number of UPDATE transactions
427      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
428      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
429      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
430      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
431      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
432      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
433      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
434      uint32_t     m_cpt_ll;            // Number of LL transactions
435      uint32_t     m_cpt_sc;            // Number of SC transactions
436      uint32_t     m_cpt_cas;           // Number of CAS transactions
437
438      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
439
440      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
441      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
442
443      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
444
445      uint32_t     m_cpt_get;
446
447      uint32_t     m_cpt_put;
448
449      size_t       m_prev_count;
450
451      protected:
452
453      SC_HAS_PROCESS(VciMemCache);
454
455      public:
456      sc_in<bool>                                 p_clk;
457      sc_in<bool>                                 p_resetn;
458      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
459      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
460      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
461      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
462      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
463
464      VciMemCache(
465          sc_module_name name,                                // Instance Name
466          const soclib::common::MappingTable &mtp,            // Mapping table INT network
467          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
468          const soclib::common::IntTab       &srcid_x,        // global index RAM network
469          const soclib::common::IntTab       &tgtid_d,        // global index INT network
470          const size_t                       cc_global_id,    // global index CC network
471          const size_t                       nways,           // Number of ways per set
472          const size_t                       nsets,           // Number of sets
473          const size_t                       nwords,          // Number of words per line
474          const size_t                       max_copies,      // max number of copies
475          const size_t                       heap_size=HEAP_ENTRIES,
476          const size_t                       trt_lines=TRT_ENTRIES, 
477          const size_t                       upt_lines=UPT_ENTRIES,     
478          const size_t                       ivt_lines=IVT_ENTRIES,     
479          const size_t                       debug_start_cycle=0,
480          const bool                         debug_ok=false );
481
482      ~VciMemCache();
483
484      void print_stats();
485      void print_trace();
486      void copies_monitor(addr_t addr);
487      void start_monitor(addr_t addr, addr_t length);
488      void stop_monitor();
489
490      private:
491
492      void transition();
493      void genMoore();
494      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
495
496      // Component attributes
497      std::list<soclib::common::Segment> m_seglist;          // segments allocated
498      size_t                             m_nseg;             // number of segments
499      soclib::common::Segment            **m_seg;            // array of segments pointers
500      size_t                             m_seg_config;       // config segment index
501      const size_t                       m_srcid_x;          // global index on RAM network
502      const size_t                       m_initiators;       // Number of initiators
503      const size_t                       m_heap_size;        // Size of the heap
504      const size_t                       m_ways;             // Number of ways in a set
505      const size_t                       m_sets;             // Number of cache sets
506      const size_t                       m_words;            // Number of words in a line
507      const size_t                       m_cc_global_id;     // global_index on cc network
508      size_t                             m_debug_start_cycle;
509      bool                               m_debug_ok;
510      uint32_t                           m_trt_lines;
511      TransactionTab                     m_trt;              // xram transaction table
512      uint32_t                           m_upt_lines;
513      UpdateTab                          m_upt;              // pending update
514      UpdateTab                          m_ivt;              // pending invalidate
515      CacheDirectory                     m_cache_directory;  // data cache directory
516      CacheData                          m_cache_data;       // data array[set][way][word]
517      HeapDirectory                      m_heap;             // heap for copies
518      size_t                             m_max_copies;       // max number of copies in heap
519      GenericLLSCGlobalTable
520      < 32  ,    // number of slots
521        4096,    // number of processors in the system
522        8000,    // registration life (# of LL operations)
523        addr_t >                         m_llsc_table;       // ll/sc registration table
524
525      // adress masks
526      const soclib::common::AddressMaskingTable<addr_t>   m_x;
527      const soclib::common::AddressMaskingTable<addr_t>   m_y;
528      const soclib::common::AddressMaskingTable<addr_t>   m_z;
529      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
530
531      // broadcast address
532      uint32_t                           m_broadcast_boundaries;
533
534      //////////////////////////////////////////////////
535      // Registers controlled by the TGT_CMD fsm
536      //////////////////////////////////////////////////
537
538      sc_signal<int>         r_tgt_cmd_fsm;
539
540      // Fifo between TGT_CMD fsm and READ fsm
541      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
542      GenericFifo<size_t>    m_cmd_read_length_fifo;
543      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
544      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
545      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
546
547      // Fifo between TGT_CMD fsm and WRITE fsm
548      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
549      GenericFifo<bool>      m_cmd_write_eop_fifo;
550      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
551      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
552      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
553      GenericFifo<data_t>    m_cmd_write_data_fifo;
554      GenericFifo<be_t>      m_cmd_write_be_fifo;
555
556      // Fifo between TGT_CMD fsm and CAS fsm
557      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
558      GenericFifo<bool>      m_cmd_cas_eop_fifo;
559      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
560      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
561      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
562      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
563
564      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
565      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
566     
567      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
568      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
569
570      // Buffer between TGT_CMD fsm and TGT_RSP fsm
571      // (segmentation violation response request)
572      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
573
574      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
575      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
576      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
577      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
578      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
579
580      sc_signal<addr_t>   r_tgt_cmd_config_addr;
581      sc_signal<size_t>   r_tgt_cmd_config_cmd;
582
583      ///////////////////////////////////////////////////////
584      // Registers controlled by the CONFIG fsm
585      ///////////////////////////////////////////////////////
586
587      sc_signal<int>      r_config_fsm;            // FSM state
588      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
589      sc_signal<int>      r_config_cmd;            // config request status
590      sc_signal<addr_t>   r_config_address;        // target buffer physical address
591      sc_signal<size_t>   r_config_srcid;          // config request srcid
592      sc_signal<size_t>   r_config_trdid;          // config request trdid
593      sc_signal<size_t>   r_config_pktid;          // config request pktid
594      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
595      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
596      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
597      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
598      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
599      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
600      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
601      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
602
603      sc_signal<size_t>   r_config_ivt_index;      // IVT index
604
605      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
606      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
607      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
608      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
609      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
610      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
611
612      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
613      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
614      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
615      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
616      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
617      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
618      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
619
620#if L1_MULTI_CACHE
621      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
622#endif
623
624      ///////////////////////////////////////////////////////
625      // Registers controlled by the READ fsm
626      ///////////////////////////////////////////////////////
627
628      sc_signal<int>      r_read_fsm;          // FSM state
629      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
630      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
631      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
632      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
633      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
634      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
635      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
636      sc_signal<size_t>   r_read_count;        // number of copies
637      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
638      sc_signal<data_t> * r_read_data;         // data (one cache line)
639      sc_signal<size_t>   r_read_way;          // associative way (in cache)
640      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
641      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
642      sc_signal<bool>     r_read_last_free;    // Last free entry
643      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
644
645      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
646      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
647      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
648      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
649
650      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
651      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
652      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
653      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
654      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
655      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
656      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
657      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
658      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
659
660      ///////////////////////////////////////////////////////////////
661      // Registers controlled by the WRITE fsm
662      ///////////////////////////////////////////////////////////////
663
664      sc_signal<int>      r_write_fsm;        // FSM state
665      sc_signal<addr_t>   r_write_address;    // first word address
666      sc_signal<size_t>   r_write_word_index; // first word index in line
667      sc_signal<size_t>   r_write_word_count; // number of words in line
668      sc_signal<size_t>   r_write_srcid;      // transaction srcid
669      sc_signal<size_t>   r_write_trdid;      // transaction trdid
670      sc_signal<size_t>   r_write_pktid;      // transaction pktid
671      sc_signal<data_t> * r_write_data;       // data (one cache line)
672      sc_signal<be_t>   * r_write_be;         // one byte enable per word
673      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
674      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
675      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
676      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
677      sc_signal<size_t>   r_write_copy;       // first owner of the line
678      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
679      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
680      sc_signal<size_t>   r_write_count;      // number of copies
681      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
682      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
683      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
684      sc_signal<size_t>   r_write_way;        // way of the line
685      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
686      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
687      sc_signal<bool>     r_write_sc_fail;    // sc command failed
688      sc_signal<bool>     r_write_pending_sc; // sc command pending
689
690      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
691      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
692      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
693      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
694      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
695      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
696
697      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
698      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
699      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
700      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
701      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
702      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
703
704      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
705      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
706      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
707      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
708      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
709      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
710      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
711      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
712      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
713      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
714      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
715
716#if L1_MULTI_CACHE
717      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
718#endif
719
720      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
721      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
722      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
723
724      /////////////////////////////////////////////////////////
725      // Registers controlled by MULTI_ACK fsm
726      //////////////////////////////////////////////////////////
727
728      sc_signal<int>      r_multi_ack_fsm;       // FSM state
729      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
730      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
731      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
732      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
733      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
734
735      // signaling completion of multi-inval to CONFIG fsm
736      sc_signal<bool>     r_multi_ack_to_config_ack; 
737
738      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
739      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
740      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
741      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
742      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
743
744      ///////////////////////////////////////////////////////
745      // Registers controlled by CLEANUP fsm
746      ///////////////////////////////////////////////////////
747
748      sc_signal<int>      r_cleanup_fsm;           // FSM state
749      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
750      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
751      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
752      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
753
754#if L1_MULTI_CACHE
755      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
756#endif
757
758      sc_signal<copy_t>   r_cleanup_copy;          // first copy
759      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
760      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
761      sc_signal<copy_t>   r_cleanup_count;         // number of copies
762      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
763      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
764      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
765      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
766      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
767      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
768      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
769      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
770      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
771      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
772      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
773
774      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
775      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
776      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
777
778      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
779      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
780
781      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
782
783      // signaling completion of broadcast-inval to CONFIG fsm
784      sc_signal<bool>     r_cleanup_to_config_ack; 
785       
786      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
787      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
788      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
789      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
790      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
791
792      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
793      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
794      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
795      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
796      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
797      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
798
799      ///////////////////////////////////////////////////////
800      // Registers controlled by CAS fsm
801      ///////////////////////////////////////////////////////
802
803      sc_signal<int>      r_cas_fsm;        // FSM state
804      sc_signal<data_t>   r_cas_wdata;      // write data word
805      sc_signal<data_t> * r_cas_rdata;      // read data word
806      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
807      sc_signal<size_t>   r_cas_cpt;        // size of command
808      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
809      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
810      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
811      sc_signal<size_t>   r_cas_count;      // number of copies
812      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
813      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
814      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
815      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
816      sc_signal<size_t>   r_cas_way;        // way in directory
817      sc_signal<size_t>   r_cas_set;        // set in directory
818      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
819      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
820      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
821      sc_signal<data_t> * r_cas_data;       // cache line data
822
823      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
824      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
825      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
826      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
827      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
828      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
829
830
831      // Buffer between CAS fsm and TGT_RSP fsm
832      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
833      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
834      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
835      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
836      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
837
838      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
839      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
840      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
841      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
842      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
843      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
844      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
845      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
846      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
847      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
848      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
849
850#if L1_MULTI_CACHE
851      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
852#endif
853
854      ////////////////////////////////////////////////////
855      // Registers controlled by the IXR_RSP fsm
856      ////////////////////////////////////////////////////
857
858      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
859      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
860      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
861
862      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
863      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
864
865      ////////////////////////////////////////////////////
866      // Registers controlled by the XRAM_RSP fsm
867      ////////////////////////////////////////////////////
868
869      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
870      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
871      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
872      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
873      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
874      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
875      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
876      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
877      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
878      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
879      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
880      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
881      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
882      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
883      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
884      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
885      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
886
887      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
888      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
889      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
890      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
891      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
892      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
893      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
894      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
895      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
896      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
897
898      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
899      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
900      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
901      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
902      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
903      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
904      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
905
906#if L1_MULTI_CACHE
907      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
908#endif
909
910      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
911      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
912      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
913      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
914      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
915
916      ////////////////////////////////////////////////////
917      // Registers controlled by the IXR_CMD fsm
918      ////////////////////////////////////////////////////
919
920      sc_signal<int>      r_ixr_cmd_fsm;
921      sc_signal<size_t>   r_ixr_cmd_cpt;
922
923      ////////////////////////////////////////////////////
924      // Registers controlled by TGT_RSP fsm
925      ////////////////////////////////////////////////////
926
927      sc_signal<int>      r_tgt_rsp_fsm;
928      sc_signal<size_t>   r_tgt_rsp_cpt;
929      sc_signal<bool>     r_tgt_rsp_key_sent;
930
931      ////////////////////////////////////////////////////
932      // Registers controlled by CC_SEND fsm
933      ////////////////////////////////////////////////////
934
935      sc_signal<int>      r_cc_send_fsm;
936      sc_signal<size_t>   r_cc_send_cpt;
937      sc_signal<bool>     r_cc_send_inst;
938
939      ////////////////////////////////////////////////////
940      // Registers controlled by CC_RECEIVE fsm
941      ////////////////////////////////////////////////////
942
943      sc_signal<int>      r_cc_receive_fsm;
944
945      ////////////////////////////////////////////////////
946      // Registers controlled by ALLOC_DIR fsm
947      ////////////////////////////////////////////////////
948
949      sc_signal<int>      r_alloc_dir_fsm;
950      sc_signal<unsigned> r_alloc_dir_reset_cpt;
951
952      ////////////////////////////////////////////////////
953      // Registers controlled by ALLOC_TRT fsm
954      ////////////////////////////////////////////////////
955
956      sc_signal<int>      r_alloc_trt_fsm;
957
958      ////////////////////////////////////////////////////
959      // Registers controlled by ALLOC_UPT fsm
960      ////////////////////////////////////////////////////
961
962      sc_signal<int>      r_alloc_upt_fsm;
963
964      ////////////////////////////////////////////////////
965      // Registers controlled by ALLOC_IVT fsm
966      ////////////////////////////////////////////////////
967
968      sc_signal<int>      r_alloc_ivt_fsm;
969
970      ////////////////////////////////////////////////////
971      // Registers controlled by ALLOC_HEAP fsm
972      ////////////////////////////////////////////////////
973
974      sc_signal<int>      r_alloc_heap_fsm;
975      sc_signal<unsigned> r_alloc_heap_reset_cpt;
976    }; // end class VciMemCache
977
978}}
979
980#endif
981
982// Local Variables:
983// tab-width: 2
984// c-basic-offset: 2
985// c-file-offsets:((innamespace . 0)(inline-open . 0))
986// indent-tabs-mode: nil
987// End:
988
989// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
990
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