source: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 445

Last change on this file since 445 was 442, checked in by cfuguet, 11 years ago

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port
File size: 40.7 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define IVT_ENTRIES      4      // Number of entries in IVT
57#define HEAP_ENTRIES     1024   // Number of entries in HEAP
58
59namespace soclib {  namespace caba {
60
61  using namespace sc_core;
62
63  template<typename vci_param_int, 
64           typename vci_param_ext,
65           size_t   dspin_in_width,
66           size_t   dspin_out_width>
67    class VciMemCache
68    : public soclib::caba::BaseModule
69    {
70      typedef typename vci_param_int::fast_addr_t  addr_t;
71
72      typedef typename sc_dt::sc_uint<64>          wide_data_t;
73
74      typedef uint32_t data_t;
75      typedef uint32_t tag_t;
76      typedef uint32_t be_t;
77      typedef uint32_t copy_t;
78
79      /* States of the TGT_CMD fsm */
80      enum tgt_cmd_fsm_state_e
81      {
82        TGT_CMD_IDLE,
83        TGT_CMD_ERROR,
84        TGT_CMD_READ,
85        TGT_CMD_WRITE,
86        TGT_CMD_CAS,
87        TGT_CMD_CONFIG
88      };
89
90      /* States of the TGT_RSP fsm */
91      enum tgt_rsp_fsm_state_e
92      {
93        TGT_RSP_CONFIG_IDLE,
94        TGT_RSP_TGT_CMD_IDLE,
95        TGT_RSP_READ_IDLE,
96        TGT_RSP_WRITE_IDLE,
97        TGT_RSP_CAS_IDLE,
98        TGT_RSP_XRAM_IDLE,
99        TGT_RSP_MULTI_ACK_IDLE,
100        TGT_RSP_CLEANUP_IDLE,
101        TGT_RSP_CONFIG,
102        TGT_RSP_TGT_CMD,
103        TGT_RSP_READ,
104        TGT_RSP_WRITE,
105        TGT_RSP_CAS,
106        TGT_RSP_XRAM,
107        TGT_RSP_MULTI_ACK,
108        TGT_RSP_CLEANUP
109      };
110
111      /* States of the DSPIN_TGT fsm */
112      enum cc_receive_fsm_state_e
113      {
114        CC_RECEIVE_IDLE,
115        CC_RECEIVE_CLEANUP,
116        CC_RECEIVE_CLEANUP_EOP,
117        CC_RECEIVE_MULTI_ACK
118      };
119
120      /* States of the CC_SEND fsm */
121      enum cc_send_fsm_state_e
122      {
123        CC_SEND_CONFIG_IDLE,
124        CC_SEND_XRAM_RSP_IDLE,
125        CC_SEND_WRITE_IDLE,
126        CC_SEND_CAS_IDLE,
127        CC_SEND_CONFIG_INVAL_HEADER,
128        CC_SEND_CONFIG_INVAL_NLINE,
129        CC_SEND_CONFIG_BRDCAST_HEADER,
130        CC_SEND_CONFIG_BRDCAST_NLINE,
131        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
132        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
133        CC_SEND_XRAM_RSP_INVAL_HEADER,
134        CC_SEND_XRAM_RSP_INVAL_NLINE,
135        CC_SEND_WRITE_BRDCAST_HEADER,
136        CC_SEND_WRITE_BRDCAST_NLINE,
137        CC_SEND_WRITE_UPDT_HEADER,
138        CC_SEND_WRITE_UPDT_NLINE,
139        CC_SEND_WRITE_UPDT_DATA,
140        CC_SEND_CAS_BRDCAST_HEADER,
141        CC_SEND_CAS_BRDCAST_NLINE,
142        CC_SEND_CAS_UPDT_HEADER,
143        CC_SEND_CAS_UPDT_NLINE,
144        CC_SEND_CAS_UPDT_DATA,
145        CC_SEND_CAS_UPDT_DATA_HIGH
146      };
147
148      /* States of the MULTI_ACK fsm */
149      enum multi_ack_fsm_state_e
150      {
151        MULTI_ACK_IDLE,
152        MULTI_ACK_UPT_LOCK,
153        MULTI_ACK_UPT_CLEAR,
154        MULTI_ACK_WRITE_RSP,
155        MULTI_ACK_CONFIG_ACK
156      };
157
158      /* States of the CONFIG fsm */
159      enum config_fsm_state_e
160      {
161        CONFIG_IDLE,
162        CONFIG_LOOP,
163        CONFIG_RSP,
164        CONFIG_DIR_REQ,
165        CONFIG_DIR_ACCESS,
166        CONFIG_DIR_IVT_LOCK,
167        CONFIG_BC_SEND,
168        CONFIG_BC_WAIT,
169        CONFIG_INV_SEND,
170        CONFIG_HEAP_REQ,
171        CONFIG_HEAP_SCAN,
172        CONFIG_HEAP_LAST,
173        CONFIG_INV_WAIT
174      };
175
176      /* States of the READ fsm */
177      enum read_fsm_state_e
178      {
179        READ_IDLE,
180        READ_DIR_REQ,
181        READ_DIR_LOCK,
182        READ_DIR_HIT,
183        READ_HEAP_REQ,
184        READ_HEAP_LOCK,
185        READ_HEAP_WRITE,
186        READ_HEAP_ERASE,
187        READ_HEAP_LAST,
188        READ_RSP,
189        READ_TRT_LOCK,
190        READ_TRT_SET,
191        READ_TRT_REQ
192      };
193
194      /* States of the WRITE fsm */
195      enum write_fsm_state_e
196      {
197        WRITE_IDLE,
198        WRITE_NEXT,
199        WRITE_DIR_REQ,
200        WRITE_DIR_LOCK,
201        WRITE_DIR_READ,
202        WRITE_DIR_HIT,
203        WRITE_UPT_LOCK,
204        WRITE_UPT_HEAP_LOCK,
205        WRITE_UPT_REQ,
206        WRITE_UPT_NEXT,
207        WRITE_UPT_DEC,
208        WRITE_RSP,
209        WRITE_MISS_TRT_LOCK,
210        WRITE_MISS_TRT_DATA,
211        WRITE_MISS_TRT_SET,
212        WRITE_MISS_XRAM_REQ,
213        WRITE_BC_TRT_LOCK,
214        WRITE_BC_IVT_LOCK,
215        WRITE_BC_DIR_INVAL,
216        WRITE_BC_CC_SEND,
217        WRITE_BC_XRAM_REQ,
218        WRITE_WAIT
219      };
220
221      /* States of the IXR_RSP fsm */
222      enum ixr_rsp_fsm_state_e
223      {
224        IXR_RSP_IDLE,
225        IXR_RSP_ACK,
226        IXR_RSP_TRT_ERASE,
227        IXR_RSP_TRT_READ
228      };
229
230      /* States of the XRAM_RSP fsm */
231      enum xram_rsp_fsm_state_e
232      {
233        XRAM_RSP_IDLE,
234        XRAM_RSP_TRT_COPY,
235        XRAM_RSP_TRT_DIRTY,
236        XRAM_RSP_DIR_LOCK,
237        XRAM_RSP_DIR_UPDT,
238        XRAM_RSP_DIR_RSP,
239        XRAM_RSP_INVAL_LOCK,
240        XRAM_RSP_INVAL_WAIT,
241        XRAM_RSP_INVAL,
242        XRAM_RSP_WRITE_DIRTY,
243        XRAM_RSP_HEAP_REQ,
244        XRAM_RSP_HEAP_ERASE,
245        XRAM_RSP_HEAP_LAST,
246        XRAM_RSP_ERROR_ERASE,
247        XRAM_RSP_ERROR_RSP
248      };
249
250      /* States of the IXR_CMD fsm */
251      enum ixr_cmd_fsm_state_e
252      {
253        IXR_CMD_READ_IDLE,
254        IXR_CMD_WRITE_IDLE,
255        IXR_CMD_CAS_IDLE,
256        IXR_CMD_XRAM_IDLE,
257        IXR_CMD_READ,
258        IXR_CMD_WRITE,
259        IXR_CMD_CAS,
260        IXR_CMD_XRAM
261      };
262
263      /* States of the CAS fsm */
264      enum cas_fsm_state_e
265      {
266        CAS_IDLE,
267        CAS_DIR_REQ,
268        CAS_DIR_LOCK,
269        CAS_DIR_HIT_READ,
270        CAS_DIR_HIT_COMPARE,
271        CAS_DIR_HIT_WRITE,
272        CAS_UPT_LOCK,
273        CAS_UPT_HEAP_LOCK,
274        CAS_UPT_REQ,
275        CAS_UPT_NEXT,
276        CAS_BC_TRT_LOCK,
277        CAS_BC_IVT_LOCK,
278        CAS_BC_DIR_INVAL,
279        CAS_BC_CC_SEND,
280        CAS_BC_XRAM_REQ,
281        CAS_RSP_FAIL,
282        CAS_RSP_SUCCESS,
283        CAS_MISS_TRT_LOCK,
284        CAS_MISS_TRT_SET,
285        CAS_MISS_XRAM_REQ,
286        CAS_WAIT
287      };
288
289      /* States of the CLEANUP fsm */
290      enum cleanup_fsm_state_e
291      {
292        CLEANUP_IDLE,
293        CLEANUP_GET_NLINE,
294        CLEANUP_DIR_REQ,
295        CLEANUP_DIR_LOCK,
296        CLEANUP_DIR_WRITE,
297        CLEANUP_HEAP_REQ,
298        CLEANUP_HEAP_LOCK,
299        CLEANUP_HEAP_SEARCH,
300        CLEANUP_HEAP_CLEAN,
301        CLEANUP_HEAP_FREE,
302        CLEANUP_IVT_LOCK,
303        CLEANUP_IVT_DECREMENT,
304        CLEANUP_IVT_CLEAR,
305        CLEANUP_WRITE_RSP,
306        CLEANUP_CONFIG_ACK,
307        CLEANUP_SEND_CLACK
308      };
309
310      /* States of the ALLOC_DIR fsm */
311      enum alloc_dir_fsm_state_e
312      {
313        ALLOC_DIR_RESET,
314        ALLOC_DIR_CONFIG,
315        ALLOC_DIR_READ,
316        ALLOC_DIR_WRITE,
317        ALLOC_DIR_CAS,
318        ALLOC_DIR_CLEANUP,
319        ALLOC_DIR_XRAM_RSP
320      };
321
322      /* States of the ALLOC_TRT fsm */
323      enum alloc_trt_fsm_state_e
324      {
325        ALLOC_TRT_READ,
326        ALLOC_TRT_WRITE,
327        ALLOC_TRT_CAS,
328        ALLOC_TRT_XRAM_RSP,
329        ALLOC_TRT_IXR_RSP
330      };
331
332      /* States of the ALLOC_UPT fsm */
333      enum alloc_upt_fsm_state_e
334      {
335        ALLOC_UPT_WRITE,
336        ALLOC_UPT_CAS,
337        ALLOC_UPT_MULTI_ACK
338      };
339
340      /* States of the ALLOC_IVT fsm */
341      enum alloc_ivt_fsm_state_e
342      {
343        ALLOC_IVT_WRITE,
344        ALLOC_IVT_XRAM_RSP,
345        ALLOC_IVT_CLEANUP,
346        ALLOC_IVT_CAS,
347        ALLOC_IVT_CONFIG
348      };
349
350      /* States of the ALLOC_HEAP fsm */
351      enum alloc_heap_fsm_state_e
352      {
353        ALLOC_HEAP_RESET,
354        ALLOC_HEAP_READ,
355        ALLOC_HEAP_WRITE,
356        ALLOC_HEAP_CAS,
357        ALLOC_HEAP_CLEANUP,
358        ALLOC_HEAP_XRAM_RSP,
359        ALLOC_HEAP_CONFIG
360      };
361
362      /* transaction type, pktid field */
363      enum transaction_type_e
364      {
365          // b3 unused
366          // b2 READ / NOT READ
367          // Si READ
368          //  b1 DATA / INS
369          //  b0 UNC / MISS
370          // Si NOT READ
371          //  b1 accÚs table llsc type SW / other
372          //  b2 WRITE/CAS/LL/SC
373          TYPE_READ_DATA_UNC          = 0x0,
374          TYPE_READ_DATA_MISS         = 0x1,
375          TYPE_READ_INS_UNC           = 0x2,
376          TYPE_READ_INS_MISS          = 0x3,
377          TYPE_WRITE                  = 0x4,
378          TYPE_CAS                    = 0x5,
379          TYPE_LL                     = 0x6,
380          TYPE_SC                     = 0x7
381      };
382
383      /* SC return values */
384      enum sc_status_type_e
385      {
386          SC_SUCCESS  =   0x00000000,
387          SC_FAIL     =   0x00000001
388      };
389
390      /* Configuration commands */
391      enum cmd_config_type_e
392      {
393          CMD_CONFIG_INVAL = 0,
394          CMD_CONFIG_SYNC  = 1
395      };
396
397      // debug variables (for each FSM)
398      bool         m_debug;
399      bool         m_debug_previous_hit;
400      size_t       m_debug_previous_count;
401
402      bool         m_monitor_ok;
403      addr_t       m_monitor_base;
404      addr_t       m_monitor_length;
405
406      // instrumentation counters
407      uint32_t     m_cpt_cycles;        // Counter of cycles
408
409      uint32_t     m_cpt_read;          // Number of READ transactions
410      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
411      uint32_t     m_cpt_read_flits;    // number of flits for READs
412      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
413
414      uint32_t     m_cpt_read_miss;     // Number of MISS READ
415
416      uint32_t     m_cpt_write;         // Number of WRITE transactions
417      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
418      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
419      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
420
421      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
422      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
423      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
424      uint32_t     m_cpt_update;        // Number of UPDATE transactions
425      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
426      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
427      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
428      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
429      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
430      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
431      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
432      uint32_t     m_cpt_ll;            // Number of LL transactions
433      uint32_t     m_cpt_sc;            // Number of SC transactions
434      uint32_t     m_cpt_cas;           // Number of CAS transactions
435
436      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
437
438      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
439      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
440
441      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
442
443      uint32_t     m_cpt_get;
444
445      uint32_t     m_cpt_put;
446
447      size_t       m_prev_count;
448
449      protected:
450
451      SC_HAS_PROCESS(VciMemCache);
452
453      public:
454      sc_in<bool>                                 p_clk;
455      sc_in<bool>                                 p_resetn;
456      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
457      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
458      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
459      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
460      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
461
462      VciMemCache(
463          sc_module_name name,                                // Instance Name
464          const soclib::common::MappingTable &mtp,            // Mapping table INT network
465          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
466          const soclib::common::IntTab       &srcid_x,        // global index RAM network
467          const soclib::common::IntTab       &tgtid_d,        // global index INT network
468          const size_t                       cc_global_id,    // global index CC network
469          const size_t                       nways,           // Number of ways per set
470          const size_t                       nsets,           // Number of sets
471          const size_t                       nwords,          // Number of words per line
472          const size_t                       max_copies,      // max number of copies
473          const size_t                       heap_size=HEAP_ENTRIES,
474          const size_t                       trt_lines=TRT_ENTRIES, 
475          const size_t                       upt_lines=UPT_ENTRIES,     
476          const size_t                       ivt_lines=IVT_ENTRIES,     
477          const size_t                       debug_start_cycle=0,
478          const bool                         debug_ok=false );
479
480      ~VciMemCache();
481
482      void print_stats();
483      void print_trace();
484      void copies_monitor(addr_t addr);
485      void start_monitor(addr_t addr, addr_t length);
486      void stop_monitor();
487
488      private:
489
490      void transition();
491      void genMoore();
492      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
493
494      // Component attributes
495      std::list<soclib::common::Segment> m_seglist;          // segments allocated
496      size_t                             m_nseg;             // number of segments
497      soclib::common::Segment            **m_seg;            // array of segments pointers
498      size_t                             m_seg_config;       // config segment index
499      const size_t                       m_srcid_x;          // global index on RAM network
500      const size_t                       m_initiators;       // Number of initiators
501      const size_t                       m_heap_size;        // Size of the heap
502      const size_t                       m_ways;             // Number of ways in a set
503      const size_t                       m_sets;             // Number of cache sets
504      const size_t                       m_words;            // Number of words in a line
505      const size_t                       m_cc_global_id;     // global_index on cc network
506      size_t                             m_debug_start_cycle;
507      bool                               m_debug_ok;
508      uint32_t                           m_trt_lines;
509      TransactionTab                     m_trt;              // xram transaction table
510      uint32_t                           m_upt_lines;
511      UpdateTab                          m_upt;              // pending update
512      UpdateTab                          m_ivt;              // pending invalidate
513      CacheDirectory                     m_cache_directory;  // data cache directory
514      CacheData                          m_cache_data;       // data array[set][way][word]
515      HeapDirectory                      m_heap;             // heap for copies
516      size_t                             m_max_copies;       // max number of copies in heap
517      GenericLLSCGlobalTable
518      < 32  ,    // number of slots
519        4096,    // number of processors in the system
520        8000,    // registration life (# of LL operations)
521        addr_t >                         m_llsc_table;       // ll/sc registration table
522
523      // adress masks
524      const soclib::common::AddressMaskingTable<addr_t>   m_x;
525      const soclib::common::AddressMaskingTable<addr_t>   m_y;
526      const soclib::common::AddressMaskingTable<addr_t>   m_z;
527      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
528
529      // broadcast address
530      uint32_t                           m_broadcast_boundaries;
531
532      //////////////////////////////////////////////////
533      // Registers controlled by the TGT_CMD fsm
534      //////////////////////////////////////////////////
535
536      sc_signal<int>         r_tgt_cmd_fsm;
537
538      // Fifo between TGT_CMD fsm and READ fsm
539      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
540      GenericFifo<size_t>    m_cmd_read_length_fifo;
541      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
542      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
543      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
544
545      // Fifo between TGT_CMD fsm and WRITE fsm
546      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
547      GenericFifo<bool>      m_cmd_write_eop_fifo;
548      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
549      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
550      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
551      GenericFifo<data_t>    m_cmd_write_data_fifo;
552      GenericFifo<be_t>      m_cmd_write_be_fifo;
553
554      // Fifo between TGT_CMD fsm and CAS fsm
555      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
556      GenericFifo<bool>      m_cmd_cas_eop_fifo;
557      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
558      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
559      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
560      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
561
562      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
563      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
564     
565      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
566      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
567
568      // Buffer between TGT_CMD fsm and TGT_RSP fsm
569      // (segmentation violation response request)
570      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
571
572      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
573      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
574      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
575      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
576      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
577
578      sc_signal<addr_t>   r_tgt_cmd_config_addr;
579      sc_signal<size_t>   r_tgt_cmd_config_cmd;
580
581      ///////////////////////////////////////////////////////
582      // Registers controlled by the CONFIG fsm
583      ///////////////////////////////////////////////////////
584
585      sc_signal<int>      r_config_fsm;            // FSM state
586      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
587      sc_signal<int>      r_config_cmd;            // config request status
588      sc_signal<addr_t>   r_config_address;        // target buffer physical address
589      sc_signal<size_t>   r_config_srcid;          // config request srcid
590      sc_signal<size_t>   r_config_trdid;          // config request trdid
591      sc_signal<size_t>   r_config_pktid;          // config request pktid
592      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
593      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
594      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
595      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
596      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
597      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
598      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
599      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
600
601      sc_signal<size_t>   r_config_ivt_index;      // IVT index
602
603      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
604      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
605      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
606      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
607      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
608      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
609
610      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
611      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
612      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
613      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
614      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
615      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
616      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
617
618#if L1_MULTI_CACHE
619      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
620#endif
621
622      ///////////////////////////////////////////////////////
623      // Registers controlled by the READ fsm
624      ///////////////////////////////////////////////////////
625
626      sc_signal<int>      r_read_fsm;          // FSM state
627      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
628      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
629      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
630      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
631      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
632      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
633      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
634      sc_signal<size_t>   r_read_count;        // number of copies
635      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
636      sc_signal<data_t> * r_read_data;         // data (one cache line)
637      sc_signal<size_t>   r_read_way;          // associative way (in cache)
638      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
639      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
640      sc_signal<bool>     r_read_last_free;    // Last free entry
641      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
642
643      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
644      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
645      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
646      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
647
648      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
649      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
650      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
651      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
652      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
653      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
654      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
655      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
656      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
657
658      ///////////////////////////////////////////////////////////////
659      // Registers controlled by the WRITE fsm
660      ///////////////////////////////////////////////////////////////
661
662      sc_signal<int>      r_write_fsm;        // FSM state
663      sc_signal<addr_t>   r_write_address;    // first word address
664      sc_signal<size_t>   r_write_word_index; // first word index in line
665      sc_signal<size_t>   r_write_word_count; // number of words in line
666      sc_signal<size_t>   r_write_srcid;      // transaction srcid
667      sc_signal<size_t>   r_write_trdid;      // transaction trdid
668      sc_signal<size_t>   r_write_pktid;      // transaction pktid
669      sc_signal<data_t> * r_write_data;       // data (one cache line)
670      sc_signal<be_t>   * r_write_be;         // one byte enable per word
671      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
672      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
673      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
674      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
675      sc_signal<size_t>   r_write_copy;       // first owner of the line
676      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
677      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
678      sc_signal<size_t>   r_write_count;      // number of copies
679      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
680      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
681      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
682      sc_signal<size_t>   r_write_way;        // way of the line
683      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
684      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
685      sc_signal<bool>     r_write_sc_fail;    // sc command failed
686      sc_signal<bool>     r_write_pending_sc; // sc command pending
687
688      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
689      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
690      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
691      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
692      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
693      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
694
695      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
696      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
697      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
698      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
699      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
700      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
701
702      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
703      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
704      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
705      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
706      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
707      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
708      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
709      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
710      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
711      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
712      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
713
714#if L1_MULTI_CACHE
715      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
716#endif
717
718      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
719      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
720      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
721
722      /////////////////////////////////////////////////////////
723      // Registers controlled by MULTI_ACK fsm
724      //////////////////////////////////////////////////////////
725
726      sc_signal<int>      r_multi_ack_fsm;       // FSM state
727      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
728      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
729      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
730      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
731      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
732
733      // signaling completion of multi-inval to CONFIG fsm
734      sc_signal<bool>     r_multi_ack_to_config_ack; 
735
736      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
737      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
738      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
739      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
740      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
741
742      ///////////////////////////////////////////////////////
743      // Registers controlled by CLEANUP fsm
744      ///////////////////////////////////////////////////////
745
746      sc_signal<int>      r_cleanup_fsm;           // FSM state
747      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
748      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
749      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
750      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
751
752#if L1_MULTI_CACHE
753      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
754#endif
755
756      sc_signal<copy_t>   r_cleanup_copy;          // first copy
757      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
758      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
759      sc_signal<copy_t>   r_cleanup_count;         // number of copies
760      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
761      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
762      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
763      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
764      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
765      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
766      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
767      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
768      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
769      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
770      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
771
772      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
773      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
774      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
775
776      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
777      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
778
779      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
780
781      // signaling completion of broadcast-inval to CONFIG fsm
782      sc_signal<bool>     r_cleanup_to_config_ack; 
783       
784      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
785      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
786      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
787      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
788      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
789
790      ///////////////////////////////////////////////////////
791      // Registers controlled by CAS fsm
792      ///////////////////////////////////////////////////////
793
794      sc_signal<int>      r_cas_fsm;        // FSM state
795      sc_signal<data_t>   r_cas_wdata;      // write data word
796      sc_signal<data_t> * r_cas_rdata;      // read data word
797      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
798      sc_signal<size_t>   r_cas_cpt;        // size of command
799      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
800      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
801      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
802      sc_signal<size_t>   r_cas_count;      // number of copies
803      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
804      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
805      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
806      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
807      sc_signal<size_t>   r_cas_way;        // way in directory
808      sc_signal<size_t>   r_cas_set;        // set in directory
809      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
810      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
811      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
812      sc_signal<data_t> * r_cas_data;       // cache line data
813
814      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
815      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
816      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
817      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
818      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
819      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
820
821
822      // Buffer between CAS fsm and TGT_RSP fsm
823      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
824      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
825      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
826      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
827      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
828
829      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
830      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
831      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
832      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
833      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
834      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
835      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
836      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
837      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
838      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
839      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
840
841#if L1_MULTI_CACHE
842      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
843#endif
844
845      ////////////////////////////////////////////////////
846      // Registers controlled by the IXR_RSP fsm
847      ////////////////////////////////////////////////////
848
849      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
850      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
851      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
852
853      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
854      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
855
856      ////////////////////////////////////////////////////
857      // Registers controlled by the XRAM_RSP fsm
858      ////////////////////////////////////////////////////
859
860      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
861      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
862      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
863      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
864      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
865      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
866      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
867      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
868      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
869      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
870      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
871      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
872      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
873      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
874      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
875      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
876      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
877
878      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
879      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
880      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
881      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
882      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
883      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
884      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
885      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
886      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
887      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
888
889      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
890      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
891      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
892      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
893      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
894      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
895      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
896
897#if L1_MULTI_CACHE
898      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
899#endif
900
901      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
902      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
903      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
904      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
905      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
906
907      ////////////////////////////////////////////////////
908      // Registers controlled by the IXR_CMD fsm
909      ////////////////////////////////////////////////////
910
911      sc_signal<int>      r_ixr_cmd_fsm;
912      sc_signal<size_t>   r_ixr_cmd_cpt;
913
914      ////////////////////////////////////////////////////
915      // Registers controlled by TGT_RSP fsm
916      ////////////////////////////////////////////////////
917
918      sc_signal<int>      r_tgt_rsp_fsm;
919      sc_signal<size_t>   r_tgt_rsp_cpt;
920      sc_signal<bool>     r_tgt_rsp_key_sent;
921
922      ////////////////////////////////////////////////////
923      // Registers controlled by CC_SEND fsm
924      ////////////////////////////////////////////////////
925
926      sc_signal<int>      r_cc_send_fsm;
927      sc_signal<size_t>   r_cc_send_cpt;
928      sc_signal<bool>     r_cc_send_inst;
929
930      ////////////////////////////////////////////////////
931      // Registers controlled by CC_RECEIVE fsm
932      ////////////////////////////////////////////////////
933
934      sc_signal<int>      r_cc_receive_fsm;
935
936      ////////////////////////////////////////////////////
937      // Registers controlled by ALLOC_DIR fsm
938      ////////////////////////////////////////////////////
939
940      sc_signal<int>      r_alloc_dir_fsm;
941      sc_signal<unsigned> r_alloc_dir_reset_cpt;
942
943      ////////////////////////////////////////////////////
944      // Registers controlled by ALLOC_TRT fsm
945      ////////////////////////////////////////////////////
946
947      sc_signal<int>      r_alloc_trt_fsm;
948
949      ////////////////////////////////////////////////////
950      // Registers controlled by ALLOC_UPT fsm
951      ////////////////////////////////////////////////////
952
953      sc_signal<int>      r_alloc_upt_fsm;
954
955      ////////////////////////////////////////////////////
956      // Registers controlled by ALLOC_IVT fsm
957      ////////////////////////////////////////////////////
958
959      sc_signal<int>      r_alloc_ivt_fsm;
960
961      ////////////////////////////////////////////////////
962      // Registers controlled by ALLOC_HEAP fsm
963      ////////////////////////////////////////////////////
964
965      sc_signal<int>      r_alloc_heap_fsm;
966      sc_signal<unsigned> r_alloc_heap_reset_cpt;
967    }; // end class VciMemCache
968
969}}
970
971#endif
972
973// Local Variables:
974// tab-width: 2
975// c-basic-offset: 2
976// c-file-offsets:((innamespace . 0)(inline-open . 0))
977// indent-tabs-mode: nil
978// End:
979
980// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
981
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