[344] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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[396] | 5 | // Date : may 2013 |
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[344] | 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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[396] | 8 | // This file define a generic TSAR architecture. |
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| 9 | // The physical address space is 40 bits. |
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| 10 | // |
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[344] | 11 | // The number of clusters cannot be larger than 256. |
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| 12 | // The number of processors per cluster cannot be larger than 8. |
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| 13 | // |
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| 14 | // - It uses four dspin_local_crossbar per cluster as local interconnect |
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| 15 | // - It uses two virtual_dspin routers per cluster as global interconnect |
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| 16 | // - It uses the vci_cc_vcache_wrapper |
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| 17 | // - It uses the vci_mem_cache |
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[396] | 18 | // - It contains one vci_xicu per cluster. |
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| 19 | // - It contains one vci_multi_dma per cluster. |
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| 20 | // - It contains one vci_simple_ram per cluster to model the L3 cache. |
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[344] | 21 | // |
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[396] | 22 | // The communication between the MemCache and the Xram is 64 bits. |
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| 23 | // |
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| 24 | // All clusters are identical, but the cluster 0 (called io_cluster), |
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| 25 | // contains 5 extra components: |
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[344] | 26 | // - the boot rom (BROM) |
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| 27 | // - the disk controller (BDEV) |
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| 28 | // - the multi-channel network controller (MNIC) |
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| 29 | // - the multi-channel tty controller (MTTY) |
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| 30 | // - the frame buffer controller (FBUF) |
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| 31 | // |
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[396] | 32 | // It is build with one single component implementing a cluster, |
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| 33 | // defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) |
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[344] | 34 | // |
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| 35 | // The IRQs are connected to XICUs as follow: |
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| 36 | // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. |
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| 37 | // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. |
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| 38 | // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. |
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| 39 | // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. |
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| 40 | // |
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[396] | 41 | // Some hardware parameters are used when compiling the OS, and are used |
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| 42 | // by this top.cpp file. They must be defined in the hard_config.h file : |
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[344] | 43 | // - CLUSTER_X : number of clusters in a row (power of 2) |
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| 44 | // - CLUSTER_Y : number of clusters in a column (power of 2) |
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| 45 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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| 46 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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[438] | 47 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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| 48 | // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) |
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| 49 | // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) |
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[344] | 50 | // |
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[396] | 51 | // Some other hardware parameters are not used when compiling the OS, |
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| 52 | // and can be directly defined in this top.cpp file: |
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[344] | 53 | // - XRAM_LATENCY : external ram latency |
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| 54 | // - MEMC_WAYS : L2 cache number of ways |
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| 55 | // - MEMC_SETS : L2 cache number of sets |
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| 56 | // - L1_IWAYS |
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| 57 | // - L1_ISETS |
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| 58 | // - L1_DWAYS |
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| 59 | // - L1_DSETS |
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| 60 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 61 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 62 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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| 63 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 64 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 65 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 66 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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[396] | 67 | ///////////////////////////////////////////////////////////////////////// |
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| 68 | // General policy for 40 bits physical address decoding: |
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| 69 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 70 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[344] | 71 | // The (x_width + y_width) MSB bits (left aligned) define |
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[396] | 72 | // the cluster index, and the LADR bits define the local index: |
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[344] | 73 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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[396] | 74 | // |x_width|y_width|---| 8 | 24 | |
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[344] | 75 | ///////////////////////////////////////////////////////////////////////// |
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[396] | 76 | // General policy for 14 bits SRCID decoding: |
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| 77 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 78 | // | X_ID | Y_ID |---| L_ID | |
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| 79 | // |x_width|y_width|---| 6 | |
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| 80 | ///////////////////////////////////////////////////////////////////////// |
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[344] | 81 | |
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| 82 | #include <systemc> |
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| 83 | #include <sys/time.h> |
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| 84 | #include <iostream> |
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| 85 | #include <sstream> |
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| 86 | #include <cstdlib> |
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| 87 | #include <cstdarg> |
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| 88 | #include <stdint.h> |
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| 89 | |
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| 90 | #include "gdbserver.h" |
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| 91 | #include "mapping_table.h" |
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[378] | 92 | #include "tsar_xbar_cluster.h" |
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[344] | 93 | #include "alloc_elems.h" |
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| 94 | |
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| 95 | /////////////////////////////////////////////////// |
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| 96 | // OS |
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| 97 | /////////////////////////////////////////////////// |
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| 98 | #define USE_ALMOS 0 |
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| 99 | |
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| 100 | #define almos_bootloader_pathname "bootloader.bin" |
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| 101 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 102 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 103 | |
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| 104 | /////////////////////////////////////////////////// |
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| 105 | // Parallelisation |
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| 106 | /////////////////////////////////////////////////// |
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| 107 | #define USE_OPENMP 0 |
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| 108 | |
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| 109 | #if USE_OPENMP |
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| 110 | #include <omp.h> |
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| 111 | #endif |
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| 112 | |
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| 113 | // cluster index (computed from x,y coordinates) |
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[438] | 114 | #define cluster(x,y) (y + YMAX*x) |
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[344] | 115 | |
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| 116 | /////////////////////////////////////////////////////////// |
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| 117 | // DSPIN parameters |
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| 118 | /////////////////////////////////////////////////////////// |
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| 119 | |
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[404] | 120 | #define dspin_cmd_width 39 |
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| 121 | #define dspin_rsp_width 32 |
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[344] | 122 | |
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[396] | 123 | /////////////////////////////////////////////////////////// |
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| 124 | // VCI parameters |
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| 125 | /////////////////////////////////////////////////////////// |
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| 126 | |
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[438] | 127 | #define vci_cell_width_int 4 |
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| 128 | #define vci_cell_width_ext 8 |
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[396] | 129 | |
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[438] | 130 | #define vci_plen_width 8 |
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| 131 | #define vci_address_width 40 |
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| 132 | #define vci_rerror_width 1 |
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| 133 | #define vci_clen_width 1 |
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| 134 | #define vci_rflag_width 1 |
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| 135 | #define vci_srcid_width 14 |
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| 136 | #define vci_pktid_width 4 |
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| 137 | #define vci_trdid_width 4 |
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| 138 | #define vci_wrplen_width 1 |
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[396] | 139 | |
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[344] | 140 | //////////////////////////////////////////////////////////// |
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| 141 | // Main Hardware Parameters values |
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| 142 | //////////////////////i///////////////////////////////////// |
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| 143 | |
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[447] | 144 | #include "hard_config.h" |
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[344] | 145 | |
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| 146 | //////////////////////////////////////////////////////////// |
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[396] | 147 | // Secondary Hardware Parameters |
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[344] | 148 | //////////////////////i///////////////////////////////////// |
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| 149 | |
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[438] | 150 | #define XMAX CLUSTER_X |
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| 151 | #define YMAX CLUSTER_Y |
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| 152 | |
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[344] | 153 | #define XRAM_LATENCY 0 |
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| 154 | |
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| 155 | #define MEMC_WAYS 16 |
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| 156 | #define MEMC_SETS 256 |
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| 157 | |
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| 158 | #define L1_IWAYS 4 |
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| 159 | #define L1_ISETS 64 |
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| 160 | |
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| 161 | #define L1_DWAYS 4 |
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| 162 | #define L1_DSETS 64 |
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| 163 | |
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| 164 | #define FBUF_X_SIZE 128 |
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| 165 | #define FBUF_Y_SIZE 128 |
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| 166 | |
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| 167 | #define BDEV_SECTOR_SIZE 512 |
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[447] | 168 | #define BDEV_IMAGE_NAME "images.raw" |
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[344] | 169 | |
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[379] | 170 | #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" |
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| 171 | #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" |
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[344] | 172 | #define NIC_TIMEOUT 10000 |
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| 173 | |
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[438] | 174 | #define NORTH 0 |
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| 175 | #define SOUTH 1 |
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| 176 | #define EAST 2 |
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| 177 | #define WEST 3 |
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| 178 | |
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[344] | 179 | //////////////////////////////////////////////////////////// |
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| 180 | // Software to be loaded in ROM & RAM |
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| 181 | //////////////////////i///////////////////////////////////// |
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| 182 | |
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[447] | 183 | #define SOFT_NAME "soft.elf" |
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[344] | 184 | |
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| 185 | //////////////////////////////////////////////////////////// |
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| 186 | // DEBUG Parameters default values |
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| 187 | //////////////////////i///////////////////////////////////// |
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| 188 | |
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| 189 | #define MAX_FROZEN_CYCLES 10000 |
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| 190 | |
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| 191 | ///////////////////////////////////////////////////////// |
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| 192 | // Physical segments definition |
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| 193 | ///////////////////////////////////////////////////////// |
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| 194 | // There is 3 segments replicated in all clusters |
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| 195 | // and 5 specific segments in the "IO" cluster |
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| 196 | // (containing address 0xBF000000) |
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| 197 | ///////////////////////////////////////////////////////// |
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| 198 | |
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| 199 | // specific segments in "IO" cluster : absolute physical address |
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| 200 | |
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[396] | 201 | #define BROM_BASE 0x00BFC00000 |
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| 202 | #define BROM_SIZE 0x0000100000 // 1 Mbytes |
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[344] | 203 | |
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[396] | 204 | #define FBUF_BASE 0x00B2000000 |
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| 205 | #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE |
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[344] | 206 | |
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[396] | 207 | #define BDEV_BASE 0x00B3000000 |
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| 208 | #define BDEV_SIZE 0x0000001000 // 4 Kbytes |
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[344] | 209 | |
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[396] | 210 | #define MTTY_BASE 0x00B4000000 |
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| 211 | #define MTTY_SIZE 0x0000001000 // 4 Kbytes |
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[344] | 212 | |
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[396] | 213 | #define MNIC_BASE 0x00B5000000 |
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[402] | 214 | #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) |
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[344] | 215 | |
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| 216 | // replicated segments : address is incremented by a cluster offset |
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| 217 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 218 | |
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[396] | 219 | #define MEMC_BASE 0x0000000000 |
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| 220 | #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster |
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[344] | 221 | |
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[396] | 222 | #define XICU_BASE 0x00B0000000 |
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| 223 | #define XICU_SIZE 0x0000001000 // 4 Kbytes |
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[344] | 224 | |
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[396] | 225 | #define MDMA_BASE 0x00B1000000 |
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| 226 | #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel |
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[344] | 227 | |
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| 228 | //////////////////////////////////////////////////////////////////// |
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| 229 | // TGTID definition in direct space |
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| 230 | // For all components: global TGTID = global SRCID = cluster_index |
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| 231 | //////////////////////////////////////////////////////////////////// |
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| 232 | |
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[396] | 233 | #define MEMC_TGTID 0 |
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| 234 | #define XICU_TGTID 1 |
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| 235 | #define MDMA_TGTID 2 |
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| 236 | #define MTTY_TGTID 3 |
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| 237 | #define FBUF_TGTID 4 |
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| 238 | #define BDEV_TGTID 5 |
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[438] | 239 | #define MNIC_TGTID 6 |
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| 240 | #define BROM_TGTID 7 |
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[344] | 241 | |
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| 242 | ///////////////////////////////// |
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| 243 | int _main(int argc, char *argv[]) |
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| 244 | { |
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| 245 | using namespace sc_core; |
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| 246 | using namespace soclib::caba; |
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| 247 | using namespace soclib::common; |
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| 248 | |
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[438] | 249 | |
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[396] | 250 | char soft_name[256] = SOFT_NAME; // pathname to binary code |
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[447] | 251 | uint64_t ncycles = 100000000000; // simulated cycles |
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[344] | 252 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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| 253 | char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file |
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| 254 | char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file |
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| 255 | ssize_t threads_nr = 1; // simulator's threads number |
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| 256 | bool debug_ok = false; // trace activated |
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| 257 | size_t debug_period = 1; // trace period |
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[438] | 258 | size_t debug_memc_id = 0; // index of memc to be traced |
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| 259 | size_t debug_proc_id = 0; // index of proc to be traced |
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[344] | 260 | uint32_t debug_from = 0; // trace start cycle |
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| 261 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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[396] | 262 | size_t cluster_io_id = 0; // index of cluster containing IOs |
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[344] | 263 | |
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| 264 | ////////////// command line arguments ////////////////////// |
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| 265 | if (argc > 1) |
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| 266 | { |
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| 267 | for (int n = 1; n < argc; n = n + 2) |
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| 268 | { |
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| 269 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 270 | { |
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| 271 | ncycles = atoi(argv[n+1]); |
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| 272 | } |
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| 273 | else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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| 274 | { |
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| 275 | strcpy(soft_name, argv[n+1]); |
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| 276 | } |
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| 277 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 278 | { |
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| 279 | strcpy(disk_name, argv[n+1]); |
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| 280 | } |
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| 281 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 282 | { |
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| 283 | debug_ok = true; |
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| 284 | debug_from = atoi(argv[n+1]); |
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| 285 | } |
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| 286 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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| 287 | { |
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| 288 | debug_memc_id = atoi(argv[n+1]); |
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[438] | 289 | assert( (debug_memc_id < (XMAX*YMAX) ) && |
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[344] | 290 | "debug_memc_id larger than XMAX * YMAX" ); |
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| 291 | } |
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| 292 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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| 293 | { |
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| 294 | debug_proc_id = atoi(argv[n+1]); |
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[438] | 295 | assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) && |
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[344] | 296 | "debug_proc_id larger than XMAX * YMAX * NB_PROCS" ); |
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| 297 | } |
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| 298 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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| 299 | { |
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| 300 | threads_nr = atoi(argv[n+1]); |
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| 301 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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| 302 | } |
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| 303 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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| 304 | { |
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| 305 | frozen_cycles = atoi(argv[n+1]); |
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| 306 | } |
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| 307 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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| 308 | { |
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| 309 | debug_period = atoi(argv[n+1]); |
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| 310 | } |
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| 311 | else |
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| 312 | { |
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| 313 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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| 314 | std::cout << " The order is not important." << std::endl; |
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| 315 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 316 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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| 317 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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| 318 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 319 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 320 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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| 321 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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| 322 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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| 323 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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| 324 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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| 325 | exit(0); |
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| 326 | } |
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| 327 | } |
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| 328 | } |
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| 329 | |
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[396] | 330 | // checking hardware parameters |
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[438] | 331 | assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or |
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| 332 | (XMAX == 8) or (XMAX == 16) ) and |
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| 333 | "The XMAX parameter must be 1, 2, 4, 8 or 16" ); |
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[344] | 334 | |
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[438] | 335 | assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or |
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| 336 | (YMAX == 8) or (YMAX == 16) ) and |
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| 337 | "The YMAX parameter must be 1, 2, 4, 8 or 16" ); |
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[344] | 338 | |
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[396] | 339 | assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or |
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| 340 | (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and |
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| 341 | "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); |
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[344] | 342 | |
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[396] | 343 | assert( (NB_DMA_CHANNELS < 9) and |
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| 344 | "The NB_DMA_CHANNELS parameter must be smaller than 9" ); |
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[344] | 345 | |
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[396] | 346 | assert( (NB_TTY_CHANNELS < 15) and |
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| 347 | "The NB_TTY_CHANNELS parameter must be smaller than 15" ); |
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[344] | 348 | |
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[396] | 349 | assert( (NB_NIC_CHANNELS < 9) and |
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| 350 | "The NB_NIC_CHANNELS parameter must be smaller than 9" ); |
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[344] | 351 | |
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[438] | 352 | assert( (vci_address_width == 40) and |
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[396] | 353 | "VCI address width must be 40 bits" ); |
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[344] | 354 | |
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[396] | 355 | std::cout << std::endl; |
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[438] | 356 | std::cout << " - XMAX = " << XMAX << std::endl; |
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| 357 | std::cout << " - YMAX = " << YMAX << std::endl; |
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| 358 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
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[396] | 359 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
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[438] | 360 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
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| 361 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
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| 362 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
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| 363 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
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| 364 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
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| 365 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
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[396] | 366 | |
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| 367 | std::cout << std::endl; |
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| 368 | |
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| 369 | // Internal and External VCI parameters definition |
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[438] | 370 | typedef soclib::caba::VciParams<vci_cell_width_int, |
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| 371 | vci_plen_width, |
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| 372 | vci_address_width, |
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| 373 | vci_rerror_width, |
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| 374 | vci_clen_width, |
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| 375 | vci_rflag_width, |
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| 376 | vci_srcid_width, |
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| 377 | vci_pktid_width, |
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| 378 | vci_trdid_width, |
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| 379 | vci_wrplen_width> vci_param_int; |
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[396] | 380 | |
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[438] | 381 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
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| 382 | vci_plen_width, |
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| 383 | vci_address_width, |
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| 384 | vci_rerror_width, |
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| 385 | vci_clen_width, |
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| 386 | vci_rflag_width, |
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| 387 | vci_srcid_width, |
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| 388 | vci_pktid_width, |
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| 389 | vci_trdid_width, |
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| 390 | vci_wrplen_width> vci_param_ext; |
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[396] | 391 | |
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[344] | 392 | #if USE_OPENMP |
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| 393 | omp_set_dynamic(false); |
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| 394 | omp_set_num_threads(threads_nr); |
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| 395 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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| 396 | #endif |
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| 397 | |
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| 398 | // Define parameters depending on mesh size |
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| 399 | size_t x_width; |
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| 400 | size_t y_width; |
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| 401 | |
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[438] | 402 | if (XMAX == 1) x_width = 0; |
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| 403 | else if (XMAX == 2) x_width = 1; |
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| 404 | else if (XMAX <= 4) x_width = 2; |
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| 405 | else if (XMAX <= 8) x_width = 3; |
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[389] | 406 | else x_width = 4; |
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[344] | 407 | |
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[438] | 408 | if (YMAX == 1) y_width = 0; |
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| 409 | else if (YMAX == 2) y_width = 1; |
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| 410 | else if (YMAX <= 4) y_width = 2; |
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| 411 | else if (YMAX <= 8) y_width = 3; |
---|
[389] | 412 | else y_width = 4; |
---|
[344] | 413 | |
---|
| 414 | ///////////////////// |
---|
| 415 | // Mapping Tables |
---|
| 416 | ///////////////////// |
---|
| 417 | |
---|
[396] | 418 | // internal network |
---|
[438] | 419 | MappingTable maptabd(vci_address_width, |
---|
[396] | 420 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
[438] | 421 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
[396] | 422 | 0x00FF000000); |
---|
[344] | 423 | |
---|
[438] | 424 | for (size_t x = 0; x < XMAX; x++) |
---|
[344] | 425 | { |
---|
[438] | 426 | for (size_t y = 0; y < YMAX; y++) |
---|
[344] | 427 | { |
---|
[438] | 428 | sc_uint<vci_address_width> offset; |
---|
| 429 | offset = (sc_uint<vci_address_width>)cluster(x,y) |
---|
| 430 | << (vci_address_width-x_width-y_width); |
---|
[344] | 431 | |
---|
| 432 | std::ostringstream sh; |
---|
[396] | 433 | sh << "seg_memc_" << x << "_" << y; |
---|
| 434 | maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, |
---|
| 435 | IntTab(cluster(x,y),MEMC_TGTID), true)); |
---|
[344] | 436 | |
---|
| 437 | std::ostringstream si; |
---|
[396] | 438 | si << "seg_xicu_" << x << "_" << y; |
---|
| 439 | maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, |
---|
| 440 | IntTab(cluster(x,y),XICU_TGTID), false)); |
---|
[344] | 441 | |
---|
| 442 | std::ostringstream sd; |
---|
[396] | 443 | sd << "seg_mdma_" << x << "_" << y; |
---|
| 444 | maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE, |
---|
| 445 | IntTab(cluster(x,y),MDMA_TGTID), false)); |
---|
[344] | 446 | |
---|
| 447 | if ( cluster(x,y) == cluster_io_id ) |
---|
| 448 | { |
---|
[396] | 449 | maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, |
---|
| 450 | IntTab(cluster(x,y),MTTY_TGTID), false)); |
---|
| 451 | maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, |
---|
| 452 | IntTab(cluster(x,y),FBUF_TGTID), false)); |
---|
| 453 | maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, |
---|
| 454 | IntTab(cluster(x,y),BDEV_TGTID), false)); |
---|
| 455 | maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, |
---|
| 456 | IntTab(cluster(x,y),MNIC_TGTID), false)); |
---|
| 457 | maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, |
---|
| 458 | IntTab(cluster(x,y),BROM_TGTID), true)); |
---|
[344] | 459 | } |
---|
| 460 | } |
---|
| 461 | } |
---|
| 462 | std::cout << maptabd << std::endl; |
---|
| 463 | |
---|
| 464 | // external network |
---|
[438] | 465 | MappingTable maptabx(vci_address_width, |
---|
[396] | 466 | IntTab(x_width+y_width), |
---|
| 467 | IntTab(x_width+y_width), |
---|
| 468 | 0xFFFF000000ULL); |
---|
[344] | 469 | |
---|
[438] | 470 | for (size_t x = 0; x < XMAX; x++) |
---|
[344] | 471 | { |
---|
[438] | 472 | for (size_t y = 0; y < YMAX ; y++) |
---|
[344] | 473 | { |
---|
[396] | 474 | |
---|
[438] | 475 | sc_uint<vci_address_width> offset; |
---|
| 476 | offset = (sc_uint<vci_address_width>)cluster(x,y) |
---|
| 477 | << (vci_address_width-x_width-y_width); |
---|
[396] | 478 | |
---|
[344] | 479 | std::ostringstream sh; |
---|
| 480 | sh << "x_seg_memc_" << x << "_" << y; |
---|
[396] | 481 | |
---|
[344] | 482 | maptabx.add(Segment(sh.str(), MEMC_BASE+offset, |
---|
| 483 | MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
| 484 | } |
---|
| 485 | } |
---|
| 486 | std::cout << maptabx << std::endl; |
---|
| 487 | |
---|
| 488 | //////////////////// |
---|
| 489 | // Signals |
---|
| 490 | /////////////////// |
---|
| 491 | |
---|
[389] | 492 | sc_clock signal_clk("clk"); |
---|
[344] | 493 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 494 | |
---|
| 495 | // Horizontal inter-clusters DSPIN signals |
---|
[396] | 496 | DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = |
---|
[466] | 497 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3); |
---|
[396] | 498 | DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = |
---|
[466] | 499 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3); |
---|
[396] | 500 | DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = |
---|
[438] | 501 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2); |
---|
[396] | 502 | DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = |
---|
[438] | 503 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2); |
---|
[344] | 504 | |
---|
| 505 | // Vertical inter-clusters DSPIN signals |
---|
[396] | 506 | DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = |
---|
[466] | 507 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3); |
---|
[396] | 508 | DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = |
---|
[466] | 509 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3); |
---|
[396] | 510 | DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = |
---|
[438] | 511 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2); |
---|
[396] | 512 | DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = |
---|
[438] | 513 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2); |
---|
[344] | 514 | |
---|
| 515 | // Mesh boundaries DSPIN signals |
---|
[396] | 516 | DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = |
---|
[466] | 517 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3); |
---|
[396] | 518 | DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = |
---|
[466] | 519 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3); |
---|
[396] | 520 | DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = |
---|
[466] | 521 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2); |
---|
[396] | 522 | DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = |
---|
[466] | 523 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2); |
---|
[344] | 524 | |
---|
| 525 | |
---|
| 526 | //////////////////////////// |
---|
| 527 | // Loader |
---|
| 528 | //////////////////////////// |
---|
| 529 | |
---|
| 530 | #if USE_ALMOS |
---|
| 531 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 532 | almos_archinfo_pathname, |
---|
| 533 | almos_kernel_pathname); |
---|
| 534 | #else |
---|
| 535 | soclib::common::Loader loader(soft_name); |
---|
| 536 | #endif |
---|
| 537 | |
---|
| 538 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 539 | proc_iss::set_loader(loader); |
---|
| 540 | |
---|
| 541 | //////////////////////////// |
---|
| 542 | // Clusters construction |
---|
| 543 | //////////////////////////// |
---|
| 544 | |
---|
[396] | 545 | TsarXbarCluster<dspin_cmd_width, |
---|
| 546 | dspin_rsp_width, |
---|
| 547 | vci_param_int, |
---|
[438] | 548 | vci_param_ext>* clusters[XMAX][YMAX]; |
---|
[344] | 549 | |
---|
| 550 | #if USE_OPENMP |
---|
| 551 | #pragma omp parallel |
---|
| 552 | { |
---|
| 553 | #pragma omp for |
---|
| 554 | #endif |
---|
[438] | 555 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
[344] | 556 | { |
---|
[438] | 557 | size_t x = i / YMAX; |
---|
| 558 | size_t y = i % YMAX; |
---|
[344] | 559 | |
---|
| 560 | #if USE_OPENMP |
---|
| 561 | #pragma omp critical |
---|
| 562 | { |
---|
| 563 | #endif |
---|
[438] | 564 | std::cout << std::endl; |
---|
| 565 | std::cout << "Cluster_" << x << "_" << y << std::endl; |
---|
| 566 | std::cout << std::endl; |
---|
[389] | 567 | |
---|
[344] | 568 | std::ostringstream sc; |
---|
| 569 | sc << "cluster_" << x << "_" << y; |
---|
[396] | 570 | clusters[x][y] = new TsarXbarCluster<dspin_cmd_width, |
---|
| 571 | dspin_rsp_width, |
---|
| 572 | vci_param_int, |
---|
| 573 | vci_param_ext> |
---|
[344] | 574 | ( |
---|
| 575 | sc.str().c_str(), |
---|
[396] | 576 | NB_PROCS_MAX, |
---|
| 577 | NB_TTY_CHANNELS, |
---|
| 578 | NB_DMA_CHANNELS, |
---|
| 579 | x, |
---|
| 580 | y, |
---|
| 581 | cluster(x,y), |
---|
| 582 | maptabd, |
---|
| 583 | maptabx, |
---|
| 584 | x_width, |
---|
| 585 | y_width, |
---|
[438] | 586 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
[396] | 587 | MEMC_TGTID, |
---|
| 588 | XICU_TGTID, |
---|
| 589 | MDMA_TGTID, |
---|
| 590 | FBUF_TGTID, |
---|
| 591 | MTTY_TGTID, |
---|
| 592 | BROM_TGTID, |
---|
| 593 | MNIC_TGTID, |
---|
| 594 | BDEV_TGTID, |
---|
| 595 | MEMC_WAYS, |
---|
| 596 | MEMC_SETS, |
---|
| 597 | L1_IWAYS, |
---|
| 598 | L1_ISETS, |
---|
| 599 | L1_DWAYS, |
---|
| 600 | L1_DSETS, |
---|
| 601 | XRAM_LATENCY, |
---|
| 602 | (cluster(x,y) == cluster_io_id), |
---|
| 603 | FBUF_X_SIZE, |
---|
| 604 | FBUF_Y_SIZE, |
---|
| 605 | disk_name, |
---|
| 606 | BDEV_SECTOR_SIZE, |
---|
| 607 | NB_NIC_CHANNELS, |
---|
| 608 | nic_rx_name, |
---|
| 609 | nic_tx_name, |
---|
| 610 | NIC_TIMEOUT, |
---|
| 611 | loader, |
---|
[344] | 612 | frozen_cycles, |
---|
[389] | 613 | debug_from , |
---|
[344] | 614 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
| 615 | debug_ok and (cluster(x,y) == debug_proc_id) |
---|
| 616 | ); |
---|
| 617 | |
---|
| 618 | #if USE_OPENMP |
---|
| 619 | } // end critical |
---|
| 620 | #endif |
---|
| 621 | } // end for |
---|
| 622 | #if USE_OPENMP |
---|
| 623 | } |
---|
| 624 | #endif |
---|
| 625 | |
---|
| 626 | /////////////////////////////////////////////////////////////// |
---|
| 627 | // Net-list |
---|
| 628 | /////////////////////////////////////////////////////////////// |
---|
| 629 | |
---|
| 630 | // Clock & RESET |
---|
[438] | 631 | for (size_t x = 0; x < (XMAX); x++){ |
---|
| 632 | for (size_t y = 0; y < YMAX; y++){ |
---|
[389] | 633 | clusters[x][y]->p_clk (signal_clk); |
---|
| 634 | clusters[x][y]->p_resetn (signal_resetn); |
---|
[344] | 635 | } |
---|
| 636 | } |
---|
| 637 | |
---|
| 638 | // Inter Clusters horizontal connections |
---|
[438] | 639 | if (XMAX > 1){ |
---|
| 640 | for (size_t x = 0; x < (XMAX-1); x++){ |
---|
| 641 | for (size_t y = 0; y < YMAX; y++){ |
---|
[466] | 642 | for (size_t k = 0; k < 3; k++){ |
---|
| 643 | clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 644 | clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 645 | clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 646 | clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 647 | } |
---|
| 648 | |
---|
[344] | 649 | for (size_t k = 0; k < 2; k++){ |
---|
[466] | 650 | clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 651 | clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 652 | clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
| 653 | clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
[344] | 654 | } |
---|
| 655 | } |
---|
| 656 | } |
---|
| 657 | } |
---|
| 658 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
| 659 | |
---|
| 660 | // Inter Clusters vertical connections |
---|
[438] | 661 | if (YMAX > 1) { |
---|
| 662 | for (size_t y = 0; y < (YMAX-1); y++){ |
---|
| 663 | for (size_t x = 0; x < XMAX; x++){ |
---|
[466] | 664 | for (size_t k = 0; k < 3; k++){ |
---|
| 665 | clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 666 | clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 667 | clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 668 | clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 669 | } |
---|
| 670 | |
---|
[344] | 671 | for (size_t k = 0; k < 2; k++){ |
---|
[466] | 672 | clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 673 | clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 674 | clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
| 675 | clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
[344] | 676 | } |
---|
| 677 | } |
---|
| 678 | } |
---|
| 679 | } |
---|
| 680 | std::cout << "Vertical connections established" << std::endl; |
---|
| 681 | |
---|
| 682 | // East & West boundary cluster connections |
---|
[438] | 683 | for (size_t y = 0; y < YMAX; y++) |
---|
[344] | 684 | { |
---|
[466] | 685 | for (size_t k = 0; k < 3; k++) |
---|
| 686 | { |
---|
| 687 | clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); |
---|
| 688 | clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); |
---|
| 689 | clusters[XMAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]); |
---|
| 690 | clusters[XMAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]); |
---|
| 691 | } |
---|
| 692 | |
---|
[344] | 693 | for (size_t k = 0; k < 2; k++) |
---|
| 694 | { |
---|
[466] | 695 | clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); |
---|
| 696 | clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); |
---|
| 697 | clusters[XMAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]); |
---|
| 698 | clusters[XMAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]); |
---|
[344] | 699 | } |
---|
| 700 | } |
---|
| 701 | |
---|
| 702 | // North & South boundary clusters connections |
---|
[438] | 703 | for (size_t x = 0; x < XMAX; x++) |
---|
[344] | 704 | { |
---|
[466] | 705 | for (size_t k = 0; k < 3; k++) |
---|
| 706 | { |
---|
| 707 | clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); |
---|
| 708 | clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); |
---|
| 709 | clusters[x][YMAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]); |
---|
| 710 | clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]); |
---|
| 711 | } |
---|
| 712 | |
---|
[344] | 713 | for (size_t k = 0; k < 2; k++) |
---|
| 714 | { |
---|
[466] | 715 | clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); |
---|
| 716 | clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); |
---|
| 717 | clusters[x][YMAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]); |
---|
| 718 | clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]); |
---|
[344] | 719 | } |
---|
| 720 | } |
---|
[396] | 721 | std::cout << "North, South, West, East connections established" << std::endl; |
---|
| 722 | std::cout << std::endl; |
---|
[344] | 723 | |
---|
| 724 | |
---|
| 725 | //////////////////////////////////////////////////////// |
---|
| 726 | // Simulation |
---|
| 727 | /////////////////////////////////////////////////////// |
---|
| 728 | |
---|
| 729 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 730 | signal_resetn = false; |
---|
| 731 | |
---|
| 732 | // network boundaries signals |
---|
[438] | 733 | for (size_t x = 0; x < XMAX ; x++){ |
---|
| 734 | for (size_t y = 0; y < YMAX ; y++){ |
---|
[466] | 735 | for (size_t a = 0; a < 4; a++){ |
---|
| 736 | for (size_t k = 0; k < 3; k++){ |
---|
| 737 | signal_dspin_false_cmd_in [x][y][a][k].write = false; |
---|
| 738 | signal_dspin_false_cmd_in [x][y][a][k].read = true; |
---|
| 739 | signal_dspin_false_cmd_out[x][y][a][k].write = false; |
---|
| 740 | signal_dspin_false_cmd_out[x][y][a][k].read = true; |
---|
| 741 | } |
---|
[344] | 742 | |
---|
[466] | 743 | for (size_t k = 0; k < 2; k++){ |
---|
| 744 | signal_dspin_false_rsp_in [x][y][a][k].write = false; |
---|
| 745 | signal_dspin_false_rsp_in [x][y][a][k].read = true; |
---|
| 746 | signal_dspin_false_rsp_out[x][y][a][k].write = false; |
---|
| 747 | signal_dspin_false_rsp_out[x][y][a][k].read = true; |
---|
[344] | 748 | } |
---|
| 749 | } |
---|
| 750 | } |
---|
| 751 | } |
---|
| 752 | |
---|
| 753 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 754 | signal_resetn = true; |
---|
| 755 | |
---|
[447] | 756 | for (uint64_t n = 1; n < ncycles; n++) |
---|
[344] | 757 | { |
---|
[396] | 758 | // Monitor a specific address for L1 & L2 caches |
---|
| 759 | //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); |
---|
| 760 | //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); |
---|
| 761 | |
---|
[344] | 762 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
| 763 | { |
---|
| 764 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 765 | std::cout << " ************************************************" << std::endl; |
---|
| 766 | |
---|
[379] | 767 | // trace proc[debug_proc_id] |
---|
[438] | 768 | size_t l = debug_proc_id % NB_PROCS_MAX ; |
---|
| 769 | size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; |
---|
| 770 | size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; |
---|
[379] | 771 | |
---|
[438] | 772 | std::ostringstream proc_signame; |
---|
| 773 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 774 | std::ostringstream p2m_signame; |
---|
| 775 | p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; |
---|
| 776 | std::ostringstream m2p_signame; |
---|
| 777 | m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; |
---|
| 778 | std::ostringstream p_cmd_signame; |
---|
| 779 | p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; |
---|
| 780 | std::ostringstream p_rsp_signame; |
---|
| 781 | p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; |
---|
[379] | 782 | |
---|
[438] | 783 | clusters[x][y]->proc[l]->print_trace(); |
---|
| 784 | clusters[x][y]->wi_proc[l]->print_trace(); |
---|
| 785 | clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
| 786 | clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); |
---|
| 787 | clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); |
---|
| 788 | clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); |
---|
| 789 | clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); |
---|
[404] | 790 | |
---|
[438] | 791 | clusters[x][y]->xbar_rsp_d->print_trace(); |
---|
| 792 | clusters[x][y]->xbar_cmd_d->print_trace(); |
---|
| 793 | clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); |
---|
| 794 | clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); |
---|
| 795 | clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); |
---|
| 796 | clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); |
---|
[404] | 797 | |
---|
[379] | 798 | // trace memc[debug_memc_id] |
---|
[438] | 799 | x = debug_memc_id / YMAX; |
---|
| 800 | y = debug_memc_id % YMAX; |
---|
[344] | 801 | |
---|
[438] | 802 | std::ostringstream smemc; |
---|
| 803 | smemc << "[SIG]MEMC_" << x << "_" << y; |
---|
| 804 | std::ostringstream sxram; |
---|
| 805 | sxram << "[SIG]XRAM_" << x << "_" << y; |
---|
| 806 | std::ostringstream sm2p; |
---|
| 807 | sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; |
---|
| 808 | std::ostringstream sp2m; |
---|
| 809 | sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; |
---|
| 810 | std::ostringstream m_cmd_signame; |
---|
| 811 | m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; |
---|
| 812 | std::ostringstream m_rsp_signame; |
---|
| 813 | m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; |
---|
[344] | 814 | |
---|
[438] | 815 | clusters[x][y]->memc->print_trace(); |
---|
| 816 | clusters[x][y]->wt_memc->print_trace(); |
---|
| 817 | clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); |
---|
| 818 | clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); |
---|
| 819 | clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); |
---|
| 820 | clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); |
---|
| 821 | clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); |
---|
| 822 | clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); |
---|
[396] | 823 | |
---|
| 824 | // trace replicated peripherals |
---|
[404] | 825 | // clusters[1][1]->mdma->print_trace(); |
---|
| 826 | // clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); |
---|
| 827 | // clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); |
---|
[396] | 828 | |
---|
| 829 | |
---|
[379] | 830 | // trace external peripherals |
---|
[438] | 831 | size_t io_x = cluster_io_id / YMAX; |
---|
| 832 | size_t io_y = cluster_io_id % YMAX; |
---|
[379] | 833 | |
---|
[404] | 834 | clusters[io_x][io_y]->brom->print_trace(); |
---|
| 835 | clusters[io_x][io_y]->wt_brom->print_trace(); |
---|
| 836 | clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); |
---|
| 837 | clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD"); |
---|
| 838 | clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP"); |
---|
[396] | 839 | |
---|
[404] | 840 | // clusters[io_x][io_y]->bdev->print_trace(); |
---|
| 841 | // clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
| 842 | // clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
[344] | 843 | } |
---|
| 844 | |
---|
| 845 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 846 | } |
---|
| 847 | return EXIT_SUCCESS; |
---|
| 848 | } |
---|
| 849 | |
---|
| 850 | int sc_main (int argc, char *argv[]) |
---|
| 851 | { |
---|
| 852 | try { |
---|
| 853 | return _main(argc, argv); |
---|
| 854 | } catch (std::exception &e) { |
---|
| 855 | std::cout << e.what() << std::endl; |
---|
| 856 | } catch (...) { |
---|
| 857 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 858 | throw; |
---|
| 859 | } |
---|
| 860 | return 1; |
---|
| 861 | } |
---|
| 862 | |
---|
| 863 | |
---|
| 864 | // Local Variables: |
---|
| 865 | // tab-width: 3 |
---|
| 866 | // c-basic-offset: 3 |
---|
| 867 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 868 | // indent-tabs-mode: nil |
---|
| 869 | // End: |
---|
| 870 | |
---|
| 871 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|