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source: branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h @ 447

Last change on this file since 447 was 447, checked in by cfuguet, 11 years ago

Adding tsar_generic_xbar platform in branches/v5/platforms:

This platform contains a third local crossbar interconnect for the CLACK network.

It works only in a monocluster topology

File size: 11.3 KB

Rev	Line
[345]	1	//////////////////////////////////////////////////////////////////////////////
[396]	2	// File: tsar_xbar_cluster.h
[428]	3	// Author: Alain Greiner
[345]	4	// Copyright: UPMC/LIP6
[396]	5	// Date : march 2013
[345]	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8
[378]	9	#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H
	10	#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H
[345]	11
	12	#include <systemc>
	13	#include <sys/time.h>
	14	#include <iostream>
	15	#include <sstream>
	16	#include <cstdlib>
	17	#include <cstdarg>
	18
	19	#include "gdbserver.h"
	20	#include "mapping_table.h"
	21	#include "mips32.h"
	22	#include "vci_simple_ram.h"
[436]	23	#include "vci_simple_rom.h"
[345]	24	#include "vci_xicu.h"
	25	#include "dspin_local_crossbar.h"
	26	#include "vci_dspin_initiator_wrapper.h"
	27	#include "vci_dspin_target_wrapper.h"
	28	#include "virtual_dspin_router.h"
	29	#include "vci_multi_tty.h"
	30	#include "vci_multi_nic.h"
[378]	31	#include "vci_block_device_tsar.h"
[345]	32	#include "vci_framebuffer.h"
	33	#include "vci_multi_dma.h"
[351]	34	#include "vci_mem_cache.h"
	35	#include "vci_cc_vcache_wrapper.h"
[345]	36
[389]	37	namespace soclib { namespace caba {
	38
[345]	39	///////////////////////////////////////////////////////////////////////////
[396]	40	template<size_t dspin_cmd_width,
[428]	41	size_t dspin_rsp_width,
[396]	42	typename vci_param_int,
[428]	43	typename vci_param_ext> class TsarXbarCluster
[345]	44	///////////////////////////////////////////////////////////////////////////
	45	: public soclib::caba::BaseModule
	46	{
[396]	47	public:
[345]	48
[428]	49	// Ports
	50	sc_in<bool> p_clk;
	51	sc_in<bool> p_resetn;
	52	soclib::caba::DspinOutput<dspin_cmd_width> **p_cmd_out;
	53	soclib::caba::DspinInput<dspin_cmd_width> **p_cmd_in;
	54	soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out;
	55	soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in;
[389]	56
[345]	57	// interrupt signals
[428]	58	sc_signal<bool> signal_false;
	59	sc_signal<bool> signal_proc_it[8];
	60	sc_signal<bool> signal_irq_mdma[8];
	61	sc_signal<bool> signal_irq_mtty[23];
	62	sc_signal<bool> signal_irq_mnic_rx[8]; // unused
	63	sc_signal<bool> signal_irq_mnic_tx[8]; // unused
	64	sc_signal<bool> signal_irq_bdev;
[345]	65
[428]	66	// DSPIN signals between DSPIN routers and local_crossbars
	67	DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d;
	68	DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d;
	69	DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c;
	70	DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c;
[447]	71	DspinSignals<dspin_cmd_width> signal_dspin_clack_l2g_c;
	72	DspinSignals<dspin_cmd_width> signal_dspin_clack_g2l_c;
[428]	73	DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d;
	74	DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d;
	75	DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c;
	76	DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c;
[345]	77
[428]	78	// Direct VCI signals to VCI/DSPIN wrappers
	79	VciSignals<vci_param_int> signal_vci_ini_proc[8];
	80	VciSignals<vci_param_int> signal_vci_ini_mdma;
	81	VciSignals<vci_param_int> signal_vci_ini_bdev;
[345]	82
[428]	83	VciSignals<vci_param_int> signal_vci_tgt_memc;
	84	VciSignals<vci_param_int> signal_vci_tgt_xicu;
	85	VciSignals<vci_param_int> signal_vci_tgt_mdma;
	86	VciSignals<vci_param_int> signal_vci_tgt_mtty;
	87	VciSignals<vci_param_int> signal_vci_tgt_bdev;
	88	VciSignals<vci_param_int> signal_vci_tgt_brom;
	89	VciSignals<vci_param_int> signal_vci_tgt_fbuf;
	90	VciSignals<vci_param_int> signal_vci_tgt_mnic;
[345]	91
[428]	92	// Direct DSPIN signals to local crossbars
	93	DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc_i[8];
	94	DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc_i[8];
	95	DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_i;
	96	DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_i;
	97	DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_i;
	98	DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_i;
[345]	99
[428]	100	DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t;
	101	DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t;
	102	DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t;
	103	DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t;
	104	DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_t;
	105	DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_t;
	106	DspinSignals<dspin_cmd_width> signal_dspin_cmd_mtty_t;
	107	DspinSignals<dspin_rsp_width> signal_dspin_rsp_mtty_t;
	108	DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_t;
	109	DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_t;
	110	DspinSignals<dspin_cmd_width> signal_dspin_cmd_brom_t;
	111	DspinSignals<dspin_rsp_width> signal_dspin_rsp_brom_t;
	112	DspinSignals<dspin_cmd_width> signal_dspin_cmd_fbuf_t;
	113	DspinSignals<dspin_rsp_width> signal_dspin_rsp_fbuf_t;
	114	DspinSignals<dspin_cmd_width> signal_dspin_cmd_mnic_t;
	115	DspinSignals<dspin_rsp_width> signal_dspin_rsp_mnic_t;
[345]	116
[428]	117	// Coherence DSPIN signals to local crossbar
	118	DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc;
[447]	119	DspinSignals<dspin_cmd_width> signal_dspin_clack_memc;
[428]	120	DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc;
	121	DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[8];
[447]	122	DspinSignals<dspin_cmd_width> signal_dspin_clack_proc[8];
[428]	123	DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[8];
	124
	125	// external RAM to MEMC VCI signal
	126	VciSignals<vci_param_ext> signal_vci_xram;
	127
[345]	128	// Components
	129
[428]	130	VciCcVCacheWrapper<vci_param_int,
[396]	131	dspin_cmd_width,
	132	dspin_rsp_width,
	133	GdbServer<Mips32ElIss> >* proc[8];
[345]	134
[396]	135	VciDspinInitiatorWrapper<vci_param_int,
	136	dspin_cmd_width,
	137	dspin_rsp_width>* wi_proc[8];
[345]	138
[428]	139	VciMemCache<vci_param_int,
	140	vci_param_ext,
	141	dspin_rsp_width,
[396]	142	dspin_cmd_width>* memc;
[345]	143
[396]	144	VciDspinTargetWrapper<vci_param_int,
	145	dspin_cmd_width,
	146	dspin_rsp_width>* wt_memc;
[345]	147
[396]	148	VciXicu<vci_param_int>* xicu;
[345]	149
[396]	150	VciDspinTargetWrapper<vci_param_int,
	151	dspin_cmd_width,
	152	dspin_rsp_width>* wt_xicu;
[345]	153
[396]	154	VciMultiDma<vci_param_int>* mdma;
[345]	155
[396]	156	VciDspinInitiatorWrapper<vci_param_int,
	157	dspin_cmd_width,
	158	dspin_rsp_width>* wi_mdma;
[345]	159
[396]	160	VciDspinTargetWrapper<vci_param_int,
	161	dspin_cmd_width,
	162	dspin_rsp_width>* wt_mdma;
[345]	163
[396]	164	VciSimpleRam<vci_param_ext>* xram;
[345]	165
[436]	166	VciSimpleRom<vci_param_int>* brom;
[345]	167
[396]	168	VciDspinTargetWrapper<vci_param_int,
	169	dspin_cmd_width,
	170	dspin_rsp_width>* wt_brom;
[345]	171
[396]	172	VciMultiTty<vci_param_int>* mtty;
	173
	174	VciDspinTargetWrapper<vci_param_int,
	175	dspin_cmd_width,
	176	dspin_rsp_width>* wt_mtty;
	177
	178	VciFrameBuffer<vci_param_int>* fbuf;
	179
	180	VciDspinTargetWrapper<vci_param_int,
	181	dspin_cmd_width,
	182	dspin_rsp_width>* wt_fbuf;
	183
	184	VciMultiNic<vci_param_int>* mnic;
	185
	186	VciDspinTargetWrapper<vci_param_int,
	187	dspin_cmd_width,
	188	dspin_rsp_width>* wt_mnic;
	189
	190	VciBlockDeviceTsar<vci_param_int>* bdev;
	191
	192	VciDspinInitiatorWrapper<vci_param_int,
	193	dspin_cmd_width,
	194	dspin_rsp_width>* wi_bdev;
	195
	196	VciDspinTargetWrapper<vci_param_int,
	197	dspin_cmd_width,
	198	dspin_rsp_width>* wt_bdev;
	199
	200	DspinLocalCrossbar<dspin_cmd_width>* xbar_cmd_d;
	201	DspinLocalCrossbar<dspin_rsp_width>* xbar_rsp_d;
	202	DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p_c;
	203	DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m_c;
[447]	204	DspinLocalCrossbar<dspin_cmd_width>* xbar_clack_c;
[396]	205
	206	VirtualDspinRouter<dspin_cmd_width>* router_cmd;
	207	VirtualDspinRouter<dspin_rsp_width>* router_rsp;
	208
[428]	209	TsarXbarCluster( sc_module_name insname,
	210	size_t nb_procs, // processors
	211	size_t nb_ttys, // TTY terminals
	212	size_t nb_dmas, // DMA channels
[345]	213	size_t x, // x coordinate
	214	size_t y, // y coordinate
	215	size_t cluster, // y + ymax*x
[396]	216	const soclib::common::MappingTable &mtd, // internal
	217	const soclib::common::MappingTable &mtx, // external
[428]	218	size_t x_width, // x field bits
	219	size_t y_width, // y field bits
	220	size_t l_width, // l field bits
	221	size_t tgtid_memc,
	222	size_t tgtid_xicu,
[345]	223	size_t tgtid_mdma,
[389]	224	size_t tgtid_fbuf,
[345]	225	size_t tgtid_mtty,
	226	size_t tgtid_brom,
	227	size_t tgtid_mnic,
	228	size_t tgtid_bdev,
	229	size_t memc_ways,
	230	size_t memc_sets,
	231	size_t l1_i_ways,
[428]	232	size_t l1_i_sets,
[345]	233	size_t l1_d_ways,
[428]	234	size_t l1_d_sets,
	235	size_t xram_latency, // external ram
	236	bool io, // I/O cluster
[396]	237	size_t xfb, // fbf pixels
	238	size_t yfb, // fbf lines
[428]	239	char* disk_name, // virtual disk
	240	size_t block_size, // block size
[396]	241	size_t nic_channels, // number channels
[428]	242	char* nic_rx_name, // filename rx
	243	char* nic_tx_name, // filename tx
	244	uint32_t nic_timeout, // cycles
	245	const Loader &loader,
	246	uint32_t frozen_cycles,
[345]	247	uint32_t start_debug_cycle,
[428]	248	bool memc_debug_ok,
	249	bool proc_debug_ok);
[345]	250
	251	};
	252	}}
	253
	254	#endif

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