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source: branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 447

Last change on this file since 447 was 447, checked in by cfuguet, 11 years ago

Adding tsar_generic_xbar platform in branches/v5/platforms:

This platform contains a third local crossbar interconnect for the CLACK network.

It works only in a monocluster topology

File size: 33.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_bdev,
60	size_t memc_ways,
61	size_t memc_sets,
62	size_t l1_i_ways,
63	size_t l1_i_sets,
64	size_t l1_d_ways,
65	size_t l1_d_sets,
66	size_t xram_latency,
67	bool io,
68	size_t xfb,
69	size_t yfb,
70	char* disk_name,
71	size_t block_size,
72	size_t nic_channels,
73	char* nic_rx_name,
74	char* nic_tx_name,
75	uint32_t nic_timeout,
76	const Loader &loader,
77	uint32_t frozen_cycles,
78	uint32_t debug_start_cycle,
79	bool memc_debug_ok,
80	bool proc_debug_ok)
81	: soclib::caba::BaseModule(insname),
82	p_clk("clk"),
83	p_resetn("resetn")
84
85	{
86	// Vectors of ports definition
87	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4);
88	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4);
89	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4);
90	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4);
91
92	/////////////////////////////////////////////////////////////////////////////
93	// Components definition
94	/////////////////////////////////////////////////////////////////////////////
95
96	for (size_t p = 0; p < nb_procs; p++)
97	{
98	std::ostringstream sproc;
99	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
100	proc[p] = new VciCcVCacheWrapper<vci_param_int,
101	dspin_cmd_width,
102	dspin_rsp_width,
103	GdbServer<Mips32ElIss> >(
104	sproc.str().c_str(),
105	cluster_id*nb_procs + p, // GLOBAL PROC_ID
106	mtd, // Mapping Table
107	IntTab(cluster_id,p), // SRCID
108	(cluster_id << l_width) + p, // CC_GLOBAL_ID
109	8, // ITLB ways
110	8, // ITLB sets
111	8, // DTLB ways
112	8, // DTLB sets
113	l1_i_ways,l1_i_sets,16, // ICACHE size
114	l1_d_ways,l1_d_sets,16, // DCACHE size
115	4, // WBUF nlines
116	4, // WBUF nwords
117	x_width,
118	y_width,
119	frozen_cycles, // max frozen cycles
120	debug_start_cycle,
121	proc_debug_ok);
122
123	std::ostringstream swip;
124	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
125	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
126	dspin_cmd_width,
127	dspin_rsp_width>(
128	swip.str().c_str(),
129	x_width + y_width + l_width);
130	}
131
132	/////////////////////////////////////////////////////////////////////////////
133	std::ostringstream smemc;
134	smemc << "memc_" << x_id << "_" << y_id;
135	memc = new VciMemCache<vci_param_int,
136	vci_param_ext,
137	dspin_rsp_width,
138	dspin_cmd_width>(
139	smemc.str().c_str(),
140	mtd, // Mapping Table direct space
141	mtx, // Mapping Table external space
142	IntTab(cluster_id), // SRCID external space
143	IntTab(cluster_id, tgtid_memc), // TGTID direct space
144	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
145	memc_ways, memc_sets, 16, // CACHE SIZE
146	3, // MAX NUMBER OF COPIES
147	4096, // HEAP SIZE
148	8, // TRANSACTION TABLE DEPTH
149	8, // UPDATE TABLE DEPTH
150	8, // INVALIDATE TABLE DEPTH
151	debug_start_cycle,
152	memc_debug_ok );
153
154	wt_memc = new VciDspinTargetWrapper<vci_param_int,
155	dspin_cmd_width,
156	dspin_rsp_width>(
157	"wt_memc",
158	x_width + y_width + l_width);
159
160	/////////////////////////////////////////////////////////////////////////////
161	std::ostringstream sxram;
162	sxram << "xram_" << x_id << "_" << y_id;
163	xram = new VciSimpleRam<vci_param_ext>(
164	sxram.str().c_str(),
165	IntTab(cluster_id),
166	mtx,
167	loader,
168	xram_latency);
169
170	/////////////////////////////////////////////////////////////////////////////
171	std::ostringstream sxicu;
172	sxicu << "xicu_" << x_id << "_" << y_id;
173	xicu = new VciXicu<vci_param_int>(
174	sxicu.str().c_str(),
175	mtd, // mapping table
176	IntTab(cluster_id, tgtid_xicu), // TGTID_D
177	nb_procs, // number of timer IRQs
178	32, // number of hard IRQs
179	32, // number of soft IRQs
180	nb_procs); // number of output IRQs
181
182	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
183	dspin_cmd_width,
184	dspin_rsp_width>(
185	"wt_xicu",
186	x_width + y_width + l_width);
187
188	/////////////////////////////////////////////////////////////////////////////
189	std::ostringstream smdma;
190	smdma << "mdma_" << x_id << "_" << y_id;
191	mdma = new VciMultiDma<vci_param_int>(
192	smdma.str().c_str(),
193	mtd,
194	IntTab(cluster_id, nb_procs), // SRCID
195	IntTab(cluster_id, tgtid_mdma), // TGTID
196	64, // burst size
197	nb_dmas); // number of IRQs
198
199	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
200	dspin_cmd_width,
201	dspin_rsp_width>(
202	"wt_mdma",
203	x_width + y_width + l_width);
204
205	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
206	dspin_cmd_width,
207	dspin_rsp_width>(
208	"wi_mdma",
209	x_width + y_width + l_width);
210
211	/////////////////////////////////////////////////////////////////////////////
212	size_t nb_direct_initiators = nb_procs + 1;
213	size_t nb_direct_targets = 3;
214	if ( io )
215	{
216	nb_direct_initiators = nb_procs + 2;
217	nb_direct_targets = 8;
218	}
219
220	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
221	"xbar_cmd_d",
222	mtd, // mapping table
223	x_id, y_id, // cluster coordinates
224	x_width, y_width, l_width,
225	nb_direct_initiators, // number of local of sources
226	nb_direct_targets, // number of local dests
227	2, 2, // fifo depths
228	true, // CMD
229	true, // use local routing table
230	false ); // no broadcast
231
232	/////////////////////////////////////////////////////////////////////////////
233	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
234	"xbar_rsp_d",
235	mtd, // mapping table
236	x_id, y_id, // cluster coordinates
237	x_width, y_width, l_width,
238	nb_direct_targets, // number of local sources
239	nb_direct_initiators, // number of local dests
240	2, 2, // fifo depths
241	false, // RSP
242	false, // don't use local routing table
243	false ); // no broadcast
244
245	/////////////////////////////////////////////////////////////////////////////
246	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
247	"xbar_m2p_c",
248	mtd, // mapping table
249	x_id, y_id, // cluster coordinates
250	x_width, y_width, l_width,
251	1, // number of local sources
252	nb_procs, // number of local targets
253	2, 2, // fifo depths
254	true, // CMD
255	false, // don't use local routing table
256	true ); // broadcast
257
258	/////////////////////////////////////////////////////////////////////////////
259	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
260	"xbar_p2m_c",
261	mtd, // mapping table
262	x_id, y_id, // cluster coordinates
263	x_width, y_width, 0, // l_width unused on p2m network
264	nb_procs, // number of local sources
265	1, // number of local dests
266	2, 2, // fifo depths
267	false, // RSP
268	false, // don't use local routing table
269	false ); // no broadcast
270
271	/////////////////////////////////////////////////////////////////////////////
272	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
273	"xbar_clack_c",
274	mtd, // mapping table
275	x_id, y_id, // cluster coordinates
276	x_width, y_width, l_width,
277	1, // number of local sources
278	nb_procs, // number of local targets
279	1, 1, // fifo depths
280	true, // CMD
281	false, // don't use local routing table
282	false); // broadcast
283
284	/////////////////////////////////////////////////////////////////////////////
285	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
286	"router_cmd",
287	x_id,y_id, // coordinate in the mesh
288	x_width, y_width, // x & y fields width
289	4,4); // input & output fifo depths
290
291	/////////////////////////////////////////////////////////////////////////////
292	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
293	"router_rsp",
294	x_id,y_id, // coordinates in mesh
295	x_width, y_width, // x & y fields width
296	4,4); // input & output fifo depths
297
298	// IO cluster components
299	if ( io )
300	{
301	/////////////////////////////////////////////
302	brom = new VciSimpleRom<vci_param_int>(
303	"brom",
304	IntTab(cluster_id, tgtid_brom),
305	mtd,
306	loader);
307
308	wt_brom = new VciDspinTargetWrapper<vci_param_int,
309	dspin_cmd_width,
310	dspin_rsp_width>(
311	"wt_brom",
312	x_width + y_width + l_width);
313
314	/////////////////////////////////////////////
315	fbuf = new VciFrameBuffer<vci_param_int>(
316	"fbuf",
317	IntTab(cluster_id, tgtid_fbuf),
318	mtd,
319	xfb, yfb);
320
321	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
322	dspin_cmd_width,
323	dspin_rsp_width>(
324	"wt_fbuf",
325	x_width + y_width + l_width);
326
327	/////////////////////////////////////////////
328	bdev = new VciBlockDeviceTsar<vci_param_int>(
329	"bdev",
330	mtd,
331	IntTab(cluster_id, nb_procs+1),
332	IntTab(cluster_id, tgtid_bdev),
333	disk_name,
334	block_size,
335	64); // burst size
336
337	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
338	dspin_cmd_width,
339	dspin_rsp_width>(
340	"wt_bdev",
341	x_width + y_width + l_width);
342
343	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
344	dspin_cmd_width,
345	dspin_rsp_width>(
346	"wi_bdev",
347	x_width + y_width + l_width);
348
349	/////////////////////////////////////////////
350	mnic = new VciMultiNic<vci_param_int>(
351	"mnic",
352	IntTab(cluster_id, tgtid_mnic),
353	mtd,
354	nic_channels,
355	nic_rx_name,
356	nic_tx_name,
357	0, // mac_4 address
358	0 ); // mac_2 address
359
360	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
361	dspin_cmd_width,
362	dspin_rsp_width>(
363	"wt_mnic",
364	x_width + y_width + l_width);
365
366	/////////////////////////////////////////////
367	std::vector<std::string> vect_names;
368	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
369	{
370	std::ostringstream term_name;
371	term_name << "term" << tid;
372	vect_names.push_back(term_name.str().c_str());
373	}
374	mtty = new VciMultiTty<vci_param_int>(
375	"mtty",
376	IntTab(cluster_id, tgtid_mtty),
377	mtd,
378	vect_names);
379
380	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
381	dspin_cmd_width,
382	dspin_rsp_width>(
383	"wt_mtty",
384	x_width + y_width + l_width);
385	}
386
387	////////////////////////////////////
388	// Connections are defined here
389	////////////////////////////////////
390
391	//////////////////////// CMD ROUTER and RSP ROUTER
392	router_cmd->p_clk (this->p_clk);
393	router_cmd->p_resetn (this->p_resetn);
394	router_rsp->p_clk (this->p_clk);
395	router_rsp->p_resetn (this->p_resetn);
396	for (int x = 0; x < 2; x++)
397	{
398	for(int y = 0; y < 4; y++)
399	{
400	router_cmd->p_out[x][y] (this->p_cmd_out[x][y]);
401	router_cmd->p_in[x][y] (this->p_cmd_in[x][y]);
402	router_rsp->p_out[x][y] (this->p_rsp_out[x][y]);
403	router_rsp->p_in[x][y] (this->p_rsp_in[x][y]);
404	}
405	}
406
407	router_cmd->p_out[0][4] (signal_dspin_cmd_g2l_d);
408	router_cmd->p_out[1][4] (signal_dspin_m2p_g2l_c);
409	router_cmd->p_in[0][4] (signal_dspin_cmd_l2g_d);
410	router_cmd->p_in[1][4] (signal_dspin_m2p_l2g_c);
411
412	router_rsp->p_out[0][4] (signal_dspin_rsp_g2l_d);
413	router_rsp->p_out[1][4] (signal_dspin_p2m_g2l_c);
414	router_rsp->p_in[0][4] (signal_dspin_rsp_l2g_d);
415	router_rsp->p_in[1][4] (signal_dspin_p2m_l2g_c);
416
417	std::cout << " - CMD & RSP routers connected" << std::endl;
418
419	///////////////////// CMD DSPIN local crossbar direct
420	xbar_cmd_d->p_clk (this->p_clk);
421	xbar_cmd_d->p_resetn (this->p_resetn);
422	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
423	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
424
425	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
426	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
427	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
428
429	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
430
431	for (size_t p = 0; p < nb_procs; p++)
432	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
433
434	if ( io )
435	{
436	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
437	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
438	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
439	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
440	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
441
442	xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i);
443	}
444
445	std::cout << " - Command Direct crossbar connected" << std::endl;
446
447	//////////////////////// RSP DSPIN local crossbar direct
448	xbar_rsp_d->p_clk (this->p_clk);
449	xbar_rsp_d->p_resetn (this->p_resetn);
450	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
451	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
452
453	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
454	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
455	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
456
457	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
458
459	for (size_t p = 0; p < nb_procs; p++)
460	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
461
462	if ( io )
463	{
464	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
465	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
466	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
467	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
468	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
469
470	xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i);
471	}
472
473	std::cout << " - Response Direct crossbar connected" << std::endl;
474
475	////////////////////// M2P DSPIN local crossbar coherence
476	xbar_m2p_c->p_clk (this->p_clk);
477	xbar_m2p_c->p_resetn (this->p_resetn);
478	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
479	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
480	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
481	for (size_t p = 0; p < nb_procs; p++)
482	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
483
484	std::cout << " - M2P Coherence crossbar connected" << std::endl;
485
486	////////////////////// CLACK DSPIN local crossbar coherence
487	xbar_clack_c->p_clk (this->p_clk);
488	xbar_clack_c->p_resetn (this->p_resetn);
489	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
490	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
491	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
492	for (size_t p = 0; p < nb_procs; p++)
493	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
494
495	std::cout << " - Clack Coherence crossbar connected" << std::endl;
496
497	////////////////////////// P2M DSPIN local crossbar coherence
498	xbar_p2m_c->p_clk (this->p_clk);
499	xbar_p2m_c->p_resetn (this->p_resetn);
500	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
501	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
502	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
503	for (size_t p = 0; p < nb_procs; p++)
504	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
505
506	std::cout << " - P2M Coherence crossbar connected" << std::endl;
507
508
509	//////////////////////////////////// Processors
510	for (size_t p = 0; p < nb_procs; p++)
511	{
512	proc[p]->p_clk (this->p_clk);
513	proc[p]->p_resetn (this->p_resetn);
514	proc[p]->p_vci (signal_vci_ini_proc[p]);
515	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
516	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
517	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
518	proc[p]->p_irq[0] (signal_proc_it[p]);
519	for ( size_t j = 1 ; j < 6 ; j++)
520	{
521	proc[p]->p_irq[j] (signal_false);
522	}
523
524	wi_proc[p]->p_clk (this->p_clk);
525	wi_proc[p]->p_resetn (this->p_resetn);
526	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
527	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
528	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
529	}
530
531	std::cout << " - Processors connected" << std::endl;
532
533	///////////////////////////////////// XICU
534	xicu->p_clk (this->p_clk);
535	xicu->p_resetn (this->p_resetn);
536	xicu->p_vci (signal_vci_tgt_xicu);
537	for ( size_t p=0 ; p<nb_procs ; p++)
538	{
539	xicu->p_irq[p] (signal_proc_it[p]);
540	}
541	for ( size_t i=0 ; i<32 ; i++)
542	{
543	if ( io ) // I/O cluster
544	{
545	if (i < 8) xicu->p_hwi[i] (signal_false);
546	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
547	else if (i < 16) xicu->p_hwi[i] (signal_false);
548	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
549	else if (i < 31) xicu->p_hwi[i] (signal_false);
550	else xicu->p_hwi[i] (signal_irq_bdev);
551	}
552	else // other clusters
553	{
554	if (i < 8) xicu->p_hwi[i] (signal_false);
555	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
556	else xicu->p_hwi[i] (signal_false);
557	}
558	}
559
560	// wrapper XICU
561	wt_xicu->p_clk (this->p_clk);
562	wt_xicu->p_resetn (this->p_resetn);
563	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
564	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
565	wt_xicu->p_vci (signal_vci_tgt_xicu);
566
567	std::cout << " - XICU connected" << std::endl;
568
569	//////////////////////////////////////////////// MEMC
570	memc->p_clk (this->p_clk);
571	memc->p_resetn (this->p_resetn);
572	memc->p_vci_ixr (signal_vci_xram);
573	memc->p_vci_tgt (signal_vci_tgt_memc);
574	memc->p_dspin_p2m (signal_dspin_p2m_memc);
575	memc->p_dspin_m2p (signal_dspin_m2p_memc);
576	memc->p_dspin_clack (signal_dspin_clack_memc);
577
578	// wrapper MEMC
579	wt_memc->p_clk (this->p_clk);
580	wt_memc->p_resetn (this->p_resetn);
581	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
582	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
583	wt_memc->p_vci (signal_vci_tgt_memc);
584
585	std::cout << " - MEMC connected" << std::endl;
586
587	/////////////////////////////////////////////// XRAM
588	xram->p_clk (this->p_clk);
589	xram->p_resetn (this->p_resetn);
590	xram->p_vci (signal_vci_xram);
591
592	std::cout << " - XRAM connected" << std::endl;
593
594	////////////////////////////////////////////// MDMA
595	mdma->p_clk (this->p_clk);
596	mdma->p_resetn (this->p_resetn);
597	mdma->p_vci_target (signal_vci_tgt_mdma);
598	mdma->p_vci_initiator (signal_vci_ini_mdma);
599	for (size_t i=0 ; i<nb_dmas ; i++)
600	mdma->p_irq[i] (signal_irq_mdma[i]);
601
602	// wrapper tgt MDMA
603	wt_mdma->p_clk (this->p_clk);
604	wt_mdma->p_resetn (this->p_resetn);
605	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
606	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
607	wt_mdma->p_vci (signal_vci_tgt_mdma);
608
609	// wrapper ini MDMA
610	wi_mdma->p_clk (this->p_clk);
611	wi_mdma->p_resetn (this->p_resetn);
612	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
613	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
614	wi_mdma->p_vci (signal_vci_ini_mdma);
615
616	std::cout << " - MDMA connected" << std::endl;
617
618	/////////////////////////////// Components in I/O cluster
619
620	if ( io )
621	{
622	// BDEV
623	bdev->p_clk (this->p_clk);
624	bdev->p_resetn (this->p_resetn);
625	bdev->p_irq (signal_irq_bdev);
626	bdev->p_vci_target (signal_vci_tgt_bdev);
627	bdev->p_vci_initiator (signal_vci_ini_bdev);
628
629	// wrapper tgt BDEV
630	wt_bdev->p_clk (this->p_clk);
631	wt_bdev->p_resetn (this->p_resetn);
632	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
633	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
634	wt_bdev->p_vci (signal_vci_tgt_bdev);
635
636	// wrapper ini BDEV
637	wi_bdev->p_clk (this->p_clk);
638	wi_bdev->p_resetn (this->p_resetn);
639	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
640	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
641	wi_bdev->p_vci (signal_vci_ini_bdev);
642
643	std::cout << " - BDEV connected" << std::endl;
644
645	// FBUF
646	fbuf->p_clk (this->p_clk);
647	fbuf->p_resetn (this->p_resetn);
648	fbuf->p_vci (signal_vci_tgt_fbuf);
649
650	// wrapper tgt FBUF
651	wt_fbuf->p_clk (this->p_clk);
652	wt_fbuf->p_resetn (this->p_resetn);
653	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
654	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
655	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
656
657	std::cout << " - FBUF connected" << std::endl;
658
659	// MNIC
660	mnic->p_clk (this->p_clk);
661	mnic->p_resetn (this->p_resetn);
662	mnic->p_vci (signal_vci_tgt_mnic);
663	for ( size_t i=0 ; i<nic_channels ; i++ )
664	{
665	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
666	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
667	}
668
669	// wrapper tgt MNIC
670	wt_mnic->p_clk (this->p_clk);
671	wt_mnic->p_resetn (this->p_resetn);
672	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
673	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
674	wt_mnic->p_vci (signal_vci_tgt_mnic);
675
676	std::cout << " - MNIC connected" << std::endl;
677
678	// BROM
679	brom->p_clk (this->p_clk);
680	brom->p_resetn (this->p_resetn);
681	brom->p_vci (signal_vci_tgt_brom);
682
683	// wrapper tgt BROM
684	wt_brom->p_clk (this->p_clk);
685	wt_brom->p_resetn (this->p_resetn);
686	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
687	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
688	wt_brom->p_vci (signal_vci_tgt_brom);
689
690	std::cout << " - BROM connected" << std::endl;
691
692	// MTTY
693	mtty->p_clk (this->p_clk);
694	mtty->p_resetn (this->p_resetn);
695	mtty->p_vci (signal_vci_tgt_mtty);
696	for ( size_t i=0 ; i<nb_ttys ; i++ )
697	{
698	mtty->p_irq[i] (signal_irq_mtty[i]);
699	}
700
701	// wrapper tgt MTTY
702	wt_mtty->p_clk (this->p_clk);
703	wt_mtty->p_resetn (this->p_resetn);
704	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
705	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
706	wt_mtty->p_vci (signal_vci_tgt_mtty);
707
708	std::cout << " - MTTY connected" << std::endl;
709	}
710	} // end constructor
711
712	}}
713
714	// Local Variables:
715	// tab-width: 3
716	// c-basic-offset: 3
717	// c-file-offsets:((innamespace . 0)(inline-open . 0))
718	// indent-tabs-mode: nil
719	// End:
720
721	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
722
723
724

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
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