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source: branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 448

Last change on this file since 448 was 448, checked in by cfuguet, 11 years ago

Modification in branches/v5/platforms/tsar_generic_xbar:

Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

File size: 34.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_bdev,
60	size_t memc_ways,
61	size_t memc_sets,
62	size_t l1_i_ways,
63	size_t l1_i_sets,
64	size_t l1_d_ways,
65	size_t l1_d_sets,
66	size_t xram_latency,
67	bool io,
68	size_t xfb,
69	size_t yfb,
70	char* disk_name,
71	size_t block_size,
72	size_t nic_channels,
73	char* nic_rx_name,
74	char* nic_tx_name,
75	uint32_t nic_timeout,
76	const Loader &loader,
77	uint32_t frozen_cycles,
78	uint32_t debug_start_cycle,
79	bool memc_debug_ok,
80	bool proc_debug_ok)
81	: soclib::caba::BaseModule(insname),
82	p_clk("clk"),
83	p_resetn("resetn")
84
85	{
86	// Vectors of ports definition
87	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4);
88	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4);
89	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4);
90	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4);
91	p_clack_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_clack_in", 4);
92	p_clack_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_clack_out", 4);
93
94	/////////////////////////////////////////////////////////////////////////////
95	// Components definition
96	/////////////////////////////////////////////////////////////////////////////
97
98	for (size_t p = 0; p < nb_procs; p++)
99	{
100	std::ostringstream sproc;
101	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
102	proc[p] = new VciCcVCacheWrapper<vci_param_int,
103	dspin_cmd_width,
104	dspin_rsp_width,
105	GdbServer<Mips32ElIss> >(
106	sproc.str().c_str(),
107	cluster_id*nb_procs + p, // GLOBAL PROC_ID
108	mtd, // Mapping Table
109	IntTab(cluster_id,p), // SRCID
110	(cluster_id << l_width) + p, // CC_GLOBAL_ID
111	8, // ITLB ways
112	8, // ITLB sets
113	8, // DTLB ways
114	8, // DTLB sets
115	l1_i_ways,l1_i_sets,16, // ICACHE size
116	l1_d_ways,l1_d_sets,16, // DCACHE size
117	4, // WBUF nlines
118	4, // WBUF nwords
119	x_width,
120	y_width,
121	frozen_cycles, // max frozen cycles
122	debug_start_cycle,
123	proc_debug_ok);
124
125	std::ostringstream swip;
126	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
127	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
128	dspin_cmd_width,
129	dspin_rsp_width>(
130	swip.str().c_str(),
131	x_width + y_width + l_width);
132	}
133
134	/////////////////////////////////////////////////////////////////////////////
135	std::ostringstream smemc;
136	smemc << "memc_" << x_id << "_" << y_id;
137	memc = new VciMemCache<vci_param_int,
138	vci_param_ext,
139	dspin_rsp_width,
140	dspin_cmd_width>(
141	smemc.str().c_str(),
142	mtd, // Mapping Table direct space
143	mtx, // Mapping Table external space
144	IntTab(cluster_id), // SRCID external space
145	IntTab(cluster_id, tgtid_memc), // TGTID direct space
146	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
147	memc_ways, memc_sets, 16, // CACHE SIZE
148	3, // MAX NUMBER OF COPIES
149	4096, // HEAP SIZE
150	8, // TRANSACTION TABLE DEPTH
151	8, // UPDATE TABLE DEPTH
152	8, // INVALIDATE TABLE DEPTH
153	debug_start_cycle,
154	memc_debug_ok );
155
156	wt_memc = new VciDspinTargetWrapper<vci_param_int,
157	dspin_cmd_width,
158	dspin_rsp_width>(
159	"wt_memc",
160	x_width + y_width + l_width);
161
162	/////////////////////////////////////////////////////////////////////////////
163	std::ostringstream sxram;
164	sxram << "xram_" << x_id << "_" << y_id;
165	xram = new VciSimpleRam<vci_param_ext>(
166	sxram.str().c_str(),
167	IntTab(cluster_id),
168	mtx,
169	loader,
170	xram_latency);
171
172	/////////////////////////////////////////////////////////////////////////////
173	std::ostringstream sxicu;
174	sxicu << "xicu_" << x_id << "_" << y_id;
175	xicu = new VciXicu<vci_param_int>(
176	sxicu.str().c_str(),
177	mtd, // mapping table
178	IntTab(cluster_id, tgtid_xicu), // TGTID_D
179	nb_procs, // number of timer IRQs
180	32, // number of hard IRQs
181	32, // number of soft IRQs
182	nb_procs); // number of output IRQs
183
184	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
185	dspin_cmd_width,
186	dspin_rsp_width>(
187	"wt_xicu",
188	x_width + y_width + l_width);
189
190	/////////////////////////////////////////////////////////////////////////////
191	std::ostringstream smdma;
192	smdma << "mdma_" << x_id << "_" << y_id;
193	mdma = new VciMultiDma<vci_param_int>(
194	smdma.str().c_str(),
195	mtd,
196	IntTab(cluster_id, nb_procs), // SRCID
197	IntTab(cluster_id, tgtid_mdma), // TGTID
198	64, // burst size
199	nb_dmas); // number of IRQs
200
201	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
202	dspin_cmd_width,
203	dspin_rsp_width>(
204	"wt_mdma",
205	x_width + y_width + l_width);
206
207	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
208	dspin_cmd_width,
209	dspin_rsp_width>(
210	"wi_mdma",
211	x_width + y_width + l_width);
212
213	/////////////////////////////////////////////////////////////////////////////
214	size_t nb_direct_initiators = nb_procs + 1;
215	size_t nb_direct_targets = 3;
216	if ( io )
217	{
218	nb_direct_initiators = nb_procs + 2;
219	nb_direct_targets = 8;
220	}
221
222	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
223	"xbar_cmd_d",
224	mtd, // mapping table
225	x_id, y_id, // cluster coordinates
226	x_width, y_width, l_width,
227	nb_direct_initiators, // number of local of sources
228	nb_direct_targets, // number of local dests
229	2, 2, // fifo depths
230	true, // CMD
231	true, // use local routing table
232	false ); // no broadcast
233
234	/////////////////////////////////////////////////////////////////////////////
235	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
236	"xbar_rsp_d",
237	mtd, // mapping table
238	x_id, y_id, // cluster coordinates
239	x_width, y_width, l_width,
240	nb_direct_targets, // number of local sources
241	nb_direct_initiators, // number of local dests
242	2, 2, // fifo depths
243	false, // RSP
244	false, // don't use local routing table
245	false ); // no broadcast
246
247	/////////////////////////////////////////////////////////////////////////////
248	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
249	"xbar_m2p_c",
250	mtd, // mapping table
251	x_id, y_id, // cluster coordinates
252	x_width, y_width, l_width,
253	1, // number of local sources
254	nb_procs, // number of local targets
255	2, 2, // fifo depths
256	true, // CMD
257	false, // don't use local routing table
258	true ); // broadcast
259
260	/////////////////////////////////////////////////////////////////////////////
261	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
262	"xbar_p2m_c",
263	mtd, // mapping table
264	x_id, y_id, // cluster coordinates
265	x_width, y_width, 0, // l_width unused on p2m network
266	nb_procs, // number of local sources
267	1, // number of local dests
268	2, 2, // fifo depths
269	false, // RSP
270	false, // don't use local routing table
271	false ); // no broadcast
272
273	/////////////////////////////////////////////////////////////////////////////
274	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
275	"xbar_clack_c",
276	mtd, // mapping table
277	x_id, y_id, // cluster coordinates
278	x_width, y_width, l_width,
279	1, // number of local sources
280	nb_procs, // number of local targets
281	1, 1, // fifo depths
282	true, // CMD
283	false, // don't use local routing table
284	false); // broadcast
285
286	/////////////////////////////////////////////////////////////////////////////
287	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
288	"router_cmd",
289	x_id,y_id, // coordinate in the mesh
290	x_width, y_width, // x & y fields width
291	4,4); // input & output fifo depths
292
293	/////////////////////////////////////////////////////////////////////////////
294	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
295	"router_rsp",
296	x_id,y_id, // coordinates in mesh
297	x_width, y_width, // x & y fields width
298	4,4); // input & output fifo depths
299
300	/////////////////////////////////////////////////////////////////////////////
301	router_clack = new DspinRouter<dspin_cmd_width>(
302	"router_clack",
303	x_id,y_id, // coordinates in mesh
304	x_width, y_width, // x & y fields width
305	4,4); // input & output fifo depths
306
307	// IO cluster components
308	if ( io )
309	{
310	/////////////////////////////////////////////
311	brom = new VciSimpleRom<vci_param_int>(
312	"brom",
313	IntTab(cluster_id, tgtid_brom),
314	mtd,
315	loader);
316
317	wt_brom = new VciDspinTargetWrapper<vci_param_int,
318	dspin_cmd_width,
319	dspin_rsp_width>(
320	"wt_brom",
321	x_width + y_width + l_width);
322
323	/////////////////////////////////////////////
324	fbuf = new VciFrameBuffer<vci_param_int>(
325	"fbuf",
326	IntTab(cluster_id, tgtid_fbuf),
327	mtd,
328	xfb, yfb);
329
330	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
331	dspin_cmd_width,
332	dspin_rsp_width>(
333	"wt_fbuf",
334	x_width + y_width + l_width);
335
336	/////////////////////////////////////////////
337	bdev = new VciBlockDeviceTsar<vci_param_int>(
338	"bdev",
339	mtd,
340	IntTab(cluster_id, nb_procs+1),
341	IntTab(cluster_id, tgtid_bdev),
342	disk_name,
343	block_size,
344	64); // burst size
345
346	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
347	dspin_cmd_width,
348	dspin_rsp_width>(
349	"wt_bdev",
350	x_width + y_width + l_width);
351
352	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
353	dspin_cmd_width,
354	dspin_rsp_width>(
355	"wi_bdev",
356	x_width + y_width + l_width);
357
358	/////////////////////////////////////////////
359	mnic = new VciMultiNic<vci_param_int>(
360	"mnic",
361	IntTab(cluster_id, tgtid_mnic),
362	mtd,
363	nic_channels,
364	nic_rx_name,
365	nic_tx_name,
366	0, // mac_4 address
367	0 ); // mac_2 address
368
369	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
370	dspin_cmd_width,
371	dspin_rsp_width>(
372	"wt_mnic",
373	x_width + y_width + l_width);
374
375	/////////////////////////////////////////////
376	std::vector<std::string> vect_names;
377	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
378	{
379	std::ostringstream term_name;
380	term_name << "term" << tid;
381	vect_names.push_back(term_name.str().c_str());
382	}
383	mtty = new VciMultiTty<vci_param_int>(
384	"mtty",
385	IntTab(cluster_id, tgtid_mtty),
386	mtd,
387	vect_names);
388
389	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
390	dspin_cmd_width,
391	dspin_rsp_width>(
392	"wt_mtty",
393	x_width + y_width + l_width);
394	}
395
396	////////////////////////////////////
397	// Connections are defined here
398	////////////////////////////////////
399
400	//////////////////////// CMD ROUTER and RSP ROUTER
401	router_cmd->p_clk (this->p_clk);
402	router_cmd->p_resetn (this->p_resetn);
403	router_rsp->p_clk (this->p_clk);
404	router_rsp->p_resetn (this->p_resetn);
405	router_clack->p_clk (this->p_clk);
406	router_clack->p_resetn (this->p_resetn);
407
408	for (int x = 0; x < 2; x++)
409	{
410	for(int y = 0; y < 4; y++)
411	{
412	router_cmd->p_out[x][y] (this->p_cmd_out[x][y]);
413	router_cmd->p_in[x][y] (this->p_cmd_in[x][y]);
414	router_rsp->p_out[x][y] (this->p_rsp_out[x][y]);
415	router_rsp->p_in[x][y] (this->p_rsp_in[x][y]);
416	}
417	}
418
419	for(int x = 0; x < 4; x++)
420	{
421	router_clack->p_out[x] (this->p_clack_out[x]);
422	router_clack->p_in[x] (this->p_clack_in[x]);
423	}
424
425	router_cmd->p_out[0][4] (signal_dspin_cmd_g2l_d);
426	router_cmd->p_out[1][4] (signal_dspin_m2p_g2l_c);
427	router_cmd->p_in[0][4] (signal_dspin_cmd_l2g_d);
428	router_cmd->p_in[1][4] (signal_dspin_m2p_l2g_c);
429
430	router_rsp->p_out[0][4] (signal_dspin_rsp_g2l_d);
431	router_rsp->p_out[1][4] (signal_dspin_p2m_g2l_c);
432	router_rsp->p_in[0][4] (signal_dspin_rsp_l2g_d);
433	router_rsp->p_in[1][4] (signal_dspin_p2m_l2g_c);
434
435	router_clack->p_out[4] (signal_dspin_clack_g2l_c);
436	router_clack->p_in[4] (signal_dspin_clack_l2g_c);
437
438
439	std::cout << " - CMD & RSP routers connected" << std::endl;
440
441	///////////////////// CMD DSPIN local crossbar direct
442	xbar_cmd_d->p_clk (this->p_clk);
443	xbar_cmd_d->p_resetn (this->p_resetn);
444	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
445	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
446
447	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
448	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
449	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
450
451	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
452
453	for (size_t p = 0; p < nb_procs; p++)
454	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
455
456	if ( io )
457	{
458	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
459	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
460	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
461	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
462	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
463
464	xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i);
465	}
466
467	std::cout << " - Command Direct crossbar connected" << std::endl;
468
469	//////////////////////// RSP DSPIN local crossbar direct
470	xbar_rsp_d->p_clk (this->p_clk);
471	xbar_rsp_d->p_resetn (this->p_resetn);
472	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
473	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
474
475	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
476	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
477	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
478
479	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
480
481	for (size_t p = 0; p < nb_procs; p++)
482	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
483
484	if ( io )
485	{
486	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
487	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
488	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
489	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
490	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
491
492	xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i);
493	}
494
495	std::cout << " - Response Direct crossbar connected" << std::endl;
496
497	////////////////////// M2P DSPIN local crossbar coherence
498	xbar_m2p_c->p_clk (this->p_clk);
499	xbar_m2p_c->p_resetn (this->p_resetn);
500	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
501	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
502	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
503	for (size_t p = 0; p < nb_procs; p++)
504	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
505
506	std::cout << " - M2P Coherence crossbar connected" << std::endl;
507
508	////////////////////// CLACK DSPIN local crossbar coherence
509	xbar_clack_c->p_clk (this->p_clk);
510	xbar_clack_c->p_resetn (this->p_resetn);
511	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
512	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
513	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
514	for (size_t p = 0; p < nb_procs; p++)
515	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
516
517	std::cout << " - Clack Coherence crossbar connected" << std::endl;
518
519	////////////////////////// P2M DSPIN local crossbar coherence
520	xbar_p2m_c->p_clk (this->p_clk);
521	xbar_p2m_c->p_resetn (this->p_resetn);
522	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
523	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
524	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
525	for (size_t p = 0; p < nb_procs; p++)
526	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
527
528	std::cout << " - P2M Coherence crossbar connected" << std::endl;
529
530
531	//////////////////////////////////// Processors
532	for (size_t p = 0; p < nb_procs; p++)
533	{
534	proc[p]->p_clk (this->p_clk);
535	proc[p]->p_resetn (this->p_resetn);
536	proc[p]->p_vci (signal_vci_ini_proc[p]);
537	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
538	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
539	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
540	proc[p]->p_irq[0] (signal_proc_it[p]);
541	for ( size_t j = 1 ; j < 6 ; j++)
542	{
543	proc[p]->p_irq[j] (signal_false);
544	}
545
546	wi_proc[p]->p_clk (this->p_clk);
547	wi_proc[p]->p_resetn (this->p_resetn);
548	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
549	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
550	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
551	}
552
553	std::cout << " - Processors connected" << std::endl;
554
555	///////////////////////////////////// XICU
556	xicu->p_clk (this->p_clk);
557	xicu->p_resetn (this->p_resetn);
558	xicu->p_vci (signal_vci_tgt_xicu);
559	for ( size_t p=0 ; p<nb_procs ; p++)
560	{
561	xicu->p_irq[p] (signal_proc_it[p]);
562	}
563	for ( size_t i=0 ; i<32 ; i++)
564	{
565	if ( io ) // I/O cluster
566	{
567	if (i < 8) xicu->p_hwi[i] (signal_false);
568	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
569	else if (i < 16) xicu->p_hwi[i] (signal_false);
570	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
571	else if (i < 31) xicu->p_hwi[i] (signal_false);
572	else xicu->p_hwi[i] (signal_irq_bdev);
573	}
574	else // other clusters
575	{
576	if (i < 8) xicu->p_hwi[i] (signal_false);
577	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
578	else xicu->p_hwi[i] (signal_false);
579	}
580	}
581
582	// wrapper XICU
583	wt_xicu->p_clk (this->p_clk);
584	wt_xicu->p_resetn (this->p_resetn);
585	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
586	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
587	wt_xicu->p_vci (signal_vci_tgt_xicu);
588
589	std::cout << " - XICU connected" << std::endl;
590
591	//////////////////////////////////////////////// MEMC
592	memc->p_clk (this->p_clk);
593	memc->p_resetn (this->p_resetn);
594	memc->p_vci_ixr (signal_vci_xram);
595	memc->p_vci_tgt (signal_vci_tgt_memc);
596	memc->p_dspin_p2m (signal_dspin_p2m_memc);
597	memc->p_dspin_m2p (signal_dspin_m2p_memc);
598	memc->p_dspin_clack (signal_dspin_clack_memc);
599
600	// wrapper MEMC
601	wt_memc->p_clk (this->p_clk);
602	wt_memc->p_resetn (this->p_resetn);
603	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
604	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
605	wt_memc->p_vci (signal_vci_tgt_memc);
606
607	std::cout << " - MEMC connected" << std::endl;
608
609	/////////////////////////////////////////////// XRAM
610	xram->p_clk (this->p_clk);
611	xram->p_resetn (this->p_resetn);
612	xram->p_vci (signal_vci_xram);
613
614	std::cout << " - XRAM connected" << std::endl;
615
616	////////////////////////////////////////////// MDMA
617	mdma->p_clk (this->p_clk);
618	mdma->p_resetn (this->p_resetn);
619	mdma->p_vci_target (signal_vci_tgt_mdma);
620	mdma->p_vci_initiator (signal_vci_ini_mdma);
621	for (size_t i=0 ; i<nb_dmas ; i++)
622	mdma->p_irq[i] (signal_irq_mdma[i]);
623
624	// wrapper tgt MDMA
625	wt_mdma->p_clk (this->p_clk);
626	wt_mdma->p_resetn (this->p_resetn);
627	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
628	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
629	wt_mdma->p_vci (signal_vci_tgt_mdma);
630
631	// wrapper ini MDMA
632	wi_mdma->p_clk (this->p_clk);
633	wi_mdma->p_resetn (this->p_resetn);
634	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
635	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
636	wi_mdma->p_vci (signal_vci_ini_mdma);
637
638	std::cout << " - MDMA connected" << std::endl;
639
640	/////////////////////////////// Components in I/O cluster
641
642	if ( io )
643	{
644	// BDEV
645	bdev->p_clk (this->p_clk);
646	bdev->p_resetn (this->p_resetn);
647	bdev->p_irq (signal_irq_bdev);
648	bdev->p_vci_target (signal_vci_tgt_bdev);
649	bdev->p_vci_initiator (signal_vci_ini_bdev);
650
651	// wrapper tgt BDEV
652	wt_bdev->p_clk (this->p_clk);
653	wt_bdev->p_resetn (this->p_resetn);
654	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
655	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
656	wt_bdev->p_vci (signal_vci_tgt_bdev);
657
658	// wrapper ini BDEV
659	wi_bdev->p_clk (this->p_clk);
660	wi_bdev->p_resetn (this->p_resetn);
661	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
662	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
663	wi_bdev->p_vci (signal_vci_ini_bdev);
664
665	std::cout << " - BDEV connected" << std::endl;
666
667	// FBUF
668	fbuf->p_clk (this->p_clk);
669	fbuf->p_resetn (this->p_resetn);
670	fbuf->p_vci (signal_vci_tgt_fbuf);
671
672	// wrapper tgt FBUF
673	wt_fbuf->p_clk (this->p_clk);
674	wt_fbuf->p_resetn (this->p_resetn);
675	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
676	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
677	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
678
679	std::cout << " - FBUF connected" << std::endl;
680
681	// MNIC
682	mnic->p_clk (this->p_clk);
683	mnic->p_resetn (this->p_resetn);
684	mnic->p_vci (signal_vci_tgt_mnic);
685	for ( size_t i=0 ; i<nic_channels ; i++ )
686	{
687	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
688	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
689	}
690
691	// wrapper tgt MNIC
692	wt_mnic->p_clk (this->p_clk);
693	wt_mnic->p_resetn (this->p_resetn);
694	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
695	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
696	wt_mnic->p_vci (signal_vci_tgt_mnic);
697
698	std::cout << " - MNIC connected" << std::endl;
699
700	// BROM
701	brom->p_clk (this->p_clk);
702	brom->p_resetn (this->p_resetn);
703	brom->p_vci (signal_vci_tgt_brom);
704
705	// wrapper tgt BROM
706	wt_brom->p_clk (this->p_clk);
707	wt_brom->p_resetn (this->p_resetn);
708	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
709	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
710	wt_brom->p_vci (signal_vci_tgt_brom);
711
712	std::cout << " - BROM connected" << std::endl;
713
714	// MTTY
715	mtty->p_clk (this->p_clk);
716	mtty->p_resetn (this->p_resetn);
717	mtty->p_vci (signal_vci_tgt_mtty);
718	for ( size_t i=0 ; i<nb_ttys ; i++ )
719	{
720	mtty->p_irq[i] (signal_irq_mtty[i]);
721	}
722
723	// wrapper tgt MTTY
724	wt_mtty->p_clk (this->p_clk);
725	wt_mtty->p_resetn (this->p_resetn);
726	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
727	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
728	wt_mtty->p_vci (signal_vci_tgt_mtty);
729
730	std::cout << " - MTTY connected" << std::endl;
731	}
732	} // end constructor
733
734	}}
735
736	// Local Variables:
737	// tab-width: 3
738	// c-basic-offset: 3
739	// c-file-offsets:((innamespace . 0)(inline-open . 0))
740	// indent-tabs-mode: nil
741	// End:
742
743	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
744
745
746

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Project-Id-Version: Trac 0.12
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