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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 383

Last change on this file since 383 was 383, checked in by haoliu, 11 years ago
bug fix in dcache fsm: in state DCACHE_MISS_CLEAN, we should use the victim nline for scan itlb and dtlb
File size: 228.6 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 1
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using namespace soclib::common;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	const int proc_id,
170	const MappingTable &mtd,
171	const IntTab &srcid,
172	const size_t cc_global_id,
173	const size_t itlb_ways,
174	const size_t itlb_sets,
175	const size_t dtlb_ways,
176	const size_t dtlb_sets,
177	const size_t icache_ways,
178	const size_t icache_sets,
179	const size_t icache_words,
180	const size_t dcache_ways,
181	const size_t dcache_sets,
182	const size_t dcache_words,
183	const size_t wbuf_nlines,
184	const size_t wbuf_nwords,
185	const size_t x_width,
186	const size_t y_width,
187	const uint32_t max_frozen_cycles,
188	const uint32_t debug_start_cycle,
189	const bool debug_ok )
190	: soclib::caba::BaseModule(name),
191
192	p_clk("p_clk"),
193	p_resetn("p_resetn"),
194	p_vci("p_vci"),
195	p_dspin_in("p_dspin_in"),
196	p_dspin_out("p_dspin_out"),
197
198	m_cacheability_table( mtd.getCacheabilityTable() ),
199	m_srcid( mtd.indexForId(srcid) ),
200	m_cc_global_id( cc_global_id ),
201	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
202	m_itlb_ways( itlb_ways ),
203	m_itlb_sets( itlb_sets ),
204	m_dtlb_ways( dtlb_ways ),
205	m_dtlb_sets( dtlb_sets ),
206	m_icache_ways( icache_ways ),
207	m_icache_sets( icache_sets ),
208	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
209	m_icache_words( icache_words ),
210	m_dcache_ways( dcache_ways ),
211	m_dcache_sets( dcache_sets ),
212	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
213	m_dcache_words( dcache_words ),
214	m_x_width( x_width ),
215	m_y_width( y_width ),
216	m_proc_id( proc_id ),
217	m_max_frozen_cycles( max_frozen_cycles ),
218	m_paddr_nbits( vci_param::N ),
219	m_debug_start_cycle( debug_start_cycle ),
220	m_debug_ok( debug_ok ),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240	r_icache_miss_clack("r_icache_miss_clack"),
241
242	r_icache_cc_way("r_icache_cc_way"),
243	r_icache_cc_set("r_icache_cc_set"),
244	r_icache_cc_word("r_icache_cc_word"),
245	r_icache_cc_need_write("r_icache_cc_need_write"),
246
247	r_icache_flush_count("r_icache_flush_count"),
248
249	r_icache_miss_req("r_icache_miss_req"),
250	r_icache_unc_req("r_icache_unc_req"),
251
252	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
253	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
254
255	r_icache_cc_send_req("r_icache_cc_send_req"),
256	r_icache_cc_send_type("r_icache_cc_send_type"),
257	r_icache_cc_send_nline("r_icache_cc_send_nline"),
258	r_icache_cc_send_way("r_icache_cc_send_way"),
259	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
260
261	r_dcache_fsm("r_dcache_fsm"),
262	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
263	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
264
265	r_dcache_wbuf_req("r_dcache_wbuf_req"),
266	r_dcache_updt_req("r_dcache_updt_req"),
267	r_dcache_save_vaddr("r_dcache_save_vaddr"),
268	r_dcache_save_wdata("r_dcache_save_wdata"),
269	r_dcache_save_be("r_dcache_save_be"),
270	r_dcache_save_paddr("r_dcache_save_paddr"),
271	r_dcache_save_cacheable("r_dcache_save_cacheable"),
272	r_dcache_save_cache_way("r_dcache_save_cache_way"),
273	r_dcache_save_cache_set("r_dcache_save_cache_set"),
274	r_dcache_save_cache_word("r_dcache_save_cache_word"),
275
276	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
277	r_dcache_dirty_way("r_dcache_dirty_way"),
278	r_dcache_dirty_set("r_dcache_dirty_set"),
279
280	r_dcache_vci_paddr("r_dcache_vci_paddr"),
281	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
282	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
283	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
284	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
285	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
286	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
287	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
290
291	r_dcache_xtn_way("r_dcache_xtn_way"),
292	r_dcache_xtn_set("r_dcache_xtn_set"),
293
294	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
295
296	r_dcache_miss_type("r_dcache_miss_type"),
297	r_dcache_miss_word("r_dcache_miss_word"),
298	r_dcache_miss_way("r_dcache_miss_way"),
299	r_dcache_miss_set("r_dcache_miss_set"),
300	r_dcache_miss_inval("r_dcache_miss_inval"),
301
302	r_dcache_cc_way("r_dcache_cc_way"),
303	r_dcache_cc_set("r_dcache_cc_set"),
304	r_dcache_cc_word("r_dcache_cc_word"),
305	r_dcache_cc_need_write("r_dcache_cc_need_write"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
310
311	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
312	r_dcache_tlb_ins("r_dcache_tlb_ins"),
313	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
314	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
315	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
316	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
317	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
318	r_dcache_tlb_way("r_dcache_tlb_way"),
319	r_dcache_tlb_set("r_dcache_tlb_set"),
320
321	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
322	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
323
324	r_dcache_xtn_req("r_dcache_xtn_req"),
325	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
326
327	r_dcache_cc_send_req("r_dcache_cc_send_req"),
328	r_dcache_cc_send_type("r_dcache_cc_send_type"),
329	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
330	r_dcache_cc_send_way("r_dcache_cc_send_way"),
331	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
332
333	r_vci_cmd_fsm("r_vci_cmd_fsm"),
334	r_vci_cmd_min("r_vci_cmd_min"),
335	r_vci_cmd_max("r_vci_cmd_max"),
336	r_vci_cmd_cpt("r_vci_cmd_cpt"),
337	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
338
339	r_vci_rsp_fsm("r_vci_rsp_fsm"),
340	r_vci_rsp_cpt("r_vci_rsp_cpt"),
341	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
342	r_vci_rsp_data_error("r_vci_rsp_data_error"),
343	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
344	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
345
346	r_cc_send_fsm("r_cc_send_fsm"),
347	r_cc_send_last_client("r_cc_send_last_client"),
348
349	r_cc_receive_fsm("r_cc_receive_fsm"),
350	r_cc_receive_data_ins("r_cc_receive_data_ins"),
351	r_cc_receive_word_idx("r_cc_receive_word_idx"),
352	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
353	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
354	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
355
356	r_cc_receive_icache_req("r_cc_receive_icache_req"),
357	r_cc_receive_icache_type("r_cc_receive_icache_type"),
358	r_cc_receive_icache_way("r_cc_receive_icache_way"),
359	r_cc_receive_icache_set("r_cc_receive_icache_set"),
360	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
361	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
362
363	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
364	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
365	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
366	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
367	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
368	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
369
370	r_iss(this->name(), proc_id),
371	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
372	r_icache("icache", icache_ways, icache_sets, icache_words),
373	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
374	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
375	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
376	{
377	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
378	"Need more PLEN bits.");
379
380	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
381	"Need more TRDID bits.");
382
383	assert( (icache_words == dcache_words) and
384	"icache_words and dcache_words parameters must be equal");
385
386	assert( (itlb_sets == dtlb_sets) and
387	"itlb_sets and dtlb_sets parameters must be etqual");
388
389	assert( (itlb_ways == dtlb_ways) and
390	"itlb_ways and dtlb_ways parameters must be etqual");
391
392	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
393	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
394	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
395	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
396	(uint32_log2(m_icache_words<<2));
397
398	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
399
400	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapper()
424	/////////////////////////////////////
425	{
426	delete [] r_dcache_in_tlb;
427	delete [] r_dcache_contains_ptd;
428	}
429
430	////////////////////////
431	tmpl(void)::print_cpi()
432	////////////////////////
433	{
434	std::cout << name() << " CPI = "
435	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
436	}
437
438	////////////////////////////////////
439	tmpl(void)::print_trace(size_t mode)
440	////////////////////////////////////
441	{
442	// b0 : write buffer trace
443	// b1 : write buffer verbose
444	// b2 : dcache trace
445	// b3 : icache trace
446	// b4 : dtlb trace
447	// b5 : itlb trace
448
449	std::cout << std::dec << "PROC " << name() << std::endl;
450
451	std::cout << " " << m_ireq << std::endl;
452	std::cout << " " << m_irsp << std::endl;
453	std::cout << " " << m_dreq << std::endl;
454	std::cout << " " << m_drsp << std::endl;
455
456	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
457	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
458	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
459	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
460	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
461	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
462	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
463	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
464	std::cout << std::endl;
465
466	if(mode & 0x01)
467	{
468	r_wbuf.printTrace((mode>>1)&1);
469	}
470	if(mode & 0x04)
471	{
472	std::cout << " Data Cache" << std::endl;
473	r_dcache.printTrace();
474	}
475	if(mode & 0x08)
476	{
477	std::cout << " Instruction Cache" << std::endl;
478	r_icache.printTrace();
479	}
480	if(mode & 0x10)
481	{
482	std::cout << " Data TLB" << std::endl;
483	r_dtlb.printTrace();
484	}
485	if(mode & 0x20)
486	{
487	std::cout << " Instruction TLB" << std::endl;
488	r_itlb.printTrace();
489	}
490	}
491
492	//////////////////////////////////////////
493	tmpl(void)::cache_monitor( paddr_t addr )
494	//////////////////////////////////////////
495	{
496	size_t cache_way;
497	size_t cache_set;
498	size_t cache_word;
499	uint32_t cache_rdata;
500	bool cache_hit = r_dcache.read_neutral( addr,
501	&cache_rdata,
502	&cache_way,
503	&cache_set,
504	&cache_word );
505	bool icache_hit = r_icache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	if ( cache_hit != m_debug_previous_hit )
511	{
512	std::cout << "PROC " << name()
513	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
514	<< " for adresse " << std::hex << addr
515	<< " / HIT = " << std::dec << cache_hit << std::endl;
516	m_debug_previous_hit = cache_hit;
517	}
518	if ( icache_hit != m_idebug_previous_hit )
519	{
520	std::cout << "PROC " << name()
521	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
522	<< " for adresse " << std::hex << addr
523	<< " / HIT = " << icache_hit << std::endl;
524	m_idebug_previous_hit = icache_hit;
525	}
526	}
527
528	/*
529	////////////////////////
530	tmpl(void)::print_stats()
531	////////////////////////
532	{
533	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
534	std::cout << name() << std::endl
535	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
536	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
537	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
538	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
539	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
540	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
541	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
542	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
543	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
544	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
545	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
546	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
547	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
548	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
549	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
550	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
551	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
552	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
553	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
555	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
556	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
557	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
558	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
559	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
560	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
561	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
562	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
563	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
564	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
565	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
566	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
567	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
568	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
569	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
570	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
571	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
572	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
573	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
574	}
575
576	////////////////////////
577	tmpl(void)::clear_stats()
578	////////////////////////
579	{
580	m_cpt_dcache_data_read = 0;
581	m_cpt_dcache_data_write = 0;
582	m_cpt_dcache_dir_read = 0;
583	m_cpt_dcache_dir_write = 0;
584	m_cpt_icache_data_read = 0;
585	m_cpt_icache_data_write = 0;
586	m_cpt_icache_dir_read = 0;
587	m_cpt_icache_dir_write = 0;
588
589	m_cpt_frz_cycles = 0;
590	m_cpt_dcache_frz_cycles = 0;
591	m_cpt_total_cycles = 0;
592
593	m_cpt_read = 0;
594	m_cpt_write = 0;
595	m_cpt_data_miss = 0;
596	m_cpt_ins_miss = 0;
597	m_cpt_unc_read = 0;
598	m_cpt_write_cached = 0;
599	m_cpt_ins_read = 0;
600
601	m_cost_write_frz = 0;
602	m_cost_data_miss_frz = 0;
603	m_cost_unc_read_frz = 0;
604	m_cost_ins_miss_frz = 0;
605
606	m_cpt_imiss_transaction = 0;
607	m_cpt_dmiss_transaction = 0;
608	m_cpt_unc_transaction = 0;
609	m_cpt_write_transaction = 0;
610	m_cpt_icache_unc_transaction = 0;
611
612	m_cost_imiss_transaction = 0;
613	m_cost_dmiss_transaction = 0;
614	m_cost_unc_transaction = 0;
615	m_cost_write_transaction = 0;
616	m_cost_icache_unc_transaction = 0;
617	m_length_write_transaction = 0;
618
619	m_cpt_ins_tlb_read = 0;
620	m_cpt_ins_tlb_miss = 0;
621	m_cpt_ins_tlb_update_acc = 0;
622
623	m_cpt_data_tlb_read = 0;
624	m_cpt_data_tlb_miss = 0;
625	m_cpt_data_tlb_update_acc = 0;
626	m_cpt_data_tlb_update_dirty = 0;
627	m_cpt_ins_tlb_hit_dcache = 0;
628	m_cpt_data_tlb_hit_dcache = 0;
629	m_cpt_ins_tlb_occup_cache = 0;
630	m_cpt_data_tlb_occup_cache = 0;
631
632	m_cost_ins_tlb_miss_frz = 0;
633	m_cost_data_tlb_miss_frz = 0;
634	m_cost_ins_tlb_update_acc_frz = 0;
635	m_cost_data_tlb_update_acc_frz = 0;
636	m_cost_data_tlb_update_dirty_frz = 0;
637	m_cost_ins_tlb_occup_cache_frz = 0;
638	m_cost_data_tlb_occup_cache_frz = 0;
639
640	m_cpt_itlbmiss_transaction = 0;
641	m_cpt_itlb_ll_transaction = 0;
642	m_cpt_itlb_sc_transaction = 0;
643	m_cpt_dtlbmiss_transaction = 0;
644	m_cpt_dtlb_ll_transaction = 0;
645	m_cpt_dtlb_sc_transaction = 0;
646	m_cpt_dtlb_ll_dirty_transaction = 0;
647	m_cpt_dtlb_sc_dirty_transaction = 0;
648
649	m_cost_itlbmiss_transaction = 0;
650	m_cost_itlb_ll_transaction = 0;
651	m_cost_itlb_sc_transaction = 0;
652	m_cost_dtlbmiss_transaction = 0;
653	m_cost_dtlb_ll_transaction = 0;
654	m_cost_dtlb_sc_transaction = 0;
655	m_cost_dtlb_ll_dirty_transaction = 0;
656	m_cost_dtlb_sc_dirty_transaction = 0;
657
658	m_cpt_cc_update_data = 0;
659	m_cpt_cc_inval_ins = 0;
660	m_cpt_cc_inval_data = 0;
661	m_cpt_cc_broadcast = 0;
662
663	m_cost_updt_data_frz = 0;
664	m_cost_inval_ins_frz = 0;
665	m_cost_inval_data_frz = 0;
666	m_cost_broadcast_frz = 0;
667
668	m_cpt_cc_cleanup_data = 0;
669	m_cpt_cc_cleanup_ins = 0;
670	}
671
672	*/
673
674	/////////////////////////
675	tmpl(void)::transition()
676	/////////////////////////
677	{
678	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
679	if ( not p_resetn.read() )
680	{
681	r_iss.reset();
682	r_wbuf.reset();
683	r_icache.reset();
684	r_dcache.reset();
685	r_itlb.reset();
686	r_dtlb.reset();
687
688	r_dcache_fsm = DCACHE_IDLE;
689	r_icache_fsm = ICACHE_IDLE;
690	r_vci_cmd_fsm = CMD_IDLE;
691	r_vci_rsp_fsm = RSP_IDLE;
692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
693	r_cc_send_fsm = CC_SEND_IDLE;
694
695	// reset dcache directory extension
696	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
697	{
698	r_dcache_in_tlb[i] = false;
699	r_dcache_contains_ptd[i] = false;
700	}
701
702	// Response FIFOs and cleanup buffer
703	r_vci_rsp_fifo_icache.init();
704	r_vci_rsp_fifo_dcache.init();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CC_SEND FSM
717	r_icache_cc_send_req = false;
718
719	// No pending write in pipeline
720	r_dcache_wbuf_req = false;
721	r_dcache_updt_req = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_cas_req = false;
727	r_dcache_vci_ll_req = false;
728	r_dcache_vci_sc_req = false;
729
730	// No uncacheable write pending
731	r_dcache_pending_unc_write = false;
732
733	// No processor XTN request pending
734	r_dcache_xtn_req = false;
735
736	// No request from DCACHE FSM to CC_SEND FSM
737	r_dcache_cc_send_req = false;
738
739	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
740	r_cc_receive_icache_req = false;
741	r_cc_receive_dcache_req = false;
742
743	// last cc_send client was dcache
744	r_cc_send_last_client = false;
745
746	// No pending cleanup after a replacement
747	r_icache_miss_clack = false;
748	r_dcache_miss_clack = false;
749
750	// No signalisation of a coherence request matching a pending miss
751	r_icache_miss_inval = false;
752	r_dcache_miss_inval = false;
753
754	// No signalisation of errors
755	r_vci_rsp_ins_error = false;
756	r_vci_rsp_data_error = false;
757
758	// Debug variables
759	m_debug_previous_hit = false;
760	m_idebug_previous_hit = false;
761	m_debug_dcache_fsm = false;
762	m_debug_icache_fsm = false;
763
764	// activity counters
765	m_cpt_dcache_data_read = 0;
766	m_cpt_dcache_data_write = 0;
767	m_cpt_dcache_dir_read = 0;
768	m_cpt_dcache_dir_write = 0;
769	m_cpt_icache_data_read = 0;
770	m_cpt_icache_data_write = 0;
771	m_cpt_icache_dir_read = 0;
772	m_cpt_icache_dir_write = 0;
773
774	m_cpt_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776	m_cpt_stop_simulation = 0;
777
778	m_cpt_data_miss = 0;
779	m_cpt_ins_miss = 0;
780	m_cpt_unc_read = 0;
781	m_cpt_write_cached = 0;
782	m_cpt_ins_read = 0;
783
784	m_cost_write_frz = 0;
785	m_cost_data_miss_frz = 0;
786	m_cost_unc_read_frz = 0;
787	m_cost_ins_miss_frz = 0;
788
789	m_cpt_imiss_transaction = 0;
790	m_cpt_dmiss_transaction = 0;
791	m_cpt_unc_transaction = 0;
792	m_cpt_write_transaction = 0;
793	m_cpt_icache_unc_transaction = 0;
794
795	m_cost_imiss_transaction = 0;
796	m_cost_dmiss_transaction = 0;
797	m_cost_unc_transaction = 0;
798	m_cost_write_transaction = 0;
799	m_cost_icache_unc_transaction = 0;
800	m_length_write_transaction = 0;
801
802	m_cpt_ins_tlb_read = 0;
803	m_cpt_ins_tlb_miss = 0;
804	m_cpt_ins_tlb_update_acc = 0;
805
806	m_cpt_data_tlb_read = 0;
807	m_cpt_data_tlb_miss = 0;
808	m_cpt_data_tlb_update_acc = 0;
809	m_cpt_data_tlb_update_dirty = 0;
810	m_cpt_ins_tlb_hit_dcache = 0;
811	m_cpt_data_tlb_hit_dcache = 0;
812	m_cpt_ins_tlb_occup_cache = 0;
813	m_cpt_data_tlb_occup_cache = 0;
814
815	m_cost_ins_tlb_miss_frz = 0;
816	m_cost_data_tlb_miss_frz = 0;
817	m_cost_ins_tlb_update_acc_frz = 0;
818	m_cost_data_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_dirty_frz = 0;
820	m_cost_ins_tlb_occup_cache_frz = 0;
821	m_cost_data_tlb_occup_cache_frz = 0;
822
823	m_cpt_ins_tlb_inval = 0;
824	m_cpt_data_tlb_inval = 0;
825	m_cost_ins_tlb_inval_frz = 0;
826	m_cost_data_tlb_inval_frz = 0;
827
828	m_cpt_cc_broadcast = 0;
829
830	m_cost_updt_data_frz = 0;
831	m_cost_inval_ins_frz = 0;
832	m_cost_inval_data_frz = 0;
833	m_cost_broadcast_frz = 0;
834
835	m_cpt_cc_cleanup_data = 0;
836	m_cpt_cc_cleanup_ins = 0;
837
838	m_cpt_itlbmiss_transaction = 0;
839	m_cpt_itlb_ll_transaction = 0;
840	m_cpt_itlb_sc_transaction = 0;
841	m_cpt_dtlbmiss_transaction = 0;
842	m_cpt_dtlb_ll_transaction = 0;
843	m_cpt_dtlb_sc_transaction = 0;
844	m_cpt_dtlb_ll_dirty_transaction = 0;
845	m_cpt_dtlb_sc_dirty_transaction = 0;
846
847	m_cost_itlbmiss_transaction = 0;
848	m_cost_itlb_ll_transaction = 0;
849	m_cost_itlb_sc_transaction = 0;
850	m_cost_dtlbmiss_transaction = 0;
851	m_cost_dtlb_ll_transaction = 0;
852	m_cost_dtlb_sc_transaction = 0;
853	m_cost_dtlb_ll_dirty_transaction = 0;
854	m_cost_dtlb_sc_dirty_transaction = 0;
855	/*
856	m_cpt_dcache_frz_cycles = 0;
857	m_cpt_read = 0;
858	m_cpt_write = 0;
859	m_cpt_cc_update_data = 0;
860	m_cpt_cc_inval_ins = 0;
861	m_cpt_cc_inval_data = 0;
862	*/
863
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
867	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
868
869	// init the llsc reservation buffer
870	r_dcache_llsc_valid = false;
871
872	return;
873	}
874
875	// Response FIFOs default values
876	bool vci_rsp_fifo_icache_get = false;
877	bool vci_rsp_fifo_icache_put = false;
878	uint32_t vci_rsp_fifo_icache_data = 0;
879
880	bool vci_rsp_fifo_dcache_get = false;
881	bool vci_rsp_fifo_dcache_put = false;
882	uint32_t vci_rsp_fifo_dcache_data = 0;
883
884	// updt fifo
885	bool cc_receive_updt_fifo_get = false;
886	bool cc_receive_updt_fifo_put = false;
887	uint32_t cc_receive_updt_fifo_be = 0;
888	uint32_t cc_receive_updt_fifo_data = 0;
889	bool cc_receive_updt_fifo_eop = false;
890
891	#ifdef INSTRUMENTATION
892	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
893	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
894	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
895	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
896	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
897	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
898	#endif
899
900	m_cpt_total_cycles++;
901
902	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
903	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904
905	/////////////////////////////////////////////////////////////////////
906	// Get data and instruction requests from processor
907	///////////////////////////////////////////////////////////////////////
908
909	r_iss.getRequests(m_ireq, m_dreq);
910
911	////////////////////////////////////////////////////////////////////////////////////
912	// ICACHE_FSM
913	//
914	// 1/ Coherence operations
915	// They are handled as interrupts generated by the CC_RECEIVE FSM.
916	// - There is a coherence request when r_tgt_icache_req is set.
917	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
918	// - There is a cleanup ack request when r_cleanup_icache_req is set.
919	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
920	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
921	// - For both types of requests, actions associated to the pre-empted state
922	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
923	// or CC_CLACK) to execute the requested coherence operation, and returns
924	// to the pre-empted state.
925	//
926	// 2/ Processor requests
927	// They are taken in IDLE state only. In case of cache miss, or uncacheable
928	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
929	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
930	// flip-flops are reset when the transaction starts.
931	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
932	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
933	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
934	// The availability of the missing cache line is signaled by the response fifo,
935	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
936	// and ICACHE_MISS_DIR_UPDT states.
937	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
938	// to wait the response from the RSP FSM, through the response fifo.
939	// The missing instruction is directly returned to processor in this state.
940	//
941	// 3/ TLB miss
942	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
943	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
944	// register, and goes to the ICACHE_TLB_WAIT state.
945	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
946	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
947	// to signal the completion.
948	//
949	// 4/ XTN requests
950	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
951	// using the r_dcache_xtn_req flip-flop.
952	// The request opcode and the address to be invalidated are transmitted
953	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
954	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
955	// is completed.
956	//
957	// 5/ Error Handling
958	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
959	// in a cache miss or uncacheable read VCI transaction. Nothing is written
960	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
961	////////////////////////////////////////////////////////////////////////////////////////
962
963	// default value for m_irsp
964	m_irsp.valid = false;
965	m_irsp.error = false;
966	m_irsp.instruction = 0;
967
968	switch( r_icache_fsm.read() )
969	{
970	/////////////////
971	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
972	// and coherence requests with a fixed priority:
973	// 1/ Coherence requests => ICACHE_CC_CHECK
974	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
975	// 3/ tlb miss => ICACHE_TLB_WAIT
976	// 4/ cacheable read miss => ICACHE_MISS_SELECT
977	// 5/ uncacheable read miss => ICACHE_UNC_REQ
978	{
979	// coherence interrupt
980	if ( r_cc_receive_icache_req.read() )
981	{
982	r_icache_fsm = ICACHE_CC_CHECK;
983	r_icache_fsm_save = r_icache_fsm.read();
984	break;
985	}
986
987	// XTN requests sent by DCACHE FSM
988	// These request are not executed in this IDLE state, because
989	// they require access to icache or itlb, that are already accessed
990	if ( r_dcache_xtn_req.read() )
991	{
992	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
993	{
994	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
995	}
996	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
997	{
998	r_icache_flush_count = 0;
999	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1002	{
1003	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1004	}
1005	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1006	{
1007	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1008	}
1009	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1010	{
1011	if (sizeof(paddr_t) <= 32)
1012	{
1013	assert(r_mmu_word_hi.read() == 0 &&
1014	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1015	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1016	}
1017	else
1018	{
1019	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1020	(paddr_t)r_mmu_word_lo.read();
1021	}
1022	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1023	}
1024	else
1025	{
1026	assert( false and
1027	"undefined XTN request received by ICACHE FSM");
1028	}
1029	break;
1030	} // end if xtn_req
1031
1032	// processor request
1033	if ( m_ireq.valid )
1034	{
1035	bool cacheable;
1036	paddr_t paddr;
1037	bool tlb_hit = false;
1038	pte_info_t tlb_flags;
1039	size_t tlb_way;
1040	size_t tlb_set;
1041	paddr_t tlb_nline;
1042	uint32_t cache_inst = 0;
1043	size_t cache_way;
1044	size_t cache_set;
1045	size_t cache_word;
1046	int cache_state = CACHE_SLOT_STATE_EMPTY;
1047
1048	// We register processor request
1049	r_icache_vaddr_save = m_ireq.addr;
1050
1051	// sytematic itlb access (if activated)
1052	if ( r_mmu_mode.read() & INS_TLB_MASK )
1053	{
1054
1055	#ifdef INSTRUMENTATION
1056	m_cpt_itlb_read++;
1057	#endif
1058	tlb_hit = r_itlb.translate( m_ireq.addr,
1059	&paddr,
1060	&tlb_flags,
1061	&tlb_nline, // unused
1062	&tlb_way, // unused
1063	&tlb_set ); // unused
1064	}
1065	else
1066	{
1067	paddr = (paddr_t)m_ireq.addr;
1068	}
1069
1070	// systematic icache access (if activated)
1071	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1072	{
1073
1074
1075	#ifdef INSTRUMENTATION
1076	m_cpt_icache_data_read++;
1077	m_cpt_icache_dir_read++;
1078	#endif
1079	r_icache.read( paddr,
1080	&cache_inst,
1081	&cache_way,
1082	&cache_set,
1083	&cache_word,
1084	&cache_state );
1085	}
1086
1087	// We compute cacheability and check access rights:
1088	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1089	// and the access rights are defined by the U and X bits in the PTE.
1090	// - If MMU not activated : cacheability is defined by the segment table,
1091	// and there is no access rights checking
1092
1093	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1094	{
1095	// cacheability
1096	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1097	else cacheable = m_cacheability_table[m_ireq.addr];
1098	}
1099	else // itlb activated
1100	{
1101	if ( tlb_hit ) // ITLB hit
1102	{
1103	// cacheability
1104	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1105	else cacheable = tlb_flags.c;
1106
1107	// access rights checking
1108	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1109	{
1110	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1111	r_mmu_ibvar = m_ireq.addr;
1112	m_irsp.valid = true;
1113	m_irsp.error = true;
1114	m_irsp.instruction = 0;
1115	break;
1116	}
1117	else if ( not tlb_flags.x )
1118	{
1119	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1120	r_mmu_ibvar = m_ireq.addr;
1121	m_irsp.valid = true;
1122	m_irsp.error = true;
1123	m_irsp.instruction = 0;
1124	break;
1125	}
1126	}
1127	else // ITLB miss
1128	{
1129
1130	#ifdef INSTRUMENTATION
1131	m_cpt_itlb_miss++;
1132	#endif
1133	r_icache_fsm = ICACHE_TLB_WAIT;
1134	r_icache_tlb_miss_req = true;
1135	break;
1136	}
1137	} // end if itlb activated
1138
1139	// physical address registration
1140	r_icache_vci_paddr = paddr;
1141
1142	// Finally, we send the response to processor, and compute next state
1143	if ( cacheable )
1144	{
1145	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_icache_miss++;
1150	#endif
1151	// we request a VCI transaction
1152	r_icache_fsm = ICACHE_MISS_SELECT;
1153	r_icache_miss_req = true;
1154	}
1155	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1156	{
1157	// stalled until cleanup is acknowledged
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	else // cache hit
1161	{
1162
1163	#ifdef INSTRUMENTATION
1164	m_cpt_ins_read++;
1165	#endif
1166	// return instruction to processor
1167	m_irsp.valid = true;
1168	m_irsp.instruction = cache_inst;
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	}
1172	else // non cacheable read
1173	{
1174	r_icache_unc_req = true;
1175	r_icache_fsm = ICACHE_UNC_WAIT;
1176	}
1177	} // end if m_ireq.valid
1178	break;
1179	}
1180	/////////////////////
1181	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1182	// the itlb is udated by the DCACHE FSM, as well as the
1183	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1184	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1185	// reset the r_icache_tlb_miss_req flip-flop
1186	// external coherence request are accepted in this state.
1187	{
1188	// coherence interrupt
1189	if ( r_cc_receive_icache_req.read() )
1190	{
1191	r_icache_fsm = ICACHE_CC_CHECK;
1192	r_icache_fsm_save = r_icache_fsm.read();
1193	break;
1194	}
1195
1196	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1197
1198	// DCACHE FSM signals response by reseting the request flip-flop
1199	if ( not r_icache_tlb_miss_req.read() )
1200	{
1201	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1202	{
1203	r_icache_tlb_rsp_error = false;
1204	m_irsp.error = true;
1205	m_irsp.valid = true;
1206	r_icache_fsm = ICACHE_IDLE;
1207	}
1208	else // tlb updated : return to IDLE state
1209	{
1210	r_icache_fsm = ICACHE_IDLE;
1211	}
1212	}
1213	break;
1214	}
1215	//////////////////////////
1216	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1217	{
1218	r_itlb.flush();
1219	r_dcache_xtn_req = false;
1220	r_icache_fsm = ICACHE_IDLE;
1221	break;
1222	}
1223	////////////////////////////
1224	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1225	// r_icache_flush_count as a slot counter,
1226	// looping in this state until all slots are visited.
1227	// It can require two cycles per slot:
1228	// We test here the slot state, and make the actual inval
1229	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1230	// A cleanup request is generated for each valid line
1231	{
1232	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1233	{
1234	int state;
1235	uint32_t tag;
1236	size_t way = r_icache_flush_count.read()/m_icache_sets;
1237	size_t set = r_icache_flush_count.read()%m_icache_sets;
1238
1239	#ifdef INSTRUMENTATION
1240	m_cpt_icache_dir_read++;
1241	#endif
1242	r_icache.read_dir( way,
1243	set,
1244	&tag,
1245	&state );
1246
1247	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1248	{
1249	// request cleanup
1250	r_icache_cc_send_req = true;
1251	r_icache_cc_send_nline = tag * m_icache_sets;
1252	r_icache_cc_send_way = way;
1253	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1254
1255	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1256	r_icache_miss_way = way;
1257	r_icache_miss_set = set;
1258	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1259	}
1260	else if ( r_icache_flush_count.read() ==
1261	(m_icache_sets*m_icache_ways - 1) ) // last slot
1262	{
1263	r_dcache_xtn_req = false;
1264	m_drsp.valid = true;
1265	r_icache_fsm = ICACHE_IDLE;
1266	}
1267
1268	// saturation counter, to have the same last slot condition
1269	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1270	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1271	{
1272	r_icache_flush_count = r_icache_flush_count.read() + 1;
1273	}
1274	}
1275	break;
1276	}
1277	///////////////////////////////
1278	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1279	{
1280	size_t way = r_icache_miss_way.read();
1281	size_t set = r_icache_miss_set.read();
1282
1283	#ifdef INSTRUMENTATION
1284	m_cpt_icache_dir_write++;
1285	#endif
1286
1287	r_icache.write_dir( way,
1288	set,
1289	CACHE_SLOT_STATE_ZOMBI );
1290
1291	if ( r_icache_flush_count.read() ==
1292	(m_icache_sets*m_icache_ways - 1) ) // last slot
1293	{
1294	r_dcache_xtn_req = false;
1295	m_drsp.valid = true;
1296	r_icache_fsm = ICACHE_IDLE;
1297	}
1298	else
1299	{
1300	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1301	}
1302	break;
1303	}
1304
1305	//////////////////////////
1306	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1307	// stored in the r_dcache_save_wdata register
1308	{
1309	r_itlb.inval(r_dcache_save_wdata.read());
1310	r_dcache_xtn_req = false;
1311	r_icache_fsm = ICACHE_IDLE;
1312	break;
1313	}
1314	///////////////////////////////
1315	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1316	// requires 3 cycles (in case of hit on itlb and icache).
1317	// In this state, access TLB to translate virtual address
1318	// stored in the r_dcache_save_wdata register.
1319	{
1320	paddr_t paddr;
1321	bool hit;
1322
1323	// read physical address in TLB when MMU activated
1324	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1325	{
1326
1327	#ifdef INSTRUMENTATION
1328	m_cpt_itlb_read++;
1329	#endif
1330	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1331	&paddr);
1332	}
1333	else // itlb not activated
1334	{
1335	paddr = (paddr_t)r_dcache_save_wdata.read();
1336	hit = true;
1337	}
1338
1339	if ( hit ) // continue the selective inval process
1340	{
1341	r_icache_vci_paddr = paddr;
1342	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1343	}
1344	else // miss : send a request to DCACHE FSM
1345	{
1346
1347	#ifdef INSTRUMENTATION
1348	m_cpt_itlb_miss++;
1349	#endif
1350	r_icache_tlb_miss_req = true;
1351	r_icache_vaddr_save = r_dcache_save_wdata.read();
1352	r_icache_fsm = ICACHE_TLB_WAIT;
1353	}
1354	break;
1355	}
1356	///////////////////////////////
1357	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1358	// require 2 cycles. In this state, we read directory
1359	// with address stored in r_icache_vci_paddr register.
1360	{
1361	int state;
1362	size_t way;
1363	size_t set;
1364	size_t word;
1365
1366	#ifdef INSTRUMENTATION
1367	m_cpt_icache_dir_read++;
1368	#endif
1369	r_icache.read_dir(r_icache_vci_paddr.read(),
1370	&state,
1371	&way,
1372	&set,
1373	&word);
1374
1375	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1376	{
1377	r_icache_miss_way = way;
1378	r_icache_miss_set = set;
1379	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1380	}
1381	else // miss : acknowlege the XTN request and return
1382	{
1383	r_dcache_xtn_req = false;
1384	r_icache_fsm = ICACHE_IDLE;
1385	}
1386	break;
1387	}
1388	///////////////////////////////
1389	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1390	{
1391	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1392	{
1393
1394	#ifdef INSTRUMENTATION
1395	m_cpt_icache_dir_write++;
1396	#endif
1397	r_icache.write_dir( r_icache_miss_way.read(),
1398	r_icache_miss_set.read(),
1399	CACHE_SLOT_STATE_ZOMBI );
1400
1401	// request cleanup
1402	r_icache_cc_send_req = true;
1403	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1404	r_icache_cc_send_way = r_icache_miss_way.read();
1405	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1406
1407	// acknowledge the XTN request and return
1408	r_dcache_xtn_req = false;
1409	r_icache_fsm = ICACHE_IDLE;
1410	}
1411	break;
1412	}
1413	////////////////////////
1414	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1415	// if previous cleanup has been sent.
1416	// Waiting in this state if no slot available.
1417	// Set the r_icache_cleanup_req flip-flop
1418	// and the r_icache_miss_clack flip-flop,
1419	// when a cleanup is required
1420	{
1421	if (m_ireq.valid) m_cost_ins_miss_frz++;
1422
1423	// coherence interrupt
1424	if ( r_cc_receive_icache_req.read() )
1425	{
1426	r_icache_fsm = ICACHE_CC_CHECK;
1427	r_icache_fsm_save = r_icache_fsm.read();
1428	break;
1429	}
1430
1431	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1432	{
1433	bool found;
1434	bool cleanup;
1435	size_t way;
1436	size_t set;
1437	paddr_t victim;
1438
1439	#ifdef INSTRUMENTATION
1440	m_cpt_icache_dir_read++;
1441	#endif
1442	r_icache.read_select(r_icache_vci_paddr.read(),
1443	&victim,
1444	&way,
1445	&set,
1446	&found,
1447	&cleanup );
1448	if ( found )
1449	{
1450	r_icache_miss_way = way;
1451	r_icache_miss_set = set;
1452
1453	if ( cleanup )
1454	{
1455	r_icache_fsm = ICACHE_MISS_CLEAN;
1456	r_icache_miss_clack = true;
1457	// request cleanup
1458	r_icache_cc_send_req = true;
1459	r_icache_cc_send_nline = victim;
1460	r_icache_cc_send_way = way;
1461	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1462	}
1463	else
1464	{
1465	r_icache_fsm = ICACHE_MISS_WAIT;
1466	}
1467
1468	#if DEBUG_ICACHE
1469	if ( m_debug_dcache_fsm )
1470	{
1471	std::cout << " <PROC " << name()
1472	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1473	<< " / WAY = " << way
1474	<< " / SET = " << set;
1475	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1476	else std::cout << std::endl;
1477	}
1478	#endif
1479	}
1480	}
1481	break;
1482	}
1483	///////////////////////
1484	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1485	{
1486	if (m_ireq.valid) m_cost_ins_miss_frz++;
1487
1488	#ifdef INSTRUMENTATION
1489	m_cpt_icache_dir_write++;
1490	#endif
1491	r_icache.write_dir( r_icache_miss_way.read(),
1492	r_icache_miss_set.read(),
1493	CACHE_SLOT_STATE_ZOMBI);
1494	#if DEBUG_ICACHE
1495	if ( m_debug_dcache_fsm )
1496	{
1497	std::cout << " <PROC " << name()
1498	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1499	<< " / WAY = " << r_icache_miss_way.read()
1500	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1501	}
1502	#endif
1503
1504	r_icache_fsm = ICACHE_MISS_WAIT;
1505	break;
1506	}
1507	//////////////////////
1508	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1509	{
1510	if (m_ireq.valid) m_cost_ins_miss_frz++;
1511
1512	// coherence interrupt
1513	if ( r_cc_receive_icache_req.read() )
1514	{
1515	r_icache_fsm = ICACHE_CC_CHECK;
1516	r_icache_fsm_save = r_icache_fsm.read();
1517	break;
1518	}
1519
1520	if ( r_vci_rsp_ins_error.read() ) // bus error
1521	{
1522	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1523	r_mmu_ibvar = r_icache_vaddr_save.read();
1524	m_irsp.valid = true;
1525	m_irsp.error = true;
1526	r_vci_rsp_ins_error = false;
1527	r_icache_fsm = ICACHE_IDLE;
1528	}
1529	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1530	{
1531	r_icache_miss_word = 0;
1532	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1533	}
1534	break;
1535	}
1536	///////////////////////////
1537	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1538	{
1539	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1540
1541	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1542	{
1543
1544	#ifdef INSTRUMENTATION
1545	m_cpt_icache_data_write++;
1546	#endif
1547	r_icache.write( r_icache_miss_way.read(),
1548	r_icache_miss_set.read(),
1549	r_icache_miss_word.read(),
1550	r_vci_rsp_fifo_icache.read() );
1551	#if DEBUG_ICACHE
1552	if ( m_debug_icache_fsm )
1553	{
1554	std::cout << " <PROC " << name()
1555	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1556	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1557	<< " WAY = " << r_icache_miss_way.read()
1558	<< " SET = " << r_icache_miss_set.read()
1559	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1560	}
1561	#endif
1562	vci_rsp_fifo_icache_get = true;
1563	r_icache_miss_word = r_icache_miss_word.read() + 1;
1564
1565	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1566	{
1567	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1568	}
1569	}
1570	break;
1571	}
1572	//////////////////////////
1573	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1574	// and the cleanup ack has not been received,
1575	// as indicated by r_icache_miss_clack.
1576	// - If no matching coherence request (r_icache_miss_inval)
1577	// switch directory slot to VALID state.
1578	// - If matching coherence request, switch directory slot
1579	// to ZOMBI state, and send a cleanup request.
1580	{
1581	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1582
1583	// coherence interrupt
1584	if ( r_cc_receive_icache_req.read() )
1585	{
1586	r_icache_fsm = ICACHE_CC_CHECK;
1587	r_icache_fsm_save = r_icache_fsm.read();
1588	break;
1589	}
1590
1591	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1592	{
1593	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1594	{
1595	if ( not r_icache_cc_send_req.read() )
1596	{
1597	r_icache_miss_inval = false;
1598	// request cleanup
1599	r_icache_cc_send_req = true;
1600	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1601	r_icache_cc_send_way = r_icache_miss_way.read();
1602	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1603
1604	#ifdef INSTRUMENTATION
1605	m_cpt_icache_dir_write++;
1606	#endif
1607	r_icache.write_dir( r_icache_vci_paddr.read(),
1608	r_icache_miss_way.read(),
1609	r_icache_miss_set.read(),
1610	CACHE_SLOT_STATE_ZOMBI );
1611	#if DEBUG_ICACHE
1612	if ( m_debug_icache_fsm )
1613	{
1614	std::cout << " <PROC " << name()
1615	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1616	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1617	<< " WAY = " << std::dec << r_icache_miss_way.read()
1618	<< " SET = " << r_icache_miss_set.read() << std::endl;
1619	}
1620	#endif
1621	}
1622	else
1623	break;
1624	}
1625	else // Switch slot to VALID state
1626	{
1627
1628	#ifdef INSTRUMENTATION
1629	m_cpt_icache_dir_write++;
1630	#endif
1631	r_icache.write_dir( r_icache_vci_paddr.read(),
1632	r_icache_miss_way.read(),
1633	r_icache_miss_set.read(),
1634	CACHE_SLOT_STATE_VALID );
1635	#if DEBUG_ICACHE
1636	if ( m_debug_icache_fsm )
1637	{
1638	std::cout << " <PROC " << name()
1639	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1640	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1641	<< " WAY = " << std::dec << r_icache_miss_way.read()
1642	<< " SET = " << r_icache_miss_set.read() << std::endl;
1643	}
1644	#endif
1645	}
1646
1647	r_icache_fsm = ICACHE_IDLE;
1648	}
1649	break;
1650	}
1651	////////////////////
1652	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1653	{
1654	// coherence interrupt
1655	if ( r_cc_receive_icache_req.read() )
1656	{
1657	r_icache_fsm = ICACHE_CC_CHECK;
1658	r_icache_fsm_save = r_icache_fsm.read();
1659	break;
1660	}
1661
1662	if ( r_vci_rsp_ins_error.read() ) // bus error
1663	{
1664	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1665	r_mmu_ibvar = m_ireq.addr;
1666	r_vci_rsp_ins_error = false;
1667	m_irsp.valid = true;
1668	m_irsp.error = true;
1669	r_icache_fsm = ICACHE_IDLE;
1670	}
1671	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1672	{
1673	vci_rsp_fifo_icache_get = true;
1674	r_icache_fsm = ICACHE_IDLE;
1675	if ( m_ireq.valid and
1676	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1677	{
1678	m_irsp.valid = true;
1679	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1680	}
1681	}
1682	break;
1683	}
1684	/////////////////////
1685	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1686	// handling coherence requests.
1687	// if there is a matching pending miss, it is
1688	// signaled in the r_icache_miss_inval flip-flop.
1689	// The return state is defined in r_icache_fsm_save.
1690	{
1691	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1692	paddr_t mask = ~((m_icache_words<<2)-1);
1693
1694	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1695	// We switch the directory slot to EMPTY state
1696	// and reset r_icache_miss_clack if the cleanup ack
1697	// is matching a pending miss
1698	{
1699
1700	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1701
1702	#ifdef INSTRUMENTATION
1703	m_cpt_icache_dir_write++;
1704	#endif
1705	r_icache.write_dir( 0,
1706	r_cc_receive_icache_way.read(),
1707	r_cc_receive_icache_set.read(),
1708	CACHE_SLOT_STATE_EMPTY);
1709
1710	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1711	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1712	r_icache_miss_clack = false;
1713
1714	r_icache_fsm = r_icache_fsm_save.read() ;
1715	r_cc_receive_icache_req = false;
1716
1717	#if DEBUG_ICACHE
1718	if ( m_debug_icache_fsm )
1719	{
1720	std::cout << " <PROC " << name()
1721	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1722	<< " set = " << r_cc_receive_icache_set.read()
1723	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1724	}
1725	#endif
1726	}
1727	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1728	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1729	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1730	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1731	{
1732	// signaling the matching
1733	r_icache_miss_inval = true;
1734
1735	// in case of update, go to CC_UPDT
1736	// JUST TO POP THE FIFO
1737	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1738	{
1739	r_icache_fsm = ICACHE_CC_UPDT;
1740	r_icache_cc_word = r_cc_receive_word_idx.read();
1741	// just pop the fifo , don't write in icache
1742	r_icache_cc_need_write = false;
1743	}
1744	// the request is dealt with
1745	else
1746	{
1747	r_cc_receive_icache_req = false;
1748	r_icache_fsm = r_icache_fsm_save.read();
1749	}
1750	#if DEBUG_ICACHE
1751	if ( m_debug_icache_fsm )
1752	{
1753	std::cout << " <PROC " << name()
1754	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1755	<< " PADDR = " << std::hex << paddr << std::endl;
1756	}
1757	#endif
1758	}
1759	else // no match
1760	{
1761	int state;
1762	size_t way;
1763	size_t set;
1764	size_t word;
1765
1766	#ifdef INSTRUMENTATION
1767	m_cpt_icache_dir_read++;
1768	#endif
1769	r_icache.read_dir(paddr,
1770	&state,
1771	&way,
1772	&set,
1773	&word);
1774
1775	r_icache_cc_way = way;
1776	r_icache_cc_set = set;
1777
1778	if ( state == CACHE_SLOT_STATE_VALID) // hit
1779	{
1780	// need to update the cache state
1781	r_icache_cc_need_write = true;
1782	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1783	{
1784	r_icache_fsm = ICACHE_CC_UPDT;
1785	r_icache_cc_word = r_cc_receive_word_idx.read();
1786	}
1787	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1788	{
1789	r_icache_fsm = ICACHE_CC_INVAL;
1790	}
1791	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1792	{
1793	r_icache_fsm = ICACHE_CC_BROADCAST;
1794	}
1795	}
1796	else // miss
1797	{
1798	// multicast acknowledgement required in case of update
1799	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1800	{
1801	r_icache_fsm = ICACHE_CC_UPDT;
1802	r_icache_cc_word = r_cc_receive_word_idx.read();
1803	// just pop the fifo , don't write in icache
1804	r_icache_cc_need_write = false;
1805	}
1806	else // No response needed
1807	{
1808	r_cc_receive_icache_req = false;
1809	r_icache_fsm = r_icache_fsm_save.read();
1810	}
1811	}
1812	}
1813	break;
1814	}
1815	/////////////////////
1816	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1817	{
1818
1819	#if DEBUG_ICACHE
1820	if ( m_debug_icache_fsm )
1821	{
1822	std::cout << " <PROC " << name()
1823	<< " ICACHE_CC_INVAL> slot returns to empty state"
1824	<< " set = " << r_icache_cc_set.read()
1825	<< " / way = " << r_icache_cc_way.read() << std::endl;
1826	}
1827	#endif
1828
1829	#ifdef INSTRUMENTATION
1830	m_cpt_icache_dir_read++;
1831	#endif
1832	if (r_icache_cc_need_write.read())
1833	{
1834	r_icache.write_dir( 0,
1835	r_icache_cc_way.read(),
1836	r_icache_cc_set.read(),
1837	CACHE_SLOT_STATE_EMPTY );
1838	// no need to write in the cache anymore
1839	r_icache_cc_need_write = false;
1840	}
1841
1842	// multicast acknowledgement
1843	// send a request to cc_send_fsm
1844	if(not r_icache_cc_send_req.read()) // cc_send is available
1845	{
1846	// coherence request completed
1847	r_cc_receive_icache_req = false;
1848	// request multicast acknowledgement
1849	r_icache_cc_send_req = true;
1850	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1851	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1852	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1853
1854	r_icache_fsm = r_icache_fsm_save.read();
1855	}
1856	//else wait for previous cc_send request to be sent
1857	break;
1858	}
1859	////////////////////
1860	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1861	{
1862
1863	#if DEBUG_ICACHE
1864	if ( m_debug_icache_fsm )
1865	{
1866	std::cout << " <PROC " << name()
1867	<< " ICACHE_CC_UPDT> Write one word "
1868	<< " set = " << r_icache_cc_set.read()
1869	<< " / way = " << r_icache_cc_way.read()
1870	<< " / word = " << r_icache_cc_word.read() << std::endl;
1871	}
1872	#endif
1873
1874	#ifdef INSTRUMENTATION
1875	m_cpt_icache_data_write++;
1876	#endif
1877	size_t word = r_icache_cc_word.read();
1878	size_t way = r_icache_cc_way.read();
1879	size_t set = r_icache_cc_set.read();
1880
1881	if (r_cc_receive_updt_fifo_be.rok())
1882	{
1883	if (r_icache_cc_need_write.read())
1884	{
1885	r_icache.write( way,
1886	set,
1887	word,
1888	r_cc_receive_updt_fifo_data.read(),
1889	r_cc_receive_updt_fifo_be.read() );
1890
1891	r_icache_cc_word = word+1;
1892	}
1893	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1894	{
1895	// no need to write in the cache anymore
1896	r_icache_cc_need_write = false;
1897	// wait to send a request to cc_send_fsm
1898	if(not r_icache_cc_send_req.read()) // cc_send is available
1899	{
1900	//consume last flit
1901	cc_receive_updt_fifo_get = true;
1902	// coherence request completed
1903	r_cc_receive_icache_req = false;
1904	// request multicast acknowledgement
1905	r_icache_cc_send_req = true;
1906	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1907	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1908	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1909
1910	r_icache_fsm = r_icache_fsm_save.read();
1911	}
1912	}
1913	else
1914	{
1915	//consume fifo if not eop
1916	cc_receive_updt_fifo_get = true;
1917	}
1918	}
1919	break;
1920	}
1921	/////////////////////////
1922	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1923	// and request a cleanup
1924	{
1925
1926	#if DEBUG_ICACHE
1927	if ( m_debug_icache_fsm )
1928	{
1929	std::cout << " <PROC " << name()
1930	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1931	<< " set = " << r_icache_cc_set.read()
1932	<< " / way = " << r_icache_cc_way.read() << std::endl;
1933	}
1934	#endif
1935
1936	#ifdef INSTRUMENTATION
1937	m_cpt_icache_dir_write++;
1938	#endif
1939	if (r_icache_cc_need_write.read())
1940	{
1941	r_icache.write_dir( r_icache_cc_way.read(),
1942	r_icache_cc_set.read(),
1943	CACHE_SLOT_STATE_ZOMBI );
1944	// no need to write in the cache anymore
1945	r_icache_cc_need_write = false;
1946	}
1947
1948	// cleanup
1949	// send a request to cc_send_fsm
1950	if(not r_icache_cc_send_req.read()) // cc_send is available
1951	{
1952	// coherence request completed
1953	r_cc_receive_icache_req = false;
1954	// request cleanup
1955	r_icache_cc_send_req = true;
1956	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1957	r_icache_cc_send_way = r_icache_cc_way.read();
1958	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1959
1960	r_icache_fsm = r_icache_fsm_save.read();
1961	}
1962	//else wait for previous cc_send request to be sent
1963	break;
1964	}
1965	} // end switch r_icache_fsm
1966
1967	////////////////////////////////////////////////////////////////////////////////////
1968	// DCACHE FSM
1969	//
1970	// 1/ Coherence operations
1971	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1972	// - There is a coherence request when r_tgt_dcache_req is set.
1973	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1974	// and SC_WAIT states.
1975	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1976	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1977	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1978	// - For both types of requests, actions associated to the pre-empted state
1979	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1980	// or CC_CLACK) to execute the requested coherence operation, and returns
1981	// to the pre-empted state.
1982	//
1983	// 2/ TLB miss
1984	// The page tables are generally cacheable.
1985	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1986	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1987	// this sub-fsm implement the table-walk...
1988	//
1989	// 3/ processor requests
1990	// Processor requests are taken in IDLE state only.
1991	// The IDLE state implements a two stages pipe-line to handle write bursts:
1992	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
1993	// - The registration in wbuf and the dcache update is done in stage P1
1994	// (if the processor request is a write).
1995	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
1996	// the operations that must be done in P1 stage, and the access type
1997	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
1998	// READ requests are delayed if a cache update is requested.
1999	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2000	// that is done (before handling the processor request) by a dedicated sub-fsm.
2001	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2002	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2003	//
2004	// 4/ Atomic instructions LL/SC
2005	// The LL/SC address are non cacheable (systematic access to memory).
2006	// The llsc buffer contains a registration for an active LL/SC operation
2007	// (with an address, a registration key, an aging counter and a valid bit).
2008	// - LL requests from the processor are transmitted as a one flit VCI command
2009	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2010	// be 8 as the response is 2 flits long (data and registration key)
2011	// - SC requests from the processor are systematically transmitted to the
2012	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2013	// as PKTID value). The first flit contains the registration key, the second
2014	// flit contains the data to write in case of success.
2015	// The cache is not updated, as this is done in case of success by the
2016	// coherence transaction.
2017	//
2018	// 5/ Non cacheable access:
2019	// This component implement a strong order between non cacheable access
2020	// (read or write) : A new non cacheable VCI transaction starts only when
2021	// the previous non cacheable transaction is completed. Both cacheable and
2022	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2023	// a non cacheable write transaction posted in the write buffer by setting the
2024	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2025	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2026	// pending non cacheable write transaction completes).
2027	//
2028	// 6/ Error handling:
2029	// When the MMU is not activated, Read Bus Errors are synchronous events,
2030	// but Write Bus Errors are asynchronous events (processor is not frozen).
2031	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2032	// r_vci_rsp_data_error flip-flop, without writing any data in the
2033	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2034	// by the DCACHE FSM.
2035	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2036	// the asynchronous error using the setWriteBerr() method.
2037	// When the MMU is activated bus error are rare events, as the MMU
2038	// checks the physical address before the VCI transaction starts.
2039	////////////////////////////////////////////////////////////////////////////////////////
2040
2041	// default value for m_drsp
2042	m_drsp.valid = false;
2043	m_drsp.error = false;
2044	m_drsp.rdata = 0;
2045
2046	switch ( r_dcache_fsm.read() )
2047	{
2048	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2049	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2050	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2051	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2052	// 4) XTN request (processor) => DCACHE_XTN_*
2053	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2054	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2055	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2056	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2057	// 9) LL access (processor) => DCACHE_LL_WAIT
2058	// 10) SC access (processor) => DCACHE_SC_WAIT
2059	//
2060	// There is a fixed priority to handle requests to DCACHE:
2061	// 1/ the ITLB/DTLB invalidate requests
2062	// 2/ the coherence requests,
2063	// 3/ the processor requests (including DTLB miss),
2064	// 4/ the ITLB miss requests,
2065	// The address space processor request are handled as follows:
2066	// - WRITE request is blocked if the Dirty bit mus be set.
2067	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2068	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2069	// - READ request generate a simultaneouss access to DCACHE.DATA
2070	// and DCACHE.DIR, but is delayed if DCACHE update required.
2071	//
2072	// There is 4 configurations defining the access type to
2073	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2074	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2075	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2076	// 0 / 0 / NOP / NOP / NOP /
2077	// 0 / 1 / NOP / NOP / WRITE /
2078	// 1 / 0 / READ / READ / NOP /
2079	// 1 / 1 / READ / READ / WRITE /
2080	// Those two registers are set at each cycle from the 3 signals
2081	// updt_request, wbuf_request, wbuf_write_miss.
2082	{
2083	paddr_t paddr; // physical address
2084	pte_info_t tlb_flags;
2085	size_t tlb_way;
2086	size_t tlb_set;
2087	paddr_t tlb_nline;
2088	size_t cache_way;
2089	size_t cache_set;
2090	size_t cache_word;
2091	uint32_t cache_rdata = 0;
2092	bool tlb_hit = false;
2093	int cache_state = CACHE_SLOT_STATE_EMPTY;
2094
2095	bool tlb_inval_required = false; // request TLB inval after cache update
2096	bool wbuf_write_miss = false; // miss a WBUF write request
2097	bool updt_request = false; // request DCACHE update in P1 stage
2098	bool wbuf_request = false; // request WBUF write in P1 stage
2099
2100	// physical address computation : systematic DTLB access if activated)
2101	if ( m_dreq.valid )
2102	{
2103	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2104	{
2105	tlb_hit = r_dtlb.translate( m_dreq.addr,
2106	&paddr,
2107	&tlb_flags,
2108	&tlb_nline,
2109	&tlb_way,
2110	&tlb_set );
2111	#ifdef INSTRUMENTATION
2112	m_cpt_dtlb_read++;
2113	#endif
2114	}
2115	else // identity mapping
2116	{
2117	paddr = (paddr_t)m_dreq.addr;
2118	}
2119	} // end physical address computation
2120
2121	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2122	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2123	{
2124	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2125	{
2126	r_dcache.read_dir( paddr,
2127	&cache_state,
2128	&cache_way,
2129	&cache_set,
2130	&cache_word );
2131
2132	r_dcache.write( r_dcache_save_cache_way.read(),
2133	r_dcache_save_cache_set.read(),
2134	r_dcache_save_cache_word.read(),
2135	r_dcache_save_wdata.read(),
2136	r_dcache_save_be.read() );
2137	#ifdef INSTRUMENTATION
2138	m_cpt_dcache_dir_read++;
2139	m_cpt_dcache_data_write++;
2140	#endif
2141	}
2142	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2143	{
2144	r_dcache.read( paddr,
2145	&cache_rdata,
2146	&cache_way,
2147	&cache_set,
2148	&cache_word,
2149	&cache_state );
2150
2151	#ifdef INSTRUMENTATION
2152	m_cpt_dcache_dir_read++;
2153	m_cpt_dcache_data_read++;
2154	#endif
2155	}
2156	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2157	{
2158	r_dcache.write( r_dcache_save_cache_way.read(),
2159	r_dcache_save_cache_set.read(),
2160	r_dcache_save_cache_word.read(),
2161	r_dcache_save_wdata.read(),
2162	r_dcache_save_be.read() );
2163	#ifdef INSTRUMENTATION
2164	m_cpt_dcache_data_write++;
2165	#endif
2166	}
2167	} // end dcache access
2168
2169	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2170	if ( r_dcache_updt_req.read() )
2171	{
2172	size_t way = r_dcache_save_cache_way.read();
2173	size_t set = r_dcache_save_cache_set.read();
2174
2175	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2176	{
2177	tlb_inval_required = true;
2178	r_dcache_tlb_inval_set = 0;
2179	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2180	(uint32_log2(m_dcache_words<<2));
2181	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2182	}
2183	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2184	{
2185	r_itlb.reset();
2186	r_dtlb.reset();
2187	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2188	}
2189
2190	#if DEBUG_DCACHE
2191	if ( m_debug_dcache_fsm )
2192	{
2193	std::cout << " <PROC " << name()
2194	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2195	<< " / WAY = " << r_dcache_save_cache_way.read()
2196	<< " / SET = " << r_dcache_save_cache_set.read()
2197	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2198	<< " / DATA = " << r_dcache_save_wdata.read()
2199	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2200	}
2201	#endif
2202	} // end test TLB inval
2203
2204	// Try WBUF update in P1 stage
2205	// Miss if the write request is non cacheable, and there is a pending
2206	// non cacheable write, or if the write buffer is full.
2207	if ( r_dcache_wbuf_req.read() )
2208	{
2209	// miss if write not cacheable, and previous non cacheable write registered
2210	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2211	{
2212	wbuf_write_miss = true;
2213	}
2214	else // try a registration into write buffer
2215	{
2216	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2217	r_dcache_save_be.read(),
2218	r_dcache_save_wdata.read(),
2219	r_dcache_save_cacheable.read() );
2220	#ifdef INSTRUMENTATION
2221	m_cpt_wbuf_write++;
2222	#endif
2223	if ( not wok ) // miss if write buffer full
2224	{
2225	wbuf_write_miss = true;
2226	}
2227	else // update the write_buffer state extension
2228	{
2229	if(not r_dcache_pending_unc_write.read())
2230	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2231	}
2232	}
2233	} // end WBUF update
2234
2235	// Computing the response to processor,
2236	// and the next value for r_dcache_fsm
2237
2238	// itlb/dtlb invalidation self-request
2239	if ( tlb_inval_required )
2240	{
2241	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2242	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2243	}
2244
2245	// coherence request (from CC_RECEIVE FSM)
2246	else if ( r_cc_receive_dcache_req.read() )
2247	{
2248	r_dcache_fsm = DCACHE_CC_CHECK;
2249	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2250	}
2251
2252	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2253	// we don't take the processor request, and registers
2254	// are frozen in case of wbuf_write_miss
2255	else if ( m_dreq.valid and not wbuf_write_miss )
2256	{
2257	// register processor request and DCACHE response
2258	r_dcache_save_vaddr = m_dreq.addr;
2259	r_dcache_save_be = m_dreq.be;
2260	r_dcache_save_wdata = m_dreq.wdata;
2261	r_dcache_save_paddr = paddr;
2262	r_dcache_save_cache_way = cache_way;
2263	r_dcache_save_cache_set = cache_set;
2264	r_dcache_save_cache_word = cache_word;
2265
2266	// READ XTN requests from processor
2267	// They are executed in this DCACHE_IDLE state.
2268	// The processor must not be in user mode
2269	if (m_dreq.type == iss_t::XTN_READ)
2270	{
2271	int xtn_opcode = (int)m_dreq.addr/4;
2272
2273	// checking processor mode:
2274	if (m_dreq.mode == iss_t::MODE_USER)
2275	{
2276	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2277	r_mmu_dbvar = m_dreq.addr;
2278	m_drsp.valid = true;
2279	m_drsp.error = true;
2280	m_drsp.rdata = 0;
2281	r_dcache_fsm = DCACHE_IDLE;
2282	}
2283	else
2284	{
2285	switch( xtn_opcode )
2286	{
2287	case iss_t::XTN_INS_ERROR_TYPE:
2288	m_drsp.rdata = r_mmu_ietr.read();
2289	m_drsp.valid = true;
2290	m_drsp.error = false;
2291	break;
2292
2293	case iss_t::XTN_DATA_ERROR_TYPE:
2294	m_drsp.rdata = r_mmu_detr.read();
2295	m_drsp.valid = true;
2296	m_drsp.error = false;
2297	break;
2298
2299	case iss_t::XTN_INS_BAD_VADDR:
2300	m_drsp.rdata = r_mmu_ibvar.read();
2301	m_drsp.valid = true;
2302	m_drsp.error = false;
2303	break;
2304
2305	case iss_t::XTN_DATA_BAD_VADDR:
2306	m_drsp.rdata = r_mmu_dbvar.read();
2307	m_drsp.valid = true;
2308	m_drsp.error = false;
2309	break;
2310
2311	case iss_t::XTN_PTPR:
2312	m_drsp.rdata = r_mmu_ptpr.read();
2313	m_drsp.valid = true;
2314	m_drsp.error = false;
2315	break;
2316
2317	case iss_t::XTN_TLB_MODE:
2318	m_drsp.rdata = r_mmu_mode.read();
2319	m_drsp.valid = true;
2320	m_drsp.error = false;
2321	break;
2322
2323	case iss_t::XTN_MMU_PARAMS:
2324	m_drsp.rdata = r_mmu_params;
2325	m_drsp.valid = true;
2326	m_drsp.error = false;
2327	break;
2328
2329	case iss_t::XTN_MMU_RELEASE:
2330	m_drsp.rdata = r_mmu_release;
2331	m_drsp.valid = true;
2332	m_drsp.error = false;
2333	break;
2334
2335	case iss_t::XTN_MMU_WORD_LO:
2336	m_drsp.rdata = r_mmu_word_lo.read();
2337	m_drsp.valid = true;
2338	m_drsp.error = false;
2339	break;
2340
2341	case iss_t::XTN_MMU_WORD_HI:
2342	m_drsp.rdata = r_mmu_word_hi.read();
2343	m_drsp.valid = true;
2344	m_drsp.error = false;
2345	break;
2346
2347	default:
2348	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2349	r_mmu_dbvar = m_dreq.addr;
2350	m_drsp.valid = true;
2351	m_drsp.error = true;
2352	m_drsp.rdata = 0;
2353	break;
2354	} // end switch xtn_opcode
2355	} // end else
2356	} // end if XTN_READ
2357
2358	// Handling WRITE XTN requests from processor.
2359	// They are not executed in this DCACHE_IDLE state
2360	// if they require access to the caches or the TLBs
2361	// that are already accessed.
2362	// Caches can be invalidated or flushed in user mode,
2363	// and the sync instruction can be executed in user mode
2364	else if (m_dreq.type == iss_t::XTN_WRITE)
2365	{
2366	int xtn_opcode = (int)m_dreq.addr/4;
2367	r_dcache_xtn_opcode = xtn_opcode;
2368
2369	// checking processor mode:
2370	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2371	(xtn_opcode != iss_t::XTN_SYNC) &&
2372	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2373	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2374	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2375	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2376	{
2377	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2378	r_mmu_dbvar = m_dreq.addr;
2379	m_drsp.valid = true;
2380	m_drsp.error = true;
2381	m_drsp.rdata = 0;
2382	r_dcache_fsm = DCACHE_IDLE;
2383	}
2384	else
2385	{
2386	switch( xtn_opcode )
2387	{
2388	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2389	r_dcache_xtn_req = true;
2390	r_dcache_fsm = DCACHE_XTN_SWITCH;
2391	break;
2392
2393	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2394	r_mmu_mode = m_dreq.wdata;
2395	m_drsp.valid = true;
2396	r_dcache_fsm = DCACHE_IDLE;
2397	break;
2398
2399	case iss_t::XTN_DTLB_INVAL: // dtlb access
2400	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2401	break;
2402
2403	case iss_t::XTN_ITLB_INVAL: // itlb access
2404	r_dcache_xtn_req = true;
2405	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2406	break;
2407
2408	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2409	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2410	break;
2411
2412	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2413	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2414	if (sizeof(paddr_t) <= 32)
2415	{
2416	assert(r_mmu_word_hi.read() == 0 &&
2417	"high bits should be 0 for 32bit paddr");
2418	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2419	}
2420	else
2421	{
2422	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2423	(paddr_t)r_mmu_word_lo.read();
2424	}
2425	break;
2426
2427	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2428	r_dcache_flush_count = 0;
2429	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2430	break;
2431
2432	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2433	r_dcache_xtn_req = true;
2434	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2435	break;
2436
2437	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2438	r_dcache_xtn_req = true;
2439	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2440	break;
2441
2442	case iss_t::XTN_ICACHE_FLUSH: // icache access
2443	r_dcache_xtn_req = true;
2444	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2445	break;
2446
2447	case iss_t::XTN_SYNC: // wait until write buffer empty
2448	r_dcache_fsm = DCACHE_XTN_SYNC;
2449	break;
2450
2451	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2452	r_mmu_word_lo = m_dreq.wdata;
2453	m_drsp.valid = true;
2454	r_dcache_fsm = DCACHE_IDLE;
2455	break;
2456
2457	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2458	r_mmu_word_hi = m_dreq.wdata;
2459	m_drsp.valid = true;
2460	r_dcache_fsm = DCACHE_IDLE;
2461	break;
2462
2463	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2464	r_dcache_llsc_valid = false;
2465	m_drsp.valid = true;
2466	r_dcache_fsm = DCACHE_IDLE;
2467	break;
2468
2469	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2470	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2471	m_drsp.valid = true;
2472	r_dcache_fsm = DCACHE_IDLE;
2473	break;
2474
2475	default:
2476	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2477	r_mmu_dbvar = m_dreq.addr;
2478	m_drsp.valid = true;
2479	m_drsp.error = true;
2480	r_dcache_fsm = DCACHE_IDLE;
2481	break;
2482	} // end switch xtn_opcode
2483	} // end else
2484	} // end if XTN_WRITE
2485
2486	// Handling processor requests to address space (READ/WRITE/LL/SC)
2487	// The dtlb and dcache can be activated or not.
2488	// We compute the cacheability, and check processor request validity:
2489	// - If DTLB not activated : cacheability is defined by the segment table,
2490	// and there is no access rights checking.
2491	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2492	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2493	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2494	else
2495	{
2496	bool valid_req;
2497	bool cacheable;
2498
2499	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2500	{
2501	valid_req = true;
2502
2503	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2504	else cacheable = m_cacheability_table[m_dreq.addr];
2505	}
2506	else // dtlb activated
2507	{
2508	if ( tlb_hit ) // tlb hit
2509	{
2510	// cacheability
2511	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2512	else cacheable = tlb_flags.c;
2513
2514	// access rights checking
2515	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2516	{
2517	if ( (m_dreq.type == iss_t::DATA_READ) or
2518	(m_dreq.type == iss_t::DATA_LL) )
2519	{
2520	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2521	}
2522	else
2523	{
2524	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2525	}
2526	valid_req = false;
2527	r_mmu_dbvar = m_dreq.addr;
2528	m_drsp.valid = true;
2529	m_drsp.error = true;
2530	m_drsp.rdata = 0;
2531	#if DEBUG_DCACHE
2532	if ( m_debug_dcache_fsm )
2533	{
2534	std::cout << " <PROC " << name()
2535	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2536	}
2537	#endif
2538	}
2539	else if ( not tlb_flags.w and
2540	((m_dreq.type == iss_t::DATA_WRITE) or
2541	(m_dreq.type == iss_t::DATA_SC)) )
2542	{
2543	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2544	valid_req = false;
2545	r_mmu_dbvar = m_dreq.addr;
2546	m_drsp.valid = true;
2547	m_drsp.error = true;
2548	m_drsp.rdata = 0;
2549	#if DEBUG_DCACHE
2550	if ( m_debug_dcache_fsm )
2551	{
2552	std::cout << " <PROC " << name()
2553	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2554	}
2555	#endif
2556	}
2557	else
2558	{
2559	valid_req = true;
2560	}
2561	}
2562	else // tlb miss
2563	{
2564	valid_req = false;
2565	r_dcache_tlb_vaddr = m_dreq.addr;
2566	r_dcache_tlb_ins = false;
2567	r_dcache_fsm = DCACHE_TLB_MISS;
2568	}
2569	} // end DTLB activated
2570
2571	if ( valid_req ) // processor request is valid after TLB check
2572	{
2573	r_dcache_save_cacheable = cacheable;
2574
2575	// READ request
2576	// The read requests are taken only if there is no cache update.
2577	// We request a VCI transaction to CMD FSM if miss or uncachable
2578
2579	if ( ((m_dreq.type == iss_t::DATA_READ))
2580	and not r_dcache_updt_req.read() )
2581	{
2582	if ( cacheable ) // cacheable read
2583	{
2584	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2585	{
2586	#ifdef INSTRUMENTATION
2587	m_cpt_dcache_miss++;
2588	#endif
2589	// request a VCI DMISS transaction
2590	r_dcache_vci_paddr = paddr;
2591	r_dcache_vci_miss_req = true;
2592	r_dcache_miss_type = PROC_MISS;
2593	r_dcache_fsm = DCACHE_MISS_SELECT;
2594	#if DEBUG_DCACHE
2595	if ( m_debug_dcache_fsm )
2596	{
2597	std::cout << " <PROC " << name()
2598	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2599	}
2600	#endif
2601	}
2602	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2603	{
2604	// stalled until cleanup is acknowledged
2605	r_dcache_fsm = DCACHE_IDLE;
2606	}
2607	else // cache hit
2608	{
2609	#ifdef INSTRUMENTATION
2610	m_cpt_data_read++;
2611	#endif
2612	// returns data to processor
2613	m_drsp.valid = true;
2614	m_drsp.error = false;
2615	m_drsp.rdata = cache_rdata;
2616	#if DEBUG_DCACHE
2617	if ( m_debug_dcache_fsm )
2618	{
2619	std::cout << " <PROC " << name()
2620	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2621	}
2622	#endif
2623	}
2624	}
2625	else // uncacheable read
2626	{
2627	r_dcache_vci_paddr = paddr;
2628	r_dcache_vci_unc_be = m_dreq.be;
2629	r_dcache_vci_unc_req = true;
2630	r_dcache_fsm = DCACHE_UNC_WAIT;
2631	#if DEBUG_DCACHE
2632	if ( m_debug_dcache_fsm )
2633	{
2634	std::cout << " <PROC " << name()
2635	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2636	}
2637	#endif
2638	}
2639	} // end READ
2640
2641	// LL request (non cachable)
2642	// We request a VCI LL transaction to CMD FSM and register
2643	// the LL/SC operation in llsc buffer.
2644	else if (m_dreq.type == iss_t::DATA_LL)
2645	{
2646	// register paddr in LLSC buffer
2647	r_dcache_llsc_paddr = paddr;
2648	r_dcache_llsc_count = LLSC_TIMEOUT;
2649	r_dcache_llsc_valid = true;
2650
2651	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2652	r_dcache_vci_ll_req = true;
2653	r_dcache_vci_paddr = paddr;
2654	r_dcache_ll_rsp_count = 0;
2655	r_dcache_fsm = DCACHE_LL_WAIT;
2656
2657	}// end LL
2658
2659	// WRITE request:
2660	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2661	// the processor and set the Dirty bit before handling the write request,
2662	// going to the DCACHE_DIRTY_GT_PTE state.
2663	// If we don't need to set the Dirty bit, we can acknowledge
2664	// the processor request, as the write arguments (including the
2665	// physical address) are registered in r_dcache_save registers,
2666	// and the write will be done in the P1 pipeline stage.
2667	else if ( m_dreq.type == iss_t::DATA_WRITE )
2668	{
2669	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2670	and not tlb_flags.d ) // Dirty bit must be set
2671	{
2672	// The PTE physical address is obtained from the nline value (dtlb),
2673	// and from the virtual address (word index)
2674	if ( tlb_flags.b ) // PTE1
2675	{
2676	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2677	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2678	}
2679	else // PTE2
2680	{
2681	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2682	(paddr_t)((m_dreq.addr>>9) & 0x38);
2683	}
2684	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2685	}
2686	else // Write request accepted
2687	{
2688	#ifdef INSTRUMENTATION
2689	m_cpt_data_write++;
2690	#endif
2691	// cleaning llsc buffer if address matching
2692	if ( paddr == r_dcache_llsc_paddr.read() )
2693	r_dcache_llsc_valid = false;
2694
2695	// response to processor
2696	m_drsp.valid = true;
2697
2698	// activating P1 stage
2699	wbuf_request = true;
2700	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2701	}
2702	} // end WRITE
2703
2704	// SC request:
2705	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2706	// the processor and set the Dirty bit before handling the write request,
2707	// going to the DCACHE_DIRTY_GT_PTE state.
2708	// If we don't need to set the Dirty bit, we test the llsc buffer:
2709	// If failure, we send a negative response to processor.
2710	// If success, we request a SC transaction to CMD FSM and go
2711	// to DCACHE_SC_WAIT state.
2712	// We don't check a possible write hit in dcache, as the cache update
2713	// is done by the coherence transaction induced by the SC...
2714	else if ( m_dreq.type == iss_t::DATA_SC )
2715	{
2716	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2717	and not tlb_flags.d ) // Dirty bit must be set
2718	{
2719	// The PTE physical address is obtained from the nline value (dtlb),
2720	// and the word index (virtual address)
2721	if ( tlb_flags.b ) // PTE1
2722	{
2723	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2724	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2725	}
2726	else // PTE2
2727	{
2728	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2729	(paddr_t)((m_dreq.addr>>9) & 0x38);
2730	}
2731	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2732	m_drsp.valid = false;
2733	m_drsp.error = false;
2734	m_drsp.rdata = 0;
2735	}
2736	else // SC request accepted
2737	{
2738	#ifdef INSTRUMENTATION
2739	m_cpt_data_sc++;
2740	#endif
2741	// checking local success
2742	if( r_dcache_llsc_valid.read() and
2743	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2744	{
2745	// request an SC CMD and go to DCACHE_SC_WAIT state
2746	r_dcache_vci_paddr = paddr;
2747	r_dcache_vci_sc_req = true;
2748	r_dcache_vci_sc_data = m_dreq.wdata;
2749	r_dcache_fsm = DCACHE_SC_WAIT;
2750	}
2751	else // local fail
2752	{
2753	m_drsp.valid = true;
2754	m_drsp.error = false;
2755	m_drsp.rdata = 0x1;
2756	}
2757	}
2758	} // end SC
2759	} // end valid_req
2760	} // end if read/write/ll/sc request
2761	} // end processor request
2762
2763	// itlb miss request
2764	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2765	{
2766	r_dcache_tlb_ins = true;
2767	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2768	r_dcache_fsm = DCACHE_TLB_MISS;
2769	}
2770
2771	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2772	r_dcache_updt_req = updt_request;
2773	r_dcache_wbuf_req = wbuf_request or
2774	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2775	break;
2776	}
2777	/////////////////////
2778	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2779	// Input arguments are:
2780	// - r_dcache_tlb_vaddr
2781	// - r_dcache_tlb_ins (true when itlb miss)
2782	// The sub-fsm access the dcache to find the missing TLB entry,
2783	// and activates the cache miss procedure in case of miss.
2784	// It bypass the first level page table access if possible.
2785	// It uses atomic access to update the R/L access bits
2786	// in the page table if required.
2787	// It directly updates the itlb or dtlb, and writes into the
2788	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2789	{
2790	uint32_t ptba = 0;
2791	bool bypass;
2792	paddr_t pte_paddr;
2793
2794	// evaluate bypass in order to skip first level page table access
2795	if ( r_dcache_tlb_ins.read() ) // itlb miss
2796	{
2797	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2798	}
2799	else // dtlb miss
2800	{
2801	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2802	}
2803
2804	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2805	{
2806	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2807	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2808	r_dcache_tlb_paddr = pte_paddr;
2809	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2810	}
2811	else // Try to read PTE2 in dcache
2812	{
2813	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2814	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2815	r_dcache_tlb_paddr = pte_paddr;
2816	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2817	}
2818
2819	#if DEBUG_DCACHE
2820	if ( m_debug_dcache_fsm )
2821	{
2822	if ( r_dcache_tlb_ins.read() )
2823	{
2824	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2825	}
2826	else
2827	{
2828	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2829	}
2830	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2831	<< " / BYPASS = " << bypass
2832	<< " / PTE_ADR = " << pte_paddr << std::endl;
2833	}
2834	#endif
2835
2836	break;
2837	}
2838	/////////////////////////
2839	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2840	{
2841	// coherence request (from CC_RECEIVE FSM)
2842	if ( r_cc_receive_dcache_req.read() )
2843	{
2844	r_dcache_fsm = DCACHE_CC_CHECK;
2845	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2846	break;
2847	}
2848
2849	uint32_t entry;
2850	size_t way;
2851	size_t set;
2852	size_t word;
2853	int cache_state;
2854	r_dcache.read( r_dcache_tlb_paddr.read(),
2855	&entry,
2856	&way,
2857	&set,
2858	&word,
2859	&cache_state );
2860	#ifdef INSTRUMENTATION
2861	m_cpt_dcache_data_read++;
2862	m_cpt_dcache_dir_read++;
2863	#endif
2864	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2865	{
2866	if ( not (entry & PTE_V_MASK) ) // unmapped
2867	{
2868	if ( r_dcache_tlb_ins.read() )
2869	{
2870	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2871	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2872	r_icache_tlb_miss_req = false;
2873	r_icache_tlb_rsp_error = true;
2874	}
2875	else
2876	{
2877	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2878	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2879	m_drsp.valid = true;
2880	m_drsp.error = true;
2881	}
2882	r_dcache_fsm = DCACHE_IDLE;
2883
2884	#if DEBUG_DCACHE
2885	if ( m_debug_dcache_fsm )
2886	{
2887	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2888	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2889	<< std::dec << " / way = " << way
2890	<< std::dec << " / set = " << set
2891	<< std::dec << " / word = " << word
2892	<< std::hex << " / PTE1 = " << entry << std::endl;
2893	}
2894	#endif
2895
2896	}
2897	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2898	{
2899	// mark the cache line ac containing a PTD
2900	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2901
2902	// register bypass
2903	if ( r_dcache_tlb_ins.read() ) // itlb
2904	{
2905	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2906	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2907	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2908	}
2909	else // dtlb
2910	{
2911	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2912	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2913	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2914	}
2915	r_dcache_tlb_paddr =
2916	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2917	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2918	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2919
2920	#if DEBUG_DCACHE
2921	if ( m_debug_dcache_fsm )
2922	{
2923	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2924	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2925	<< std::dec << " / way = " << way
2926	<< std::dec << " / set = " << set
2927	<< std::dec << " / word = " << word
2928	<< std::hex << " / PTD = " << entry << std::endl;
2929	}
2930	#endif
2931	}
2932	else // PTE1 : we must update the TLB
2933	{
2934	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2935	r_dcache_tlb_pte_flags = entry;
2936	r_dcache_tlb_cache_way = way;
2937	r_dcache_tlb_cache_set = set;
2938	r_dcache_tlb_cache_word = word;
2939	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2940
2941	#if DEBUG_DCACHE
2942	if ( m_debug_dcache_fsm )
2943	{
2944	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2945	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2946	<< std::dec << " / way = " << way
2947	<< std::dec << " / set = " << set
2948	<< std::dec << " / word = " << word
2949	<< std::hex << " / PTE1 = " << entry << std::endl;
2950	}
2951	#endif
2952	}
2953	}
2954	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2955	{
2956	// stalled until cleanup is acknowledged
2957	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2958	}
2959	else // we must load the missing cache line in dcache
2960	{
2961	r_dcache_vci_miss_req = true;
2962	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2963	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2964	r_dcache_miss_type = PTE1_MISS;
2965	r_dcache_fsm = DCACHE_MISS_SELECT;
2966
2967	#if DEBUG_DCACHE
2968	if ( m_debug_dcache_fsm )
2969	{
2970	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2971	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2972	}
2973	#endif
2974	}
2975	break;
2976	}
2977	////////////////////////////
2978	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2979	{
2980	size_t way;
2981	size_t set;
2982
2983	if ( r_dcache_tlb_ins.read() )
2984	{
2985	r_itlb.select( r_dcache_tlb_vaddr.read(),
2986	true, // PTE1
2987	&way,
2988	&set );
2989	#ifdef INSTRUMENTATION
2990	m_cpt_itlb_read++;
2991	#endif
2992	}
2993	else
2994	{
2995	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2996	true, // PTE1
2997	&way,
2998	&set );
2999	#ifdef INSTRUMENTATION
3000	m_cpt_dtlb_read++;
3001	#endif
3002	}
3003	r_dcache_tlb_way = way;
3004	r_dcache_tlb_set = set;
3005	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3006
3007	#if DEBUG_DCACHE
3008	if ( m_debug_dcache_fsm )
3009	{
3010	if ( r_dcache_tlb_ins.read() )
3011	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3012	else
3013	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3014	std::cout << " way = " << std::dec << way
3015	<< " / set = " << set << std::endl;
3016	}
3017	#endif
3018	break;
3019	}
3020	//////////////////////////
3021	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3022	// - if L/R bit already set, exit the sub-fsm.
3023	// - if not, we update the page table but we dont write
3024	// neither in DCACHE, nor in TLB, as this will be done by
3025	// the coherence mechanism.
3026	{
3027	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3028	uint32_t pte = r_dcache_tlb_pte_flags.read();
3029	bool pt_updt = false;
3030	bool local = true;
3031
3032	// We should compute the access locality:
3033	// The PPN MSB bits define the destination cluster index.
3034	// The m_srcid MSB bits define the source cluster index.
3035	// The number of bits to compare depends on the number of clusters,
3036	// and can be obtained in the mapping table.
3037	// As long as this computation is not done, all access are local.
3038
3039	if ( local ) // local access
3040	{
3041	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3042	{
3043	pt_updt = true;
3044	r_dcache_vci_cas_old = pte;
3045	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3046	pte = pte \| PTE_L_MASK;
3047	r_dcache_tlb_pte_flags = pte;
3048	}
3049	}
3050	else // remote access
3051	{
3052	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3053	{
3054	pt_updt = true;
3055	r_dcache_vci_cas_old = pte;
3056	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3057	pte = pte \| PTE_R_MASK;
3058	r_dcache_tlb_pte_flags = pte;
3059	}
3060	}
3061
3062	if ( not pt_updt ) // update TLB and return
3063	{
3064	if ( r_dcache_tlb_ins.read() )
3065	{
3066	r_itlb.write( true, // 2M page
3067	pte,
3068	0, // argument unused for a PTE1
3069	r_dcache_tlb_vaddr.read(),
3070	r_dcache_tlb_way.read(),
3071	r_dcache_tlb_set.read(),
3072	nline );
3073	#ifdef INSTRUMENTATION
3074	m_cpt_itlb_write++;
3075	#endif
3076
3077	#if DEBUG_DCACHE
3078	if ( m_debug_dcache_fsm )
3079	{
3080	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3081	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3082	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3083	r_itlb.printTrace();
3084	}
3085	#endif
3086	}
3087	else
3088	{
3089	r_dtlb.write( true, // 2M page
3090	pte,
3091	0, // argument unused for a PTE1
3092	r_dcache_tlb_vaddr.read(),
3093	r_dcache_tlb_way.read(),
3094	r_dcache_tlb_set.read(),
3095	nline );
3096	#ifdef INSTRUMENTATION
3097	m_cpt_dtlb_write++;
3098	#endif
3099
3100	#if DEBUG_DCACHE
3101	if ( m_debug_dcache_fsm )
3102	{
3103	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3104	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3105	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3106	r_dtlb.printTrace();
3107	}
3108	#endif
3109	}
3110	r_dcache_fsm = DCACHE_TLB_RETURN;
3111	}
3112	else // update page table but not TLB
3113	{
3114	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3115
3116	#if DEBUG_DCACHE
3117	if ( m_debug_dcache_fsm )
3118	{
3119	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3120	<< std::endl;
3121	}
3122	#endif
3123	}
3124	break;
3125	}
3126	/////////////////////////
3127	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3128	{
3129	// coherence request (from CC_RECEIVE FSM)
3130	if ( r_cc_receive_dcache_req.read() )
3131	{
3132	r_dcache_fsm = DCACHE_CC_CHECK;
3133	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3134	break;
3135	}
3136
3137	uint32_t pte_flags;
3138	uint32_t pte_ppn;
3139	size_t way;
3140	size_t set;
3141	size_t word;
3142	int cache_state;
3143
3144	r_dcache.read( r_dcache_tlb_paddr.read(),
3145	&pte_flags,
3146	&pte_ppn,
3147	&way,
3148	&set,
3149	&word,
3150	&cache_state );
3151	#ifdef INSTRUMENTATION
3152	m_cpt_dcache_data_read++;
3153	m_cpt_dcache_dir_read++;
3154	#endif
3155	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3156	{
3157	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3158	{
3159	if ( r_dcache_tlb_ins.read() )
3160	{
3161	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3162	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3163	r_icache_tlb_miss_req = false;
3164	r_icache_tlb_rsp_error = true;
3165	}
3166	else
3167	{
3168	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3169	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3170	m_drsp.valid = true;
3171	m_drsp.error = true;
3172	}
3173	r_dcache_fsm = DCACHE_IDLE;
3174
3175	#if DEBUG_DCACHE
3176	if ( m_debug_dcache_fsm )
3177	{
3178	std::cout << " <PROC " << name()
3179	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3180	<< " PTE_FLAGS = " << std::hex << pte_flags
3181	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3182	}
3183	#endif
3184	}
3185	else // mapped : we must update the TLB
3186	{
3187	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3188	r_dcache_tlb_pte_flags = pte_flags;
3189	r_dcache_tlb_pte_ppn = pte_ppn;
3190	r_dcache_tlb_cache_way = way;
3191	r_dcache_tlb_cache_set = set;
3192	r_dcache_tlb_cache_word = word;
3193	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3194
3195	#if DEBUG_DCACHE
3196	if ( m_debug_dcache_fsm )
3197	{
3198	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3199	<< " PTE_FLAGS = " << std::hex << pte_flags
3200	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3201	}
3202	#endif
3203	}
3204	}
3205	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3206	{
3207	// stalled until cleanup is acknowledged
3208	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3209	}
3210	else // we must load the missing cache line in dcache
3211	{
3212	r_dcache_fsm = DCACHE_MISS_SELECT;
3213	r_dcache_vci_miss_req = true;
3214	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3215	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3216	r_dcache_miss_type = PTE2_MISS;
3217
3218	#if DEBUG_DCACHE
3219	if ( m_debug_dcache_fsm )
3220	{
3221	std::cout << " <PROC " << name()
3222	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3223	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3224	}
3225	#endif
3226	}
3227	break;
3228	}
3229	////////////////////////////
3230	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3231	{
3232	size_t way;
3233	size_t set;
3234
3235	if ( r_dcache_tlb_ins.read() )
3236	{
3237	r_itlb.select( r_dcache_tlb_vaddr.read(),
3238	false, // PTE2
3239	&way,
3240	&set );
3241	#ifdef INSTRUMENTATION
3242	m_cpt_itlb_read++;
3243	#endif
3244	}
3245	else
3246	{
3247	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3248	false, // PTE2
3249	&way,
3250	&set );
3251	#ifdef INSTRUMENTATION
3252	m_cpt_dtlb_read++;
3253	#endif
3254	}
3255
3256	#if DEBUG_DCACHE
3257	if ( m_debug_dcache_fsm )
3258	{
3259	if ( r_dcache_tlb_ins.read() )
3260	std::cout << " <PROC " << name()
3261	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3262	else
3263	std::cout << " <PROC " << name()
3264	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3265	std::cout << " way = " << std::dec << way
3266	<< " / set = " << set << std::endl;
3267	}
3268	#endif
3269	r_dcache_tlb_way = way;
3270	r_dcache_tlb_set = set;
3271	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3272	break;
3273	}
3274	//////////////////////////
3275	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3276	// - if L/R bit already set, exit the sub-fsm.
3277	// - if not, we update the page table but we dont write
3278	// neither in DCACHE, nor in TLB, as this will be done by
3279	// the coherence mechanism.
3280	{
3281	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3282	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3283	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3284	bool pt_updt = false;
3285	bool local = true;
3286
3287	// We should compute the access locality:
3288	// The PPN MSB bits define the destination cluster index.
3289	// The m_srcid MSB bits define the source cluster index.
3290	// The number of bits to compare depends on the number of clusters,
3291	// and can be obtained in the mapping table.
3292	// As long as this computation is not done, all access are local.
3293
3294	if ( local ) // local access
3295	{
3296	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3297	{
3298	pt_updt = true;
3299	r_dcache_vci_cas_old = pte_flags;
3300	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3301	pte_flags = pte_flags \| PTE_L_MASK;
3302	r_dcache_tlb_pte_flags = pte_flags;
3303	}
3304	}
3305	else // remote access
3306	{
3307	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3308	{
3309	pt_updt = true;
3310	r_dcache_vci_cas_old = pte_flags;
3311	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3312	pte_flags = pte_flags \| PTE_R_MASK;
3313	r_dcache_tlb_pte_flags = pte_flags;
3314	}
3315	}
3316
3317	if ( not pt_updt ) // update TLB
3318	{
3319	if ( r_dcache_tlb_ins.read() )
3320	{
3321	r_itlb.write( false, // 4K page
3322	pte_flags,
3323	pte_ppn,
3324	r_dcache_tlb_vaddr.read(),
3325	r_dcache_tlb_way.read(),
3326	r_dcache_tlb_set.read(),
3327	nline );
3328	#ifdef INSTRUMENTATION
3329	m_cpt_itlb_write++;
3330	#endif
3331
3332	#if DEBUG_DCACHE
3333	if ( m_debug_dcache_fsm )
3334	{
3335	std::cout << " <PROC " << name()
3336	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3337	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3338	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3339	r_itlb.printTrace();
3340	}
3341	#endif
3342	}
3343	else
3344	{
3345	r_dtlb.write( false, // 4K page
3346	pte_flags,
3347	pte_ppn,
3348	r_dcache_tlb_vaddr.read(),
3349	r_dcache_tlb_way.read(),
3350	r_dcache_tlb_set.read(),
3351	nline );
3352	#ifdef INSTRUMENTATION
3353	m_cpt_dtlb_write++;
3354	#endif
3355
3356	#if DEBUG_DCACHE
3357	if ( m_debug_dcache_fsm )
3358	{
3359	std::cout << " <PROC " << name()
3360	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3361	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3362	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3363	r_dtlb.printTrace();
3364	}
3365	#endif
3366
3367	}
3368	r_dcache_fsm = DCACHE_TLB_RETURN;
3369	}
3370	else // update page table but not TLB
3371	{
3372	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3373
3374	#if DEBUG_DCACHE
3375	if ( m_debug_dcache_fsm )
3376	{
3377	std::cout << " <PROC " << name()
3378	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3379	}
3380	#endif
3381	}
3382	break;
3383	}
3384	////////////////////////
3385	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3386	{
3387	#if DEBUG_DCACHE
3388	if ( m_debug_dcache_fsm )
3389	{
3390	std::cout << " <PROC " << name()
3391	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3392	}
3393	#endif
3394	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3395	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3396
3397	// checking llsc reservation buffer
3398	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3399	r_dcache_llsc_valid = false;
3400
3401	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3402	r_dcache_vci_cas_req = true;
3403	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3404	break;
3405	}
3406	////////////////////////
3407	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3408	// We consume the response in rsp FIFO,
3409	// and exit the sub-fsm, but we don't
3410	// analyse the response, because we don't
3411	// care if the L/R bit update is not done.
3412	// We must take the coherence requests because
3413	// there is a risk of dead-lock
3414
3415	{
3416	// coherence request (from CC_RECEIVE FSM)
3417	if ( r_cc_receive_dcache_req.read() )
3418	{
3419	r_dcache_fsm = DCACHE_CC_CHECK;
3420	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3421	break;
3422	}
3423
3424	if ( r_vci_rsp_data_error.read() ) // bus error
3425	{
3426	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3427	std::cout << "This should not happen in this state" << std::endl;
3428	exit(0);
3429	}
3430	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3431	{
3432	#if DEBUG_DCACHE
3433	if ( m_debug_dcache_fsm )
3434	{
3435	std::cout << " <PROC " << name()
3436	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3437	}
3438	#endif
3439	vci_rsp_fifo_dcache_get = true;
3440	r_dcache_fsm = DCACHE_TLB_RETURN;
3441	}
3442	break;
3443	}
3444	///////////////////////
3445	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3446	{
3447	#if DEBUG_DCACHE
3448	if ( m_debug_dcache_fsm )
3449	{
3450	std::cout << " <PROC " << name()
3451	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3452	}
3453	#endif
3454	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3455	r_dcache_fsm = DCACHE_IDLE;
3456	break;
3457	}
3458	///////////////////////
3459	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3460	// and both itlb and dtlb must be flushed.
3461	// Caution : the itlb miss requests must be taken
3462	// to avoid dead-lock in case of simultaneous ITLB miss
3463	{
3464	// itlb miss request
3465	if ( r_icache_tlb_miss_req.read() )
3466	{
3467	r_dcache_tlb_ins = true;
3468	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3469	r_dcache_fsm = DCACHE_TLB_MISS;
3470	break;
3471	}
3472
3473	if ( not r_dcache_xtn_req.read() )
3474	{
3475	r_dtlb.flush();
3476	r_mmu_ptpr = m_dreq.wdata;
3477	r_dcache_fsm = DCACHE_IDLE;
3478	m_drsp.valid = true;
3479	}
3480	break;
3481	}
3482	/////////////////////
3483	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3484	// The coherence request must be taken
3485	// as there is a risk of dead-lock
3486	{
3487	// coherence request (from CC_RECEIVE FSM)
3488	if ( r_cc_receive_dcache_req.read() )
3489	{
3490	r_dcache_fsm = DCACHE_CC_CHECK;
3491	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3492	}
3493
3494	if ( r_wbuf.empty() )
3495	{
3496	m_drsp.valid = true;
3497	r_dcache_fsm = DCACHE_IDLE;
3498	}
3499	break;
3500	}
3501	////////////////////////
3502	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3503	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3504	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3505	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3506	// and because it can exist a simultaneous ITLB miss
3507	{
3508	// coherence request (from CC_RECEIVE FSM)
3509	if ( r_cc_receive_dcache_req.read() )
3510	{
3511	r_dcache_fsm = DCACHE_CC_CHECK;
3512	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3513	break;
3514	}
3515
3516	// itlb miss request
3517	if ( r_icache_tlb_miss_req.read() )
3518	{
3519	r_dcache_tlb_ins = true;
3520	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3521	r_dcache_fsm = DCACHE_TLB_MISS;
3522	break;
3523	}
3524
3525	// test if XTN request to icache completed
3526	if ( not r_dcache_xtn_req.read() )
3527	{
3528	r_dcache_fsm = DCACHE_IDLE;
3529	m_drsp.valid = true;
3530	}
3531	break;
3532	}
3533	/////////////////////////
3534	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3535	// r_dcache_flush_count as a slot counter,
3536	// looping in this state until all slots have been visited.
3537	// It can require two cycles per slot:
3538	// We test here the slot state, and make the actual inval
3539	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3540	// A cleanup request is generated for each valid line.
3541	// returns to IDLE and flush TLBs when last slot
3542	{
3543	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3544	{
3545	int state;
3546	uint32_t tag;
3547	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3548	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3549
3550	#ifdef INSTRUMENTATION
3551	m_cpt_dcache_dir_read++;
3552	#endif
3553	r_dcache.read_dir( way,
3554	set,
3555	&tag,
3556	&state );
3557
3558	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3559	{
3560	// request cleanup
3561	r_dcache_cc_send_req = true;
3562	r_dcache_cc_send_nline = tag * m_dcache_sets;
3563	r_dcache_cc_send_way = way;
3564	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3565
3566	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3567	r_dcache_miss_way = way;
3568	r_dcache_miss_set = set;
3569	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3570	}
3571	else if ( r_dcache_flush_count.read() ==
3572	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3573	{
3574	r_dtlb.reset();
3575	r_itlb.reset();
3576	r_dcache_fsm = DCACHE_IDLE;
3577	m_drsp.valid = true;
3578	}
3579
3580	// saturation counter
3581	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3582	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3583	}
3584	break;
3585	}
3586	////////////////////////////
3587	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3588	// and reset directory extension.
3589	// returns to IDLE and flush TLBs when last slot
3590	{
3591	size_t way = r_dcache_miss_way.read();
3592	size_t set = r_dcache_miss_set.read();
3593
3594	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3595	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3596
3597	#ifdef INSTRUMENTATION
3598	m_cpt_dcache_dir_write++;
3599	#endif
3600	r_dcache.write_dir( way,
3601	set,
3602	CACHE_SLOT_STATE_ZOMBI );
3603
3604	if ( r_dcache_flush_count.read() ==
3605	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3606	{
3607	r_dtlb.reset();
3608	r_itlb.reset();
3609	r_dcache_fsm = DCACHE_IDLE;
3610	m_drsp.valid = true;
3611	}
3612	else
3613	{
3614	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3615	}
3616	break;
3617	}
3618	/////////////////////////
3619	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3620	{
3621	r_dtlb.inval(r_dcache_save_wdata.read());
3622	r_dcache_fsm = DCACHE_IDLE;
3623	m_drsp.valid = true;
3624	break;
3625	}
3626	////////////////////////////
3627	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3628	// requires 3 cycles: access tlb, read cache, inval cache
3629	// we compute the physical address in this state
3630	{
3631	paddr_t paddr;
3632	bool hit;
3633
3634	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3635	{
3636
3637	#ifdef INSTRUMENTATION
3638	m_cpt_dtlb_read++;
3639	#endif
3640	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3641	&paddr );
3642	}
3643	else // dtlb not activated
3644	{
3645	paddr = (paddr_t)r_dcache_save_wdata.read();
3646	hit = true;
3647	}
3648
3649	if ( hit ) // tlb hit
3650	{
3651	r_dcache_save_paddr = paddr;
3652	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3653	}
3654	else // tlb miss
3655	{
3656
3657	#ifdef INSTRUMENTATION
3658	m_cpt_dtlb_miss++;
3659	#endif
3660	r_dcache_tlb_ins = false; // dtlb
3661	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3662	r_dcache_fsm = DCACHE_TLB_MISS;
3663	}
3664
3665	#if DEBUG_DCACHE
3666	if ( m_debug_dcache_fsm )
3667	{
3668	std::cout << " <PROC " << name()
3669	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3670	<< " / VADDR = " << r_dcache_save_wdata.read()
3671	<< " / PADDR = " << paddr << std::endl;
3672	}
3673	#endif
3674
3675	break;
3676	}
3677	////////////////////////////
3678	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3679	// requires 2 cycles: read cache / inval cache
3680	// In this state we read dcache.
3681	{
3682	size_t way;
3683	size_t set;
3684	size_t word;
3685	int state;
3686
3687	#ifdef INSTRUMENTATION
3688	m_cpt_dcache_dir_read++;
3689	#endif
3690	r_dcache.read_dir( r_dcache_save_paddr.read(),
3691	&state,
3692	&way,
3693	&set,
3694	&word );
3695
3696	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3697	{
3698	r_dcache_xtn_way = way;
3699	r_dcache_xtn_set = set;
3700	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3701	}
3702	else // miss : nothing to do
3703	{
3704	r_dcache_fsm = DCACHE_IDLE;
3705	m_drsp.valid = true;
3706	}
3707
3708	#if DEBUG_DCACHE
3709	if ( m_debug_dcache_fsm )
3710	{
3711	std::cout << " <PROC " << name()
3712	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3713	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3714	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3715	<< " / SET = " << set
3716	<< " / WAY = " << way << std::endl;
3717	}
3718	#endif
3719	break;
3720	}
3721	////////////////////////////
3722	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3723	// Blocked if previous cleanup not completed
3724	// Test if itlb or dtlb inval is required
3725	{
3726	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3727	{
3728	size_t way = r_dcache_xtn_way.read();
3729	size_t set = r_dcache_xtn_set.read();
3730	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3731
3732	#ifdef INSTRUMENTATION
3733	m_cpt_dcache_dir_write++;
3734	#endif
3735	r_dcache.write_dir( way,
3736	set,
3737	CACHE_SLOT_STATE_ZOMBI );
3738
3739	// request cleanup
3740	r_dcache_cc_send_req = true;
3741	r_dcache_cc_send_nline = nline;
3742	r_dcache_cc_send_way = way;
3743	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3744
3745	// possible itlb & dtlb invalidate
3746	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3747	{
3748	r_dcache_tlb_inval_line = nline;
3749	r_dcache_tlb_inval_set = 0;
3750	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3751	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3752	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3753	}
3754	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3755	{
3756	r_itlb.reset();
3757	r_dtlb.reset();
3758	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3759	r_dcache_fsm = DCACHE_IDLE;
3760	m_drsp.valid = true;
3761	}
3762	else
3763	{
3764	r_dcache_fsm = DCACHE_IDLE;
3765	m_drsp.valid = true;
3766	}
3767
3768	#if DEBUG_DCACHE
3769	if ( m_debug_dcache_fsm )
3770	{
3771	std::cout << " <PROC " << name()
3772	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3773	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3774	}
3775	#endif
3776	}
3777	break;
3778	}
3779	//////////////////////////////
3780	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3781	{
3782	r_dcache_fsm = DCACHE_IDLE;
3783	m_drsp.valid = true;
3784	break;
3785	}
3786	////////////////////////
3787	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3788	// if previous cleanup has been sent.
3789	// Waiting in this state if no slot available
3790	// Set the r_dcache_cleanup_req flip-flop
3791	// and the r_dcache_miss_clack flip-flop
3792	// when a cleanup is required
3793	{
3794	if ( m_dreq.valid) m_cost_data_miss_frz++;
3795
3796	// coherence request (from CC_RECEIVE FSM)
3797	if ( r_cc_receive_dcache_req.read() )
3798	{
3799	r_dcache_fsm = DCACHE_CC_CHECK;
3800	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3801	break;
3802	}
3803
3804	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3805	{
3806	bool found;
3807	bool cleanup;
3808	size_t way;
3809	size_t set;
3810	paddr_t victim;
3811
3812	#ifdef INSTRUMENTATION
3813	m_cpt_dcache_dir_read++;
3814	#endif
3815	r_dcache.read_select( r_dcache_save_paddr.read(),
3816	&victim,
3817	&way,
3818	&set,
3819	&found,
3820	&cleanup );
3821
3822	if ( found )
3823	{
3824	r_dcache_miss_way = way;
3825	r_dcache_miss_set = set;
3826
3827	if ( cleanup )
3828	{
3829	r_dcache_miss_clack = true;
3830	r_dcache_fsm = DCACHE_MISS_CLEAN;
3831	// request cleanup
3832	r_dcache_cc_send_req = true;
3833	r_dcache_cc_send_nline = victim;
3834	r_dcache_cc_send_way = way;
3835	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3836	}
3837	else
3838	{
3839	r_dcache_fsm = DCACHE_MISS_WAIT;
3840	}
3841
3842	#if DEBUG_DCACHE
3843	if ( m_debug_dcache_fsm )
3844	{
3845	std::cout << " <PROC " << name()
3846	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3847	<< " / WAY = " << way
3848	<< " / SET = " << set
3849	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3850	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3851	else std::cout << std::endl;
3852	}
3853	#endif
3854	} // end found
3855	}
3856	break;
3857	}
3858	///////////////////////
3859	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3860	// and possibly request itlb or dtlb invalidate
3861	{
3862	if ( m_dreq.valid) m_cost_data_miss_frz++;
3863
3864	size_t way = r_dcache_miss_way.read();
3865	size_t set = r_dcache_miss_set.read();
3866	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3867
3868	#ifdef INSTRUMENTATION
3869	m_cpt_dcache_dir_read++;
3870	#endif
3871	r_dcache.write_dir( way,
3872	set,
3873	CACHE_SLOT_STATE_ZOMBI );
3874	#if DEBUG_DCACHE
3875	if ( m_debug_dcache_fsm )
3876	{
3877	std::cout << " <PROC " << name()
3878	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3879	<< " / way = " << way
3880	<< " / set = " << set << std::endl;
3881	}
3882	#endif
3883	// if selective itlb & dtlb invalidate are required
3884	// the miss response is not handled before invalidate completed
3885	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3886	{
3887	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3888	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
3889	r_dcache_tlb_inval_set = 0;
3890	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3891	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3892	}
3893	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3894	{
3895	r_itlb.reset();
3896	r_dtlb.reset();
3897	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3898	r_dcache_fsm = DCACHE_MISS_WAIT;
3899	}
3900	else
3901	{
3902	r_dcache_fsm = DCACHE_MISS_WAIT;
3903	}
3904	break;
3905	}
3906	//////////////////////
3907	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3908	// This state is in charge of error signaling
3909	// There is 5 types of error depending on the requester
3910	{
3911	if ( m_dreq.valid) m_cost_data_miss_frz++;
3912
3913	// coherence request (from CC_RECEIVE FSM)
3914	if ( r_cc_receive_dcache_req.read() )
3915	{
3916	r_dcache_fsm = DCACHE_CC_CHECK;
3917	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3918	break;
3919	}
3920
3921	if ( r_vci_rsp_data_error.read() ) // bus error
3922	{
3923	switch ( r_dcache_miss_type.read() )
3924	{
3925	case PROC_MISS:
3926	{
3927	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3928	r_mmu_dbvar = r_dcache_save_vaddr.read();
3929	m_drsp.valid = true;
3930	m_drsp.error = true;
3931	r_dcache_fsm = DCACHE_IDLE;
3932	break;
3933	}
3934	case PTE1_MISS:
3935	{
3936	if ( r_dcache_tlb_ins.read() )
3937	{
3938	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3939	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3940	r_icache_tlb_miss_req = false;
3941	r_icache_tlb_rsp_error = true;
3942	}
3943	else
3944	{
3945	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3946	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3947	m_drsp.valid = true;
3948	m_drsp.error = true;
3949	}
3950	r_dcache_fsm = DCACHE_IDLE;
3951	break;
3952	}
3953	case PTE2_MISS:
3954	{
3955	if ( r_dcache_tlb_ins.read() )
3956	{
3957	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3958	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3959	r_icache_tlb_miss_req = false;
3960	r_icache_tlb_rsp_error = true;
3961	}
3962	else
3963	{
3964	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3965	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3966	m_drsp.valid = true;
3967	m_drsp.error = true;
3968	}
3969	r_dcache_fsm = DCACHE_IDLE;
3970	break;
3971	}
3972	} // end switch type
3973	r_vci_rsp_data_error = false;
3974	}
3975	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3976	{
3977	r_dcache_miss_word = 0;
3978	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3979	}
3980	break;
3981	}
3982	//////////////////////////
3983	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3984	{
3985	if ( m_dreq.valid) m_cost_data_miss_frz++;
3986
3987	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3988	{
3989	#ifdef INSTRUMENTATION
3990	m_cpt_dcache_data_write++;
3991	#endif
3992	r_dcache.write( r_dcache_miss_way.read(),
3993	r_dcache_miss_set.read(),
3994	r_dcache_miss_word.read(),
3995	r_vci_rsp_fifo_dcache.read() );
3996	#if DEBUG_DCACHE
3997	if ( m_debug_dcache_fsm )
3998	{
3999	std::cout << " <PROC " << name()
4000	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4001	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4002	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4003	<< " / SET = " << r_dcache_miss_set.read()
4004	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4005	}
4006	#endif
4007	vci_rsp_fifo_dcache_get = true;
4008	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4009
4010	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4011	{
4012	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4013	}
4014	}
4015	break;
4016	}
4017	//////////////////////////
4018	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4019	// and the cleanup ack has not been received,
4020	// as indicated by the r_dcache_miss clack.
4021	// - If no matching coherence request (r_dcache_inval_miss)
4022	// switch directory slot to VALID state.
4023	// - If matching coherence request, switch directory slot
4024	// to ZOMBI state, and send a cleanup request.
4025	{
4026	if ( m_dreq.valid) m_cost_data_miss_frz++;
4027
4028	// coherence request (from CC_RECEIVE FSM)
4029	if ( r_cc_receive_dcache_req.read() )
4030	{
4031	r_dcache_fsm = DCACHE_CC_CHECK;
4032	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4033	break;
4034	}
4035
4036	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4037	{
4038	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4039	{
4040	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4041	{
4042	r_dcache_miss_inval = false;
4043	// request cleanup
4044	r_dcache_cc_send_req = true;
4045	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4046	r_dcache_cc_send_way = r_dcache_miss_way.read();
4047	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4048
4049	#ifdef INSTRUMENTATION
4050	m_cpt_dcache_dir_write++;
4051	#endif
4052	r_dcache.write_dir( r_dcache_save_paddr.read(),
4053	r_dcache_miss_way.read(),
4054	r_dcache_miss_set.read(),
4055	CACHE_SLOT_STATE_ZOMBI );
4056	#if DEBUG_DCACHE
4057	if ( m_debug_dcache_fsm )
4058	{
4059	std::cout << " <PROC " << name()
4060	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4061	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4062	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4063	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4064	}
4065	#endif
4066	}
4067	else
4068	break;
4069	}
4070	else // switch slot to VALID state
4071	{
4072
4073	#ifdef INSTRUMENTATION
4074	m_cpt_dcache_dir_write++;
4075	#endif
4076	r_dcache.write_dir( r_dcache_save_paddr.read(),
4077	r_dcache_miss_way.read(),
4078	r_dcache_miss_set.read(),
4079	CACHE_SLOT_STATE_VALID );
4080
4081	#if DEBUG_DCACHE
4082	if ( m_debug_dcache_fsm )
4083	{
4084	std::cout << " <PROC " << name()
4085	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4086	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4087	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4088	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4089
4090	r_dcache.printTrace();
4091
4092
4093	}
4094	#endif
4095	// reset directory extension
4096	size_t way = r_dcache_miss_way.read();
4097	size_t set = r_dcache_miss_set.read();
4098	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4099	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4100	}
4101	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4102	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4103	else r_dcache_fsm = DCACHE_IDLE;
4104	}
4105	break;
4106	}
4107	/////////////////////
4108	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4109	{
4110	// coherence request (from CC_RECEIVE FSM)
4111	if ( r_cc_receive_dcache_req.read() )
4112	{
4113	r_dcache_fsm = DCACHE_CC_CHECK;
4114	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4115	break;
4116	}
4117
4118	if ( r_vci_rsp_data_error.read() ) // bus error
4119	{
4120	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4121	r_mmu_dbvar = m_dreq.addr;
4122	r_vci_rsp_data_error = false;
4123	m_drsp.error = true;
4124	m_drsp.valid = true;
4125	r_dcache_fsm = DCACHE_IDLE;
4126	break;
4127	}
4128	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4129	{
4130	// consume data
4131	vci_rsp_fifo_dcache_get = true;
4132	r_dcache_fsm = DCACHE_IDLE;
4133
4134	// acknowledge the processor request if it has not been modified
4135	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4136	{
4137	m_drsp.valid = true;
4138	m_drsp.error = false;
4139	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4140	}
4141	}
4142	break;
4143	}
4144	/////////////////////
4145	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4146	{
4147	// coherence request (from CC_RECEIVE FSM)
4148	if ( r_cc_receive_dcache_req.read() )
4149	{
4150	r_dcache_fsm = DCACHE_CC_CHECK;
4151	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4152	break;
4153	}
4154
4155	if ( r_vci_rsp_data_error.read() ) // bus error
4156	{
4157	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4158	r_mmu_dbvar = m_dreq.addr;
4159	r_vci_rsp_data_error = false;
4160	m_drsp.error = true;
4161	m_drsp.valid = true;
4162	r_dcache_fsm = DCACHE_IDLE;
4163	break;
4164	}
4165	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4166	{
4167	// consume data
4168	vci_rsp_fifo_dcache_get = true;
4169
4170	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4171	{
4172	// set key value in llsc reservation buffer
4173	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4174	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4175	}
4176	else // last flit
4177	{
4178	// acknowledge the processor request if it has not been modified
4179	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4180	{
4181	m_drsp.valid = true;
4182	m_drsp.error = false;
4183	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4184	}
4185	r_dcache_fsm = DCACHE_IDLE;
4186	}
4187	}
4188	break;
4189	}
4190	////////////////////
4191	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4192	{
4193	// coherence request (from CC_RECEIVE FSM)
4194	if ( r_cc_receive_dcache_req.read() )
4195	{
4196	r_dcache_fsm = DCACHE_CC_CHECK;
4197	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4198	break;
4199	}
4200
4201	if ( r_vci_rsp_data_error.read() ) // bus error
4202	{
4203	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4204	r_mmu_dbvar = m_dreq.addr;
4205	r_vci_rsp_data_error = false;
4206	m_drsp.error = true;
4207	m_drsp.valid = true;
4208	r_dcache_fsm = DCACHE_IDLE;
4209	break;
4210	}
4211	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4212	{
4213	// consume response
4214	vci_rsp_fifo_dcache_get = true;
4215	m_drsp.valid = true;
4216	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4217	r_dcache_fsm = DCACHE_IDLE;
4218	}
4219	break;
4220	}
4221	//////////////////////////
4222	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4223	// before handling a processor WRITE or SC request
4224	// Input argument is r_dcache_dirty_paddr
4225	// In this first state, we get PTE value in dcache
4226	// and post a CAS request to CMD FSM
4227	{
4228	// get PTE in dcache
4229	uint32_t pte;
4230	size_t way;
4231	size_t set;
4232	size_t word; // unused
4233	int state;
4234
4235	#ifdef INSTRUMENTATION
4236	m_cpt_dcache_data_read++;
4237	m_cpt_dcache_dir_read++;
4238	#endif
4239	r_dcache.read( r_dcache_dirty_paddr.read(),
4240	&pte,
4241	&way,
4242	&set,
4243	&word,
4244	&state );
4245
4246	assert( (state == CACHE_SLOT_STATE_VALID) and
4247	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4248
4249	// request CAS transaction to CMD_FSM
4250	r_dcache_dirty_way = way;
4251	r_dcache_dirty_set = set;
4252
4253	// check llsc reservation buffer
4254	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4255	r_dcache_llsc_valid = false;
4256
4257	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4258	r_dcache_vci_cas_req = true;
4259	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4260	r_dcache_vci_cas_old = pte;
4261	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4262	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4263
4264	#if DEBUG_DCACHE
4265	if ( m_debug_dcache_fsm )
4266	{
4267	std::cout << " <PROC " << name()
4268	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4269	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4270	<< " / PTE_VALUE = " << pte << std::dec
4271	<< " / SET = " << set
4272	<< " / WAY = " << way << std::endl;
4273	}
4274	#endif
4275	break;
4276	}
4277	///////////////////////
4278	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4279	// and return to IDLE state when response is received.
4280	// we don't care if the CAS is a failure:
4281	// - if the CAS is a success, the coherence mechanism
4282	// updates the local copy.
4283	// - if the CAS is a failure, we just retry the write.
4284	{
4285	// coherence request (from CC_RECEIVE FSM)
4286	if ( r_cc_receive_dcache_req.read() )
4287	{
4288	r_dcache_fsm = DCACHE_CC_CHECK;
4289	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4290	break;
4291	}
4292
4293	if ( r_vci_rsp_data_error.read() ) // bus error
4294	{
4295	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4296	std::cout << "This should not happen in this state" << std::endl;
4297	exit(0);
4298	}
4299	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4300	{
4301	vci_rsp_fifo_dcache_get = true;
4302	r_dcache_fsm = DCACHE_IDLE;
4303
4304	#if DEBUG_DCACHE
4305	if ( m_debug_dcache_fsm )
4306	{
4307	std::cout << " <PROC " << name()
4308	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4309	}
4310	#endif
4311	}
4312	break;
4313	}
4314	/////////////////////
4315	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4316	// handling coherence requests for DCACHE.
4317	// If there is a matching pending miss on the modified cache
4318	// line this is signaled in the r_dcache_miss inval flip-flop.
4319	// If the updated (or invalidated) cache line has copies in TLBs
4320	// these TLB copies are invalidated.
4321	// The return state is defined in r_dcache_fsm_cc_save
4322	{
4323	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4324	paddr_t mask = ~((m_dcache_words<<2)-1);
4325
4326	#if DEBUG_DCACHE
4327	if ( m_debug_dcache_fsm )
4328	{
4329	std::cout << " <PROC " << name()
4330	<< " DCACHE_CC_CHECK> paddr = " << paddr
4331	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4332	<< " mask = " << mask
4333	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4334	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4335	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4336	<<std::endl;
4337	}
4338	#endif
4339
4340	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4341	// We switch the directory slot to EMPTY state
4342	// and reset r_icache_miss_clack if the cleanup ack
4343	// is matching a pending miss.
4344	{
4345
4346	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4347
4348	#ifdef INSTRUMENTATION
4349	m_cpt_dcache_dir_write++;
4350	#endif
4351	r_dcache.write_dir( 0,
4352	r_cc_receive_dcache_way.read(),
4353	r_cc_receive_dcache_set.read(),
4354	CACHE_SLOT_STATE_EMPTY);
4355
4356	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4357	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4358	r_dcache_miss_clack = false;
4359
4360	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4361	r_cc_receive_dcache_req = false;
4362	#if DEBUG_DCACHE
4363	if ( m_debug_dcache_fsm )
4364	{
4365	std::cout << " <PROC " << name()
4366	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4367	<< " set = " << r_cc_receive_dcache_set.read()
4368	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4369	}
4370	#endif
4371	}
4372	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4373	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4374	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4375	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4376	{
4377	// signaling matching
4378	r_dcache_miss_inval = true;
4379
4380	// in case of update, go to CC_UPDT
4381	// JUST TO POP THE FIFO
4382	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4383	{
4384	r_dcache_fsm = DCACHE_CC_UPDT;
4385	r_dcache_cc_word = r_cc_receive_word_idx.read();
4386	// just pop the fifo , don't write in icache
4387	r_dcache_cc_need_write = false;
4388	}
4389	// the request is dealt with
4390	else
4391	{
4392	r_cc_receive_dcache_req = false;
4393	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4394	}
4395
4396	#if DEBUG_DCACHE
4397	if ( m_debug_dcache_fsm )
4398	{
4399	std::cout << " <PROC " << name()
4400	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4401	<< " PADDR = " << std::hex << paddr << std::endl;
4402	}
4403	#endif
4404
4405	}
4406	else // no match
4407	{
4408	int state;
4409	size_t way;
4410	size_t set;
4411	size_t word;
4412
4413	#ifdef INSTRUMENTATION
4414	m_cpt_dcache_dir_read++;
4415	#endif
4416	r_dcache.read_dir( paddr,
4417	&state,
4418	&way,
4419	&set,
4420	&word ); // unused
4421
4422	r_dcache_cc_way = way;
4423	r_dcache_cc_set = set;
4424
4425	if ( state == CACHE_SLOT_STATE_VALID) // hit
4426	{
4427	// need to update the cache state
4428	r_dcache_cc_need_write = true;
4429	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4430	{
4431	r_dcache_fsm = DCACHE_CC_UPDT;
4432	r_dcache_cc_word = r_cc_receive_word_idx.read();
4433	}
4434	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4435	{
4436	r_dcache_fsm = DCACHE_CC_INVAL;
4437	}
4438	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4439	{
4440	r_dcache_fsm = DCACHE_CC_BROADCAST;
4441	}
4442	}
4443	else // miss
4444	{
4445	// multicast acknowledgement required in case of update
4446	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4447	{
4448	r_dcache_fsm = DCACHE_CC_UPDT;
4449	r_dcache_cc_word = r_cc_receive_word_idx.read();
4450	// just pop the fifo , don't write in icache
4451	r_dcache_cc_need_write = false;
4452	}
4453	else // No response needed
4454	{
4455	r_cc_receive_dcache_req = false;
4456	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4457	}
4458	}
4459
4460	#if DEBUG_DCACHE
4461	if ( m_debug_dcache_fsm )
4462	{
4463	std::cout << " <PROC " << name()
4464	<< " DCACHE_CC_CHECK> Coherence request received:"
4465	<< " PADDR = " << std::hex << paddr
4466	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4467	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4468	}
4469	#endif
4470	}
4471	break;
4472	}
4473	/////////////////////
4474	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4475	// after possible invalidation of copies in TLBs
4476	{
4477	size_t way = r_dcache_cc_way.read();
4478	size_t set = r_dcache_cc_set.read();
4479
4480	if (r_dcache_cc_need_write.read())
4481	{
4482	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4483	{
4484	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4485	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4486	r_dcache_tlb_inval_set = 0;
4487	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4488	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4489	break;
4490	}
4491	else
4492	{
4493	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4494	{
4495	r_itlb.reset();
4496	r_dtlb.reset();
4497	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4498
4499	#if DEBUG_DCACHE
4500	if ( m_debug_dcache_fsm )
4501	{
4502	std::cout << " <PROC " << name()
4503	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4504	}
4505	#endif
4506	}
4507
4508	r_dcache.write_dir( 0,
4509	way,
4510	set,
4511	CACHE_SLOT_STATE_EMPTY );
4512
4513	r_dcache_cc_need_write = false;
4514
4515	#if DEBUG_DCACHE
4516	if ( m_debug_dcache_fsm )
4517	{
4518	std::cout << " <PROC " << name()
4519	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4520	<< " / WAY = " << way
4521	<< " / SET = " << set << std::endl;
4522	}
4523	#endif
4524	}
4525	}
4526	// multicast acknowledgement
4527	// send a request to cc_send_fsm
4528	if(not r_dcache_cc_send_req.read()) // cc_send is available
4529	{
4530	// coherence request completed
4531	r_cc_receive_dcache_req = false;
4532	// request multicast acknowledgement
4533	r_dcache_cc_send_req = true;
4534	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4535	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4536	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4537
4538	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4539	}
4540	//else wait for previous cc_send request to be sent
4541	break;
4542	}
4543	///////////////////
4544	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4545	// after possible invalidation of copies in TLBs
4546	{
4547	size_t word = r_dcache_cc_word.read();
4548	size_t way = r_dcache_cc_way.read();
4549	size_t set = r_dcache_cc_set.read();
4550
4551	if (r_cc_receive_updt_fifo_be.rok())
4552	{
4553	if (r_dcache_cc_need_write.read())
4554	{
4555	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4556	{
4557	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4558	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4559	r_dcache_tlb_inval_set = 0;
4560	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4561	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4562	break;
4563	}
4564
4565	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4566	{
4567	r_itlb.reset();
4568	r_dtlb.reset();
4569	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4570
4571	#if DEBUG_DCACHE
4572	if ( m_debug_dcache_fsm )
4573	{
4574	std::cout << " <PROC " << name()
4575	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4576	}
4577	#endif
4578	}
4579
4580	#ifdef INSTRUMENTATION
4581	m_cpt_dcache_data_write++;
4582	#endif
4583	r_dcache.write( way,
4584	set,
4585	word,
4586	r_cc_receive_updt_fifo_data.read(),
4587	r_cc_receive_updt_fifo_be.read() );
4588
4589	r_dcache_cc_word = word + 1;
4590
4591	#if DEBUG_DCACHE
4592	if ( m_debug_dcache_fsm )
4593	{
4594	std::cout << " <PROC " << name()
4595	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4596	<< " / WAY = " << way
4597	<< " / SET = " << set
4598	<< " / WORD = " << word
4599	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4600	}
4601	#endif
4602	}
4603
4604	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4605	{
4606	// no need to write in the cache anymore
4607	r_dcache_cc_need_write = false;
4608
4609	// wait to send a request to cc_send_fsm
4610	if(not r_icache_cc_send_req.read())
4611	// cc_send is available
4612	{
4613	//consume last fifo flit if eop and request to cc_send possible
4614	cc_receive_updt_fifo_get = true;
4615
4616	// coherence request completed
4617	r_cc_receive_dcache_req = false;
4618
4619	// request multicast acknowledgement
4620	r_dcache_cc_send_req = true;
4621	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4622	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4623	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4624
4625	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4626	}
4627	}
4628	else
4629	{
4630	//consume fifo if not eop
4631	cc_receive_updt_fifo_get = true;
4632	}
4633	}
4634	break;
4635	}
4636	/////////////////////////
4637	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4638	// and request a cleanup, after possible
4639	// invalidation of copies in TLBs
4640	{
4641	size_t way = r_dcache_cc_way.read();
4642	size_t set = r_dcache_cc_set.read();
4643	paddr_t nline = r_cc_receive_dcache_nline.read();
4644
4645	if (r_dcache_cc_need_write.read())
4646	{
4647	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4648	{
4649	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4650	r_dcache_tlb_inval_line = nline;
4651	r_dcache_tlb_inval_set = 0;
4652	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4653	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4654	break;
4655	}
4656	else
4657	{
4658	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4659	{
4660	r_itlb.reset();
4661	r_dtlb.reset();
4662	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4663
4664	#if DEBUG_DCACHE
4665	if ( m_debug_dcache_fsm )
4666	{
4667	std::cout << " <PROC " << name()
4668	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4669	}
4670	#endif
4671	}
4672
4673	#ifdef INSTRUMENTATION
4674	m_cpt_dcache_dir_write++;
4675	#endif
4676	r_dcache.write_dir( way,
4677	set,
4678	CACHE_SLOT_STATE_ZOMBI );
4679
4680	r_dcache_cc_need_write = false;
4681	#if DEBUG_DCACHE
4682	if ( m_debug_dcache_fsm )
4683	{
4684	std::cout << " <PROC " << name()
4685	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4686	<< " SET = " << set
4687	<< " / WAY = " << way << std::endl;
4688	}
4689	#endif
4690	}
4691	}
4692	// cleanup
4693	// send a request to cc_send_fsm
4694	if(not r_dcache_cc_send_req.read()) // cc_send is available
4695	{
4696	// coherence request completed
4697	r_cc_receive_dcache_req = false;
4698	// request cleanup
4699	r_dcache_cc_send_req = true;
4700	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4701	r_dcache_cc_send_way = r_dcache_cc_way.read();
4702	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4703
4704	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4705	}
4706	//else wait for previous cc_send request to be sent
4707	break;
4708	}
4709	///////////////////////////
4710	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4711	// It makes assumption: m_itlb_sets == m_dtlb_sets
4712	// All ways are handled in parallel.
4713	// We enter this state when a DCACHE line is modified,
4714	// and there is a copy in itlb or dtlb.
4715	// It can be caused by:
4716	// - a coherence inval or updt transaction,
4717	// - a line inval caused by a cache miss
4718	// - a processor XTN inval request,
4719	// - a WRITE hit,
4720	// - a Dirty bit update
4721	// Input arguments are:
4722	// - r_dcache_tlb_inval_line
4723	// - r_dcache_tlb_inval_set
4724	// - r_dcache_fsm_scan_save
4725	{
4726	paddr_t line = r_dcache_tlb_inval_line.read();
4727	size_t set = r_dcache_tlb_inval_set.read();
4728	size_t way;
4729	bool ok;
4730
4731	for ( way = 0 ; way < m_itlb_ways ; way++ )
4732	{
4733	ok = r_itlb.inval( line, way, set );
4734
4735	#if DEBUG_DCACHE
4736	if ( m_debug_dcache_fsm and ok )
4737	{
4738	std::cout << " <PROC " << name()
4739	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4740	<< " line = " << line << std::dec
4741	<< " / set = " << set
4742	<< " / way = " << way << std::endl;
4743	}
4744	#endif
4745	}
4746
4747	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4748	{
4749	ok = r_dtlb.inval( line, way, set );
4750
4751	#if DEBUG_DCACHE
4752	if ( m_debug_dcache_fsm and ok )
4753	{
4754	std::cout << " <PROC " << name()
4755	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4756	<< " line = " << line << std::dec
4757	<< " / set = " << set
4758	<< " / way = " << way << std::endl;
4759	}
4760	#endif
4761	}
4762
4763	// return to the calling state when TLB inval completed
4764	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4765	{
4766	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4767	}
4768	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4769	break;
4770	}
4771	} // end switch r_dcache_fsm
4772
4773	///////////////// wbuf update ///////////////////////////////////////////////////////
4774	r_wbuf.update();
4775
4776	///////////////// llsc update ///////////////////////////////////////////////////////
4777	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4778	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4779
4780	//////////////// test processor frozen //////////////////////////////////////////////
4781	// The simulation exit if the number of consecutive frozen cycles
4782	// is larger than the m_max_frozen_cycles (constructor parameter)
4783	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4784	{
4785	m_cpt_frz_cycles++; // used for instrumentation
4786	m_cpt_stop_simulation++; // used for debug
4787	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4788	{
4789	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4790	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4791	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4792	<< std::endl;
4793	r_iss.dump();
4794	exit(1);
4795	}
4796	}
4797	else
4798	{
4799	m_cpt_stop_simulation = 0;
4800	}
4801
4802	/////////// execute one iss cycle /////////////////////////////////
4803	{
4804	uint32_t it = 0;
4805	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4806	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4807	}
4808
4809	////////////////////////////////////////////////////////////////////////////
4810	// The VCI_CMD FSM controls the following ressources:
4811	// - r_vci_cmd_fsm
4812	// - r_vci_cmd_min
4813	// - r_vci_cmd_max
4814	// - r_vci_cmd_cpt
4815	// - r_vci_cmd_imiss_prio
4816	// - wbuf (reset)
4817	// - r_icache_miss_req (reset)
4818	// - r_icache_unc_req (reset)
4819	// - r_dcache_vci_miss_req (reset)
4820	// - r_dcache_vci_unc_req (reset)
4821	// - r_dcache_vci_ll_req (reset)
4822	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4823	// - r_dcache_vci_cas_req (reset)
4824	//
4825	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4826	// There are 8 request types, with the following priorities :
4827	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4828	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4829	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4830	// 4 - Instruction Uncachable : r_icache_unc_req
4831	// 5 - Data Write : r_wbuf.rok()
4832	// 6 - Data Linked Load : r_dcache_vci_ll_req
4833	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4834	// 8 - Compare And Swap : r_dcache_vci_cas_req
4835	//
4836	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4837	// and the VCI_RSP_FSM are fully desynchronized.
4838	//
4839	// VCI formats:
4840	// According to the VCI advanced specification, all read requests packets
4841	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4842	// are one word packets.
4843	// For write burst packets, all words are in the same cache line,
4844	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4845	// The sc command packet implements actually a compare-and-swap mechanism
4846	// and the packet contains two flits.
4847	////////////////////////////////////////////////////////////////////////////////////
4848
4849	switch ( r_vci_cmd_fsm.read() )
4850	{
4851	//////////////
4852	case CMD_IDLE:
4853	{
4854	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4855	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4856	// to check a possible pending write on the same cache line.
4857	// As there is only one possible access per cycle to write buffer, we implement
4858	// a round-robin priority between DCACHE and ICACHE for this access,
4859	// using the r_vci_cmd_imiss_prio flip-flop.
4860
4861	size_t wbuf_min;
4862	size_t wbuf_max;
4863
4864	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4865	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4866
4867	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4868	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4869
4870	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4871	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4872
4873	bool icache_miss_req = r_icache_miss_req.read() and
4874	( not (r_dcache_vci_miss_req.read() or
4875	r_dcache_vci_ll_req.read() or
4876	r_dcache_vci_unc_req.read())
4877	or r_vci_cmd_imiss_prio.read() );
4878
4879
4880	// 1 - Data Read Miss
4881	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4882	{
4883	r_vci_cmd_fsm = CMD_DATA_MISS;
4884	r_dcache_vci_miss_req = false;
4885	r_vci_cmd_imiss_prio = true;
4886	// m_cpt_dmiss_transaction++;
4887	}
4888	// 2 - Data Read Uncachable
4889	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4890	{
4891	r_vci_cmd_fsm = CMD_DATA_UNC;
4892	r_dcache_vci_unc_req = false;
4893	// m_cpt_dunc_transaction++;
4894	}
4895	// 3 - Data Linked Load
4896	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4897	{
4898	r_dcache_vci_ll_req = false;
4899	r_vci_cmd_fsm = CMD_DATA_LL;
4900	// m_cpt_ll_transaction++;
4901	}
4902	// 4 - Instruction Miss
4903	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4904	{
4905	r_vci_cmd_fsm = CMD_INS_MISS;
4906	r_icache_miss_req = false;
4907	r_vci_cmd_imiss_prio = false;
4908	// m_cpt_imiss_transaction++;
4909	}
4910	// 5 - Instruction Uncachable
4911	else if ( r_icache_unc_req.read() )
4912	{
4913	r_vci_cmd_fsm = CMD_INS_UNC;
4914	r_icache_unc_req = false;
4915	// m_cpt_iunc_transaction++;
4916	}
4917	// 6 - Data Write
4918	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4919	{
4920	r_vci_cmd_fsm = CMD_DATA_WRITE;
4921	r_vci_cmd_cpt = wbuf_min;
4922	r_vci_cmd_min = wbuf_min;
4923	r_vci_cmd_max = wbuf_max;
4924	// m_cpt_write_transaction++;
4925	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4926	}
4927	// 7 - Data Store Conditionnal
4928	else if ( r_dcache_vci_sc_req.read() )
4929	{
4930	r_dcache_vci_sc_req = false;
4931	r_vci_cmd_cpt = 0;
4932	r_vci_cmd_fsm = CMD_DATA_SC;
4933	// m_cpt_sc_transaction++;
4934	}
4935	// 8 - Compare And Swap
4936	else if ( r_dcache_vci_cas_req.read() )
4937	{
4938	r_vci_cmd_fsm = CMD_DATA_CAS;
4939	r_dcache_vci_cas_req = false;
4940	r_vci_cmd_cpt = 0;
4941	// m_cpt_cas_transaction++;
4942	}
4943	break;
4944	}
4945	////////////////////
4946	case CMD_DATA_WRITE:
4947	{
4948	if ( p_vci.cmdack.read() )
4949	{
4950	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4951	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4952	{
4953	r_vci_cmd_fsm = CMD_IDLE ;
4954	r_wbuf.sent() ;
4955	}
4956	}
4957	break;
4958	}
4959	/////////////////
4960	case CMD_DATA_SC:
4961	case CMD_DATA_CAS:
4962	{
4963	// The CAS and SC VCI commands contain two flits
4964	if ( p_vci.cmdack.read() )
4965	{
4966	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4967	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4968	}
4969	break;
4970	}
4971	//////////////////
4972	case CMD_INS_MISS:
4973	case CMD_INS_UNC:
4974	case CMD_DATA_MISS:
4975	case CMD_DATA_UNC:
4976	case CMD_DATA_LL:
4977	{
4978	// all read VCI commands contain one single flit
4979	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4980	break;
4981	}
4982
4983	} // end switch r_vci_cmd_fsm
4984
4985	//////////////////////////////////////////////////////////////////////////
4986	// The VCI_RSP FSM controls the following ressources:
4987	// - r_vci_rsp_fsm:
4988	// - r_vci_rsp_fifo_icache (push)
4989	// - r_vci_rsp_fifo_dcache (push)
4990	// - r_vci_rsp_data_error (set)
4991	// - r_vci_rsp_ins_error (set)
4992	// - r_vci_rsp_cpt
4993	// - r_dcache_vci_sc_req (reset when SC response recieved)
4994	//
4995	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4996	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4997	// to identify the transactions.
4998	//
4999	// VCI vormat:
5000	// This component checks the response packet length and accepts only
5001	// single word packets for write response packets.
5002	//
5003	// Error handling:
5004	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5005	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5006	// flip_flop and the error is signaled by the DCACHE FSM.
5007	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5008	// flip_flop and the error is signaled by the ICACHE FSM.
5009	// In case of Cleanup Error, the simulation stops with an error message...
5010	//////////////////////////////////////////////////////////////////////////
5011
5012	switch ( r_vci_rsp_fsm.read() )
5013	{
5014	//////////////
5015	case RSP_IDLE:
5016	{
5017	if ( p_vci.rspval.read() )
5018	{
5019	r_vci_rsp_cpt = 0;
5020
5021	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5022	{
5023	r_vci_rsp_fsm = RSP_DATA_UNC;
5024	}
5025	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5026	{
5027	r_vci_rsp_fsm = RSP_DATA_MISS;
5028	}
5029	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5030	{
5031	r_vci_rsp_fsm = RSP_INS_UNC;
5032	}
5033	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5034	{
5035	r_vci_rsp_fsm = RSP_INS_MISS;
5036	}
5037	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5038	{
5039	r_vci_rsp_fsm = RSP_DATA_WRITE;
5040	}
5041	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5042	{
5043	r_vci_rsp_fsm = RSP_DATA_UNC;
5044	}
5045	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5046	{
5047	r_vci_rsp_fsm = RSP_DATA_LL;
5048	}
5049	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5050	{
5051	r_vci_rsp_fsm = RSP_DATA_UNC;
5052	}
5053	else
5054	{
5055	assert(false and "Unexpected VCI response");
5056	}
5057	}
5058	break;
5059	}
5060	//////////////////
5061	case RSP_INS_MISS:
5062	{
5063	if ( p_vci.rspval.read() )
5064	{
5065	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5066	{
5067	r_vci_rsp_ins_error = true;
5068	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5069	}
5070	else // no error reported
5071	{
5072	if ( r_vci_rsp_fifo_icache.wok() )
5073	{
5074	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5075	"The VCI response packet for instruction miss is too long" );
5076
5077	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5078	vci_rsp_fifo_icache_put = true,
5079	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5080	if ( p_vci.reop.read() )
5081	{
5082	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5083	"The VCI response packet for instruction miss is too short");
5084
5085	r_vci_rsp_fsm = RSP_IDLE;
5086	}
5087	}
5088	}
5089	}
5090	break;
5091	}
5092	/////////////////
5093	case RSP_INS_UNC:
5094	{
5095	if (p_vci.rspval.read() )
5096	{
5097	assert( p_vci.reop.read() and
5098	"illegal VCI response packet for uncachable instruction");
5099
5100	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5101	{
5102	r_vci_rsp_ins_error = true;
5103	r_vci_rsp_fsm = RSP_IDLE;
5104	}
5105	else // no error reported
5106	{
5107	if ( r_vci_rsp_fifo_icache.wok())
5108	{
5109	vci_rsp_fifo_icache_put = true;
5110	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5111	r_vci_rsp_fsm = RSP_IDLE;
5112	}
5113	}
5114	}
5115	break;
5116	}
5117	///////////////////
5118	case RSP_DATA_MISS:
5119	{
5120	if ( p_vci.rspval.read() )
5121	{
5122	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5123	{
5124	r_vci_rsp_data_error = true;
5125	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5126	}
5127	else // no error reported
5128	{
5129	if ( r_vci_rsp_fifo_dcache.wok() )
5130	{
5131	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5132	"The VCI response packet for data miss is too long");
5133
5134	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5135	vci_rsp_fifo_dcache_put = true,
5136	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5137	if ( p_vci.reop.read() )
5138	{
5139	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5140	"The VCI response packet for data miss is too short");
5141
5142	r_vci_rsp_fsm = RSP_IDLE;
5143	}
5144	}
5145	}
5146	}
5147	break;
5148	}
5149	//////////////////
5150	case RSP_DATA_UNC:
5151	{
5152	if (p_vci.rspval.read() )
5153	{
5154	assert( p_vci.reop.read() and
5155	"illegal VCI response packet for uncachable read data");
5156
5157	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5158	{
5159	r_vci_rsp_data_error = true;
5160	r_vci_rsp_fsm = RSP_IDLE;
5161	}
5162	else // no error reported
5163	{
5164	if ( r_vci_rsp_fifo_dcache.wok())
5165	{
5166	vci_rsp_fifo_dcache_put = true;
5167	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5168	r_vci_rsp_fsm = RSP_IDLE;
5169	}
5170	}
5171	}
5172	break;
5173	}
5174	////////////////////
5175	case RSP_DATA_LL:
5176	{
5177	if ( p_vci.rspval.read() )
5178	{
5179	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5180	{
5181	r_vci_rsp_data_error = true;
5182	r_vci_rsp_fsm = RSP_IDLE;
5183	}
5184	if (r_vci_rsp_cpt.read() == 0) //first flit
5185	{
5186	if(r_vci_rsp_fifo_dcache.wok())
5187	{
5188	assert(!p_vci.reop.read() &&
5189	"illegal VCI response packet for LL");
5190	vci_rsp_fifo_dcache_put = true;
5191	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5192	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5193	}
5194	break;
5195	}
5196	else // last flit
5197	{
5198	if(r_vci_rsp_fifo_dcache.wok())
5199	{
5200	assert(p_vci.reop.read() &&
5201	"illegal VCI response packet for LL");
5202	vci_rsp_fifo_dcache_put = true;
5203	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5204	r_vci_rsp_fsm = RSP_IDLE;
5205	}
5206	break;
5207	}
5208	}
5209	break;
5210	}
5211	////////////////////
5212	case RSP_DATA_WRITE:
5213	{
5214	if (p_vci.rspval.read())
5215	{
5216	assert( p_vci.reop.read() and
5217	"a VCI response packet must contain one flit for a write transaction");
5218
5219	r_vci_rsp_fsm = RSP_IDLE;
5220	uint32_t wbuf_index = p_vci.rtrdid.read();
5221	bool cacheable = r_wbuf.completed(wbuf_index);
5222	if ( not cacheable ) r_dcache_pending_unc_write = false;
5223	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5224	}
5225	break;
5226	}
5227	} // end switch r_vci_rsp_fsm
5228
5229	/////////////////////////////////////////////////////////////////////////////////////
5230	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5231	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5232	// and ICACHE FSM) that are served with a round-robin priority.
5233	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5234	// soon as the request has been sent.
5235	/////////////////////////////////////////////////////////////////////////////////////
5236	switch ( r_cc_send_fsm.read() )
5237	{
5238	///////////////////////////
5239	case CC_SEND_IDLE:
5240	{
5241	///////////////////////////////////////////////////////
5242	// handling round robin between icache and dcache : //
5243	// we first check for the last client and listen for //
5244	// a request of the other, then update the client //
5245	///////////////////////////////////////////////////////
5246	// r_cc_send_last_client : 0 dcache / 1 icache
5247	bool update_last_client = r_cc_send_last_client.read();
5248	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5249	{
5250	if (r_icache_cc_send_req.read()) // request from icache
5251	update_last_client = 1; // update last client to icache
5252	}
5253	else // last client was icache
5254	{
5255	if (r_dcache_cc_send_req.read()) // request from dcache
5256	update_last_client = 0; // update last client to dcache
5257	}
5258	r_cc_send_last_client = update_last_client;
5259
5260	// if there is an actual request
5261	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5262	{
5263	// test if the new client is dcache and has a cleanup request
5264	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5265	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5266	// test if the new client is dcache and has a multi acknowledgement request
5267	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5268	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5269	// test if the new client is icache and has a cleanup request
5270	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5271	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5272	// test if the new client is icache and has a multi acknowledgement request
5273	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5274	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5275	}
5276	break;
5277	}
5278	///////////////////////////
5279	case CC_SEND_CLEANUP_1:
5280	{
5281	// wait for the first flit to be consumed
5282	if (p_dspin_out.read.read())
5283	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5284
5285	break;
5286	}
5287	///////////////////////////
5288	case CC_SEND_CLEANUP_2:
5289	{
5290	// wait for the second flit to be consumed
5291	if (p_dspin_out.read.read())
5292	{
5293	if (r_cc_send_last_client.read() == 0) // dcache active request
5294	r_dcache_cc_send_req = false; // reset dcache request
5295	else // icache active request
5296	r_icache_cc_send_req = false; // reset icache request
5297
5298	// go back to idle state
5299	r_cc_send_fsm = CC_SEND_IDLE;
5300	}
5301	break;
5302	}
5303	///////////////////////////
5304	case CC_SEND_MULTI_ACK:
5305	{
5306	// wait for the flit to be consumed
5307	if(p_dspin_out.read.read())
5308	{
5309	if(r_cc_send_last_client.read() == 0) // dcache active request
5310	r_dcache_cc_send_req = false; // reset dcache request
5311	else // icache active request
5312	r_icache_cc_send_req = false; // reset icache request
5313	// go back to idle state
5314	r_cc_send_fsm = CC_SEND_IDLE;
5315	}
5316	break;
5317	}
5318	} // end switch CC_SEND FSM
5319
5320	///////////////////////////////////////////////////////////////////////////////
5321	// C_RECEIVE FSM
5322	// This FSM receive all coherence packets on a DSPIN40 port.
5323	// There is 4 packet types:
5324	// - CC_DATA_INVAL : DCACHE invalidate request
5325	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5326	// - CC_INST_INVAL : ICACHE invalidate request
5327	// - CC_INST_UPDT : ICACHE update request (multi-words)
5328	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5329	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5330	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5331	//////////////////////////////////////////////////////////////////////////////
5332	switch( r_cc_receive_fsm.read() )
5333	{
5334	/////////////////////
5335	case CC_RECEIVE_IDLE:
5336	{
5337	// a coherence request has arrived
5338	if (p_dspin_in.write.read())
5339	{
5340	// initialize dspin received data
5341	uint64_t receive_data = p_dspin_in.data.read();
5342	// initialize coherence packet type
5343	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5344	// initialize data/ins flip_flop (0 data / 1 ins)
5345	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5346	// test for a broadcast
5347	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5348	{
5349	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5350	}
5351	// test for a CLACK
5352	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5353	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5354	{
5355	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5356	}
5357	// test for a multi updt
5358	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5359	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5360	{
5361	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5362	}
5363	// test for a multi inval
5364	else
5365	{
5366	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5367	}
5368	}
5369	break;
5370	}
5371	//////////////////////
5372	case CC_RECEIVE_CLACK:
5373	{
5374	// initialize dspin received data
5375	uint64_t receive_data = p_dspin_in.data.read();
5376
5377	// for data CLACK, wait for dcache to take the request
5378	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5379	{
5380	// request dcache to handle the CLACK
5381	r_cc_receive_dcache_req = true;
5382	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5383	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5384	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5385	// get back to idle state
5386	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5387	break;
5388	}
5389	// for ins CLACK, wait for icache to take the request
5390	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5391	{
5392	// request icache to handle the CLACK
5393	r_cc_receive_icache_req = true;
5394	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5395	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5396	r_cc_receive_icache_type = CC_TYPE_CLACK;
5397	// get back to idle state
5398	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5399	break;
5400	}
5401	// keep waiting for the correct cache to accept the request
5402	break;
5403	}
5404	///////////////////////////////
5405	case CC_RECEIVE_BRDCAST_HEADER:
5406	{
5407	// no actual data in the HEADER, just skip to second flit
5408	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5409	break;
5410	}
5411	//////////////////////////////
5412	case CC_RECEIVE_BRDCAST_NLINE:
5413	{
5414	// initialize dspin received data
5415	uint64_t receive_data = p_dspin_in.data.read();
5416	// wait for both dcache and icache to take the request
5417	// TODO maybe we need to wait for both only to leave the state, but
5418	// not to actually post a request to an available cache => need a
5419	// flip_flop to check that ?
5420	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5421	{
5422	// request dcache to handle the BROADCAST
5423	r_cc_receive_dcache_req = true;
5424	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5425	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5426	// request icache to handle the BROADCAST
5427	r_cc_receive_icache_req = true;
5428	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5429	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5430	// get back to idle state
5431	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5432	break;
5433	}
5434	// keep waiting for the caches to accept the request
5435	break;
5436	}
5437	/////////////////////////////
5438	case CC_RECEIVE_INVAL_HEADER:
5439	{
5440	// sample updt tab index in the HEADER, then skip to second flit
5441	uint64_t receive_data = p_dspin_in.data.read();
5442	// for data INVAL, wait for dcache to take the request
5443	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5444	{
5445	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5446	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5447	break;
5448	}
5449	// for ins INVAL, wait for icache to take the request
5450	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5451	{
5452	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5453	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5454	break;
5455	}
5456	// keep waiting for the correct cache to accept the request
5457	break;
5458	}
5459	////////////////////////////
5460	case CC_RECEIVE_INVAL_NLINE:
5461	{
5462	// sample nline in the second flit
5463	uint64_t receive_data = p_dspin_in.data.read();
5464	// for data INVAL, wait for dcache to take the request
5465	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5466	{
5467	// request dcache to handle the INVAL
5468	r_cc_receive_dcache_req = true;
5469	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5470	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5471	// get back to idle state
5472	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5473	break;
5474	}
5475	// for ins INVAL, wait for icache to take the request
5476	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5477	{
5478	// request icache to handle the INVAL
5479	r_cc_receive_icache_req = true;
5480	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5481	r_cc_receive_icache_type = CC_TYPE_INVAL;
5482	// get back to idle state
5483	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5484	break;
5485	}
5486	// we should never get there
5487	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5488	}
5489	////////////////////////////
5490	case CC_RECEIVE_UPDT_HEADER:
5491	{
5492	// sample updt tab index in the HEADER, than skip to second flit
5493	uint64_t receive_data = p_dspin_in.data.read();
5494	// for data INVAL, wait for dcache to take the request and fifo to
5495	// be empty
5496	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5497	{
5498	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5499	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5500	break;
5501	}
5502	// for ins INVAL, wait for icache to take the request and fifo to be
5503	// empty
5504	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5505	{
5506	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5507	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5508	break;
5509	}
5510	// keep waiting for the correct cache to accept the request
5511	break;
5512	}
5513	///////////////////////////
5514	case CC_RECEIVE_UPDT_NLINE:
5515	{
5516	// sample nline and word index in the second flit
5517	uint64_t receive_data = p_dspin_in.data.read();
5518	// for data INVAL, wait for dcache to take the request and fifo to
5519	// be empty
5520	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5521	{
5522	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5523	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5524	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5525	// get back to idle state
5526	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5527	break;
5528	}
5529	// for ins INVAL, wait for icache to take the request and fifo to be
5530	// empty
5531	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5532	{
5533	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5534	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5535	r_cc_receive_icache_type = CC_TYPE_UPDT;
5536	// get back to idle state
5537	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5538	break;
5539	}
5540	// we should never get there
5541	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5542	break;
5543	}
5544	//////////////////////////
5545	case CC_RECEIVE_UPDT_DATA:
5546	{
5547	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5548	r_cc_receive_dcache_req = true;
5549	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5550	r_cc_receive_icache_req = true;
5551
5552	// sample data, be and eop
5553	uint64_t receive_data = p_dspin_in.data.read();
5554	// wait for the fifo
5555	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5556	{
5557	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5558	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5559	// sample eop to test for state exit
5560	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5561	cc_receive_updt_fifo_eop = flit_eop;
5562	cc_receive_updt_fifo_put = true;
5563	if(flit_eop)
5564	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5565	}
5566	break;
5567	}
5568	} // end switch CC_RECEIVE FSM
5569
5570	///////////////// Response FIFOs update //////////////////////
5571	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5572	vci_rsp_fifo_icache_put,
5573	vci_rsp_fifo_icache_data);
5574
5575	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5576	vci_rsp_fifo_dcache_put,
5577	vci_rsp_fifo_dcache_data);
5578
5579	///////////////// updt FIFO update //////////////////////
5580	//TODO check this
5581	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5582	cc_receive_updt_fifo_put,
5583	cc_receive_updt_fifo_be);
5584	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5585	cc_receive_updt_fifo_put,
5586	cc_receive_updt_fifo_data);
5587	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5588	cc_receive_updt_fifo_put,
5589	cc_receive_updt_fifo_eop);
5590
5591	} // end transition()
5592
5593	///////////////////////
5594	tmpl(void)::genMoore()
5595	///////////////////////
5596	{
5597
5598	// VCI initiator command on the direct network
5599	// it depends on the CMD FSM state
5600
5601	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5602	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5603
5604	p_vci.pktid = 0;
5605	p_vci.srcid = m_srcid;
5606	p_vci.cons = is_sc_or_cas;
5607	p_vci.contig = not is_sc_or_cas;
5608	p_vci.wrap = false;
5609	p_vci.clen = 0;
5610	p_vci.cfixed = false;
5611
5612	switch ( r_vci_cmd_fsm.read() ) {
5613
5614	case CMD_IDLE:
5615	p_vci.cmdval = false;
5616	p_vci.address = 0;
5617	p_vci.wdata = 0;
5618	p_vci.be = 0;
5619	p_vci.trdid = 0;
5620	p_vci.pktid = 0;
5621	p_vci.plen = 0;
5622	p_vci.cmd = vci_param::CMD_NOP;
5623	p_vci.eop = false;
5624	break;
5625
5626	case CMD_INS_MISS:
5627	p_vci.cmdval = true;
5628	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5629	p_vci.wdata = 0;
5630	p_vci.be = 0xF;
5631	p_vci.trdid = 0;
5632	p_vci.pktid = TYPE_READ_INS_MISS;
5633	p_vci.plen = m_icache_words<<2;
5634	p_vci.cmd = vci_param::CMD_READ;
5635	p_vci.eop = true;
5636	break;
5637
5638	case CMD_INS_UNC:
5639	p_vci.cmdval = true;
5640	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5641	p_vci.wdata = 0;
5642	p_vci.be = 0xF;
5643	p_vci.trdid = 0;
5644	p_vci.pktid = TYPE_READ_INS_UNC;
5645	p_vci.plen = 4;
5646	p_vci.cmd = vci_param::CMD_READ;
5647	p_vci.eop = true;
5648	break;
5649
5650	case CMD_DATA_MISS:
5651	p_vci.cmdval = true;
5652	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5653	p_vci.wdata = 0;
5654	p_vci.be = 0xF;
5655	p_vci.trdid = 0;
5656	p_vci.pktid = TYPE_READ_DATA_MISS;
5657	p_vci.plen = m_dcache_words << 2;
5658	p_vci.cmd = vci_param::CMD_READ;
5659	p_vci.eop = true;
5660	break;
5661
5662	case CMD_DATA_UNC:
5663	p_vci.cmdval = true;
5664	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5665	p_vci.wdata = 0;
5666	p_vci.be = r_dcache_vci_unc_be.read();
5667	p_vci.trdid = 0;
5668	p_vci.pktid = TYPE_READ_DATA_UNC;
5669	p_vci.plen = 4;
5670	p_vci.cmd = vci_param::CMD_READ;
5671	p_vci.eop = true;
5672	break;
5673
5674	case CMD_DATA_WRITE:
5675	p_vci.cmdval = true;
5676	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5677	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5678	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5679	p_vci.trdid = r_wbuf.getIndex();
5680	p_vci.pktid = TYPE_WRITE;
5681	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5682	p_vci.cmd = vci_param::CMD_WRITE;
5683	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5684	break;
5685
5686	case CMD_DATA_LL:
5687	p_vci.cmdval = true;
5688	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5689	p_vci.wdata = 0;
5690	p_vci.be = 0xF;
5691	p_vci.trdid = 0;
5692	p_vci.pktid = TYPE_LL;
5693	p_vci.plen = 8;
5694	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5695	p_vci.eop = true;
5696	break;
5697
5698	case CMD_DATA_SC:
5699	p_vci.cmdval = true;
5700	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5701	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5702	else p_vci.wdata = r_dcache_vci_sc_data.read();
5703	p_vci.be = 0xF;
5704	p_vci.trdid = 0;
5705	p_vci.pktid = TYPE_SC;
5706	p_vci.plen = 8;
5707	p_vci.cmd = vci_param::CMD_NOP;
5708	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5709	break;
5710
5711	case CMD_DATA_CAS:
5712	p_vci.cmdval = true;
5713	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5714	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5715	else p_vci.wdata = r_dcache_vci_cas_new.read();
5716	p_vci.be = 0xF;
5717	p_vci.trdid = 0;
5718	p_vci.pktid = TYPE_CAS;
5719	p_vci.plen = 8;
5720	p_vci.cmd = vci_param::CMD_NOP;
5721	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5722	break;
5723	} // end switch r_vci_cmd_fsm
5724
5725	// VCI initiator response on the direct network
5726	// it depends on the VCI_RSP FSM
5727
5728	switch (r_vci_rsp_fsm.read() )
5729	{
5730	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5731	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5732	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5733	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5734	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5735	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5736	case RSP_IDLE : p_vci.rspack = false; break;
5737	} // end switch r_vci_rsp_fsm
5738
5739
5740	// Send coherence packets on DSPIN L2M
5741	// it depends on the CC_SEND FSM
5742
5743	uint64_t dspin_send_data = 0;
5744	switch ( r_cc_send_fsm.read() )
5745	{
5746	//////////////////
5747	case CC_SEND_IDLE:
5748	{
5749	p_dspin_out.write = false;
5750	break;
5751	}
5752	///////////////////////
5753	case CC_SEND_CLEANUP_1:
5754	{
5755	// initialize dspin send data
5756	DspinDhccpParam::dspin_set(dspin_send_data,
5757	0,
5758	DspinDhccpParam::FROM_L1_EOP);
5759	DspinDhccpParam::dspin_set(dspin_send_data,
5760	m_cc_global_id,
5761	DspinDhccpParam::CLEANUP_SRCID);
5762	DspinDhccpParam::dspin_set(dspin_send_data,
5763	0,
5764	DspinDhccpParam::FROM_L1_BC);
5765
5766	if(r_cc_send_last_client.read() == 0) // dcache active request
5767	{
5768	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5769	>> (m_nline_width - m_x_width - m_y_width)
5770	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5771
5772	DspinDhccpParam::dspin_set(dspin_send_data,
5773	dest,
5774	DspinDhccpParam::CLEANUP_DEST);
5775
5776	DspinDhccpParam::dspin_set(dspin_send_data,
5777	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5778	DspinDhccpParam::CLEANUP_NLINE_MSB);
5779
5780	DspinDhccpParam::dspin_set(dspin_send_data,
5781	r_dcache_cc_send_way.read(),
5782	DspinDhccpParam::CLEANUP_WAY_INDEX);
5783
5784	DspinDhccpParam::dspin_set(dspin_send_data,
5785	DspinDhccpParam::TYPE_CLEANUP_DATA,
5786	DspinDhccpParam::FROM_L1_TYPE);
5787	}
5788	else // icache active request
5789	{
5790	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5791	>> (m_nline_width - m_x_width - m_y_width)
5792	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5793
5794	DspinDhccpParam::dspin_set(dspin_send_data,
5795	dest,
5796	DspinDhccpParam::CLEANUP_DEST);
5797
5798	DspinDhccpParam::dspin_set(dspin_send_data,
5799	r_icache_cc_send_nline.read() & 0x300000000ULL,
5800	DspinDhccpParam::CLEANUP_NLINE_MSB);
5801
5802	DspinDhccpParam::dspin_set(dspin_send_data,
5803	r_icache_cc_send_way.read(),
5804	DspinDhccpParam::CLEANUP_WAY_INDEX);
5805
5806	DspinDhccpParam::dspin_set(dspin_send_data,
5807	DspinDhccpParam::TYPE_CLEANUP_INST,
5808	DspinDhccpParam::FROM_L1_TYPE);
5809	}
5810	// send flit
5811	p_dspin_out.data = dspin_send_data;
5812	p_dspin_out.write = true;
5813	break;
5814	}
5815	///////////////////////
5816	case CC_SEND_CLEANUP_2:
5817	{
5818	// initialize dspin send data
5819	DspinDhccpParam::dspin_set(dspin_send_data,
5820	1,
5821	DspinDhccpParam::FROM_L1_EOP);
5822
5823	if(r_cc_send_last_client.read() == 0) // dcache active request
5824	{
5825	DspinDhccpParam::dspin_set(dspin_send_data,
5826	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5827	DspinDhccpParam::CLEANUP_NLINE_LSB);
5828	}
5829	else // icache active request
5830	{
5831	DspinDhccpParam::dspin_set(dspin_send_data,
5832	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5833	DspinDhccpParam::CLEANUP_NLINE_LSB);
5834	}
5835	// send flit
5836	p_dspin_out.data = dspin_send_data;
5837	p_dspin_out.write = true;
5838	break;
5839	}
5840	///////////////////////
5841	case CC_SEND_MULTI_ACK:
5842	{
5843	// initialize dspin send data
5844	DspinDhccpParam::dspin_set(dspin_send_data,
5845	1,
5846	DspinDhccpParam::FROM_L1_EOP);
5847	DspinDhccpParam::dspin_set(dspin_send_data,
5848	0,
5849	DspinDhccpParam::FROM_L1_BC);
5850	DspinDhccpParam::dspin_set(dspin_send_data,
5851	DspinDhccpParam::TYPE_MULTI_ACK,
5852	DspinDhccpParam::FROM_L1_TYPE);
5853
5854	if(r_cc_send_last_client.read() == 0) // dcache active request
5855	{
5856	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5857	>> (m_nline_width - m_x_width - m_y_width)
5858	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5859
5860	DspinDhccpParam::dspin_set(dspin_send_data,
5861	dest,
5862	DspinDhccpParam::MULTI_ACK_DEST);
5863
5864	DspinDhccpParam::dspin_set(dspin_send_data,
5865	r_dcache_cc_send_updt_tab_idx.read(),
5866	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5867	}
5868	else // icache active request
5869	{
5870	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5871	>> (m_nline_width - m_x_width - m_y_width)
5872	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5873
5874
5875	DspinDhccpParam::dspin_set(dspin_send_data,
5876	dest,
5877	DspinDhccpParam::MULTI_ACK_DEST);
5878
5879	DspinDhccpParam::dspin_set(dspin_send_data,
5880	r_icache_cc_send_updt_tab_idx.read(),
5881	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5882	}
5883	// send flit
5884	p_dspin_out.data = dspin_send_data;
5885	p_dspin_out.write = true;
5886
5887	break;
5888	}
5889	} // end switch CC_SEND FSM
5890
5891	// Receive coherence packets
5892	// It depends on the CC_RECEIVE FSM
5893
5894	switch( r_cc_receive_fsm.read() )
5895	{
5896	/////////////////////
5897	case CC_RECEIVE_IDLE:
5898	{
5899	p_dspin_in.read = false;
5900	break;
5901	}
5902	//////////////////////
5903	case CC_RECEIVE_CLACK:
5904	{
5905	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5906	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5907	p_dspin_in.read = true;
5908	else
5909	p_dspin_in.read = false;
5910	break;
5911	}
5912	///////////////////////////////
5913	case CC_RECEIVE_BRDCAST_HEADER:
5914	{
5915	p_dspin_in.read = true;
5916	break;
5917	}
5918	//////////////////////////////
5919	case CC_RECEIVE_BRDCAST_NLINE:
5920	{
5921	// TODO maybe we need to wait for both only to leave the state, but
5922	// not to actually post a request to an available cache => need a
5923	// flip_flop to check that ?
5924	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5925	p_dspin_in.read = true;
5926	else
5927	p_dspin_in.read = false;
5928	break;
5929	}
5930	/////////////////////////////
5931	case CC_RECEIVE_INVAL_HEADER:
5932	{
5933	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5934	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5935	p_dspin_in.read = true;
5936	else
5937	p_dspin_in.read = false;
5938	break;
5939	}
5940	////////////////////////////
5941	case CC_RECEIVE_INVAL_NLINE:
5942	{
5943	p_dspin_in.read = true;
5944	break;
5945	}
5946	////////////////////////////
5947	case CC_RECEIVE_UPDT_HEADER:
5948	{
5949	if (((r_cc_receive_data_ins.read() == 0) and
5950	not r_cc_receive_dcache_req.read() and
5951	r_cc_receive_updt_fifo_be.empty())
5952	or
5953	((r_cc_receive_data_ins.read() == 1) and
5954	not r_cc_receive_icache_req.read()) and
5955	r_cc_receive_updt_fifo_be.empty())
5956	p_dspin_in.read = true;
5957	else
5958	p_dspin_in.read = false;
5959	break;
5960	}
5961	///////////////////////////
5962	case CC_RECEIVE_UPDT_NLINE:
5963	{
5964	if (((r_cc_receive_data_ins.read() == 0) and
5965	not (r_cc_receive_dcache_req.read()) and
5966	r_cc_receive_updt_fifo_be.empty())
5967	or
5968	((r_cc_receive_data_ins.read() == 1) and
5969	not (r_cc_receive_icache_req.read()) and
5970	r_cc_receive_updt_fifo_be.empty()))
5971	p_dspin_in.read = true;
5972	else
5973	p_dspin_in.read = false;
5974	break;
5975	}
5976	//////////////////////////
5977	case CC_RECEIVE_UPDT_DATA:
5978	{
5979	if (r_cc_receive_updt_fifo_be.wok())
5980	p_dspin_in.read = true;
5981	else
5982	p_dspin_in.read = false;
5983	break;
5984	}
5985	} // end switch CC_RECEIVE FSM
5986
5987	} // end genMoore
5988
5989	}}
5990
5991	// Local Variables:
5992	// tab-width: 4
5993	// c-basic-offset: 4
5994	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5995	// indent-tabs-mode: nil
5996	// End:
5997
5998	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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