Context Navigation

source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 384

Last change on this file since 384 was 384, checked in by joannou, 11 years ago

Bugfix in vci_cc_vcache_wrapper :

Made cache flush states interruptible by coherence request to avoid potential deadlock situations
Fixed the cc_send_nline values sent for a cleanup in cache flush states by adding the set value
Also changed DCACHE_DIRTY_PTE_GET to DCACHE_DIRTY_GET_PTE (display purposes only)

File size: 229.1 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 1
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_GET_PTE",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using namespace soclib::common;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	const int proc_id,
170	const MappingTable &mtd,
171	const IntTab &srcid,
172	const size_t cc_global_id,
173	const size_t itlb_ways,
174	const size_t itlb_sets,
175	const size_t dtlb_ways,
176	const size_t dtlb_sets,
177	const size_t icache_ways,
178	const size_t icache_sets,
179	const size_t icache_words,
180	const size_t dcache_ways,
181	const size_t dcache_sets,
182	const size_t dcache_words,
183	const size_t wbuf_nlines,
184	const size_t wbuf_nwords,
185	const size_t x_width,
186	const size_t y_width,
187	const uint32_t max_frozen_cycles,
188	const uint32_t debug_start_cycle,
189	const bool debug_ok )
190	: soclib::caba::BaseModule(name),
191
192	p_clk("p_clk"),
193	p_resetn("p_resetn"),
194	p_vci("p_vci"),
195	p_dspin_in("p_dspin_in"),
196	p_dspin_out("p_dspin_out"),
197
198	m_cacheability_table( mtd.getCacheabilityTable() ),
199	m_srcid( mtd.indexForId(srcid) ),
200	m_cc_global_id( cc_global_id ),
201	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
202	m_itlb_ways( itlb_ways ),
203	m_itlb_sets( itlb_sets ),
204	m_dtlb_ways( dtlb_ways ),
205	m_dtlb_sets( dtlb_sets ),
206	m_icache_ways( icache_ways ),
207	m_icache_sets( icache_sets ),
208	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
209	m_icache_words( icache_words ),
210	m_dcache_ways( dcache_ways ),
211	m_dcache_sets( dcache_sets ),
212	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
213	m_dcache_words( dcache_words ),
214	m_x_width( x_width ),
215	m_y_width( y_width ),
216	m_proc_id( proc_id ),
217	m_max_frozen_cycles( max_frozen_cycles ),
218	m_paddr_nbits( vci_param::N ),
219	m_debug_start_cycle( debug_start_cycle ),
220	m_debug_ok( debug_ok ),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240	r_icache_miss_clack("r_icache_miss_clack"),
241
242	r_icache_cc_way("r_icache_cc_way"),
243	r_icache_cc_set("r_icache_cc_set"),
244	r_icache_cc_word("r_icache_cc_word"),
245	r_icache_cc_need_write("r_icache_cc_need_write"),
246
247	r_icache_flush_count("r_icache_flush_count"),
248
249	r_icache_miss_req("r_icache_miss_req"),
250	r_icache_unc_req("r_icache_unc_req"),
251
252	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
253	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
254
255	r_icache_cc_send_req("r_icache_cc_send_req"),
256	r_icache_cc_send_type("r_icache_cc_send_type"),
257	r_icache_cc_send_nline("r_icache_cc_send_nline"),
258	r_icache_cc_send_way("r_icache_cc_send_way"),
259	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
260
261	r_dcache_fsm("r_dcache_fsm"),
262	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
263	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
264
265	r_dcache_wbuf_req("r_dcache_wbuf_req"),
266	r_dcache_updt_req("r_dcache_updt_req"),
267	r_dcache_save_vaddr("r_dcache_save_vaddr"),
268	r_dcache_save_wdata("r_dcache_save_wdata"),
269	r_dcache_save_be("r_dcache_save_be"),
270	r_dcache_save_paddr("r_dcache_save_paddr"),
271	r_dcache_save_cacheable("r_dcache_save_cacheable"),
272	r_dcache_save_cache_way("r_dcache_save_cache_way"),
273	r_dcache_save_cache_set("r_dcache_save_cache_set"),
274	r_dcache_save_cache_word("r_dcache_save_cache_word"),
275
276	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
277	r_dcache_dirty_way("r_dcache_dirty_way"),
278	r_dcache_dirty_set("r_dcache_dirty_set"),
279
280	r_dcache_vci_paddr("r_dcache_vci_paddr"),
281	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
282	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
283	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
284	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
285	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
286	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
287	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
290
291	r_dcache_xtn_way("r_dcache_xtn_way"),
292	r_dcache_xtn_set("r_dcache_xtn_set"),
293
294	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
295
296	r_dcache_miss_type("r_dcache_miss_type"),
297	r_dcache_miss_word("r_dcache_miss_word"),
298	r_dcache_miss_way("r_dcache_miss_way"),
299	r_dcache_miss_set("r_dcache_miss_set"),
300	r_dcache_miss_inval("r_dcache_miss_inval"),
301
302	r_dcache_cc_way("r_dcache_cc_way"),
303	r_dcache_cc_set("r_dcache_cc_set"),
304	r_dcache_cc_word("r_dcache_cc_word"),
305	r_dcache_cc_need_write("r_dcache_cc_need_write"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
310
311	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
312	r_dcache_tlb_ins("r_dcache_tlb_ins"),
313	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
314	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
315	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
316	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
317	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
318	r_dcache_tlb_way("r_dcache_tlb_way"),
319	r_dcache_tlb_set("r_dcache_tlb_set"),
320
321	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
322	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
323
324	r_dcache_xtn_req("r_dcache_xtn_req"),
325	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
326
327	r_dcache_cc_send_req("r_dcache_cc_send_req"),
328	r_dcache_cc_send_type("r_dcache_cc_send_type"),
329	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
330	r_dcache_cc_send_way("r_dcache_cc_send_way"),
331	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
332
333	r_vci_cmd_fsm("r_vci_cmd_fsm"),
334	r_vci_cmd_min("r_vci_cmd_min"),
335	r_vci_cmd_max("r_vci_cmd_max"),
336	r_vci_cmd_cpt("r_vci_cmd_cpt"),
337	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
338
339	r_vci_rsp_fsm("r_vci_rsp_fsm"),
340	r_vci_rsp_cpt("r_vci_rsp_cpt"),
341	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
342	r_vci_rsp_data_error("r_vci_rsp_data_error"),
343	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
344	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
345
346	r_cc_send_fsm("r_cc_send_fsm"),
347	r_cc_send_last_client("r_cc_send_last_client"),
348
349	r_cc_receive_fsm("r_cc_receive_fsm"),
350	r_cc_receive_data_ins("r_cc_receive_data_ins"),
351	r_cc_receive_word_idx("r_cc_receive_word_idx"),
352	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
353	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
354	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
355
356	r_cc_receive_icache_req("r_cc_receive_icache_req"),
357	r_cc_receive_icache_type("r_cc_receive_icache_type"),
358	r_cc_receive_icache_way("r_cc_receive_icache_way"),
359	r_cc_receive_icache_set("r_cc_receive_icache_set"),
360	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
361	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
362
363	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
364	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
365	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
366	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
367	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
368	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
369
370	r_iss(this->name(), proc_id),
371	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
372	r_icache("icache", icache_ways, icache_sets, icache_words),
373	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
374	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
375	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
376	{
377	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
378	"Need more PLEN bits.");
379
380	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
381	"Need more TRDID bits.");
382
383	assert( (icache_words == dcache_words) and
384	"icache_words and dcache_words parameters must be equal");
385
386	assert( (itlb_sets == dtlb_sets) and
387	"itlb_sets and dtlb_sets parameters must be etqual");
388
389	assert( (itlb_ways == dtlb_ways) and
390	"itlb_ways and dtlb_ways parameters must be etqual");
391
392	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
393	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
394	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
395	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
396	(uint32_log2(m_icache_words<<2));
397
398	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
399
400	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapper()
424	/////////////////////////////////////
425	{
426	delete [] r_dcache_in_tlb;
427	delete [] r_dcache_contains_ptd;
428	}
429
430	////////////////////////
431	tmpl(void)::print_cpi()
432	////////////////////////
433	{
434	std::cout << name() << " CPI = "
435	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
436	}
437
438	////////////////////////////////////
439	tmpl(void)::print_trace(size_t mode)
440	////////////////////////////////////
441	{
442	// b0 : write buffer trace
443	// b1 : write buffer verbose
444	// b2 : dcache trace
445	// b3 : icache trace
446	// b4 : dtlb trace
447	// b5 : itlb trace
448
449	std::cout << std::dec << "PROC " << name() << std::endl;
450
451	std::cout << " " << m_ireq << std::endl;
452	std::cout << " " << m_irsp << std::endl;
453	std::cout << " " << m_dreq << std::endl;
454	std::cout << " " << m_drsp << std::endl;
455
456	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
457	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
458	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
459	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
460	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
461	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
462	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
463	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
464	std::cout << std::endl;
465
466	if(mode & 0x01)
467	{
468	r_wbuf.printTrace((mode>>1)&1);
469	}
470	if(mode & 0x04)
471	{
472	std::cout << " Data Cache" << std::endl;
473	r_dcache.printTrace();
474	}
475	if(mode & 0x08)
476	{
477	std::cout << " Instruction Cache" << std::endl;
478	r_icache.printTrace();
479	}
480	if(mode & 0x10)
481	{
482	std::cout << " Data TLB" << std::endl;
483	r_dtlb.printTrace();
484	}
485	if(mode & 0x20)
486	{
487	std::cout << " Instruction TLB" << std::endl;
488	r_itlb.printTrace();
489	}
490	}
491
492	//////////////////////////////////////////
493	tmpl(void)::cache_monitor( paddr_t addr )
494	//////////////////////////////////////////
495	{
496	size_t cache_way;
497	size_t cache_set;
498	size_t cache_word;
499	uint32_t cache_rdata;
500	bool cache_hit = r_dcache.read_neutral( addr,
501	&cache_rdata,
502	&cache_way,
503	&cache_set,
504	&cache_word );
505	bool icache_hit = r_icache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	if ( cache_hit != m_debug_previous_hit )
511	{
512	std::cout << "PROC " << name()
513	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
514	<< " for adresse " << std::hex << addr
515	<< " / HIT = " << std::dec << cache_hit << std::endl;
516	m_debug_previous_hit = cache_hit;
517	}
518	if ( icache_hit != m_idebug_previous_hit )
519	{
520	std::cout << "PROC " << name()
521	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
522	<< " for adresse " << std::hex << addr
523	<< " / HIT = " << icache_hit << std::endl;
524	m_idebug_previous_hit = icache_hit;
525	}
526	}
527
528	/*
529	////////////////////////
530	tmpl(void)::print_stats()
531	////////////////////////
532	{
533	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
534	std::cout << name() << std::endl
535	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
536	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
537	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
538	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
539	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
540	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
541	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
542	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
543	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
544	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
545	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
546	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
547	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
548	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
549	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
550	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
551	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
552	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
553	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
555	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
556	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
557	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
558	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
559	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
560	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
561	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
562	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
563	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
564	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
565	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
566	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
567	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
568	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
569	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
570	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
571	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
572	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
573	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
574	}
575
576	////////////////////////
577	tmpl(void)::clear_stats()
578	////////////////////////
579	{
580	m_cpt_dcache_data_read = 0;
581	m_cpt_dcache_data_write = 0;
582	m_cpt_dcache_dir_read = 0;
583	m_cpt_dcache_dir_write = 0;
584	m_cpt_icache_data_read = 0;
585	m_cpt_icache_data_write = 0;
586	m_cpt_icache_dir_read = 0;
587	m_cpt_icache_dir_write = 0;
588
589	m_cpt_frz_cycles = 0;
590	m_cpt_dcache_frz_cycles = 0;
591	m_cpt_total_cycles = 0;
592
593	m_cpt_read = 0;
594	m_cpt_write = 0;
595	m_cpt_data_miss = 0;
596	m_cpt_ins_miss = 0;
597	m_cpt_unc_read = 0;
598	m_cpt_write_cached = 0;
599	m_cpt_ins_read = 0;
600
601	m_cost_write_frz = 0;
602	m_cost_data_miss_frz = 0;
603	m_cost_unc_read_frz = 0;
604	m_cost_ins_miss_frz = 0;
605
606	m_cpt_imiss_transaction = 0;
607	m_cpt_dmiss_transaction = 0;
608	m_cpt_unc_transaction = 0;
609	m_cpt_write_transaction = 0;
610	m_cpt_icache_unc_transaction = 0;
611
612	m_cost_imiss_transaction = 0;
613	m_cost_dmiss_transaction = 0;
614	m_cost_unc_transaction = 0;
615	m_cost_write_transaction = 0;
616	m_cost_icache_unc_transaction = 0;
617	m_length_write_transaction = 0;
618
619	m_cpt_ins_tlb_read = 0;
620	m_cpt_ins_tlb_miss = 0;
621	m_cpt_ins_tlb_update_acc = 0;
622
623	m_cpt_data_tlb_read = 0;
624	m_cpt_data_tlb_miss = 0;
625	m_cpt_data_tlb_update_acc = 0;
626	m_cpt_data_tlb_update_dirty = 0;
627	m_cpt_ins_tlb_hit_dcache = 0;
628	m_cpt_data_tlb_hit_dcache = 0;
629	m_cpt_ins_tlb_occup_cache = 0;
630	m_cpt_data_tlb_occup_cache = 0;
631
632	m_cost_ins_tlb_miss_frz = 0;
633	m_cost_data_tlb_miss_frz = 0;
634	m_cost_ins_tlb_update_acc_frz = 0;
635	m_cost_data_tlb_update_acc_frz = 0;
636	m_cost_data_tlb_update_dirty_frz = 0;
637	m_cost_ins_tlb_occup_cache_frz = 0;
638	m_cost_data_tlb_occup_cache_frz = 0;
639
640	m_cpt_itlbmiss_transaction = 0;
641	m_cpt_itlb_ll_transaction = 0;
642	m_cpt_itlb_sc_transaction = 0;
643	m_cpt_dtlbmiss_transaction = 0;
644	m_cpt_dtlb_ll_transaction = 0;
645	m_cpt_dtlb_sc_transaction = 0;
646	m_cpt_dtlb_ll_dirty_transaction = 0;
647	m_cpt_dtlb_sc_dirty_transaction = 0;
648
649	m_cost_itlbmiss_transaction = 0;
650	m_cost_itlb_ll_transaction = 0;
651	m_cost_itlb_sc_transaction = 0;
652	m_cost_dtlbmiss_transaction = 0;
653	m_cost_dtlb_ll_transaction = 0;
654	m_cost_dtlb_sc_transaction = 0;
655	m_cost_dtlb_ll_dirty_transaction = 0;
656	m_cost_dtlb_sc_dirty_transaction = 0;
657
658	m_cpt_cc_update_data = 0;
659	m_cpt_cc_inval_ins = 0;
660	m_cpt_cc_inval_data = 0;
661	m_cpt_cc_broadcast = 0;
662
663	m_cost_updt_data_frz = 0;
664	m_cost_inval_ins_frz = 0;
665	m_cost_inval_data_frz = 0;
666	m_cost_broadcast_frz = 0;
667
668	m_cpt_cc_cleanup_data = 0;
669	m_cpt_cc_cleanup_ins = 0;
670	}
671
672	*/
673
674	/////////////////////////
675	tmpl(void)::transition()
676	/////////////////////////
677	{
678	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
679	if ( not p_resetn.read() )
680	{
681	r_iss.reset();
682	r_wbuf.reset();
683	r_icache.reset();
684	r_dcache.reset();
685	r_itlb.reset();
686	r_dtlb.reset();
687
688	r_dcache_fsm = DCACHE_IDLE;
689	r_icache_fsm = ICACHE_IDLE;
690	r_vci_cmd_fsm = CMD_IDLE;
691	r_vci_rsp_fsm = RSP_IDLE;
692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
693	r_cc_send_fsm = CC_SEND_IDLE;
694
695	// reset dcache directory extension
696	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
697	{
698	r_dcache_in_tlb[i] = false;
699	r_dcache_contains_ptd[i] = false;
700	}
701
702	// Response FIFOs and cleanup buffer
703	r_vci_rsp_fifo_icache.init();
704	r_vci_rsp_fifo_dcache.init();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CC_SEND FSM
717	r_icache_cc_send_req = false;
718
719	// No pending write in pipeline
720	r_dcache_wbuf_req = false;
721	r_dcache_updt_req = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_cas_req = false;
727	r_dcache_vci_ll_req = false;
728	r_dcache_vci_sc_req = false;
729
730	// No uncacheable write pending
731	r_dcache_pending_unc_write = false;
732
733	// No processor XTN request pending
734	r_dcache_xtn_req = false;
735
736	// No request from DCACHE FSM to CC_SEND FSM
737	r_dcache_cc_send_req = false;
738
739	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
740	r_cc_receive_icache_req = false;
741	r_cc_receive_dcache_req = false;
742
743	// last cc_send client was dcache
744	r_cc_send_last_client = false;
745
746	// No pending cleanup after a replacement
747	r_icache_miss_clack = false;
748	r_dcache_miss_clack = false;
749
750	// No signalisation of a coherence request matching a pending miss
751	r_icache_miss_inval = false;
752	r_dcache_miss_inval = false;
753
754	// No signalisation of errors
755	r_vci_rsp_ins_error = false;
756	r_vci_rsp_data_error = false;
757
758	// Debug variables
759	m_debug_previous_hit = false;
760	m_idebug_previous_hit = false;
761	m_debug_dcache_fsm = false;
762	m_debug_icache_fsm = false;
763
764	// activity counters
765	m_cpt_dcache_data_read = 0;
766	m_cpt_dcache_data_write = 0;
767	m_cpt_dcache_dir_read = 0;
768	m_cpt_dcache_dir_write = 0;
769	m_cpt_icache_data_read = 0;
770	m_cpt_icache_data_write = 0;
771	m_cpt_icache_dir_read = 0;
772	m_cpt_icache_dir_write = 0;
773
774	m_cpt_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776	m_cpt_stop_simulation = 0;
777
778	m_cpt_data_miss = 0;
779	m_cpt_ins_miss = 0;
780	m_cpt_unc_read = 0;
781	m_cpt_write_cached = 0;
782	m_cpt_ins_read = 0;
783
784	m_cost_write_frz = 0;
785	m_cost_data_miss_frz = 0;
786	m_cost_unc_read_frz = 0;
787	m_cost_ins_miss_frz = 0;
788
789	m_cpt_imiss_transaction = 0;
790	m_cpt_dmiss_transaction = 0;
791	m_cpt_unc_transaction = 0;
792	m_cpt_write_transaction = 0;
793	m_cpt_icache_unc_transaction = 0;
794
795	m_cost_imiss_transaction = 0;
796	m_cost_dmiss_transaction = 0;
797	m_cost_unc_transaction = 0;
798	m_cost_write_transaction = 0;
799	m_cost_icache_unc_transaction = 0;
800	m_length_write_transaction = 0;
801
802	m_cpt_ins_tlb_read = 0;
803	m_cpt_ins_tlb_miss = 0;
804	m_cpt_ins_tlb_update_acc = 0;
805
806	m_cpt_data_tlb_read = 0;
807	m_cpt_data_tlb_miss = 0;
808	m_cpt_data_tlb_update_acc = 0;
809	m_cpt_data_tlb_update_dirty = 0;
810	m_cpt_ins_tlb_hit_dcache = 0;
811	m_cpt_data_tlb_hit_dcache = 0;
812	m_cpt_ins_tlb_occup_cache = 0;
813	m_cpt_data_tlb_occup_cache = 0;
814
815	m_cost_ins_tlb_miss_frz = 0;
816	m_cost_data_tlb_miss_frz = 0;
817	m_cost_ins_tlb_update_acc_frz = 0;
818	m_cost_data_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_dirty_frz = 0;
820	m_cost_ins_tlb_occup_cache_frz = 0;
821	m_cost_data_tlb_occup_cache_frz = 0;
822
823	m_cpt_ins_tlb_inval = 0;
824	m_cpt_data_tlb_inval = 0;
825	m_cost_ins_tlb_inval_frz = 0;
826	m_cost_data_tlb_inval_frz = 0;
827
828	m_cpt_cc_broadcast = 0;
829
830	m_cost_updt_data_frz = 0;
831	m_cost_inval_ins_frz = 0;
832	m_cost_inval_data_frz = 0;
833	m_cost_broadcast_frz = 0;
834
835	m_cpt_cc_cleanup_data = 0;
836	m_cpt_cc_cleanup_ins = 0;
837
838	m_cpt_itlbmiss_transaction = 0;
839	m_cpt_itlb_ll_transaction = 0;
840	m_cpt_itlb_sc_transaction = 0;
841	m_cpt_dtlbmiss_transaction = 0;
842	m_cpt_dtlb_ll_transaction = 0;
843	m_cpt_dtlb_sc_transaction = 0;
844	m_cpt_dtlb_ll_dirty_transaction = 0;
845	m_cpt_dtlb_sc_dirty_transaction = 0;
846
847	m_cost_itlbmiss_transaction = 0;
848	m_cost_itlb_ll_transaction = 0;
849	m_cost_itlb_sc_transaction = 0;
850	m_cost_dtlbmiss_transaction = 0;
851	m_cost_dtlb_ll_transaction = 0;
852	m_cost_dtlb_sc_transaction = 0;
853	m_cost_dtlb_ll_dirty_transaction = 0;
854	m_cost_dtlb_sc_dirty_transaction = 0;
855	/*
856	m_cpt_dcache_frz_cycles = 0;
857	m_cpt_read = 0;
858	m_cpt_write = 0;
859	m_cpt_cc_update_data = 0;
860	m_cpt_cc_inval_ins = 0;
861	m_cpt_cc_inval_data = 0;
862	*/
863
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
867	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
868
869	// init the llsc reservation buffer
870	r_dcache_llsc_valid = false;
871
872	return;
873	}
874
875	// Response FIFOs default values
876	bool vci_rsp_fifo_icache_get = false;
877	bool vci_rsp_fifo_icache_put = false;
878	uint32_t vci_rsp_fifo_icache_data = 0;
879
880	bool vci_rsp_fifo_dcache_get = false;
881	bool vci_rsp_fifo_dcache_put = false;
882	uint32_t vci_rsp_fifo_dcache_data = 0;
883
884	// updt fifo
885	bool cc_receive_updt_fifo_get = false;
886	bool cc_receive_updt_fifo_put = false;
887	uint32_t cc_receive_updt_fifo_be = 0;
888	uint32_t cc_receive_updt_fifo_data = 0;
889	bool cc_receive_updt_fifo_eop = false;
890
891	#ifdef INSTRUMENTATION
892	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
893	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
894	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
895	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
896	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
897	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
898	#endif
899
900	m_cpt_total_cycles++;
901
902	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
903	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904
905	/////////////////////////////////////////////////////////////////////
906	// Get data and instruction requests from processor
907	///////////////////////////////////////////////////////////////////////
908
909	r_iss.getRequests(m_ireq, m_dreq);
910
911	////////////////////////////////////////////////////////////////////////////////////
912	// ICACHE_FSM
913	//
914	// 1/ Coherence operations
915	// They are handled as interrupts generated by the CC_RECEIVE FSM.
916	// - There is a coherence request when r_tgt_icache_req is set.
917	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
918	// - There is a cleanup ack request when r_cleanup_icache_req is set.
919	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
920	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
921	// - For both types of requests, actions associated to the pre-empted state
922	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
923	// or CC_CLACK) to execute the requested coherence operation, and returns
924	// to the pre-empted state.
925	//
926	// 2/ Processor requests
927	// They are taken in IDLE state only. In case of cache miss, or uncacheable
928	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
929	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
930	// flip-flops are reset when the transaction starts.
931	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
932	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
933	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
934	// The availability of the missing cache line is signaled by the response fifo,
935	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
936	// and ICACHE_MISS_DIR_UPDT states.
937	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
938	// to wait the response from the RSP FSM, through the response fifo.
939	// The missing instruction is directly returned to processor in this state.
940	//
941	// 3/ TLB miss
942	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
943	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
944	// register, and goes to the ICACHE_TLB_WAIT state.
945	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
946	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
947	// to signal the completion.
948	//
949	// 4/ XTN requests
950	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
951	// using the r_dcache_xtn_req flip-flop.
952	// The request opcode and the address to be invalidated are transmitted
953	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
954	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
955	// is completed.
956	//
957	// 5/ Error Handling
958	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
959	// in a cache miss or uncacheable read VCI transaction. Nothing is written
960	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
961	////////////////////////////////////////////////////////////////////////////////////////
962
963	// default value for m_irsp
964	m_irsp.valid = false;
965	m_irsp.error = false;
966	m_irsp.instruction = 0;
967
968	switch( r_icache_fsm.read() )
969	{
970	/////////////////
971	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
972	// and coherence requests with a fixed priority:
973	// 1/ Coherence requests => ICACHE_CC_CHECK
974	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
975	// 3/ tlb miss => ICACHE_TLB_WAIT
976	// 4/ cacheable read miss => ICACHE_MISS_SELECT
977	// 5/ uncacheable read miss => ICACHE_UNC_REQ
978	{
979	// coherence interrupt
980	if ( r_cc_receive_icache_req.read() )
981	{
982	r_icache_fsm = ICACHE_CC_CHECK;
983	r_icache_fsm_save = r_icache_fsm.read();
984	break;
985	}
986
987	// XTN requests sent by DCACHE FSM
988	// These request are not executed in this IDLE state, because
989	// they require access to icache or itlb, that are already accessed
990	if ( r_dcache_xtn_req.read() )
991	{
992	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
993	{
994	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
995	}
996	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
997	{
998	r_icache_flush_count = 0;
999	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1002	{
1003	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1004	}
1005	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1006	{
1007	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1008	}
1009	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1010	{
1011	if (sizeof(paddr_t) <= 32)
1012	{
1013	assert(r_mmu_word_hi.read() == 0 &&
1014	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1015	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1016	}
1017	else
1018	{
1019	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1020	(paddr_t)r_mmu_word_lo.read();
1021	}
1022	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1023	}
1024	else
1025	{
1026	assert( false and
1027	"undefined XTN request received by ICACHE FSM");
1028	}
1029	break;
1030	} // end if xtn_req
1031
1032	// processor request
1033	if ( m_ireq.valid )
1034	{
1035	bool cacheable;
1036	paddr_t paddr;
1037	bool tlb_hit = false;
1038	pte_info_t tlb_flags;
1039	size_t tlb_way;
1040	size_t tlb_set;
1041	paddr_t tlb_nline;
1042	uint32_t cache_inst = 0;
1043	size_t cache_way;
1044	size_t cache_set;
1045	size_t cache_word;
1046	int cache_state = CACHE_SLOT_STATE_EMPTY;
1047
1048	// We register processor request
1049	r_icache_vaddr_save = m_ireq.addr;
1050
1051	// sytematic itlb access (if activated)
1052	if ( r_mmu_mode.read() & INS_TLB_MASK )
1053	{
1054
1055	#ifdef INSTRUMENTATION
1056	m_cpt_itlb_read++;
1057	#endif
1058	tlb_hit = r_itlb.translate( m_ireq.addr,
1059	&paddr,
1060	&tlb_flags,
1061	&tlb_nline, // unused
1062	&tlb_way, // unused
1063	&tlb_set ); // unused
1064	}
1065	else
1066	{
1067	paddr = (paddr_t)m_ireq.addr;
1068	}
1069
1070	// systematic icache access (if activated)
1071	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1072	{
1073
1074
1075	#ifdef INSTRUMENTATION
1076	m_cpt_icache_data_read++;
1077	m_cpt_icache_dir_read++;
1078	#endif
1079	r_icache.read( paddr,
1080	&cache_inst,
1081	&cache_way,
1082	&cache_set,
1083	&cache_word,
1084	&cache_state );
1085	}
1086
1087	// We compute cacheability and check access rights:
1088	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1089	// and the access rights are defined by the U and X bits in the PTE.
1090	// - If MMU not activated : cacheability is defined by the segment table,
1091	// and there is no access rights checking
1092
1093	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1094	{
1095	// cacheability
1096	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1097	else cacheable = m_cacheability_table[m_ireq.addr];
1098	}
1099	else // itlb activated
1100	{
1101	if ( tlb_hit ) // ITLB hit
1102	{
1103	// cacheability
1104	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1105	else cacheable = tlb_flags.c;
1106
1107	// access rights checking
1108	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1109	{
1110	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1111	r_mmu_ibvar = m_ireq.addr;
1112	m_irsp.valid = true;
1113	m_irsp.error = true;
1114	m_irsp.instruction = 0;
1115	break;
1116	}
1117	else if ( not tlb_flags.x )
1118	{
1119	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1120	r_mmu_ibvar = m_ireq.addr;
1121	m_irsp.valid = true;
1122	m_irsp.error = true;
1123	m_irsp.instruction = 0;
1124	break;
1125	}
1126	}
1127	else // ITLB miss
1128	{
1129
1130	#ifdef INSTRUMENTATION
1131	m_cpt_itlb_miss++;
1132	#endif
1133	r_icache_fsm = ICACHE_TLB_WAIT;
1134	r_icache_tlb_miss_req = true;
1135	break;
1136	}
1137	} // end if itlb activated
1138
1139	// physical address registration
1140	r_icache_vci_paddr = paddr;
1141
1142	// Finally, we send the response to processor, and compute next state
1143	if ( cacheable )
1144	{
1145	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_icache_miss++;
1150	#endif
1151	// we request a VCI transaction
1152	r_icache_fsm = ICACHE_MISS_SELECT;
1153	r_icache_miss_req = true;
1154	}
1155	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1156	{
1157	// stalled until cleanup is acknowledged
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	else // cache hit
1161	{
1162
1163	#ifdef INSTRUMENTATION
1164	m_cpt_ins_read++;
1165	#endif
1166	// return instruction to processor
1167	m_irsp.valid = true;
1168	m_irsp.instruction = cache_inst;
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	}
1172	else // non cacheable read
1173	{
1174	r_icache_unc_req = true;
1175	r_icache_fsm = ICACHE_UNC_WAIT;
1176	}
1177	} // end if m_ireq.valid
1178	break;
1179	}
1180	/////////////////////
1181	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1182	// the itlb is udated by the DCACHE FSM, as well as the
1183	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1184	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1185	// reset the r_icache_tlb_miss_req flip-flop
1186	// external coherence request are accepted in this state.
1187	{
1188	// coherence interrupt
1189	if ( r_cc_receive_icache_req.read() )
1190	{
1191	r_icache_fsm = ICACHE_CC_CHECK;
1192	r_icache_fsm_save = r_icache_fsm.read();
1193	break;
1194	}
1195
1196	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1197
1198	// DCACHE FSM signals response by reseting the request flip-flop
1199	if ( not r_icache_tlb_miss_req.read() )
1200	{
1201	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1202	{
1203	r_icache_tlb_rsp_error = false;
1204	m_irsp.error = true;
1205	m_irsp.valid = true;
1206	r_icache_fsm = ICACHE_IDLE;
1207	}
1208	else // tlb updated : return to IDLE state
1209	{
1210	r_icache_fsm = ICACHE_IDLE;
1211	}
1212	}
1213	break;
1214	}
1215	//////////////////////////
1216	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1217	{
1218	r_itlb.flush();
1219	r_dcache_xtn_req = false;
1220	r_icache_fsm = ICACHE_IDLE;
1221	break;
1222	}
1223	////////////////////////////
1224	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1225	// r_icache_flush_count as a slot counter,
1226	// looping in this state until all slots are visited.
1227	// It can require two cycles per slot:
1228	// We test here the slot state, and make the actual inval
1229	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1230	// A cleanup request is generated for each valid line
1231	{
1232	// coherence request (from CC_RECEIVE FSM)
1233	if ( r_cc_receive_icache_req.read() )
1234	{
1235	r_icache_fsm = ICACHE_CC_CHECK;
1236	r_icache_fsm_save = r_icache_fsm.read();
1237	break;
1238	}
1239
1240	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1241	{
1242	int state;
1243	uint32_t tag;
1244	size_t way = r_icache_flush_count.read()/m_icache_sets;
1245	size_t set = r_icache_flush_count.read()%m_icache_sets;
1246
1247	#ifdef INSTRUMENTATION
1248	m_cpt_icache_dir_read++;
1249	#endif
1250	r_icache.read_dir( way,
1251	set,
1252	&tag,
1253	&state );
1254
1255	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1256	{
1257	// request cleanup
1258	r_icache_cc_send_req = true;
1259	r_icache_cc_send_nline = tag * m_icache_sets + set;
1260	r_icache_cc_send_way = way;
1261	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1262
1263	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1264	r_icache_miss_way = way;
1265	r_icache_miss_set = set;
1266	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1267	}
1268	else if ( r_icache_flush_count.read() ==
1269	(m_icache_sets*m_icache_ways - 1) ) // last slot
1270	{
1271	r_dcache_xtn_req = false;
1272	m_drsp.valid = true;
1273	r_icache_fsm = ICACHE_IDLE;
1274	}
1275
1276	// saturation counter, to have the same last slot condition
1277	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1278	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1279	{
1280	r_icache_flush_count = r_icache_flush_count.read() + 1;
1281	}
1282	}
1283	break;
1284	}
1285	///////////////////////////////
1286	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1287	{
1288	size_t way = r_icache_miss_way.read();
1289	size_t set = r_icache_miss_set.read();
1290
1291	#ifdef INSTRUMENTATION
1292	m_cpt_icache_dir_write++;
1293	#endif
1294
1295	r_icache.write_dir( way,
1296	set,
1297	CACHE_SLOT_STATE_ZOMBI );
1298
1299	if ( r_icache_flush_count.read() ==
1300	(m_icache_sets*m_icache_ways - 1) ) // last slot
1301	{
1302	r_dcache_xtn_req = false;
1303	m_drsp.valid = true;
1304	r_icache_fsm = ICACHE_IDLE;
1305	}
1306	else
1307	{
1308	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1309	}
1310	break;
1311	}
1312
1313	//////////////////////////
1314	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1315	// stored in the r_dcache_save_wdata register
1316	{
1317	r_itlb.inval(r_dcache_save_wdata.read());
1318	r_dcache_xtn_req = false;
1319	r_icache_fsm = ICACHE_IDLE;
1320	break;
1321	}
1322	///////////////////////////////
1323	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1324	// requires 3 cycles (in case of hit on itlb and icache).
1325	// In this state, access TLB to translate virtual address
1326	// stored in the r_dcache_save_wdata register.
1327	{
1328	paddr_t paddr;
1329	bool hit;
1330
1331	// read physical address in TLB when MMU activated
1332	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1333	{
1334
1335	#ifdef INSTRUMENTATION
1336	m_cpt_itlb_read++;
1337	#endif
1338	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1339	&paddr);
1340	}
1341	else // itlb not activated
1342	{
1343	paddr = (paddr_t)r_dcache_save_wdata.read();
1344	hit = true;
1345	}
1346
1347	if ( hit ) // continue the selective inval process
1348	{
1349	r_icache_vci_paddr = paddr;
1350	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1351	}
1352	else // miss : send a request to DCACHE FSM
1353	{
1354
1355	#ifdef INSTRUMENTATION
1356	m_cpt_itlb_miss++;
1357	#endif
1358	r_icache_tlb_miss_req = true;
1359	r_icache_vaddr_save = r_dcache_save_wdata.read();
1360	r_icache_fsm = ICACHE_TLB_WAIT;
1361	}
1362	break;
1363	}
1364	///////////////////////////////
1365	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1366	// require 2 cycles. In this state, we read directory
1367	// with address stored in r_icache_vci_paddr register.
1368	{
1369	int state;
1370	size_t way;
1371	size_t set;
1372	size_t word;
1373
1374	#ifdef INSTRUMENTATION
1375	m_cpt_icache_dir_read++;
1376	#endif
1377	r_icache.read_dir(r_icache_vci_paddr.read(),
1378	&state,
1379	&way,
1380	&set,
1381	&word);
1382
1383	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1384	{
1385	r_icache_miss_way = way;
1386	r_icache_miss_set = set;
1387	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1388	}
1389	else // miss : acknowlege the XTN request and return
1390	{
1391	r_dcache_xtn_req = false;
1392	r_icache_fsm = ICACHE_IDLE;
1393	}
1394	break;
1395	}
1396	///////////////////////////////
1397	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1398	{
1399	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1400	{
1401
1402	#ifdef INSTRUMENTATION
1403	m_cpt_icache_dir_write++;
1404	#endif
1405	r_icache.write_dir( r_icache_miss_way.read(),
1406	r_icache_miss_set.read(),
1407	CACHE_SLOT_STATE_ZOMBI );
1408
1409	// request cleanup
1410	r_icache_cc_send_req = true;
1411	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1412	r_icache_cc_send_way = r_icache_miss_way.read();
1413	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1414
1415	// acknowledge the XTN request and return
1416	r_dcache_xtn_req = false;
1417	r_icache_fsm = ICACHE_IDLE;
1418	}
1419	break;
1420	}
1421	////////////////////////
1422	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1423	// if previous cleanup has been sent.
1424	// Waiting in this state if no slot available.
1425	// Set the r_icache_cleanup_req flip-flop
1426	// and the r_icache_miss_clack flip-flop,
1427	// when a cleanup is required
1428	{
1429	if (m_ireq.valid) m_cost_ins_miss_frz++;
1430
1431	// coherence interrupt
1432	if ( r_cc_receive_icache_req.read() )
1433	{
1434	r_icache_fsm = ICACHE_CC_CHECK;
1435	r_icache_fsm_save = r_icache_fsm.read();
1436	break;
1437	}
1438
1439	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1440	{
1441	bool found;
1442	bool cleanup;
1443	size_t way;
1444	size_t set;
1445	paddr_t victim;
1446
1447	#ifdef INSTRUMENTATION
1448	m_cpt_icache_dir_read++;
1449	#endif
1450	r_icache.read_select(r_icache_vci_paddr.read(),
1451	&victim,
1452	&way,
1453	&set,
1454	&found,
1455	&cleanup );
1456	if ( found )
1457	{
1458	r_icache_miss_way = way;
1459	r_icache_miss_set = set;
1460
1461	if ( cleanup )
1462	{
1463	r_icache_fsm = ICACHE_MISS_CLEAN;
1464	r_icache_miss_clack = true;
1465	// request cleanup
1466	r_icache_cc_send_req = true;
1467	r_icache_cc_send_nline = victim;
1468	r_icache_cc_send_way = way;
1469	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1470	}
1471	else
1472	{
1473	r_icache_fsm = ICACHE_MISS_WAIT;
1474	}
1475
1476	#if DEBUG_ICACHE
1477	if ( m_debug_dcache_fsm )
1478	{
1479	std::cout << " <PROC " << name()
1480	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1481	<< " / WAY = " << way
1482	<< " / SET = " << set;
1483	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1484	else std::cout << std::endl;
1485	}
1486	#endif
1487	}
1488	}
1489	break;
1490	}
1491	///////////////////////
1492	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1493	{
1494	if (m_ireq.valid) m_cost_ins_miss_frz++;
1495
1496	#ifdef INSTRUMENTATION
1497	m_cpt_icache_dir_write++;
1498	#endif
1499	r_icache.write_dir( r_icache_miss_way.read(),
1500	r_icache_miss_set.read(),
1501	CACHE_SLOT_STATE_ZOMBI);
1502	#if DEBUG_ICACHE
1503	if ( m_debug_dcache_fsm )
1504	{
1505	std::cout << " <PROC " << name()
1506	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1507	<< " / WAY = " << r_icache_miss_way.read()
1508	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1509	}
1510	#endif
1511
1512	r_icache_fsm = ICACHE_MISS_WAIT;
1513	break;
1514	}
1515	//////////////////////
1516	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1517	{
1518	if (m_ireq.valid) m_cost_ins_miss_frz++;
1519
1520	// coherence interrupt
1521	if ( r_cc_receive_icache_req.read() )
1522	{
1523	r_icache_fsm = ICACHE_CC_CHECK;
1524	r_icache_fsm_save = r_icache_fsm.read();
1525	break;
1526	}
1527
1528	if ( r_vci_rsp_ins_error.read() ) // bus error
1529	{
1530	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1531	r_mmu_ibvar = r_icache_vaddr_save.read();
1532	m_irsp.valid = true;
1533	m_irsp.error = true;
1534	r_vci_rsp_ins_error = false;
1535	r_icache_fsm = ICACHE_IDLE;
1536	}
1537	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1538	{
1539	r_icache_miss_word = 0;
1540	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1541	}
1542	break;
1543	}
1544	///////////////////////////
1545	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1546	{
1547	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1548
1549	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1550	{
1551
1552	#ifdef INSTRUMENTATION
1553	m_cpt_icache_data_write++;
1554	#endif
1555	r_icache.write( r_icache_miss_way.read(),
1556	r_icache_miss_set.read(),
1557	r_icache_miss_word.read(),
1558	r_vci_rsp_fifo_icache.read() );
1559	#if DEBUG_ICACHE
1560	if ( m_debug_icache_fsm )
1561	{
1562	std::cout << " <PROC " << name()
1563	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1564	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1565	<< " WAY = " << r_icache_miss_way.read()
1566	<< " SET = " << r_icache_miss_set.read()
1567	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1568	}
1569	#endif
1570	vci_rsp_fifo_icache_get = true;
1571	r_icache_miss_word = r_icache_miss_word.read() + 1;
1572
1573	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1574	{
1575	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1576	}
1577	}
1578	break;
1579	}
1580	//////////////////////////
1581	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1582	// and the cleanup ack has not been received,
1583	// as indicated by r_icache_miss_clack.
1584	// - If no matching coherence request (r_icache_miss_inval)
1585	// switch directory slot to VALID state.
1586	// - If matching coherence request, switch directory slot
1587	// to ZOMBI state, and send a cleanup request.
1588	{
1589	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1590
1591	// coherence interrupt
1592	if ( r_cc_receive_icache_req.read() )
1593	{
1594	r_icache_fsm = ICACHE_CC_CHECK;
1595	r_icache_fsm_save = r_icache_fsm.read();
1596	break;
1597	}
1598
1599	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1600	{
1601	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1602	{
1603	if ( not r_icache_cc_send_req.read() )
1604	{
1605	r_icache_miss_inval = false;
1606	// request cleanup
1607	r_icache_cc_send_req = true;
1608	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1609	r_icache_cc_send_way = r_icache_miss_way.read();
1610	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1611
1612	#ifdef INSTRUMENTATION
1613	m_cpt_icache_dir_write++;
1614	#endif
1615	r_icache.write_dir( r_icache_vci_paddr.read(),
1616	r_icache_miss_way.read(),
1617	r_icache_miss_set.read(),
1618	CACHE_SLOT_STATE_ZOMBI );
1619	#if DEBUG_ICACHE
1620	if ( m_debug_icache_fsm )
1621	{
1622	std::cout << " <PROC " << name()
1623	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1624	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1625	<< " WAY = " << std::dec << r_icache_miss_way.read()
1626	<< " SET = " << r_icache_miss_set.read() << std::endl;
1627	}
1628	#endif
1629	}
1630	else
1631	break;
1632	}
1633	else // Switch slot to VALID state
1634	{
1635
1636	#ifdef INSTRUMENTATION
1637	m_cpt_icache_dir_write++;
1638	#endif
1639	r_icache.write_dir( r_icache_vci_paddr.read(),
1640	r_icache_miss_way.read(),
1641	r_icache_miss_set.read(),
1642	CACHE_SLOT_STATE_VALID );
1643	#if DEBUG_ICACHE
1644	if ( m_debug_icache_fsm )
1645	{
1646	std::cout << " <PROC " << name()
1647	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1648	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1649	<< " WAY = " << std::dec << r_icache_miss_way.read()
1650	<< " SET = " << r_icache_miss_set.read() << std::endl;
1651	}
1652	#endif
1653	}
1654
1655	r_icache_fsm = ICACHE_IDLE;
1656	}
1657	break;
1658	}
1659	////////////////////
1660	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1661	{
1662	// coherence interrupt
1663	if ( r_cc_receive_icache_req.read() )
1664	{
1665	r_icache_fsm = ICACHE_CC_CHECK;
1666	r_icache_fsm_save = r_icache_fsm.read();
1667	break;
1668	}
1669
1670	if ( r_vci_rsp_ins_error.read() ) // bus error
1671	{
1672	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1673	r_mmu_ibvar = m_ireq.addr;
1674	r_vci_rsp_ins_error = false;
1675	m_irsp.valid = true;
1676	m_irsp.error = true;
1677	r_icache_fsm = ICACHE_IDLE;
1678	}
1679	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1680	{
1681	vci_rsp_fifo_icache_get = true;
1682	r_icache_fsm = ICACHE_IDLE;
1683	if ( m_ireq.valid and
1684	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1685	{
1686	m_irsp.valid = true;
1687	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1688	}
1689	}
1690	break;
1691	}
1692	/////////////////////
1693	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1694	// handling coherence requests.
1695	// if there is a matching pending miss, it is
1696	// signaled in the r_icache_miss_inval flip-flop.
1697	// The return state is defined in r_icache_fsm_save.
1698	{
1699	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1700	paddr_t mask = ~((m_icache_words<<2)-1);
1701
1702	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1703	// We switch the directory slot to EMPTY state
1704	// and reset r_icache_miss_clack if the cleanup ack
1705	// is matching a pending miss
1706	{
1707
1708	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1709
1710	#ifdef INSTRUMENTATION
1711	m_cpt_icache_dir_write++;
1712	#endif
1713	r_icache.write_dir( 0,
1714	r_cc_receive_icache_way.read(),
1715	r_cc_receive_icache_set.read(),
1716	CACHE_SLOT_STATE_EMPTY);
1717
1718	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1719	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1720	r_icache_miss_clack = false;
1721
1722	r_icache_fsm = r_icache_fsm_save.read() ;
1723	r_cc_receive_icache_req = false;
1724
1725	#if DEBUG_ICACHE
1726	if ( m_debug_icache_fsm )
1727	{
1728	std::cout << " <PROC " << name()
1729	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1730	<< " set = " << r_cc_receive_icache_set.read()
1731	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1732	}
1733	#endif
1734	}
1735	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1736	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1737	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1738	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1739	{
1740	// signaling the matching
1741	r_icache_miss_inval = true;
1742
1743	// in case of update, go to CC_UPDT
1744	// JUST TO POP THE FIFO
1745	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1746	{
1747	r_icache_fsm = ICACHE_CC_UPDT;
1748	r_icache_cc_word = r_cc_receive_word_idx.read();
1749	// just pop the fifo , don't write in icache
1750	r_icache_cc_need_write = false;
1751	}
1752	// the request is dealt with
1753	else
1754	{
1755	r_cc_receive_icache_req = false;
1756	r_icache_fsm = r_icache_fsm_save.read();
1757	}
1758	#if DEBUG_ICACHE
1759	if ( m_debug_icache_fsm )
1760	{
1761	std::cout << " <PROC " << name()
1762	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1763	<< " PADDR = " << std::hex << paddr << std::endl;
1764	}
1765	#endif
1766	}
1767	else // no match
1768	{
1769	int state;
1770	size_t way;
1771	size_t set;
1772	size_t word;
1773
1774	#ifdef INSTRUMENTATION
1775	m_cpt_icache_dir_read++;
1776	#endif
1777	r_icache.read_dir(paddr,
1778	&state,
1779	&way,
1780	&set,
1781	&word);
1782
1783	r_icache_cc_way = way;
1784	r_icache_cc_set = set;
1785
1786	if ( state == CACHE_SLOT_STATE_VALID) // hit
1787	{
1788	// need to update the cache state
1789	r_icache_cc_need_write = true;
1790	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1791	{
1792	r_icache_fsm = ICACHE_CC_UPDT;
1793	r_icache_cc_word = r_cc_receive_word_idx.read();
1794	}
1795	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1796	{
1797	r_icache_fsm = ICACHE_CC_INVAL;
1798	}
1799	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1800	{
1801	r_icache_fsm = ICACHE_CC_BROADCAST;
1802	}
1803	}
1804	else // miss
1805	{
1806	// multicast acknowledgement required in case of update
1807	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1808	{
1809	r_icache_fsm = ICACHE_CC_UPDT;
1810	r_icache_cc_word = r_cc_receive_word_idx.read();
1811	// just pop the fifo , don't write in icache
1812	r_icache_cc_need_write = false;
1813	}
1814	else // No response needed
1815	{
1816	r_cc_receive_icache_req = false;
1817	r_icache_fsm = r_icache_fsm_save.read();
1818	}
1819	}
1820	}
1821	break;
1822	}
1823	/////////////////////
1824	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1825	{
1826
1827	#if DEBUG_ICACHE
1828	if ( m_debug_icache_fsm )
1829	{
1830	std::cout << " <PROC " << name()
1831	<< " ICACHE_CC_INVAL> slot returns to empty state"
1832	<< " set = " << r_icache_cc_set.read()
1833	<< " / way = " << r_icache_cc_way.read() << std::endl;
1834	}
1835	#endif
1836
1837	#ifdef INSTRUMENTATION
1838	m_cpt_icache_dir_read++;
1839	#endif
1840	if (r_icache_cc_need_write.read())
1841	{
1842	r_icache.write_dir( 0,
1843	r_icache_cc_way.read(),
1844	r_icache_cc_set.read(),
1845	CACHE_SLOT_STATE_EMPTY );
1846	// no need to write in the cache anymore
1847	r_icache_cc_need_write = false;
1848	}
1849
1850	// multicast acknowledgement
1851	// send a request to cc_send_fsm
1852	if(not r_icache_cc_send_req.read()) // cc_send is available
1853	{
1854	// coherence request completed
1855	r_cc_receive_icache_req = false;
1856	// request multicast acknowledgement
1857	r_icache_cc_send_req = true;
1858	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1859	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1860	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1861
1862	r_icache_fsm = r_icache_fsm_save.read();
1863	}
1864	//else wait for previous cc_send request to be sent
1865	break;
1866	}
1867	////////////////////
1868	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1869	{
1870
1871	#if DEBUG_ICACHE
1872	if ( m_debug_icache_fsm )
1873	{
1874	std::cout << " <PROC " << name()
1875	<< " ICACHE_CC_UPDT> Write one word "
1876	<< " set = " << r_icache_cc_set.read()
1877	<< " / way = " << r_icache_cc_way.read()
1878	<< " / word = " << r_icache_cc_word.read() << std::endl;
1879	}
1880	#endif
1881
1882	#ifdef INSTRUMENTATION
1883	m_cpt_icache_data_write++;
1884	#endif
1885	size_t word = r_icache_cc_word.read();
1886	size_t way = r_icache_cc_way.read();
1887	size_t set = r_icache_cc_set.read();
1888
1889	if (r_cc_receive_updt_fifo_be.rok())
1890	{
1891	if (r_icache_cc_need_write.read())
1892	{
1893	r_icache.write( way,
1894	set,
1895	word,
1896	r_cc_receive_updt_fifo_data.read(),
1897	r_cc_receive_updt_fifo_be.read() );
1898
1899	r_icache_cc_word = word+1;
1900	}
1901	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1902	{
1903	// no need to write in the cache anymore
1904	r_icache_cc_need_write = false;
1905	// wait to send a request to cc_send_fsm
1906	if(not r_icache_cc_send_req.read()) // cc_send is available
1907	{
1908	//consume last flit
1909	cc_receive_updt_fifo_get = true;
1910	// coherence request completed
1911	r_cc_receive_icache_req = false;
1912	// request multicast acknowledgement
1913	r_icache_cc_send_req = true;
1914	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1915	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1916	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1917
1918	r_icache_fsm = r_icache_fsm_save.read();
1919	}
1920	}
1921	else
1922	{
1923	//consume fifo if not eop
1924	cc_receive_updt_fifo_get = true;
1925	}
1926	}
1927	break;
1928	}
1929	/////////////////////////
1930	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1931	// and request a cleanup
1932	{
1933
1934	#if DEBUG_ICACHE
1935	if ( m_debug_icache_fsm )
1936	{
1937	std::cout << " <PROC " << name()
1938	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1939	<< " set = " << r_icache_cc_set.read()
1940	<< " / way = " << r_icache_cc_way.read() << std::endl;
1941	}
1942	#endif
1943
1944	#ifdef INSTRUMENTATION
1945	m_cpt_icache_dir_write++;
1946	#endif
1947	if (r_icache_cc_need_write.read())
1948	{
1949	r_icache.write_dir( r_icache_cc_way.read(),
1950	r_icache_cc_set.read(),
1951	CACHE_SLOT_STATE_ZOMBI );
1952	// no need to write in the cache anymore
1953	r_icache_cc_need_write = false;
1954	}
1955
1956	// cleanup
1957	// send a request to cc_send_fsm
1958	if(not r_icache_cc_send_req.read()) // cc_send is available
1959	{
1960	// coherence request completed
1961	r_cc_receive_icache_req = false;
1962	// request cleanup
1963	r_icache_cc_send_req = true;
1964	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1965	r_icache_cc_send_way = r_icache_cc_way.read();
1966	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1967
1968	r_icache_fsm = r_icache_fsm_save.read();
1969	}
1970	//else wait for previous cc_send request to be sent
1971	break;
1972	}
1973	} // end switch r_icache_fsm
1974
1975	////////////////////////////////////////////////////////////////////////////////////
1976	// DCACHE FSM
1977	//
1978	// 1/ Coherence operations
1979	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1980	// - There is a coherence request when r_tgt_dcache_req is set.
1981	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1982	// and SC_WAIT states.
1983	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1984	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1985	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1986	// - For both types of requests, actions associated to the pre-empted state
1987	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1988	// or CC_CLACK) to execute the requested coherence operation, and returns
1989	// to the pre-empted state.
1990	//
1991	// 2/ TLB miss
1992	// The page tables are generally cacheable.
1993	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1994	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1995	// this sub-fsm implement the table-walk...
1996	//
1997	// 3/ processor requests
1998	// Processor requests are taken in IDLE state only.
1999	// The IDLE state implements a two stages pipe-line to handle write bursts:
2000	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2001	// - The registration in wbuf and the dcache update is done in stage P1
2002	// (if the processor request is a write).
2003	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2004	// the operations that must be done in P1 stage, and the access type
2005	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2006	// READ requests are delayed if a cache update is requested.
2007	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2008	// that is done (before handling the processor request) by a dedicated sub-fsm.
2009	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2010	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2011	//
2012	// 4/ Atomic instructions LL/SC
2013	// The LL/SC address are non cacheable (systematic access to memory).
2014	// The llsc buffer contains a registration for an active LL/SC operation
2015	// (with an address, a registration key, an aging counter and a valid bit).
2016	// - LL requests from the processor are transmitted as a one flit VCI command
2017	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2018	// be 8 as the response is 2 flits long (data and registration key)
2019	// - SC requests from the processor are systematically transmitted to the
2020	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2021	// as PKTID value). The first flit contains the registration key, the second
2022	// flit contains the data to write in case of success.
2023	// The cache is not updated, as this is done in case of success by the
2024	// coherence transaction.
2025	//
2026	// 5/ Non cacheable access:
2027	// This component implement a strong order between non cacheable access
2028	// (read or write) : A new non cacheable VCI transaction starts only when
2029	// the previous non cacheable transaction is completed. Both cacheable and
2030	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2031	// a non cacheable write transaction posted in the write buffer by setting the
2032	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2033	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2034	// pending non cacheable write transaction completes).
2035	//
2036	// 6/ Error handling:
2037	// When the MMU is not activated, Read Bus Errors are synchronous events,
2038	// but Write Bus Errors are asynchronous events (processor is not frozen).
2039	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2040	// r_vci_rsp_data_error flip-flop, without writing any data in the
2041	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2042	// by the DCACHE FSM.
2043	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2044	// the asynchronous error using the setWriteBerr() method.
2045	// When the MMU is activated bus error are rare events, as the MMU
2046	// checks the physical address before the VCI transaction starts.
2047	////////////////////////////////////////////////////////////////////////////////////////
2048
2049	// default value for m_drsp
2050	m_drsp.valid = false;
2051	m_drsp.error = false;
2052	m_drsp.rdata = 0;
2053
2054	switch ( r_dcache_fsm.read() )
2055	{
2056	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2057	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2058	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2059	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2060	// 4) XTN request (processor) => DCACHE_XTN_*
2061	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2062	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2063	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2064	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2065	// 9) LL access (processor) => DCACHE_LL_WAIT
2066	// 10) SC access (processor) => DCACHE_SC_WAIT
2067	//
2068	// There is a fixed priority to handle requests to DCACHE:
2069	// 1/ the ITLB/DTLB invalidate requests
2070	// 2/ the coherence requests,
2071	// 3/ the processor requests (including DTLB miss),
2072	// 4/ the ITLB miss requests,
2073	// The address space processor request are handled as follows:
2074	// - WRITE request is blocked if the Dirty bit mus be set.
2075	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2076	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2077	// - READ request generate a simultaneouss access to DCACHE.DATA
2078	// and DCACHE.DIR, but is delayed if DCACHE update required.
2079	//
2080	// There is 4 configurations defining the access type to
2081	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2082	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2083	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2084	// 0 / 0 / NOP / NOP / NOP /
2085	// 0 / 1 / NOP / NOP / WRITE /
2086	// 1 / 0 / READ / READ / NOP /
2087	// 1 / 1 / READ / READ / WRITE /
2088	// Those two registers are set at each cycle from the 3 signals
2089	// updt_request, wbuf_request, wbuf_write_miss.
2090	{
2091	paddr_t paddr; // physical address
2092	pte_info_t tlb_flags;
2093	size_t tlb_way;
2094	size_t tlb_set;
2095	paddr_t tlb_nline;
2096	size_t cache_way;
2097	size_t cache_set;
2098	size_t cache_word;
2099	uint32_t cache_rdata = 0;
2100	bool tlb_hit = false;
2101	int cache_state = CACHE_SLOT_STATE_EMPTY;
2102
2103	bool tlb_inval_required = false; // request TLB inval after cache update
2104	bool wbuf_write_miss = false; // miss a WBUF write request
2105	bool updt_request = false; // request DCACHE update in P1 stage
2106	bool wbuf_request = false; // request WBUF write in P1 stage
2107
2108	// physical address computation : systematic DTLB access if activated)
2109	if ( m_dreq.valid )
2110	{
2111	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2112	{
2113	tlb_hit = r_dtlb.translate( m_dreq.addr,
2114	&paddr,
2115	&tlb_flags,
2116	&tlb_nline,
2117	&tlb_way,
2118	&tlb_set );
2119	#ifdef INSTRUMENTATION
2120	m_cpt_dtlb_read++;
2121	#endif
2122	}
2123	else // identity mapping
2124	{
2125	paddr = (paddr_t)m_dreq.addr;
2126	}
2127	} // end physical address computation
2128
2129	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2130	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2131	{
2132	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2133	{
2134	r_dcache.read_dir( paddr,
2135	&cache_state,
2136	&cache_way,
2137	&cache_set,
2138	&cache_word );
2139
2140	r_dcache.write( r_dcache_save_cache_way.read(),
2141	r_dcache_save_cache_set.read(),
2142	r_dcache_save_cache_word.read(),
2143	r_dcache_save_wdata.read(),
2144	r_dcache_save_be.read() );
2145	#ifdef INSTRUMENTATION
2146	m_cpt_dcache_dir_read++;
2147	m_cpt_dcache_data_write++;
2148	#endif
2149	}
2150	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2151	{
2152	r_dcache.read( paddr,
2153	&cache_rdata,
2154	&cache_way,
2155	&cache_set,
2156	&cache_word,
2157	&cache_state );
2158
2159	#ifdef INSTRUMENTATION
2160	m_cpt_dcache_dir_read++;
2161	m_cpt_dcache_data_read++;
2162	#endif
2163	}
2164	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2165	{
2166	r_dcache.write( r_dcache_save_cache_way.read(),
2167	r_dcache_save_cache_set.read(),
2168	r_dcache_save_cache_word.read(),
2169	r_dcache_save_wdata.read(),
2170	r_dcache_save_be.read() );
2171	#ifdef INSTRUMENTATION
2172	m_cpt_dcache_data_write++;
2173	#endif
2174	}
2175	} // end dcache access
2176
2177	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2178	if ( r_dcache_updt_req.read() )
2179	{
2180	size_t way = r_dcache_save_cache_way.read();
2181	size_t set = r_dcache_save_cache_set.read();
2182
2183	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2184	{
2185	tlb_inval_required = true;
2186	r_dcache_tlb_inval_set = 0;
2187	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2188	(uint32_log2(m_dcache_words<<2));
2189	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2190	}
2191	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2192	{
2193	r_itlb.reset();
2194	r_dtlb.reset();
2195	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2196	}
2197
2198	#if DEBUG_DCACHE
2199	if ( m_debug_dcache_fsm )
2200	{
2201	std::cout << " <PROC " << name()
2202	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2203	<< " / WAY = " << r_dcache_save_cache_way.read()
2204	<< " / SET = " << r_dcache_save_cache_set.read()
2205	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2206	<< " / DATA = " << r_dcache_save_wdata.read()
2207	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2208	}
2209	#endif
2210	} // end test TLB inval
2211
2212	// Try WBUF update in P1 stage
2213	// Miss if the write request is non cacheable, and there is a pending
2214	// non cacheable write, or if the write buffer is full.
2215	if ( r_dcache_wbuf_req.read() )
2216	{
2217	// miss if write not cacheable, and previous non cacheable write registered
2218	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2219	{
2220	wbuf_write_miss = true;
2221	}
2222	else // try a registration into write buffer
2223	{
2224	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2225	r_dcache_save_be.read(),
2226	r_dcache_save_wdata.read(),
2227	r_dcache_save_cacheable.read() );
2228	#ifdef INSTRUMENTATION
2229	m_cpt_wbuf_write++;
2230	#endif
2231	if ( not wok ) // miss if write buffer full
2232	{
2233	wbuf_write_miss = true;
2234	}
2235	else // update the write_buffer state extension
2236	{
2237	if(not r_dcache_pending_unc_write.read())
2238	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2239	}
2240	}
2241	} // end WBUF update
2242
2243	// Computing the response to processor,
2244	// and the next value for r_dcache_fsm
2245
2246	// itlb/dtlb invalidation self-request
2247	if ( tlb_inval_required )
2248	{
2249	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2250	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2251	}
2252
2253	// coherence request (from CC_RECEIVE FSM)
2254	else if ( r_cc_receive_dcache_req.read() )
2255	{
2256	r_dcache_fsm = DCACHE_CC_CHECK;
2257	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2258	}
2259
2260	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2261	// we don't take the processor request, and registers
2262	// are frozen in case of wbuf_write_miss
2263	else if ( m_dreq.valid and not wbuf_write_miss )
2264	{
2265	// register processor request and DCACHE response
2266	r_dcache_save_vaddr = m_dreq.addr;
2267	r_dcache_save_be = m_dreq.be;
2268	r_dcache_save_wdata = m_dreq.wdata;
2269	r_dcache_save_paddr = paddr;
2270	r_dcache_save_cache_way = cache_way;
2271	r_dcache_save_cache_set = cache_set;
2272	r_dcache_save_cache_word = cache_word;
2273
2274	// READ XTN requests from processor
2275	// They are executed in this DCACHE_IDLE state.
2276	// The processor must not be in user mode
2277	if (m_dreq.type == iss_t::XTN_READ)
2278	{
2279	int xtn_opcode = (int)m_dreq.addr/4;
2280
2281	// checking processor mode:
2282	if (m_dreq.mode == iss_t::MODE_USER)
2283	{
2284	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2285	r_mmu_dbvar = m_dreq.addr;
2286	m_drsp.valid = true;
2287	m_drsp.error = true;
2288	m_drsp.rdata = 0;
2289	r_dcache_fsm = DCACHE_IDLE;
2290	}
2291	else
2292	{
2293	switch( xtn_opcode )
2294	{
2295	case iss_t::XTN_INS_ERROR_TYPE:
2296	m_drsp.rdata = r_mmu_ietr.read();
2297	m_drsp.valid = true;
2298	m_drsp.error = false;
2299	break;
2300
2301	case iss_t::XTN_DATA_ERROR_TYPE:
2302	m_drsp.rdata = r_mmu_detr.read();
2303	m_drsp.valid = true;
2304	m_drsp.error = false;
2305	break;
2306
2307	case iss_t::XTN_INS_BAD_VADDR:
2308	m_drsp.rdata = r_mmu_ibvar.read();
2309	m_drsp.valid = true;
2310	m_drsp.error = false;
2311	break;
2312
2313	case iss_t::XTN_DATA_BAD_VADDR:
2314	m_drsp.rdata = r_mmu_dbvar.read();
2315	m_drsp.valid = true;
2316	m_drsp.error = false;
2317	break;
2318
2319	case iss_t::XTN_PTPR:
2320	m_drsp.rdata = r_mmu_ptpr.read();
2321	m_drsp.valid = true;
2322	m_drsp.error = false;
2323	break;
2324
2325	case iss_t::XTN_TLB_MODE:
2326	m_drsp.rdata = r_mmu_mode.read();
2327	m_drsp.valid = true;
2328	m_drsp.error = false;
2329	break;
2330
2331	case iss_t::XTN_MMU_PARAMS:
2332	m_drsp.rdata = r_mmu_params;
2333	m_drsp.valid = true;
2334	m_drsp.error = false;
2335	break;
2336
2337	case iss_t::XTN_MMU_RELEASE:
2338	m_drsp.rdata = r_mmu_release;
2339	m_drsp.valid = true;
2340	m_drsp.error = false;
2341	break;
2342
2343	case iss_t::XTN_MMU_WORD_LO:
2344	m_drsp.rdata = r_mmu_word_lo.read();
2345	m_drsp.valid = true;
2346	m_drsp.error = false;
2347	break;
2348
2349	case iss_t::XTN_MMU_WORD_HI:
2350	m_drsp.rdata = r_mmu_word_hi.read();
2351	m_drsp.valid = true;
2352	m_drsp.error = false;
2353	break;
2354
2355	default:
2356	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2357	r_mmu_dbvar = m_dreq.addr;
2358	m_drsp.valid = true;
2359	m_drsp.error = true;
2360	m_drsp.rdata = 0;
2361	break;
2362	} // end switch xtn_opcode
2363	} // end else
2364	} // end if XTN_READ
2365
2366	// Handling WRITE XTN requests from processor.
2367	// They are not executed in this DCACHE_IDLE state
2368	// if they require access to the caches or the TLBs
2369	// that are already accessed.
2370	// Caches can be invalidated or flushed in user mode,
2371	// and the sync instruction can be executed in user mode
2372	else if (m_dreq.type == iss_t::XTN_WRITE)
2373	{
2374	int xtn_opcode = (int)m_dreq.addr/4;
2375	r_dcache_xtn_opcode = xtn_opcode;
2376
2377	// checking processor mode:
2378	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2379	(xtn_opcode != iss_t::XTN_SYNC) &&
2380	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2381	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2382	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2383	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2384	{
2385	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2386	r_mmu_dbvar = m_dreq.addr;
2387	m_drsp.valid = true;
2388	m_drsp.error = true;
2389	m_drsp.rdata = 0;
2390	r_dcache_fsm = DCACHE_IDLE;
2391	}
2392	else
2393	{
2394	switch( xtn_opcode )
2395	{
2396	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2397	r_dcache_xtn_req = true;
2398	r_dcache_fsm = DCACHE_XTN_SWITCH;
2399	break;
2400
2401	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2402	r_mmu_mode = m_dreq.wdata;
2403	m_drsp.valid = true;
2404	r_dcache_fsm = DCACHE_IDLE;
2405	break;
2406
2407	case iss_t::XTN_DTLB_INVAL: // dtlb access
2408	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2409	break;
2410
2411	case iss_t::XTN_ITLB_INVAL: // itlb access
2412	r_dcache_xtn_req = true;
2413	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2414	break;
2415
2416	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2417	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2418	break;
2419
2420	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2421	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2422	if (sizeof(paddr_t) <= 32)
2423	{
2424	assert(r_mmu_word_hi.read() == 0 &&
2425	"high bits should be 0 for 32bit paddr");
2426	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2427	}
2428	else
2429	{
2430	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2431	(paddr_t)r_mmu_word_lo.read();
2432	}
2433	break;
2434
2435	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2436	r_dcache_flush_count = 0;
2437	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2438	break;
2439
2440	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2441	r_dcache_xtn_req = true;
2442	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2443	break;
2444
2445	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2446	r_dcache_xtn_req = true;
2447	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2448	break;
2449
2450	case iss_t::XTN_ICACHE_FLUSH: // icache access
2451	r_dcache_xtn_req = true;
2452	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2453	break;
2454
2455	case iss_t::XTN_SYNC: // wait until write buffer empty
2456	r_dcache_fsm = DCACHE_XTN_SYNC;
2457	break;
2458
2459	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2460	r_mmu_word_lo = m_dreq.wdata;
2461	m_drsp.valid = true;
2462	r_dcache_fsm = DCACHE_IDLE;
2463	break;
2464
2465	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2466	r_mmu_word_hi = m_dreq.wdata;
2467	m_drsp.valid = true;
2468	r_dcache_fsm = DCACHE_IDLE;
2469	break;
2470
2471	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2472	r_dcache_llsc_valid = false;
2473	m_drsp.valid = true;
2474	r_dcache_fsm = DCACHE_IDLE;
2475	break;
2476
2477	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2478	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2479	m_drsp.valid = true;
2480	r_dcache_fsm = DCACHE_IDLE;
2481	break;
2482
2483	default:
2484	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2485	r_mmu_dbvar = m_dreq.addr;
2486	m_drsp.valid = true;
2487	m_drsp.error = true;
2488	r_dcache_fsm = DCACHE_IDLE;
2489	break;
2490	} // end switch xtn_opcode
2491	} // end else
2492	} // end if XTN_WRITE
2493
2494	// Handling processor requests to address space (READ/WRITE/LL/SC)
2495	// The dtlb and dcache can be activated or not.
2496	// We compute the cacheability, and check processor request validity:
2497	// - If DTLB not activated : cacheability is defined by the segment table,
2498	// and there is no access rights checking.
2499	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2500	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2501	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2502	else
2503	{
2504	bool valid_req;
2505	bool cacheable;
2506
2507	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2508	{
2509	valid_req = true;
2510
2511	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2512	else cacheable = m_cacheability_table[m_dreq.addr];
2513	}
2514	else // dtlb activated
2515	{
2516	if ( tlb_hit ) // tlb hit
2517	{
2518	// cacheability
2519	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2520	else cacheable = tlb_flags.c;
2521
2522	// access rights checking
2523	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2524	{
2525	if ( (m_dreq.type == iss_t::DATA_READ) or
2526	(m_dreq.type == iss_t::DATA_LL) )
2527	{
2528	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2529	}
2530	else
2531	{
2532	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2533	}
2534	valid_req = false;
2535	r_mmu_dbvar = m_dreq.addr;
2536	m_drsp.valid = true;
2537	m_drsp.error = true;
2538	m_drsp.rdata = 0;
2539	#if DEBUG_DCACHE
2540	if ( m_debug_dcache_fsm )
2541	{
2542	std::cout << " <PROC " << name()
2543	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2544	}
2545	#endif
2546	}
2547	else if ( not tlb_flags.w and
2548	((m_dreq.type == iss_t::DATA_WRITE) or
2549	(m_dreq.type == iss_t::DATA_SC)) )
2550	{
2551	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2552	valid_req = false;
2553	r_mmu_dbvar = m_dreq.addr;
2554	m_drsp.valid = true;
2555	m_drsp.error = true;
2556	m_drsp.rdata = 0;
2557	#if DEBUG_DCACHE
2558	if ( m_debug_dcache_fsm )
2559	{
2560	std::cout << " <PROC " << name()
2561	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2562	}
2563	#endif
2564	}
2565	else
2566	{
2567	valid_req = true;
2568	}
2569	}
2570	else // tlb miss
2571	{
2572	valid_req = false;
2573	r_dcache_tlb_vaddr = m_dreq.addr;
2574	r_dcache_tlb_ins = false;
2575	r_dcache_fsm = DCACHE_TLB_MISS;
2576	}
2577	} // end DTLB activated
2578
2579	if ( valid_req ) // processor request is valid after TLB check
2580	{
2581	r_dcache_save_cacheable = cacheable;
2582
2583	// READ request
2584	// The read requests are taken only if there is no cache update.
2585	// We request a VCI transaction to CMD FSM if miss or uncachable
2586
2587	if ( ((m_dreq.type == iss_t::DATA_READ))
2588	and not r_dcache_updt_req.read() )
2589	{
2590	if ( cacheable ) // cacheable read
2591	{
2592	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2593	{
2594	#ifdef INSTRUMENTATION
2595	m_cpt_dcache_miss++;
2596	#endif
2597	// request a VCI DMISS transaction
2598	r_dcache_vci_paddr = paddr;
2599	r_dcache_vci_miss_req = true;
2600	r_dcache_miss_type = PROC_MISS;
2601	r_dcache_fsm = DCACHE_MISS_SELECT;
2602	#if DEBUG_DCACHE
2603	if ( m_debug_dcache_fsm )
2604	{
2605	std::cout << " <PROC " << name()
2606	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2607	}
2608	#endif
2609	}
2610	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2611	{
2612	// stalled until cleanup is acknowledged
2613	r_dcache_fsm = DCACHE_IDLE;
2614	}
2615	else // cache hit
2616	{
2617	#ifdef INSTRUMENTATION
2618	m_cpt_data_read++;
2619	#endif
2620	// returns data to processor
2621	m_drsp.valid = true;
2622	m_drsp.error = false;
2623	m_drsp.rdata = cache_rdata;
2624	#if DEBUG_DCACHE
2625	if ( m_debug_dcache_fsm )
2626	{
2627	std::cout << " <PROC " << name()
2628	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2629	}
2630	#endif
2631	}
2632	}
2633	else // uncacheable read
2634	{
2635	r_dcache_vci_paddr = paddr;
2636	r_dcache_vci_unc_be = m_dreq.be;
2637	r_dcache_vci_unc_req = true;
2638	r_dcache_fsm = DCACHE_UNC_WAIT;
2639	#if DEBUG_DCACHE
2640	if ( m_debug_dcache_fsm )
2641	{
2642	std::cout << " <PROC " << name()
2643	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2644	}
2645	#endif
2646	}
2647	} // end READ
2648
2649	// LL request (non cachable)
2650	// We request a VCI LL transaction to CMD FSM and register
2651	// the LL/SC operation in llsc buffer.
2652	else if (m_dreq.type == iss_t::DATA_LL)
2653	{
2654	// register paddr in LLSC buffer
2655	r_dcache_llsc_paddr = paddr;
2656	r_dcache_llsc_count = LLSC_TIMEOUT;
2657	r_dcache_llsc_valid = true;
2658
2659	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2660	r_dcache_vci_ll_req = true;
2661	r_dcache_vci_paddr = paddr;
2662	r_dcache_ll_rsp_count = 0;
2663	r_dcache_fsm = DCACHE_LL_WAIT;
2664
2665	}// end LL
2666
2667	// WRITE request:
2668	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2669	// the processor and set the Dirty bit before handling the write request,
2670	// going to the DCACHE_DIRTY_GT_PTE state.
2671	// If we don't need to set the Dirty bit, we can acknowledge
2672	// the processor request, as the write arguments (including the
2673	// physical address) are registered in r_dcache_save registers,
2674	// and the write will be done in the P1 pipeline stage.
2675	else if ( m_dreq.type == iss_t::DATA_WRITE )
2676	{
2677	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2678	and not tlb_flags.d ) // Dirty bit must be set
2679	{
2680	// The PTE physical address is obtained from the nline value (dtlb),
2681	// and from the virtual address (word index)
2682	if ( tlb_flags.b ) // PTE1
2683	{
2684	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2685	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2686	}
2687	else // PTE2
2688	{
2689	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2690	(paddr_t)((m_dreq.addr>>9) & 0x38);
2691	}
2692	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2693	}
2694	else // Write request accepted
2695	{
2696	#ifdef INSTRUMENTATION
2697	m_cpt_data_write++;
2698	#endif
2699	// cleaning llsc buffer if address matching
2700	if ( paddr == r_dcache_llsc_paddr.read() )
2701	r_dcache_llsc_valid = false;
2702
2703	// response to processor
2704	m_drsp.valid = true;
2705
2706	// activating P1 stage
2707	wbuf_request = true;
2708	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2709	}
2710	} // end WRITE
2711
2712	// SC request:
2713	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2714	// the processor and set the Dirty bit before handling the write request,
2715	// going to the DCACHE_DIRTY_GT_PTE state.
2716	// If we don't need to set the Dirty bit, we test the llsc buffer:
2717	// If failure, we send a negative response to processor.
2718	// If success, we request a SC transaction to CMD FSM and go
2719	// to DCACHE_SC_WAIT state.
2720	// We don't check a possible write hit in dcache, as the cache update
2721	// is done by the coherence transaction induced by the SC...
2722	else if ( m_dreq.type == iss_t::DATA_SC )
2723	{
2724	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2725	and not tlb_flags.d ) // Dirty bit must be set
2726	{
2727	// The PTE physical address is obtained from the nline value (dtlb),
2728	// and the word index (virtual address)
2729	if ( tlb_flags.b ) // PTE1
2730	{
2731	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2732	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2733	}
2734	else // PTE2
2735	{
2736	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2737	(paddr_t)((m_dreq.addr>>9) & 0x38);
2738	}
2739	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2740	m_drsp.valid = false;
2741	m_drsp.error = false;
2742	m_drsp.rdata = 0;
2743	}
2744	else // SC request accepted
2745	{
2746	#ifdef INSTRUMENTATION
2747	m_cpt_data_sc++;
2748	#endif
2749	// checking local success
2750	if( r_dcache_llsc_valid.read() and
2751	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2752	{
2753	// request an SC CMD and go to DCACHE_SC_WAIT state
2754	r_dcache_vci_paddr = paddr;
2755	r_dcache_vci_sc_req = true;
2756	r_dcache_vci_sc_data = m_dreq.wdata;
2757	r_dcache_fsm = DCACHE_SC_WAIT;
2758	}
2759	else // local fail
2760	{
2761	m_drsp.valid = true;
2762	m_drsp.error = false;
2763	m_drsp.rdata = 0x1;
2764	}
2765	}
2766	} // end SC
2767	} // end valid_req
2768	} // end if read/write/ll/sc request
2769	} // end processor request
2770
2771	// itlb miss request
2772	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2773	{
2774	r_dcache_tlb_ins = true;
2775	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2776	r_dcache_fsm = DCACHE_TLB_MISS;
2777	}
2778
2779	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2780	r_dcache_updt_req = updt_request;
2781	r_dcache_wbuf_req = wbuf_request or
2782	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2783	break;
2784	}
2785	/////////////////////
2786	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2787	// Input arguments are:
2788	// - r_dcache_tlb_vaddr
2789	// - r_dcache_tlb_ins (true when itlb miss)
2790	// The sub-fsm access the dcache to find the missing TLB entry,
2791	// and activates the cache miss procedure in case of miss.
2792	// It bypass the first level page table access if possible.
2793	// It uses atomic access to update the R/L access bits
2794	// in the page table if required.
2795	// It directly updates the itlb or dtlb, and writes into the
2796	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2797	{
2798	uint32_t ptba = 0;
2799	bool bypass;
2800	paddr_t pte_paddr;
2801
2802	// evaluate bypass in order to skip first level page table access
2803	if ( r_dcache_tlb_ins.read() ) // itlb miss
2804	{
2805	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2806	}
2807	else // dtlb miss
2808	{
2809	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2810	}
2811
2812	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2813	{
2814	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2815	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2816	r_dcache_tlb_paddr = pte_paddr;
2817	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2818	}
2819	else // Try to read PTE2 in dcache
2820	{
2821	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2822	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2823	r_dcache_tlb_paddr = pte_paddr;
2824	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2825	}
2826
2827	#if DEBUG_DCACHE
2828	if ( m_debug_dcache_fsm )
2829	{
2830	if ( r_dcache_tlb_ins.read() )
2831	{
2832	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2833	}
2834	else
2835	{
2836	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2837	}
2838	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2839	<< " / BYPASS = " << bypass
2840	<< " / PTE_ADR = " << pte_paddr << std::endl;
2841	}
2842	#endif
2843
2844	break;
2845	}
2846	/////////////////////////
2847	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2848	{
2849	// coherence request (from CC_RECEIVE FSM)
2850	if ( r_cc_receive_dcache_req.read() )
2851	{
2852	r_dcache_fsm = DCACHE_CC_CHECK;
2853	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2854	break;
2855	}
2856
2857	uint32_t entry;
2858	size_t way;
2859	size_t set;
2860	size_t word;
2861	int cache_state;
2862	r_dcache.read( r_dcache_tlb_paddr.read(),
2863	&entry,
2864	&way,
2865	&set,
2866	&word,
2867	&cache_state );
2868	#ifdef INSTRUMENTATION
2869	m_cpt_dcache_data_read++;
2870	m_cpt_dcache_dir_read++;
2871	#endif
2872	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2873	{
2874	if ( not (entry & PTE_V_MASK) ) // unmapped
2875	{
2876	if ( r_dcache_tlb_ins.read() )
2877	{
2878	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2879	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2880	r_icache_tlb_miss_req = false;
2881	r_icache_tlb_rsp_error = true;
2882	}
2883	else
2884	{
2885	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2886	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2887	m_drsp.valid = true;
2888	m_drsp.error = true;
2889	}
2890	r_dcache_fsm = DCACHE_IDLE;
2891
2892	#if DEBUG_DCACHE
2893	if ( m_debug_dcache_fsm )
2894	{
2895	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2896	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2897	<< std::dec << " / way = " << way
2898	<< std::dec << " / set = " << set
2899	<< std::dec << " / word = " << word
2900	<< std::hex << " / PTE1 = " << entry << std::endl;
2901	}
2902	#endif
2903
2904	}
2905	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2906	{
2907	// mark the cache line ac containing a PTD
2908	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2909
2910	// register bypass
2911	if ( r_dcache_tlb_ins.read() ) // itlb
2912	{
2913	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2914	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2915	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2916	}
2917	else // dtlb
2918	{
2919	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2920	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2921	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2922	}
2923	r_dcache_tlb_paddr =
2924	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2925	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2926	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2927
2928	#if DEBUG_DCACHE
2929	if ( m_debug_dcache_fsm )
2930	{
2931	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2932	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2933	<< std::dec << " / way = " << way
2934	<< std::dec << " / set = " << set
2935	<< std::dec << " / word = " << word
2936	<< std::hex << " / PTD = " << entry << std::endl;
2937	}
2938	#endif
2939	}
2940	else // PTE1 : we must update the TLB
2941	{
2942	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2943	r_dcache_tlb_pte_flags = entry;
2944	r_dcache_tlb_cache_way = way;
2945	r_dcache_tlb_cache_set = set;
2946	r_dcache_tlb_cache_word = word;
2947	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2948
2949	#if DEBUG_DCACHE
2950	if ( m_debug_dcache_fsm )
2951	{
2952	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2953	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2954	<< std::dec << " / way = " << way
2955	<< std::dec << " / set = " << set
2956	<< std::dec << " / word = " << word
2957	<< std::hex << " / PTE1 = " << entry << std::endl;
2958	}
2959	#endif
2960	}
2961	}
2962	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2963	{
2964	// stalled until cleanup is acknowledged
2965	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2966	}
2967	else // we must load the missing cache line in dcache
2968	{
2969	r_dcache_vci_miss_req = true;
2970	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2971	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2972	r_dcache_miss_type = PTE1_MISS;
2973	r_dcache_fsm = DCACHE_MISS_SELECT;
2974
2975	#if DEBUG_DCACHE
2976	if ( m_debug_dcache_fsm )
2977	{
2978	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2979	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2980	}
2981	#endif
2982	}
2983	break;
2984	}
2985	////////////////////////////
2986	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2987	{
2988	size_t way;
2989	size_t set;
2990
2991	if ( r_dcache_tlb_ins.read() )
2992	{
2993	r_itlb.select( r_dcache_tlb_vaddr.read(),
2994	true, // PTE1
2995	&way,
2996	&set );
2997	#ifdef INSTRUMENTATION
2998	m_cpt_itlb_read++;
2999	#endif
3000	}
3001	else
3002	{
3003	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3004	true, // PTE1
3005	&way,
3006	&set );
3007	#ifdef INSTRUMENTATION
3008	m_cpt_dtlb_read++;
3009	#endif
3010	}
3011	r_dcache_tlb_way = way;
3012	r_dcache_tlb_set = set;
3013	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3014
3015	#if DEBUG_DCACHE
3016	if ( m_debug_dcache_fsm )
3017	{
3018	if ( r_dcache_tlb_ins.read() )
3019	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3020	else
3021	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3022	std::cout << " way = " << std::dec << way
3023	<< " / set = " << set << std::endl;
3024	}
3025	#endif
3026	break;
3027	}
3028	//////////////////////////
3029	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3030	// - if L/R bit already set, exit the sub-fsm.
3031	// - if not, we update the page table but we dont write
3032	// neither in DCACHE, nor in TLB, as this will be done by
3033	// the coherence mechanism.
3034	{
3035	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3036	uint32_t pte = r_dcache_tlb_pte_flags.read();
3037	bool pt_updt = false;
3038	bool local = true;
3039
3040	// We should compute the access locality:
3041	// The PPN MSB bits define the destination cluster index.
3042	// The m_srcid MSB bits define the source cluster index.
3043	// The number of bits to compare depends on the number of clusters,
3044	// and can be obtained in the mapping table.
3045	// As long as this computation is not done, all access are local.
3046
3047	if ( local ) // local access
3048	{
3049	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3050	{
3051	pt_updt = true;
3052	r_dcache_vci_cas_old = pte;
3053	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3054	pte = pte \| PTE_L_MASK;
3055	r_dcache_tlb_pte_flags = pte;
3056	}
3057	}
3058	else // remote access
3059	{
3060	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3061	{
3062	pt_updt = true;
3063	r_dcache_vci_cas_old = pte;
3064	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3065	pte = pte \| PTE_R_MASK;
3066	r_dcache_tlb_pte_flags = pte;
3067	}
3068	}
3069
3070	if ( not pt_updt ) // update TLB and return
3071	{
3072	if ( r_dcache_tlb_ins.read() )
3073	{
3074	r_itlb.write( true, // 2M page
3075	pte,
3076	0, // argument unused for a PTE1
3077	r_dcache_tlb_vaddr.read(),
3078	r_dcache_tlb_way.read(),
3079	r_dcache_tlb_set.read(),
3080	nline );
3081	#ifdef INSTRUMENTATION
3082	m_cpt_itlb_write++;
3083	#endif
3084
3085	#if DEBUG_DCACHE
3086	if ( m_debug_dcache_fsm )
3087	{
3088	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3089	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3090	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3091	r_itlb.printTrace();
3092	}
3093	#endif
3094	}
3095	else
3096	{
3097	r_dtlb.write( true, // 2M page
3098	pte,
3099	0, // argument unused for a PTE1
3100	r_dcache_tlb_vaddr.read(),
3101	r_dcache_tlb_way.read(),
3102	r_dcache_tlb_set.read(),
3103	nline );
3104	#ifdef INSTRUMENTATION
3105	m_cpt_dtlb_write++;
3106	#endif
3107
3108	#if DEBUG_DCACHE
3109	if ( m_debug_dcache_fsm )
3110	{
3111	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3112	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3113	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3114	r_dtlb.printTrace();
3115	}
3116	#endif
3117	}
3118	r_dcache_fsm = DCACHE_TLB_RETURN;
3119	}
3120	else // update page table but not TLB
3121	{
3122	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3123
3124	#if DEBUG_DCACHE
3125	if ( m_debug_dcache_fsm )
3126	{
3127	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3128	<< std::endl;
3129	}
3130	#endif
3131	}
3132	break;
3133	}
3134	/////////////////////////
3135	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3136	{
3137	// coherence request (from CC_RECEIVE FSM)
3138	if ( r_cc_receive_dcache_req.read() )
3139	{
3140	r_dcache_fsm = DCACHE_CC_CHECK;
3141	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3142	break;
3143	}
3144
3145	uint32_t pte_flags;
3146	uint32_t pte_ppn;
3147	size_t way;
3148	size_t set;
3149	size_t word;
3150	int cache_state;
3151
3152	r_dcache.read( r_dcache_tlb_paddr.read(),
3153	&pte_flags,
3154	&pte_ppn,
3155	&way,
3156	&set,
3157	&word,
3158	&cache_state );
3159	#ifdef INSTRUMENTATION
3160	m_cpt_dcache_data_read++;
3161	m_cpt_dcache_dir_read++;
3162	#endif
3163	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3164	{
3165	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3166	{
3167	if ( r_dcache_tlb_ins.read() )
3168	{
3169	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3170	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3171	r_icache_tlb_miss_req = false;
3172	r_icache_tlb_rsp_error = true;
3173	}
3174	else
3175	{
3176	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3177	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3178	m_drsp.valid = true;
3179	m_drsp.error = true;
3180	}
3181	r_dcache_fsm = DCACHE_IDLE;
3182
3183	#if DEBUG_DCACHE
3184	if ( m_debug_dcache_fsm )
3185	{
3186	std::cout << " <PROC " << name()
3187	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3188	<< " PTE_FLAGS = " << std::hex << pte_flags
3189	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3190	}
3191	#endif
3192	}
3193	else // mapped : we must update the TLB
3194	{
3195	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3196	r_dcache_tlb_pte_flags = pte_flags;
3197	r_dcache_tlb_pte_ppn = pte_ppn;
3198	r_dcache_tlb_cache_way = way;
3199	r_dcache_tlb_cache_set = set;
3200	r_dcache_tlb_cache_word = word;
3201	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3202
3203	#if DEBUG_DCACHE
3204	if ( m_debug_dcache_fsm )
3205	{
3206	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3207	<< " PTE_FLAGS = " << std::hex << pte_flags
3208	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3209	}
3210	#endif
3211	}
3212	}
3213	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3214	{
3215	// stalled until cleanup is acknowledged
3216	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3217	}
3218	else // we must load the missing cache line in dcache
3219	{
3220	r_dcache_fsm = DCACHE_MISS_SELECT;
3221	r_dcache_vci_miss_req = true;
3222	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3223	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3224	r_dcache_miss_type = PTE2_MISS;
3225
3226	#if DEBUG_DCACHE
3227	if ( m_debug_dcache_fsm )
3228	{
3229	std::cout << " <PROC " << name()
3230	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3231	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3232	}
3233	#endif
3234	}
3235	break;
3236	}
3237	////////////////////////////
3238	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3239	{
3240	size_t way;
3241	size_t set;
3242
3243	if ( r_dcache_tlb_ins.read() )
3244	{
3245	r_itlb.select( r_dcache_tlb_vaddr.read(),
3246	false, // PTE2
3247	&way,
3248	&set );
3249	#ifdef INSTRUMENTATION
3250	m_cpt_itlb_read++;
3251	#endif
3252	}
3253	else
3254	{
3255	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3256	false, // PTE2
3257	&way,
3258	&set );
3259	#ifdef INSTRUMENTATION
3260	m_cpt_dtlb_read++;
3261	#endif
3262	}
3263
3264	#if DEBUG_DCACHE
3265	if ( m_debug_dcache_fsm )
3266	{
3267	if ( r_dcache_tlb_ins.read() )
3268	std::cout << " <PROC " << name()
3269	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3270	else
3271	std::cout << " <PROC " << name()
3272	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3273	std::cout << " way = " << std::dec << way
3274	<< " / set = " << set << std::endl;
3275	}
3276	#endif
3277	r_dcache_tlb_way = way;
3278	r_dcache_tlb_set = set;
3279	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3280	break;
3281	}
3282	//////////////////////////
3283	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3284	// - if L/R bit already set, exit the sub-fsm.
3285	// - if not, we update the page table but we dont write
3286	// neither in DCACHE, nor in TLB, as this will be done by
3287	// the coherence mechanism.
3288	{
3289	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3290	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3291	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3292	bool pt_updt = false;
3293	bool local = true;
3294
3295	// We should compute the access locality:
3296	// The PPN MSB bits define the destination cluster index.
3297	// The m_srcid MSB bits define the source cluster index.
3298	// The number of bits to compare depends on the number of clusters,
3299	// and can be obtained in the mapping table.
3300	// As long as this computation is not done, all access are local.
3301
3302	if ( local ) // local access
3303	{
3304	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3305	{
3306	pt_updt = true;
3307	r_dcache_vci_cas_old = pte_flags;
3308	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3309	pte_flags = pte_flags \| PTE_L_MASK;
3310	r_dcache_tlb_pte_flags = pte_flags;
3311	}
3312	}
3313	else // remote access
3314	{
3315	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3316	{
3317	pt_updt = true;
3318	r_dcache_vci_cas_old = pte_flags;
3319	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3320	pte_flags = pte_flags \| PTE_R_MASK;
3321	r_dcache_tlb_pte_flags = pte_flags;
3322	}
3323	}
3324
3325	if ( not pt_updt ) // update TLB
3326	{
3327	if ( r_dcache_tlb_ins.read() )
3328	{
3329	r_itlb.write( false, // 4K page
3330	pte_flags,
3331	pte_ppn,
3332	r_dcache_tlb_vaddr.read(),
3333	r_dcache_tlb_way.read(),
3334	r_dcache_tlb_set.read(),
3335	nline );
3336	#ifdef INSTRUMENTATION
3337	m_cpt_itlb_write++;
3338	#endif
3339
3340	#if DEBUG_DCACHE
3341	if ( m_debug_dcache_fsm )
3342	{
3343	std::cout << " <PROC " << name()
3344	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3345	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3346	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3347	r_itlb.printTrace();
3348	}
3349	#endif
3350	}
3351	else
3352	{
3353	r_dtlb.write( false, // 4K page
3354	pte_flags,
3355	pte_ppn,
3356	r_dcache_tlb_vaddr.read(),
3357	r_dcache_tlb_way.read(),
3358	r_dcache_tlb_set.read(),
3359	nline );
3360	#ifdef INSTRUMENTATION
3361	m_cpt_dtlb_write++;
3362	#endif
3363
3364	#if DEBUG_DCACHE
3365	if ( m_debug_dcache_fsm )
3366	{
3367	std::cout << " <PROC " << name()
3368	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3369	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3370	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3371	r_dtlb.printTrace();
3372	}
3373	#endif
3374
3375	}
3376	r_dcache_fsm = DCACHE_TLB_RETURN;
3377	}
3378	else // update page table but not TLB
3379	{
3380	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3381
3382	#if DEBUG_DCACHE
3383	if ( m_debug_dcache_fsm )
3384	{
3385	std::cout << " <PROC " << name()
3386	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3387	}
3388	#endif
3389	}
3390	break;
3391	}
3392	////////////////////////
3393	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3394	{
3395	#if DEBUG_DCACHE
3396	if ( m_debug_dcache_fsm )
3397	{
3398	std::cout << " <PROC " << name()
3399	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3400	}
3401	#endif
3402	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3403	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3404
3405	// checking llsc reservation buffer
3406	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3407	r_dcache_llsc_valid = false;
3408
3409	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3410	r_dcache_vci_cas_req = true;
3411	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3412	break;
3413	}
3414	////////////////////////
3415	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3416	// We consume the response in rsp FIFO,
3417	// and exit the sub-fsm, but we don't
3418	// analyse the response, because we don't
3419	// care if the L/R bit update is not done.
3420	// We must take the coherence requests because
3421	// there is a risk of dead-lock
3422
3423	{
3424	// coherence request (from CC_RECEIVE FSM)
3425	if ( r_cc_receive_dcache_req.read() )
3426	{
3427	r_dcache_fsm = DCACHE_CC_CHECK;
3428	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3429	break;
3430	}
3431
3432	if ( r_vci_rsp_data_error.read() ) // bus error
3433	{
3434	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3435	std::cout << "This should not happen in this state" << std::endl;
3436	exit(0);
3437	}
3438	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3439	{
3440	#if DEBUG_DCACHE
3441	if ( m_debug_dcache_fsm )
3442	{
3443	std::cout << " <PROC " << name()
3444	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3445	}
3446	#endif
3447	vci_rsp_fifo_dcache_get = true;
3448	r_dcache_fsm = DCACHE_TLB_RETURN;
3449	}
3450	break;
3451	}
3452	///////////////////////
3453	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3454	{
3455	#if DEBUG_DCACHE
3456	if ( m_debug_dcache_fsm )
3457	{
3458	std::cout << " <PROC " << name()
3459	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3460	}
3461	#endif
3462	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3463	r_dcache_fsm = DCACHE_IDLE;
3464	break;
3465	}
3466	///////////////////////
3467	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3468	// and both itlb and dtlb must be flushed.
3469	// Caution : the itlb miss requests must be taken
3470	// to avoid dead-lock in case of simultaneous ITLB miss
3471	{
3472	// itlb miss request
3473	if ( r_icache_tlb_miss_req.read() )
3474	{
3475	r_dcache_tlb_ins = true;
3476	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3477	r_dcache_fsm = DCACHE_TLB_MISS;
3478	break;
3479	}
3480
3481	if ( not r_dcache_xtn_req.read() )
3482	{
3483	r_dtlb.flush();
3484	r_mmu_ptpr = m_dreq.wdata;
3485	r_dcache_fsm = DCACHE_IDLE;
3486	m_drsp.valid = true;
3487	}
3488	break;
3489	}
3490	/////////////////////
3491	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3492	// The coherence request must be taken
3493	// as there is a risk of dead-lock
3494	{
3495	// coherence request (from CC_RECEIVE FSM)
3496	if ( r_cc_receive_dcache_req.read() )
3497	{
3498	r_dcache_fsm = DCACHE_CC_CHECK;
3499	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3500	}
3501
3502	if ( r_wbuf.empty() )
3503	{
3504	m_drsp.valid = true;
3505	r_dcache_fsm = DCACHE_IDLE;
3506	}
3507	break;
3508	}
3509	////////////////////////
3510	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3511	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3512	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3513	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3514	// and because it can exist a simultaneous ITLB miss
3515	{
3516	// coherence request (from CC_RECEIVE FSM)
3517	if ( r_cc_receive_dcache_req.read() )
3518	{
3519	r_dcache_fsm = DCACHE_CC_CHECK;
3520	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3521	break;
3522	}
3523
3524	// itlb miss request
3525	if ( r_icache_tlb_miss_req.read() )
3526	{
3527	r_dcache_tlb_ins = true;
3528	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3529	r_dcache_fsm = DCACHE_TLB_MISS;
3530	break;
3531	}
3532
3533	// test if XTN request to icache completed
3534	if ( not r_dcache_xtn_req.read() )
3535	{
3536	r_dcache_fsm = DCACHE_IDLE;
3537	m_drsp.valid = true;
3538	}
3539	break;
3540	}
3541	/////////////////////////
3542	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3543	// r_dcache_flush_count as a slot counter,
3544	// looping in this state until all slots have been visited.
3545	// It can require two cycles per slot:
3546	// We test here the slot state, and make the actual inval
3547	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3548	// A cleanup request is generated for each valid line.
3549	// returns to IDLE and flush TLBs when last slot
3550	{
3551	// coherence request (from CC_RECEIVE FSM)
3552	if ( r_cc_receive_dcache_req.read() )
3553	{
3554	r_dcache_fsm = DCACHE_CC_CHECK;
3555	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3556	break;
3557	}
3558
3559	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3560	{
3561	int state;
3562	uint32_t tag;
3563	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3564	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3565
3566	#ifdef INSTRUMENTATION
3567	m_cpt_dcache_dir_read++;
3568	#endif
3569	r_dcache.read_dir( way,
3570	set,
3571	&tag,
3572	&state );
3573
3574	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3575	{
3576	// request cleanup
3577	r_dcache_cc_send_req = true;
3578	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3579	r_dcache_cc_send_way = way;
3580	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3581
3582	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3583	r_dcache_miss_way = way;
3584	r_dcache_miss_set = set;
3585	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3586	}
3587	else if ( r_dcache_flush_count.read() ==
3588	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3589	{
3590	r_dtlb.reset();
3591	r_itlb.reset();
3592	r_dcache_fsm = DCACHE_IDLE;
3593	m_drsp.valid = true;
3594	}
3595
3596	// saturation counter
3597	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3598	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3599	}
3600	break;
3601	}
3602	////////////////////////////
3603	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3604	// and reset directory extension.
3605	// returns to IDLE and flush TLBs when last slot
3606	{
3607	size_t way = r_dcache_miss_way.read();
3608	size_t set = r_dcache_miss_set.read();
3609
3610	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3611	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3612
3613	#ifdef INSTRUMENTATION
3614	m_cpt_dcache_dir_write++;
3615	#endif
3616	r_dcache.write_dir( way,
3617	set,
3618	CACHE_SLOT_STATE_ZOMBI );
3619
3620	if ( r_dcache_flush_count.read() ==
3621	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3622	{
3623	r_dtlb.reset();
3624	r_itlb.reset();
3625	r_dcache_fsm = DCACHE_IDLE;
3626	m_drsp.valid = true;
3627	}
3628	else
3629	{
3630	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3631	}
3632	break;
3633	}
3634	/////////////////////////
3635	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3636	{
3637	r_dtlb.inval(r_dcache_save_wdata.read());
3638	r_dcache_fsm = DCACHE_IDLE;
3639	m_drsp.valid = true;
3640	break;
3641	}
3642	////////////////////////////
3643	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3644	// requires 3 cycles: access tlb, read cache, inval cache
3645	// we compute the physical address in this state
3646	{
3647	paddr_t paddr;
3648	bool hit;
3649
3650	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3651	{
3652
3653	#ifdef INSTRUMENTATION
3654	m_cpt_dtlb_read++;
3655	#endif
3656	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3657	&paddr );
3658	}
3659	else // dtlb not activated
3660	{
3661	paddr = (paddr_t)r_dcache_save_wdata.read();
3662	hit = true;
3663	}
3664
3665	if ( hit ) // tlb hit
3666	{
3667	r_dcache_save_paddr = paddr;
3668	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3669	}
3670	else // tlb miss
3671	{
3672
3673	#ifdef INSTRUMENTATION
3674	m_cpt_dtlb_miss++;
3675	#endif
3676	r_dcache_tlb_ins = false; // dtlb
3677	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3678	r_dcache_fsm = DCACHE_TLB_MISS;
3679	}
3680
3681	#if DEBUG_DCACHE
3682	if ( m_debug_dcache_fsm )
3683	{
3684	std::cout << " <PROC " << name()
3685	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3686	<< " / VADDR = " << r_dcache_save_wdata.read()
3687	<< " / PADDR = " << paddr << std::endl;
3688	}
3689	#endif
3690
3691	break;
3692	}
3693	////////////////////////////
3694	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3695	// requires 2 cycles: read cache / inval cache
3696	// In this state we read dcache.
3697	{
3698	size_t way;
3699	size_t set;
3700	size_t word;
3701	int state;
3702
3703	#ifdef INSTRUMENTATION
3704	m_cpt_dcache_dir_read++;
3705	#endif
3706	r_dcache.read_dir( r_dcache_save_paddr.read(),
3707	&state,
3708	&way,
3709	&set,
3710	&word );
3711
3712	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3713	{
3714	r_dcache_xtn_way = way;
3715	r_dcache_xtn_set = set;
3716	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3717	}
3718	else // miss : nothing to do
3719	{
3720	r_dcache_fsm = DCACHE_IDLE;
3721	m_drsp.valid = true;
3722	}
3723
3724	#if DEBUG_DCACHE
3725	if ( m_debug_dcache_fsm )
3726	{
3727	std::cout << " <PROC " << name()
3728	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3729	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3730	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3731	<< " / SET = " << set
3732	<< " / WAY = " << way << std::endl;
3733	}
3734	#endif
3735	break;
3736	}
3737	////////////////////////////
3738	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3739	// Blocked if previous cleanup not completed
3740	// Test if itlb or dtlb inval is required
3741	{
3742	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3743	{
3744	size_t way = r_dcache_xtn_way.read();
3745	size_t set = r_dcache_xtn_set.read();
3746	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3747
3748	#ifdef INSTRUMENTATION
3749	m_cpt_dcache_dir_write++;
3750	#endif
3751	r_dcache.write_dir( way,
3752	set,
3753	CACHE_SLOT_STATE_ZOMBI );
3754
3755	// request cleanup
3756	r_dcache_cc_send_req = true;
3757	r_dcache_cc_send_nline = nline;
3758	r_dcache_cc_send_way = way;
3759	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3760
3761	// possible itlb & dtlb invalidate
3762	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3763	{
3764	r_dcache_tlb_inval_line = nline;
3765	r_dcache_tlb_inval_set = 0;
3766	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3767	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3768	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3769	}
3770	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3771	{
3772	r_itlb.reset();
3773	r_dtlb.reset();
3774	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3775	r_dcache_fsm = DCACHE_IDLE;
3776	m_drsp.valid = true;
3777	}
3778	else
3779	{
3780	r_dcache_fsm = DCACHE_IDLE;
3781	m_drsp.valid = true;
3782	}
3783
3784	#if DEBUG_DCACHE
3785	if ( m_debug_dcache_fsm )
3786	{
3787	std::cout << " <PROC " << name()
3788	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3789	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3790	}
3791	#endif
3792	}
3793	break;
3794	}
3795	//////////////////////////////
3796	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3797	{
3798	r_dcache_fsm = DCACHE_IDLE;
3799	m_drsp.valid = true;
3800	break;
3801	}
3802	////////////////////////
3803	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3804	// if previous cleanup has been sent.
3805	// Waiting in this state if no slot available
3806	// Set the r_dcache_cleanup_req flip-flop
3807	// and the r_dcache_miss_clack flip-flop
3808	// when a cleanup is required
3809	{
3810	if ( m_dreq.valid) m_cost_data_miss_frz++;
3811
3812	// coherence request (from CC_RECEIVE FSM)
3813	if ( r_cc_receive_dcache_req.read() )
3814	{
3815	r_dcache_fsm = DCACHE_CC_CHECK;
3816	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3817	break;
3818	}
3819
3820	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3821	{
3822	bool found;
3823	bool cleanup;
3824	size_t way;
3825	size_t set;
3826	paddr_t victim;
3827
3828	#ifdef INSTRUMENTATION
3829	m_cpt_dcache_dir_read++;
3830	#endif
3831	r_dcache.read_select( r_dcache_save_paddr.read(),
3832	&victim,
3833	&way,
3834	&set,
3835	&found,
3836	&cleanup );
3837
3838	if ( found )
3839	{
3840	r_dcache_miss_way = way;
3841	r_dcache_miss_set = set;
3842
3843	if ( cleanup )
3844	{
3845	r_dcache_miss_clack = true;
3846	r_dcache_fsm = DCACHE_MISS_CLEAN;
3847	// request cleanup
3848	r_dcache_cc_send_req = true;
3849	r_dcache_cc_send_nline = victim;
3850	r_dcache_cc_send_way = way;
3851	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3852	}
3853	else
3854	{
3855	r_dcache_fsm = DCACHE_MISS_WAIT;
3856	}
3857
3858	#if DEBUG_DCACHE
3859	if ( m_debug_dcache_fsm )
3860	{
3861	std::cout << " <PROC " << name()
3862	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3863	<< " / WAY = " << way
3864	<< " / SET = " << set
3865	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3866	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3867	else std::cout << std::endl;
3868	}
3869	#endif
3870	} // end found
3871	}
3872	break;
3873	}
3874	///////////////////////
3875	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3876	// and possibly request itlb or dtlb invalidate
3877	{
3878	if ( m_dreq.valid) m_cost_data_miss_frz++;
3879
3880	size_t way = r_dcache_miss_way.read();
3881	size_t set = r_dcache_miss_set.read();
3882	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3883
3884	#ifdef INSTRUMENTATION
3885	m_cpt_dcache_dir_read++;
3886	#endif
3887	r_dcache.write_dir( way,
3888	set,
3889	CACHE_SLOT_STATE_ZOMBI );
3890	#if DEBUG_DCACHE
3891	if ( m_debug_dcache_fsm )
3892	{
3893	std::cout << " <PROC " << name()
3894	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3895	<< " / way = " << way
3896	<< " / set = " << set << std::endl;
3897	}
3898	#endif
3899	// if selective itlb & dtlb invalidate are required
3900	// the miss response is not handled before invalidate completed
3901	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3902	{
3903	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3904	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
3905	r_dcache_tlb_inval_set = 0;
3906	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3907	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3908	}
3909	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3910	{
3911	r_itlb.reset();
3912	r_dtlb.reset();
3913	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3914	r_dcache_fsm = DCACHE_MISS_WAIT;
3915	}
3916	else
3917	{
3918	r_dcache_fsm = DCACHE_MISS_WAIT;
3919	}
3920	break;
3921	}
3922	//////////////////////
3923	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3924	// This state is in charge of error signaling
3925	// There is 5 types of error depending on the requester
3926	{
3927	if ( m_dreq.valid) m_cost_data_miss_frz++;
3928
3929	// coherence request (from CC_RECEIVE FSM)
3930	if ( r_cc_receive_dcache_req.read() )
3931	{
3932	r_dcache_fsm = DCACHE_CC_CHECK;
3933	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3934	break;
3935	}
3936
3937	if ( r_vci_rsp_data_error.read() ) // bus error
3938	{
3939	switch ( r_dcache_miss_type.read() )
3940	{
3941	case PROC_MISS:
3942	{
3943	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3944	r_mmu_dbvar = r_dcache_save_vaddr.read();
3945	m_drsp.valid = true;
3946	m_drsp.error = true;
3947	r_dcache_fsm = DCACHE_IDLE;
3948	break;
3949	}
3950	case PTE1_MISS:
3951	{
3952	if ( r_dcache_tlb_ins.read() )
3953	{
3954	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3955	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3956	r_icache_tlb_miss_req = false;
3957	r_icache_tlb_rsp_error = true;
3958	}
3959	else
3960	{
3961	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3962	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3963	m_drsp.valid = true;
3964	m_drsp.error = true;
3965	}
3966	r_dcache_fsm = DCACHE_IDLE;
3967	break;
3968	}
3969	case PTE2_MISS:
3970	{
3971	if ( r_dcache_tlb_ins.read() )
3972	{
3973	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3974	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3975	r_icache_tlb_miss_req = false;
3976	r_icache_tlb_rsp_error = true;
3977	}
3978	else
3979	{
3980	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3981	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3982	m_drsp.valid = true;
3983	m_drsp.error = true;
3984	}
3985	r_dcache_fsm = DCACHE_IDLE;
3986	break;
3987	}
3988	} // end switch type
3989	r_vci_rsp_data_error = false;
3990	}
3991	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3992	{
3993	r_dcache_miss_word = 0;
3994	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3995	}
3996	break;
3997	}
3998	//////////////////////////
3999	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4000	{
4001	if ( m_dreq.valid) m_cost_data_miss_frz++;
4002
4003	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4004	{
4005	#ifdef INSTRUMENTATION
4006	m_cpt_dcache_data_write++;
4007	#endif
4008	r_dcache.write( r_dcache_miss_way.read(),
4009	r_dcache_miss_set.read(),
4010	r_dcache_miss_word.read(),
4011	r_vci_rsp_fifo_dcache.read() );
4012	#if DEBUG_DCACHE
4013	if ( m_debug_dcache_fsm )
4014	{
4015	std::cout << " <PROC " << name()
4016	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4017	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4018	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4019	<< " / SET = " << r_dcache_miss_set.read()
4020	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4021	}
4022	#endif
4023	vci_rsp_fifo_dcache_get = true;
4024	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4025
4026	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4027	{
4028	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4029	}
4030	}
4031	break;
4032	}
4033	//////////////////////////
4034	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4035	// and the cleanup ack has not been received,
4036	// as indicated by the r_dcache_miss clack.
4037	// - If no matching coherence request (r_dcache_inval_miss)
4038	// switch directory slot to VALID state.
4039	// - If matching coherence request, switch directory slot
4040	// to ZOMBI state, and send a cleanup request.
4041	{
4042	if ( m_dreq.valid) m_cost_data_miss_frz++;
4043
4044	// coherence request (from CC_RECEIVE FSM)
4045	if ( r_cc_receive_dcache_req.read() )
4046	{
4047	r_dcache_fsm = DCACHE_CC_CHECK;
4048	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4049	break;
4050	}
4051
4052	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4053	{
4054	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4055	{
4056	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4057	{
4058	r_dcache_miss_inval = false;
4059	// request cleanup
4060	r_dcache_cc_send_req = true;
4061	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4062	r_dcache_cc_send_way = r_dcache_miss_way.read();
4063	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4064
4065	#ifdef INSTRUMENTATION
4066	m_cpt_dcache_dir_write++;
4067	#endif
4068	r_dcache.write_dir( r_dcache_save_paddr.read(),
4069	r_dcache_miss_way.read(),
4070	r_dcache_miss_set.read(),
4071	CACHE_SLOT_STATE_ZOMBI );
4072	#if DEBUG_DCACHE
4073	if ( m_debug_dcache_fsm )
4074	{
4075	std::cout << " <PROC " << name()
4076	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4077	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4078	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4079	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4080	}
4081	#endif
4082	}
4083	else
4084	break;
4085	}
4086	else // switch slot to VALID state
4087	{
4088
4089	#ifdef INSTRUMENTATION
4090	m_cpt_dcache_dir_write++;
4091	#endif
4092	r_dcache.write_dir( r_dcache_save_paddr.read(),
4093	r_dcache_miss_way.read(),
4094	r_dcache_miss_set.read(),
4095	CACHE_SLOT_STATE_VALID );
4096
4097	#if DEBUG_DCACHE
4098	if ( m_debug_dcache_fsm )
4099	{
4100	std::cout << " <PROC " << name()
4101	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4102	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4103	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4104	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4105
4106	r_dcache.printTrace();
4107
4108
4109	}
4110	#endif
4111	// reset directory extension
4112	size_t way = r_dcache_miss_way.read();
4113	size_t set = r_dcache_miss_set.read();
4114	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4115	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4116	}
4117	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4118	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4119	else r_dcache_fsm = DCACHE_IDLE;
4120	}
4121	break;
4122	}
4123	/////////////////////
4124	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4125	{
4126	// coherence request (from CC_RECEIVE FSM)
4127	if ( r_cc_receive_dcache_req.read() )
4128	{
4129	r_dcache_fsm = DCACHE_CC_CHECK;
4130	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4131	break;
4132	}
4133
4134	if ( r_vci_rsp_data_error.read() ) // bus error
4135	{
4136	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4137	r_mmu_dbvar = m_dreq.addr;
4138	r_vci_rsp_data_error = false;
4139	m_drsp.error = true;
4140	m_drsp.valid = true;
4141	r_dcache_fsm = DCACHE_IDLE;
4142	break;
4143	}
4144	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4145	{
4146	// consume data
4147	vci_rsp_fifo_dcache_get = true;
4148	r_dcache_fsm = DCACHE_IDLE;
4149
4150	// acknowledge the processor request if it has not been modified
4151	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4152	{
4153	m_drsp.valid = true;
4154	m_drsp.error = false;
4155	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4156	}
4157	}
4158	break;
4159	}
4160	/////////////////////
4161	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4162	{
4163	// coherence request (from CC_RECEIVE FSM)
4164	if ( r_cc_receive_dcache_req.read() )
4165	{
4166	r_dcache_fsm = DCACHE_CC_CHECK;
4167	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4168	break;
4169	}
4170
4171	if ( r_vci_rsp_data_error.read() ) // bus error
4172	{
4173	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4174	r_mmu_dbvar = m_dreq.addr;
4175	r_vci_rsp_data_error = false;
4176	m_drsp.error = true;
4177	m_drsp.valid = true;
4178	r_dcache_fsm = DCACHE_IDLE;
4179	break;
4180	}
4181	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4182	{
4183	// consume data
4184	vci_rsp_fifo_dcache_get = true;
4185
4186	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4187	{
4188	// set key value in llsc reservation buffer
4189	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4190	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4191	}
4192	else // last flit
4193	{
4194	// acknowledge the processor request if it has not been modified
4195	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4196	{
4197	m_drsp.valid = true;
4198	m_drsp.error = false;
4199	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4200	}
4201	r_dcache_fsm = DCACHE_IDLE;
4202	}
4203	}
4204	break;
4205	}
4206	////////////////////
4207	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4208	{
4209	// coherence request (from CC_RECEIVE FSM)
4210	if ( r_cc_receive_dcache_req.read() )
4211	{
4212	r_dcache_fsm = DCACHE_CC_CHECK;
4213	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4214	break;
4215	}
4216
4217	if ( r_vci_rsp_data_error.read() ) // bus error
4218	{
4219	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4220	r_mmu_dbvar = m_dreq.addr;
4221	r_vci_rsp_data_error = false;
4222	m_drsp.error = true;
4223	m_drsp.valid = true;
4224	r_dcache_fsm = DCACHE_IDLE;
4225	break;
4226	}
4227	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4228	{
4229	// consume response
4230	vci_rsp_fifo_dcache_get = true;
4231	m_drsp.valid = true;
4232	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4233	r_dcache_fsm = DCACHE_IDLE;
4234	}
4235	break;
4236	}
4237	//////////////////////////
4238	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4239	// before handling a processor WRITE or SC request
4240	// Input argument is r_dcache_dirty_paddr
4241	// In this first state, we get PTE value in dcache
4242	// and post a CAS request to CMD FSM
4243	{
4244	// get PTE in dcache
4245	uint32_t pte;
4246	size_t way;
4247	size_t set;
4248	size_t word; // unused
4249	int state;
4250
4251	#ifdef INSTRUMENTATION
4252	m_cpt_dcache_data_read++;
4253	m_cpt_dcache_dir_read++;
4254	#endif
4255	r_dcache.read( r_dcache_dirty_paddr.read(),
4256	&pte,
4257	&way,
4258	&set,
4259	&word,
4260	&state );
4261
4262	assert( (state == CACHE_SLOT_STATE_VALID) and
4263	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4264
4265	// request CAS transaction to CMD_FSM
4266	r_dcache_dirty_way = way;
4267	r_dcache_dirty_set = set;
4268
4269	// check llsc reservation buffer
4270	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4271	r_dcache_llsc_valid = false;
4272
4273	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4274	r_dcache_vci_cas_req = true;
4275	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4276	r_dcache_vci_cas_old = pte;
4277	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4278	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4279
4280	#if DEBUG_DCACHE
4281	if ( m_debug_dcache_fsm )
4282	{
4283	std::cout << " <PROC " << name()
4284	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4285	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4286	<< " / PTE_VALUE = " << pte << std::dec
4287	<< " / SET = " << set
4288	<< " / WAY = " << way << std::endl;
4289	}
4290	#endif
4291	break;
4292	}
4293	///////////////////////
4294	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4295	// and return to IDLE state when response is received.
4296	// we don't care if the CAS is a failure:
4297	// - if the CAS is a success, the coherence mechanism
4298	// updates the local copy.
4299	// - if the CAS is a failure, we just retry the write.
4300	{
4301	// coherence request (from CC_RECEIVE FSM)
4302	if ( r_cc_receive_dcache_req.read() )
4303	{
4304	r_dcache_fsm = DCACHE_CC_CHECK;
4305	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4306	break;
4307	}
4308
4309	if ( r_vci_rsp_data_error.read() ) // bus error
4310	{
4311	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4312	std::cout << "This should not happen in this state" << std::endl;
4313	exit(0);
4314	}
4315	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4316	{
4317	vci_rsp_fifo_dcache_get = true;
4318	r_dcache_fsm = DCACHE_IDLE;
4319
4320	#if DEBUG_DCACHE
4321	if ( m_debug_dcache_fsm )
4322	{
4323	std::cout << " <PROC " << name()
4324	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4325	}
4326	#endif
4327	}
4328	break;
4329	}
4330	/////////////////////
4331	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4332	// handling coherence requests for DCACHE.
4333	// If there is a matching pending miss on the modified cache
4334	// line this is signaled in the r_dcache_miss inval flip-flop.
4335	// If the updated (or invalidated) cache line has copies in TLBs
4336	// these TLB copies are invalidated.
4337	// The return state is defined in r_dcache_fsm_cc_save
4338	{
4339	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4340	paddr_t mask = ~((m_dcache_words<<2)-1);
4341
4342	#if DEBUG_DCACHE
4343	if ( m_debug_dcache_fsm )
4344	{
4345	std::cout << " <PROC " << name()
4346	<< " DCACHE_CC_CHECK> paddr = " << paddr
4347	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4348	<< " mask = " << mask
4349	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4350	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4351	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4352	<<std::endl;
4353	}
4354	#endif
4355
4356	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4357	// We switch the directory slot to EMPTY state
4358	// and reset r_icache_miss_clack if the cleanup ack
4359	// is matching a pending miss.
4360	{
4361
4362	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4363
4364	#ifdef INSTRUMENTATION
4365	m_cpt_dcache_dir_write++;
4366	#endif
4367	r_dcache.write_dir( 0,
4368	r_cc_receive_dcache_way.read(),
4369	r_cc_receive_dcache_set.read(),
4370	CACHE_SLOT_STATE_EMPTY);
4371
4372	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4373	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4374	r_dcache_miss_clack = false;
4375
4376	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4377	r_cc_receive_dcache_req = false;
4378	#if DEBUG_DCACHE
4379	if ( m_debug_dcache_fsm )
4380	{
4381	std::cout << " <PROC " << name()
4382	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4383	<< " set = " << r_cc_receive_dcache_set.read()
4384	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4385	}
4386	#endif
4387	}
4388	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4389	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4390	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4391	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4392	{
4393	// signaling matching
4394	r_dcache_miss_inval = true;
4395
4396	// in case of update, go to CC_UPDT
4397	// JUST TO POP THE FIFO
4398	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4399	{
4400	r_dcache_fsm = DCACHE_CC_UPDT;
4401	r_dcache_cc_word = r_cc_receive_word_idx.read();
4402	// just pop the fifo , don't write in icache
4403	r_dcache_cc_need_write = false;
4404	}
4405	// the request is dealt with
4406	else
4407	{
4408	r_cc_receive_dcache_req = false;
4409	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4410	}
4411
4412	#if DEBUG_DCACHE
4413	if ( m_debug_dcache_fsm )
4414	{
4415	std::cout << " <PROC " << name()
4416	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4417	<< " PADDR = " << std::hex << paddr << std::endl;
4418	}
4419	#endif
4420
4421	}
4422	else // no match
4423	{
4424	int state;
4425	size_t way;
4426	size_t set;
4427	size_t word;
4428
4429	#ifdef INSTRUMENTATION
4430	m_cpt_dcache_dir_read++;
4431	#endif
4432	r_dcache.read_dir( paddr,
4433	&state,
4434	&way,
4435	&set,
4436	&word ); // unused
4437
4438	r_dcache_cc_way = way;
4439	r_dcache_cc_set = set;
4440
4441	if ( state == CACHE_SLOT_STATE_VALID) // hit
4442	{
4443	// need to update the cache state
4444	r_dcache_cc_need_write = true;
4445	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4446	{
4447	r_dcache_fsm = DCACHE_CC_UPDT;
4448	r_dcache_cc_word = r_cc_receive_word_idx.read();
4449	}
4450	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4451	{
4452	r_dcache_fsm = DCACHE_CC_INVAL;
4453	}
4454	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4455	{
4456	r_dcache_fsm = DCACHE_CC_BROADCAST;
4457	}
4458	}
4459	else // miss
4460	{
4461	// multicast acknowledgement required in case of update
4462	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4463	{
4464	r_dcache_fsm = DCACHE_CC_UPDT;
4465	r_dcache_cc_word = r_cc_receive_word_idx.read();
4466	// just pop the fifo , don't write in icache
4467	r_dcache_cc_need_write = false;
4468	}
4469	else // No response needed
4470	{
4471	r_cc_receive_dcache_req = false;
4472	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4473	}
4474	}
4475
4476	#if DEBUG_DCACHE
4477	if ( m_debug_dcache_fsm )
4478	{
4479	std::cout << " <PROC " << name()
4480	<< " DCACHE_CC_CHECK> Coherence request received:"
4481	<< " PADDR = " << std::hex << paddr
4482	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4483	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4484	}
4485	#endif
4486	}
4487	break;
4488	}
4489	/////////////////////
4490	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4491	// after possible invalidation of copies in TLBs
4492	{
4493	size_t way = r_dcache_cc_way.read();
4494	size_t set = r_dcache_cc_set.read();
4495
4496	if (r_dcache_cc_need_write.read())
4497	{
4498	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4499	{
4500	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4501	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4502	r_dcache_tlb_inval_set = 0;
4503	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4504	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4505	break;
4506	}
4507	else
4508	{
4509	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4510	{
4511	r_itlb.reset();
4512	r_dtlb.reset();
4513	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4514
4515	#if DEBUG_DCACHE
4516	if ( m_debug_dcache_fsm )
4517	{
4518	std::cout << " <PROC " << name()
4519	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4520	}
4521	#endif
4522	}
4523
4524	r_dcache.write_dir( 0,
4525	way,
4526	set,
4527	CACHE_SLOT_STATE_EMPTY );
4528
4529	r_dcache_cc_need_write = false;
4530
4531	#if DEBUG_DCACHE
4532	if ( m_debug_dcache_fsm )
4533	{
4534	std::cout << " <PROC " << name()
4535	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4536	<< " / WAY = " << way
4537	<< " / SET = " << set << std::endl;
4538	}
4539	#endif
4540	}
4541	}
4542	// multicast acknowledgement
4543	// send a request to cc_send_fsm
4544	if(not r_dcache_cc_send_req.read()) // cc_send is available
4545	{
4546	// coherence request completed
4547	r_cc_receive_dcache_req = false;
4548	// request multicast acknowledgement
4549	r_dcache_cc_send_req = true;
4550	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4551	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4552	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4553
4554	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4555	}
4556	//else wait for previous cc_send request to be sent
4557	break;
4558	}
4559	///////////////////
4560	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4561	// after possible invalidation of copies in TLBs
4562	{
4563	size_t word = r_dcache_cc_word.read();
4564	size_t way = r_dcache_cc_way.read();
4565	size_t set = r_dcache_cc_set.read();
4566
4567	if (r_cc_receive_updt_fifo_be.rok())
4568	{
4569	if (r_dcache_cc_need_write.read())
4570	{
4571	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4572	{
4573	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4574	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4575	r_dcache_tlb_inval_set = 0;
4576	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4577	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4578	break;
4579	}
4580
4581	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4582	{
4583	r_itlb.reset();
4584	r_dtlb.reset();
4585	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4586
4587	#if DEBUG_DCACHE
4588	if ( m_debug_dcache_fsm )
4589	{
4590	std::cout << " <PROC " << name()
4591	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4592	}
4593	#endif
4594	}
4595
4596	#ifdef INSTRUMENTATION
4597	m_cpt_dcache_data_write++;
4598	#endif
4599	r_dcache.write( way,
4600	set,
4601	word,
4602	r_cc_receive_updt_fifo_data.read(),
4603	r_cc_receive_updt_fifo_be.read() );
4604
4605	r_dcache_cc_word = word + 1;
4606
4607	#if DEBUG_DCACHE
4608	if ( m_debug_dcache_fsm )
4609	{
4610	std::cout << " <PROC " << name()
4611	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4612	<< " / WAY = " << way
4613	<< " / SET = " << set
4614	<< " / WORD = " << word
4615	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4616	}
4617	#endif
4618	}
4619
4620	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4621	{
4622	// no need to write in the cache anymore
4623	r_dcache_cc_need_write = false;
4624
4625	// wait to send a request to cc_send_fsm
4626	if(not r_icache_cc_send_req.read())
4627	// cc_send is available
4628	{
4629	//consume last fifo flit if eop and request to cc_send possible
4630	cc_receive_updt_fifo_get = true;
4631
4632	// coherence request completed
4633	r_cc_receive_dcache_req = false;
4634
4635	// request multicast acknowledgement
4636	r_dcache_cc_send_req = true;
4637	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4638	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4639	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4640
4641	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4642	}
4643	}
4644	else
4645	{
4646	//consume fifo if not eop
4647	cc_receive_updt_fifo_get = true;
4648	}
4649	}
4650	break;
4651	}
4652	/////////////////////////
4653	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4654	// and request a cleanup, after possible
4655	// invalidation of copies in TLBs
4656	{
4657	size_t way = r_dcache_cc_way.read();
4658	size_t set = r_dcache_cc_set.read();
4659	paddr_t nline = r_cc_receive_dcache_nline.read();
4660
4661	if (r_dcache_cc_need_write.read())
4662	{
4663	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4664	{
4665	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4666	r_dcache_tlb_inval_line = nline;
4667	r_dcache_tlb_inval_set = 0;
4668	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4669	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4670	break;
4671	}
4672	else
4673	{
4674	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4675	{
4676	r_itlb.reset();
4677	r_dtlb.reset();
4678	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4679
4680	#if DEBUG_DCACHE
4681	if ( m_debug_dcache_fsm )
4682	{
4683	std::cout << " <PROC " << name()
4684	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4685	}
4686	#endif
4687	}
4688
4689	#ifdef INSTRUMENTATION
4690	m_cpt_dcache_dir_write++;
4691	#endif
4692	r_dcache.write_dir( way,
4693	set,
4694	CACHE_SLOT_STATE_ZOMBI );
4695
4696	r_dcache_cc_need_write = false;
4697	#if DEBUG_DCACHE
4698	if ( m_debug_dcache_fsm )
4699	{
4700	std::cout << " <PROC " << name()
4701	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4702	<< " SET = " << set
4703	<< " / WAY = " << way << std::endl;
4704	}
4705	#endif
4706	}
4707	}
4708	// cleanup
4709	// send a request to cc_send_fsm
4710	if(not r_dcache_cc_send_req.read()) // cc_send is available
4711	{
4712	// coherence request completed
4713	r_cc_receive_dcache_req = false;
4714	// request cleanup
4715	r_dcache_cc_send_req = true;
4716	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4717	r_dcache_cc_send_way = r_dcache_cc_way.read();
4718	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4719
4720	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4721	}
4722	//else wait for previous cc_send request to be sent
4723	break;
4724	}
4725	///////////////////////////
4726	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4727	// It makes assumption: m_itlb_sets == m_dtlb_sets
4728	// All ways are handled in parallel.
4729	// We enter this state when a DCACHE line is modified,
4730	// and there is a copy in itlb or dtlb.
4731	// It can be caused by:
4732	// - a coherence inval or updt transaction,
4733	// - a line inval caused by a cache miss
4734	// - a processor XTN inval request,
4735	// - a WRITE hit,
4736	// - a Dirty bit update
4737	// Input arguments are:
4738	// - r_dcache_tlb_inval_line
4739	// - r_dcache_tlb_inval_set
4740	// - r_dcache_fsm_scan_save
4741	{
4742	paddr_t line = r_dcache_tlb_inval_line.read();
4743	size_t set = r_dcache_tlb_inval_set.read();
4744	size_t way;
4745	bool ok;
4746
4747	for ( way = 0 ; way < m_itlb_ways ; way++ )
4748	{
4749	ok = r_itlb.inval( line, way, set );
4750
4751	#if DEBUG_DCACHE
4752	if ( m_debug_dcache_fsm and ok )
4753	{
4754	std::cout << " <PROC " << name()
4755	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4756	<< " line = " << line << std::dec
4757	<< " / set = " << set
4758	<< " / way = " << way << std::endl;
4759	}
4760	#endif
4761	}
4762
4763	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4764	{
4765	ok = r_dtlb.inval( line, way, set );
4766
4767	#if DEBUG_DCACHE
4768	if ( m_debug_dcache_fsm and ok )
4769	{
4770	std::cout << " <PROC " << name()
4771	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4772	<< " line = " << line << std::dec
4773	<< " / set = " << set
4774	<< " / way = " << way << std::endl;
4775	}
4776	#endif
4777	}
4778
4779	// return to the calling state when TLB inval completed
4780	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4781	{
4782	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4783	}
4784	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4785	break;
4786	}
4787	} // end switch r_dcache_fsm
4788
4789	///////////////// wbuf update ///////////////////////////////////////////////////////
4790	r_wbuf.update();
4791
4792	///////////////// llsc update ///////////////////////////////////////////////////////
4793	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4794	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4795
4796	//////////////// test processor frozen //////////////////////////////////////////////
4797	// The simulation exit if the number of consecutive frozen cycles
4798	// is larger than the m_max_frozen_cycles (constructor parameter)
4799	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4800	{
4801	m_cpt_frz_cycles++; // used for instrumentation
4802	m_cpt_stop_simulation++; // used for debug
4803	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4804	{
4805	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4806	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4807	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4808	<< std::endl;
4809	r_iss.dump();
4810	exit(1);
4811	}
4812	}
4813	else
4814	{
4815	m_cpt_stop_simulation = 0;
4816	}
4817
4818	/////////// execute one iss cycle /////////////////////////////////
4819	{
4820	uint32_t it = 0;
4821	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4822	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4823	}
4824
4825	////////////////////////////////////////////////////////////////////////////
4826	// The VCI_CMD FSM controls the following ressources:
4827	// - r_vci_cmd_fsm
4828	// - r_vci_cmd_min
4829	// - r_vci_cmd_max
4830	// - r_vci_cmd_cpt
4831	// - r_vci_cmd_imiss_prio
4832	// - wbuf (reset)
4833	// - r_icache_miss_req (reset)
4834	// - r_icache_unc_req (reset)
4835	// - r_dcache_vci_miss_req (reset)
4836	// - r_dcache_vci_unc_req (reset)
4837	// - r_dcache_vci_ll_req (reset)
4838	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4839	// - r_dcache_vci_cas_req (reset)
4840	//
4841	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4842	// There are 8 request types, with the following priorities :
4843	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4844	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4845	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4846	// 4 - Instruction Uncachable : r_icache_unc_req
4847	// 5 - Data Write : r_wbuf.rok()
4848	// 6 - Data Linked Load : r_dcache_vci_ll_req
4849	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4850	// 8 - Compare And Swap : r_dcache_vci_cas_req
4851	//
4852	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4853	// and the VCI_RSP_FSM are fully desynchronized.
4854	//
4855	// VCI formats:
4856	// According to the VCI advanced specification, all read requests packets
4857	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4858	// are one word packets.
4859	// For write burst packets, all words are in the same cache line,
4860	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4861	// The sc command packet implements actually a compare-and-swap mechanism
4862	// and the packet contains two flits.
4863	////////////////////////////////////////////////////////////////////////////////////
4864
4865	switch ( r_vci_cmd_fsm.read() )
4866	{
4867	//////////////
4868	case CMD_IDLE:
4869	{
4870	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4871	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4872	// to check a possible pending write on the same cache line.
4873	// As there is only one possible access per cycle to write buffer, we implement
4874	// a round-robin priority between DCACHE and ICACHE for this access,
4875	// using the r_vci_cmd_imiss_prio flip-flop.
4876
4877	size_t wbuf_min;
4878	size_t wbuf_max;
4879
4880	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4881	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4882
4883	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4884	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4885
4886	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4887	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4888
4889	bool icache_miss_req = r_icache_miss_req.read() and
4890	( not (r_dcache_vci_miss_req.read() or
4891	r_dcache_vci_ll_req.read() or
4892	r_dcache_vci_unc_req.read())
4893	or r_vci_cmd_imiss_prio.read() );
4894
4895
4896	// 1 - Data Read Miss
4897	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4898	{
4899	r_vci_cmd_fsm = CMD_DATA_MISS;
4900	r_dcache_vci_miss_req = false;
4901	r_vci_cmd_imiss_prio = true;
4902	// m_cpt_dmiss_transaction++;
4903	}
4904	// 2 - Data Read Uncachable
4905	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4906	{
4907	r_vci_cmd_fsm = CMD_DATA_UNC;
4908	r_dcache_vci_unc_req = false;
4909	// m_cpt_dunc_transaction++;
4910	}
4911	// 3 - Data Linked Load
4912	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4913	{
4914	r_dcache_vci_ll_req = false;
4915	r_vci_cmd_fsm = CMD_DATA_LL;
4916	// m_cpt_ll_transaction++;
4917	}
4918	// 4 - Instruction Miss
4919	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4920	{
4921	r_vci_cmd_fsm = CMD_INS_MISS;
4922	r_icache_miss_req = false;
4923	r_vci_cmd_imiss_prio = false;
4924	// m_cpt_imiss_transaction++;
4925	}
4926	// 5 - Instruction Uncachable
4927	else if ( r_icache_unc_req.read() )
4928	{
4929	r_vci_cmd_fsm = CMD_INS_UNC;
4930	r_icache_unc_req = false;
4931	// m_cpt_iunc_transaction++;
4932	}
4933	// 6 - Data Write
4934	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4935	{
4936	r_vci_cmd_fsm = CMD_DATA_WRITE;
4937	r_vci_cmd_cpt = wbuf_min;
4938	r_vci_cmd_min = wbuf_min;
4939	r_vci_cmd_max = wbuf_max;
4940	// m_cpt_write_transaction++;
4941	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4942	}
4943	// 7 - Data Store Conditionnal
4944	else if ( r_dcache_vci_sc_req.read() )
4945	{
4946	r_dcache_vci_sc_req = false;
4947	r_vci_cmd_cpt = 0;
4948	r_vci_cmd_fsm = CMD_DATA_SC;
4949	// m_cpt_sc_transaction++;
4950	}
4951	// 8 - Compare And Swap
4952	else if ( r_dcache_vci_cas_req.read() )
4953	{
4954	r_vci_cmd_fsm = CMD_DATA_CAS;
4955	r_dcache_vci_cas_req = false;
4956	r_vci_cmd_cpt = 0;
4957	// m_cpt_cas_transaction++;
4958	}
4959	break;
4960	}
4961	////////////////////
4962	case CMD_DATA_WRITE:
4963	{
4964	if ( p_vci.cmdack.read() )
4965	{
4966	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4967	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4968	{
4969	r_vci_cmd_fsm = CMD_IDLE ;
4970	r_wbuf.sent() ;
4971	}
4972	}
4973	break;
4974	}
4975	/////////////////
4976	case CMD_DATA_SC:
4977	case CMD_DATA_CAS:
4978	{
4979	// The CAS and SC VCI commands contain two flits
4980	if ( p_vci.cmdack.read() )
4981	{
4982	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4983	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4984	}
4985	break;
4986	}
4987	//////////////////
4988	case CMD_INS_MISS:
4989	case CMD_INS_UNC:
4990	case CMD_DATA_MISS:
4991	case CMD_DATA_UNC:
4992	case CMD_DATA_LL:
4993	{
4994	// all read VCI commands contain one single flit
4995	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4996	break;
4997	}
4998
4999	} // end switch r_vci_cmd_fsm
5000
5001	//////////////////////////////////////////////////////////////////////////
5002	// The VCI_RSP FSM controls the following ressources:
5003	// - r_vci_rsp_fsm:
5004	// - r_vci_rsp_fifo_icache (push)
5005	// - r_vci_rsp_fifo_dcache (push)
5006	// - r_vci_rsp_data_error (set)
5007	// - r_vci_rsp_ins_error (set)
5008	// - r_vci_rsp_cpt
5009	// - r_dcache_vci_sc_req (reset when SC response recieved)
5010	//
5011	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5012	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5013	// to identify the transactions.
5014	//
5015	// VCI vormat:
5016	// This component checks the response packet length and accepts only
5017	// single word packets for write response packets.
5018	//
5019	// Error handling:
5020	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5021	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5022	// flip_flop and the error is signaled by the DCACHE FSM.
5023	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5024	// flip_flop and the error is signaled by the ICACHE FSM.
5025	// In case of Cleanup Error, the simulation stops with an error message...
5026	//////////////////////////////////////////////////////////////////////////
5027
5028	switch ( r_vci_rsp_fsm.read() )
5029	{
5030	//////////////
5031	case RSP_IDLE:
5032	{
5033	if ( p_vci.rspval.read() )
5034	{
5035	r_vci_rsp_cpt = 0;
5036
5037	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5038	{
5039	r_vci_rsp_fsm = RSP_DATA_UNC;
5040	}
5041	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5042	{
5043	r_vci_rsp_fsm = RSP_DATA_MISS;
5044	}
5045	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5046	{
5047	r_vci_rsp_fsm = RSP_INS_UNC;
5048	}
5049	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5050	{
5051	r_vci_rsp_fsm = RSP_INS_MISS;
5052	}
5053	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5054	{
5055	r_vci_rsp_fsm = RSP_DATA_WRITE;
5056	}
5057	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5058	{
5059	r_vci_rsp_fsm = RSP_DATA_UNC;
5060	}
5061	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5062	{
5063	r_vci_rsp_fsm = RSP_DATA_LL;
5064	}
5065	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5066	{
5067	r_vci_rsp_fsm = RSP_DATA_UNC;
5068	}
5069	else
5070	{
5071	assert(false and "Unexpected VCI response");
5072	}
5073	}
5074	break;
5075	}
5076	//////////////////
5077	case RSP_INS_MISS:
5078	{
5079	if ( p_vci.rspval.read() )
5080	{
5081	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5082	{
5083	r_vci_rsp_ins_error = true;
5084	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5085	}
5086	else // no error reported
5087	{
5088	if ( r_vci_rsp_fifo_icache.wok() )
5089	{
5090	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5091	"The VCI response packet for instruction miss is too long" );
5092
5093	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5094	vci_rsp_fifo_icache_put = true,
5095	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5096	if ( p_vci.reop.read() )
5097	{
5098	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5099	"The VCI response packet for instruction miss is too short");
5100
5101	r_vci_rsp_fsm = RSP_IDLE;
5102	}
5103	}
5104	}
5105	}
5106	break;
5107	}
5108	/////////////////
5109	case RSP_INS_UNC:
5110	{
5111	if (p_vci.rspval.read() )
5112	{
5113	assert( p_vci.reop.read() and
5114	"illegal VCI response packet for uncachable instruction");
5115
5116	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5117	{
5118	r_vci_rsp_ins_error = true;
5119	r_vci_rsp_fsm = RSP_IDLE;
5120	}
5121	else // no error reported
5122	{
5123	if ( r_vci_rsp_fifo_icache.wok())
5124	{
5125	vci_rsp_fifo_icache_put = true;
5126	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5127	r_vci_rsp_fsm = RSP_IDLE;
5128	}
5129	}
5130	}
5131	break;
5132	}
5133	///////////////////
5134	case RSP_DATA_MISS:
5135	{
5136	if ( p_vci.rspval.read() )
5137	{
5138	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5139	{
5140	r_vci_rsp_data_error = true;
5141	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5142	}
5143	else // no error reported
5144	{
5145	if ( r_vci_rsp_fifo_dcache.wok() )
5146	{
5147	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5148	"The VCI response packet for data miss is too long");
5149
5150	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5151	vci_rsp_fifo_dcache_put = true,
5152	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5153	if ( p_vci.reop.read() )
5154	{
5155	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5156	"The VCI response packet for data miss is too short");
5157
5158	r_vci_rsp_fsm = RSP_IDLE;
5159	}
5160	}
5161	}
5162	}
5163	break;
5164	}
5165	//////////////////
5166	case RSP_DATA_UNC:
5167	{
5168	if (p_vci.rspval.read() )
5169	{
5170	assert( p_vci.reop.read() and
5171	"illegal VCI response packet for uncachable read data");
5172
5173	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5174	{
5175	r_vci_rsp_data_error = true;
5176	r_vci_rsp_fsm = RSP_IDLE;
5177	}
5178	else // no error reported
5179	{
5180	if ( r_vci_rsp_fifo_dcache.wok())
5181	{
5182	vci_rsp_fifo_dcache_put = true;
5183	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5184	r_vci_rsp_fsm = RSP_IDLE;
5185	}
5186	}
5187	}
5188	break;
5189	}
5190	////////////////////
5191	case RSP_DATA_LL:
5192	{
5193	if ( p_vci.rspval.read() )
5194	{
5195	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5196	{
5197	r_vci_rsp_data_error = true;
5198	r_vci_rsp_fsm = RSP_IDLE;
5199	}
5200	if (r_vci_rsp_cpt.read() == 0) //first flit
5201	{
5202	if(r_vci_rsp_fifo_dcache.wok())
5203	{
5204	assert(!p_vci.reop.read() &&
5205	"illegal VCI response packet for LL");
5206	vci_rsp_fifo_dcache_put = true;
5207	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5208	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5209	}
5210	break;
5211	}
5212	else // last flit
5213	{
5214	if(r_vci_rsp_fifo_dcache.wok())
5215	{
5216	assert(p_vci.reop.read() &&
5217	"illegal VCI response packet for LL");
5218	vci_rsp_fifo_dcache_put = true;
5219	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5220	r_vci_rsp_fsm = RSP_IDLE;
5221	}
5222	break;
5223	}
5224	}
5225	break;
5226	}
5227	////////////////////
5228	case RSP_DATA_WRITE:
5229	{
5230	if (p_vci.rspval.read())
5231	{
5232	assert( p_vci.reop.read() and
5233	"a VCI response packet must contain one flit for a write transaction");
5234
5235	r_vci_rsp_fsm = RSP_IDLE;
5236	uint32_t wbuf_index = p_vci.rtrdid.read();
5237	bool cacheable = r_wbuf.completed(wbuf_index);
5238	if ( not cacheable ) r_dcache_pending_unc_write = false;
5239	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5240	}
5241	break;
5242	}
5243	} // end switch r_vci_rsp_fsm
5244
5245	/////////////////////////////////////////////////////////////////////////////////////
5246	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5247	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5248	// and ICACHE FSM) that are served with a round-robin priority.
5249	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5250	// soon as the request has been sent.
5251	/////////////////////////////////////////////////////////////////////////////////////
5252	switch ( r_cc_send_fsm.read() )
5253	{
5254	///////////////////////////
5255	case CC_SEND_IDLE:
5256	{
5257	///////////////////////////////////////////////////////
5258	// handling round robin between icache and dcache : //
5259	// we first check for the last client and listen for //
5260	// a request of the other, then update the client //
5261	///////////////////////////////////////////////////////
5262	// r_cc_send_last_client : 0 dcache / 1 icache
5263	bool update_last_client = r_cc_send_last_client.read();
5264	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5265	{
5266	if (r_icache_cc_send_req.read()) // request from icache
5267	update_last_client = 1; // update last client to icache
5268	}
5269	else // last client was icache
5270	{
5271	if (r_dcache_cc_send_req.read()) // request from dcache
5272	update_last_client = 0; // update last client to dcache
5273	}
5274	r_cc_send_last_client = update_last_client;
5275
5276	// if there is an actual request
5277	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5278	{
5279	// test if the new client is dcache and has a cleanup request
5280	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5281	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5282	// test if the new client is dcache and has a multi acknowledgement request
5283	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5284	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5285	// test if the new client is icache and has a cleanup request
5286	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5287	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5288	// test if the new client is icache and has a multi acknowledgement request
5289	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5290	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5291	}
5292	break;
5293	}
5294	///////////////////////////
5295	case CC_SEND_CLEANUP_1:
5296	{
5297	// wait for the first flit to be consumed
5298	if (p_dspin_out.read.read())
5299	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5300
5301	break;
5302	}
5303	///////////////////////////
5304	case CC_SEND_CLEANUP_2:
5305	{
5306	// wait for the second flit to be consumed
5307	if (p_dspin_out.read.read())
5308	{
5309	if (r_cc_send_last_client.read() == 0) // dcache active request
5310	r_dcache_cc_send_req = false; // reset dcache request
5311	else // icache active request
5312	r_icache_cc_send_req = false; // reset icache request
5313
5314	// go back to idle state
5315	r_cc_send_fsm = CC_SEND_IDLE;
5316	}
5317	break;
5318	}
5319	///////////////////////////
5320	case CC_SEND_MULTI_ACK:
5321	{
5322	// wait for the flit to be consumed
5323	if(p_dspin_out.read.read())
5324	{
5325	if(r_cc_send_last_client.read() == 0) // dcache active request
5326	r_dcache_cc_send_req = false; // reset dcache request
5327	else // icache active request
5328	r_icache_cc_send_req = false; // reset icache request
5329	// go back to idle state
5330	r_cc_send_fsm = CC_SEND_IDLE;
5331	}
5332	break;
5333	}
5334	} // end switch CC_SEND FSM
5335
5336	///////////////////////////////////////////////////////////////////////////////
5337	// C_RECEIVE FSM
5338	// This FSM receive all coherence packets on a DSPIN40 port.
5339	// There is 4 packet types:
5340	// - CC_DATA_INVAL : DCACHE invalidate request
5341	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5342	// - CC_INST_INVAL : ICACHE invalidate request
5343	// - CC_INST_UPDT : ICACHE update request (multi-words)
5344	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5345	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5346	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5347	//////////////////////////////////////////////////////////////////////////////
5348	switch( r_cc_receive_fsm.read() )
5349	{
5350	/////////////////////
5351	case CC_RECEIVE_IDLE:
5352	{
5353	// a coherence request has arrived
5354	if (p_dspin_in.write.read())
5355	{
5356	// initialize dspin received data
5357	uint64_t receive_data = p_dspin_in.data.read();
5358	// initialize coherence packet type
5359	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5360	// initialize data/ins flip_flop (0 data / 1 ins)
5361	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5362	// test for a broadcast
5363	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5364	{
5365	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5366	}
5367	// test for a CLACK
5368	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5369	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5370	{
5371	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5372	}
5373	// test for a multi updt
5374	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5375	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5376	{
5377	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5378	}
5379	// test for a multi inval
5380	else
5381	{
5382	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5383	}
5384	}
5385	break;
5386	}
5387	//////////////////////
5388	case CC_RECEIVE_CLACK:
5389	{
5390	// initialize dspin received data
5391	uint64_t receive_data = p_dspin_in.data.read();
5392
5393	// for data CLACK, wait for dcache to take the request
5394	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5395	{
5396	// request dcache to handle the CLACK
5397	r_cc_receive_dcache_req = true;
5398	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5399	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5400	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5401	// get back to idle state
5402	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5403	break;
5404	}
5405	// for ins CLACK, wait for icache to take the request
5406	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5407	{
5408	// request icache to handle the CLACK
5409	r_cc_receive_icache_req = true;
5410	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5411	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5412	r_cc_receive_icache_type = CC_TYPE_CLACK;
5413	// get back to idle state
5414	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5415	break;
5416	}
5417	// keep waiting for the correct cache to accept the request
5418	break;
5419	}
5420	///////////////////////////////
5421	case CC_RECEIVE_BRDCAST_HEADER:
5422	{
5423	// no actual data in the HEADER, just skip to second flit
5424	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5425	break;
5426	}
5427	//////////////////////////////
5428	case CC_RECEIVE_BRDCAST_NLINE:
5429	{
5430	// initialize dspin received data
5431	uint64_t receive_data = p_dspin_in.data.read();
5432	// wait for both dcache and icache to take the request
5433	// TODO maybe we need to wait for both only to leave the state, but
5434	// not to actually post a request to an available cache => need a
5435	// flip_flop to check that ?
5436	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5437	{
5438	// request dcache to handle the BROADCAST
5439	r_cc_receive_dcache_req = true;
5440	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5441	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5442	// request icache to handle the BROADCAST
5443	r_cc_receive_icache_req = true;
5444	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5445	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5446	// get back to idle state
5447	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5448	break;
5449	}
5450	// keep waiting for the caches to accept the request
5451	break;
5452	}
5453	/////////////////////////////
5454	case CC_RECEIVE_INVAL_HEADER:
5455	{
5456	// sample updt tab index in the HEADER, then skip to second flit
5457	uint64_t receive_data = p_dspin_in.data.read();
5458	// for data INVAL, wait for dcache to take the request
5459	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5460	{
5461	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5462	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5463	break;
5464	}
5465	// for ins INVAL, wait for icache to take the request
5466	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5467	{
5468	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5469	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5470	break;
5471	}
5472	// keep waiting for the correct cache to accept the request
5473	break;
5474	}
5475	////////////////////////////
5476	case CC_RECEIVE_INVAL_NLINE:
5477	{
5478	// sample nline in the second flit
5479	uint64_t receive_data = p_dspin_in.data.read();
5480	// for data INVAL, wait for dcache to take the request
5481	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5482	{
5483	// request dcache to handle the INVAL
5484	r_cc_receive_dcache_req = true;
5485	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5486	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5487	// get back to idle state
5488	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5489	break;
5490	}
5491	// for ins INVAL, wait for icache to take the request
5492	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5493	{
5494	// request icache to handle the INVAL
5495	r_cc_receive_icache_req = true;
5496	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5497	r_cc_receive_icache_type = CC_TYPE_INVAL;
5498	// get back to idle state
5499	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5500	break;
5501	}
5502	// we should never get there
5503	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5504	}
5505	////////////////////////////
5506	case CC_RECEIVE_UPDT_HEADER:
5507	{
5508	// sample updt tab index in the HEADER, than skip to second flit
5509	uint64_t receive_data = p_dspin_in.data.read();
5510	// for data INVAL, wait for dcache to take the request and fifo to
5511	// be empty
5512	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5513	{
5514	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5515	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5516	break;
5517	}
5518	// for ins INVAL, wait for icache to take the request and fifo to be
5519	// empty
5520	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5521	{
5522	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5523	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5524	break;
5525	}
5526	// keep waiting for the correct cache to accept the request
5527	break;
5528	}
5529	///////////////////////////
5530	case CC_RECEIVE_UPDT_NLINE:
5531	{
5532	// sample nline and word index in the second flit
5533	uint64_t receive_data = p_dspin_in.data.read();
5534	// for data INVAL, wait for dcache to take the request and fifo to
5535	// be empty
5536	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5537	{
5538	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5539	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5540	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5541	// get back to idle state
5542	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5543	break;
5544	}
5545	// for ins INVAL, wait for icache to take the request and fifo to be
5546	// empty
5547	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5548	{
5549	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5550	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5551	r_cc_receive_icache_type = CC_TYPE_UPDT;
5552	// get back to idle state
5553	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5554	break;
5555	}
5556	// we should never get there
5557	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5558	break;
5559	}
5560	//////////////////////////
5561	case CC_RECEIVE_UPDT_DATA:
5562	{
5563	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5564	r_cc_receive_dcache_req = true;
5565	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5566	r_cc_receive_icache_req = true;
5567
5568	// sample data, be and eop
5569	uint64_t receive_data = p_dspin_in.data.read();
5570	// wait for the fifo
5571	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5572	{
5573	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5574	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5575	// sample eop to test for state exit
5576	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5577	cc_receive_updt_fifo_eop = flit_eop;
5578	cc_receive_updt_fifo_put = true;
5579	if(flit_eop)
5580	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5581	}
5582	break;
5583	}
5584	} // end switch CC_RECEIVE FSM
5585
5586	///////////////// Response FIFOs update //////////////////////
5587	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5588	vci_rsp_fifo_icache_put,
5589	vci_rsp_fifo_icache_data);
5590
5591	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5592	vci_rsp_fifo_dcache_put,
5593	vci_rsp_fifo_dcache_data);
5594
5595	///////////////// updt FIFO update //////////////////////
5596	//TODO check this
5597	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5598	cc_receive_updt_fifo_put,
5599	cc_receive_updt_fifo_be);
5600	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5601	cc_receive_updt_fifo_put,
5602	cc_receive_updt_fifo_data);
5603	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5604	cc_receive_updt_fifo_put,
5605	cc_receive_updt_fifo_eop);
5606
5607	} // end transition()
5608
5609	///////////////////////
5610	tmpl(void)::genMoore()
5611	///////////////////////
5612	{
5613
5614	// VCI initiator command on the direct network
5615	// it depends on the CMD FSM state
5616
5617	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5618	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5619
5620	p_vci.pktid = 0;
5621	p_vci.srcid = m_srcid;
5622	p_vci.cons = is_sc_or_cas;
5623	p_vci.contig = not is_sc_or_cas;
5624	p_vci.wrap = false;
5625	p_vci.clen = 0;
5626	p_vci.cfixed = false;
5627
5628	switch ( r_vci_cmd_fsm.read() ) {
5629
5630	case CMD_IDLE:
5631	p_vci.cmdval = false;
5632	p_vci.address = 0;
5633	p_vci.wdata = 0;
5634	p_vci.be = 0;
5635	p_vci.trdid = 0;
5636	p_vci.pktid = 0;
5637	p_vci.plen = 0;
5638	p_vci.cmd = vci_param::CMD_NOP;
5639	p_vci.eop = false;
5640	break;
5641
5642	case CMD_INS_MISS:
5643	p_vci.cmdval = true;
5644	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5645	p_vci.wdata = 0;
5646	p_vci.be = 0xF;
5647	p_vci.trdid = 0;
5648	p_vci.pktid = TYPE_READ_INS_MISS;
5649	p_vci.plen = m_icache_words<<2;
5650	p_vci.cmd = vci_param::CMD_READ;
5651	p_vci.eop = true;
5652	break;
5653
5654	case CMD_INS_UNC:
5655	p_vci.cmdval = true;
5656	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5657	p_vci.wdata = 0;
5658	p_vci.be = 0xF;
5659	p_vci.trdid = 0;
5660	p_vci.pktid = TYPE_READ_INS_UNC;
5661	p_vci.plen = 4;
5662	p_vci.cmd = vci_param::CMD_READ;
5663	p_vci.eop = true;
5664	break;
5665
5666	case CMD_DATA_MISS:
5667	p_vci.cmdval = true;
5668	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5669	p_vci.wdata = 0;
5670	p_vci.be = 0xF;
5671	p_vci.trdid = 0;
5672	p_vci.pktid = TYPE_READ_DATA_MISS;
5673	p_vci.plen = m_dcache_words << 2;
5674	p_vci.cmd = vci_param::CMD_READ;
5675	p_vci.eop = true;
5676	break;
5677
5678	case CMD_DATA_UNC:
5679	p_vci.cmdval = true;
5680	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5681	p_vci.wdata = 0;
5682	p_vci.be = r_dcache_vci_unc_be.read();
5683	p_vci.trdid = 0;
5684	p_vci.pktid = TYPE_READ_DATA_UNC;
5685	p_vci.plen = 4;
5686	p_vci.cmd = vci_param::CMD_READ;
5687	p_vci.eop = true;
5688	break;
5689
5690	case CMD_DATA_WRITE:
5691	p_vci.cmdval = true;
5692	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5693	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5694	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5695	p_vci.trdid = r_wbuf.getIndex();
5696	p_vci.pktid = TYPE_WRITE;
5697	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5698	p_vci.cmd = vci_param::CMD_WRITE;
5699	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5700	break;
5701
5702	case CMD_DATA_LL:
5703	p_vci.cmdval = true;
5704	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5705	p_vci.wdata = 0;
5706	p_vci.be = 0xF;
5707	p_vci.trdid = 0;
5708	p_vci.pktid = TYPE_LL;
5709	p_vci.plen = 8;
5710	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5711	p_vci.eop = true;
5712	break;
5713
5714	case CMD_DATA_SC:
5715	p_vci.cmdval = true;
5716	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5717	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5718	else p_vci.wdata = r_dcache_vci_sc_data.read();
5719	p_vci.be = 0xF;
5720	p_vci.trdid = 0;
5721	p_vci.pktid = TYPE_SC;
5722	p_vci.plen = 8;
5723	p_vci.cmd = vci_param::CMD_NOP;
5724	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5725	break;
5726
5727	case CMD_DATA_CAS:
5728	p_vci.cmdval = true;
5729	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5730	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5731	else p_vci.wdata = r_dcache_vci_cas_new.read();
5732	p_vci.be = 0xF;
5733	p_vci.trdid = 0;
5734	p_vci.pktid = TYPE_CAS;
5735	p_vci.plen = 8;
5736	p_vci.cmd = vci_param::CMD_NOP;
5737	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5738	break;
5739	} // end switch r_vci_cmd_fsm
5740
5741	// VCI initiator response on the direct network
5742	// it depends on the VCI_RSP FSM
5743
5744	switch (r_vci_rsp_fsm.read() )
5745	{
5746	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5747	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5748	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5749	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5750	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5751	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5752	case RSP_IDLE : p_vci.rspack = false; break;
5753	} // end switch r_vci_rsp_fsm
5754
5755
5756	// Send coherence packets on DSPIN L2M
5757	// it depends on the CC_SEND FSM
5758
5759	uint64_t dspin_send_data = 0;
5760	switch ( r_cc_send_fsm.read() )
5761	{
5762	//////////////////
5763	case CC_SEND_IDLE:
5764	{
5765	p_dspin_out.write = false;
5766	break;
5767	}
5768	///////////////////////
5769	case CC_SEND_CLEANUP_1:
5770	{
5771	// initialize dspin send data
5772	DspinDhccpParam::dspin_set(dspin_send_data,
5773	0,
5774	DspinDhccpParam::FROM_L1_EOP);
5775	DspinDhccpParam::dspin_set(dspin_send_data,
5776	m_cc_global_id,
5777	DspinDhccpParam::CLEANUP_SRCID);
5778	DspinDhccpParam::dspin_set(dspin_send_data,
5779	0,
5780	DspinDhccpParam::FROM_L1_BC);
5781
5782	if(r_cc_send_last_client.read() == 0) // dcache active request
5783	{
5784	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5785	>> (m_nline_width - m_x_width - m_y_width)
5786	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5787
5788	DspinDhccpParam::dspin_set(dspin_send_data,
5789	dest,
5790	DspinDhccpParam::CLEANUP_DEST);
5791
5792	DspinDhccpParam::dspin_set(dspin_send_data,
5793	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5794	DspinDhccpParam::CLEANUP_NLINE_MSB);
5795
5796	DspinDhccpParam::dspin_set(dspin_send_data,
5797	r_dcache_cc_send_way.read(),
5798	DspinDhccpParam::CLEANUP_WAY_INDEX);
5799
5800	DspinDhccpParam::dspin_set(dspin_send_data,
5801	DspinDhccpParam::TYPE_CLEANUP_DATA,
5802	DspinDhccpParam::FROM_L1_TYPE);
5803	}
5804	else // icache active request
5805	{
5806	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5807	>> (m_nline_width - m_x_width - m_y_width)
5808	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5809
5810	DspinDhccpParam::dspin_set(dspin_send_data,
5811	dest,
5812	DspinDhccpParam::CLEANUP_DEST);
5813
5814	DspinDhccpParam::dspin_set(dspin_send_data,
5815	r_icache_cc_send_nline.read() & 0x300000000ULL,
5816	DspinDhccpParam::CLEANUP_NLINE_MSB);
5817
5818	DspinDhccpParam::dspin_set(dspin_send_data,
5819	r_icache_cc_send_way.read(),
5820	DspinDhccpParam::CLEANUP_WAY_INDEX);
5821
5822	DspinDhccpParam::dspin_set(dspin_send_data,
5823	DspinDhccpParam::TYPE_CLEANUP_INST,
5824	DspinDhccpParam::FROM_L1_TYPE);
5825	}
5826	// send flit
5827	p_dspin_out.data = dspin_send_data;
5828	p_dspin_out.write = true;
5829	break;
5830	}
5831	///////////////////////
5832	case CC_SEND_CLEANUP_2:
5833	{
5834	// initialize dspin send data
5835	DspinDhccpParam::dspin_set(dspin_send_data,
5836	1,
5837	DspinDhccpParam::FROM_L1_EOP);
5838
5839	if(r_cc_send_last_client.read() == 0) // dcache active request
5840	{
5841	DspinDhccpParam::dspin_set(dspin_send_data,
5842	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5843	DspinDhccpParam::CLEANUP_NLINE_LSB);
5844	}
5845	else // icache active request
5846	{
5847	DspinDhccpParam::dspin_set(dspin_send_data,
5848	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5849	DspinDhccpParam::CLEANUP_NLINE_LSB);
5850	}
5851	// send flit
5852	p_dspin_out.data = dspin_send_data;
5853	p_dspin_out.write = true;
5854	break;
5855	}
5856	///////////////////////
5857	case CC_SEND_MULTI_ACK:
5858	{
5859	// initialize dspin send data
5860	DspinDhccpParam::dspin_set(dspin_send_data,
5861	1,
5862	DspinDhccpParam::FROM_L1_EOP);
5863	DspinDhccpParam::dspin_set(dspin_send_data,
5864	0,
5865	DspinDhccpParam::FROM_L1_BC);
5866	DspinDhccpParam::dspin_set(dspin_send_data,
5867	DspinDhccpParam::TYPE_MULTI_ACK,
5868	DspinDhccpParam::FROM_L1_TYPE);
5869
5870	if(r_cc_send_last_client.read() == 0) // dcache active request
5871	{
5872	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5873	>> (m_nline_width - m_x_width - m_y_width)
5874	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5875
5876	DspinDhccpParam::dspin_set(dspin_send_data,
5877	dest,
5878	DspinDhccpParam::MULTI_ACK_DEST);
5879
5880	DspinDhccpParam::dspin_set(dspin_send_data,
5881	r_dcache_cc_send_updt_tab_idx.read(),
5882	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5883	}
5884	else // icache active request
5885	{
5886	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5887	>> (m_nline_width - m_x_width - m_y_width)
5888	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5889
5890
5891	DspinDhccpParam::dspin_set(dspin_send_data,
5892	dest,
5893	DspinDhccpParam::MULTI_ACK_DEST);
5894
5895	DspinDhccpParam::dspin_set(dspin_send_data,
5896	r_icache_cc_send_updt_tab_idx.read(),
5897	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5898	}
5899	// send flit
5900	p_dspin_out.data = dspin_send_data;
5901	p_dspin_out.write = true;
5902
5903	break;
5904	}
5905	} // end switch CC_SEND FSM
5906
5907	// Receive coherence packets
5908	// It depends on the CC_RECEIVE FSM
5909
5910	switch( r_cc_receive_fsm.read() )
5911	{
5912	/////////////////////
5913	case CC_RECEIVE_IDLE:
5914	{
5915	p_dspin_in.read = false;
5916	break;
5917	}
5918	//////////////////////
5919	case CC_RECEIVE_CLACK:
5920	{
5921	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5922	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5923	p_dspin_in.read = true;
5924	else
5925	p_dspin_in.read = false;
5926	break;
5927	}
5928	///////////////////////////////
5929	case CC_RECEIVE_BRDCAST_HEADER:
5930	{
5931	p_dspin_in.read = true;
5932	break;
5933	}
5934	//////////////////////////////
5935	case CC_RECEIVE_BRDCAST_NLINE:
5936	{
5937	// TODO maybe we need to wait for both only to leave the state, but
5938	// not to actually post a request to an available cache => need a
5939	// flip_flop to check that ?
5940	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5941	p_dspin_in.read = true;
5942	else
5943	p_dspin_in.read = false;
5944	break;
5945	}
5946	/////////////////////////////
5947	case CC_RECEIVE_INVAL_HEADER:
5948	{
5949	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5950	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5951	p_dspin_in.read = true;
5952	else
5953	p_dspin_in.read = false;
5954	break;
5955	}
5956	////////////////////////////
5957	case CC_RECEIVE_INVAL_NLINE:
5958	{
5959	p_dspin_in.read = true;
5960	break;
5961	}
5962	////////////////////////////
5963	case CC_RECEIVE_UPDT_HEADER:
5964	{
5965	if (((r_cc_receive_data_ins.read() == 0) and
5966	not r_cc_receive_dcache_req.read() and
5967	r_cc_receive_updt_fifo_be.empty())
5968	or
5969	((r_cc_receive_data_ins.read() == 1) and
5970	not r_cc_receive_icache_req.read()) and
5971	r_cc_receive_updt_fifo_be.empty())
5972	p_dspin_in.read = true;
5973	else
5974	p_dspin_in.read = false;
5975	break;
5976	}
5977	///////////////////////////
5978	case CC_RECEIVE_UPDT_NLINE:
5979	{
5980	if (((r_cc_receive_data_ins.read() == 0) and
5981	not (r_cc_receive_dcache_req.read()) and
5982	r_cc_receive_updt_fifo_be.empty())
5983	or
5984	((r_cc_receive_data_ins.read() == 1) and
5985	not (r_cc_receive_icache_req.read()) and
5986	r_cc_receive_updt_fifo_be.empty()))
5987	p_dspin_in.read = true;
5988	else
5989	p_dspin_in.read = false;
5990	break;
5991	}
5992	//////////////////////////
5993	case CC_RECEIVE_UPDT_DATA:
5994	{
5995	if (r_cc_receive_updt_fifo_be.wok())
5996	p_dspin_in.read = true;
5997	else
5998	p_dspin_in.read = false;
5999	break;
6000	}
6001	} // end switch CC_RECEIVE FSM
6002
6003	} // end genMoore
6004
6005	}}
6006
6007	// Local Variables:
6008	// tab-width: 4
6009	// c-basic-offset: 4
6010	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6011	// indent-tabs-mode: nil
6012	// End:
6013
6014	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0