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vci_cc_vcache_wrapper2_v1.h @ 139

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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper2_v1.h
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
28	#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
29
30	#include <inttypes.h>
31	#include <systemc>
32	#include "caba_base_module.h"
33	#include "write_buffer.h"
34	#include "generic_cache.h"
35	#include "vci_initiator.h"
36	#include "vci_target.h"
37	#include "mapping_table.h"
38	#include "generic_tlb.h"
39	#include "static_assert.h"
40
41	namespace soclib {
42	namespace caba {
43
44	using namespace sc_core;
45
46	////////////////////////////////////////////
47	template<typename vci_param, typename iss_t>
48	class VciCcVCacheWrapper2V1
49	////////////////////////////////////////////
50	: public soclib::caba::BaseModule
51	{
52	typedef uint32_t vaddr_t;
53	typedef uint32_t data_t;
54	typedef uint32_t tag_t;
55	typedef uint32_t type_t;
56	typedef typename iss_t::DataOperationType data_op_t;
57
58	typedef typename vci_param::addr_t paddr_t;
59	typedef typename vci_param::be_t vci_be_t;
60	typedef typename vci_param::srcid_t vci_srcid_t;
61	typedef typename vci_param::trdid_t vci_trdid_t;
62	typedef typename vci_param::pktid_t vci_pktid_t;
63	typedef typename vci_param::plen_t vci_plen_t;
64
65	enum icache_fsm_state_e {
66	ICACHE_IDLE, // 00
67	ICACHE_BIS, // 01
68	ICACHE_TLB1_READ, // 02
69	ICACHE_TLB1_WRITE, // 03
70	ICACHE_TLB1_UPDT_SEL, // 04
71	ICACHE_TLB1_UPDT, // 05
72	ICACHE_TLB2_READ, // 06
73	ICACHE_TLB2_WRITE, // 07
74	ICACHE_TLB2_UPDT_SEL, // 08
75	ICACHE_TLB2_UPDT, // 09
76	ICACHE_SW_FLUSH, // 0a
77	ICACHE_TLB_FLUSH, // 0b
78	ICACHE_CACHE_FLUSH, // 0c
79	ICACHE_TLB_INVAL, // 0d
80	ICACHE_CACHE_INVAL, // 0e
81	ICACHE_CACHE_INVAL_PA, // 0f
82	ICACHE_MISS_WAIT, // 10
83	ICACHE_UNC_WAIT, // 11
84	ICACHE_MISS_UPDT, // 12
85	ICACHE_ERROR, // 13
86	ICACHE_CC_INVAL, // 14
87	ICACHE_TLB_CC_INVAL, // 15
88	};
89
90	enum dcache_fsm_state_e {
91	DCACHE_IDLE, // 00
92	DCACHE_BIS, // 01
93	DCACHE_DTLB1_READ_CACHE, // 02
94	DCACHE_TLB1_LL_WAIT, // 03
95	DCACHE_TLB1_SC_WAIT, // 04
96	DCACHE_TLB1_READ, // 05
97	DCACHE_TLB1_READ_UPDT, // 06
98	DCACHE_TLB1_UPDT_SEL, // 07
99	DCACHE_TLB1_UPDT, // 08
100	DCACHE_DTLB2_READ_CACHE, // 09
101	DCACHE_TLB2_LL_WAIT, // 0a
102	DCACHE_TLB2_SC_WAIT, // 0b
103	DCACHE_TLB2_READ, // 0c
104	DCACHE_TLB2_READ_UPDT, // 0d
105	DCACHE_TLB2_UPDT_SEL, // 0e
106	DCACHE_TLB2_UPDT, // 0f
107	DCACHE_CTXT_SWITCH, // 10
108	DCACHE_ICACHE_FLUSH, // 11
109	DCACHE_DCACHE_FLUSH, // 12
110	DCACHE_ITLB_INVAL, // 13
111	DCACHE_DTLB_INVAL, // 14
112	DCACHE_ICACHE_INVAL, // 15
113	DCACHE_DCACHE_INVAL, // 16
114	DCACHE_ICACHE_INVAL_PA, // 17
115	DCACHE_DCACHE_INVAL_PA, // 18
116	DCACHE_DCACHE_SYNC, // 19
117	DCACHE_LL_DIRTY_WAIT, // 1a
118	DCACHE_SC_DIRTY_WAIT, // 1b
119	DCACHE_WRITE_UPDT, // 1c
120	DCACHE_WRITE_DIRTY, // 1d
121	DCACHE_WRITE_REQ, // 1e
122	DCACHE_MISS_WAIT, // 1f
123	DCACHE_MISS_UPDT, // 20
124	DCACHE_UNC_WAIT, // 21
125	DCACHE_ERROR, // 22
126	DCACHE_ITLB_READ, // 23
127	DCACHE_ITLB_UPDT, // 24
128	DCACHE_ITLB_LL_WAIT, // 25
129	DCACHE_ITLB_SC_WAIT, // 26
130	DCACHE_CC_CHECK, // 27
131	DCACHE_CC_INVAL, // 28
132	DCACHE_CC_UPDT, // 29
133	DCACHE_CC_NOP, // 2a
134	DCACHE_TLB_CC_INVAL, // 2b
135	DCACHE_ITLB_CLEANUP, // 2c
136	};
137
138	enum cmd_fsm_state_e {
139	CMD_IDLE, // 00
140	CMD_ITLB_READ, // 01
141	CMD_ITLB_ACC_LL, // 02
142	CMD_ITLB_ACC_SC, // 03
143	CMD_INS_MISS, // 04
144	CMD_INS_UNC, // 05
145	CMD_DTLB_READ, // 06
146	CMD_DTLB_ACC_LL, // 07
147	CMD_DTLB_ACC_SC, // 08
148	CMD_DTLB_DIRTY_LL, // 09
149	CMD_DTLB_DIRTY_SC, // 0a
150	CMD_DATA_UNC, // 0b
151	CMD_DATA_MISS, // 0c
152	CMD_DATA_WRITE, // 0d
153	};
154
155	enum rsp_fsm_state_e {
156	RSP_IDLE, // 00
157	RSP_ITLB_READ, // 01
158	RSP_ITLB_ACC_LL, // 02
159	RSP_ITLB_ACC_SC, // 03
160	RSP_INS_MISS, // 04
161	RSP_INS_UNC, // 05
162	RSP_DTLB_READ, // 06
163	RSP_DTLB_ACC_LL, // 07
164	RSP_DTLB_ACC_SC, // 08
165	RSP_DTLB_DIRTY_LL, // 09
166	RSP_DTLB_DIRTY_SC, // 0a
167	RSP_DATA_MISS, // 0b
168	RSP_DATA_UNC, // 0c
169	RSP_DATA_WRITE, // 0d
170	};
171	enum cleanup_cmd_fsm_state_e {
172	CLEANUP_CMD_IDLE, // 00
173	CLEANUP_CMD_DATA, // 01
174	CLEANUP_CMD_INS, // 02
175	};
176
177	enum cleanup_rsp_fsm_state_e {
178	CLEANUP_RSP_IDLE, // 00
179	CLEANUP_RSP_DATA, // 01
180	CLEANUP_RSP_INS, // 02
181	};
182
183	enum tgt_fsm_state_e {
184	TGT_IDLE, // 00
185	TGT_UPDT_WORD, // 01
186	TGT_UPDT_DATA, // 02
187	TGT_REQ_BROADCAST, // 03
188	TGT_REQ_ICACHE, // 04
189	TGT_REQ_DCACHE, // 05
190	TGT_RSP_BROADCAST, // 06
191	TGT_RSP_ICACHE, // 07
192	TGT_RSP_DCACHE, // 08
193	};
194
195	enum inval_itlb_fsm_state_e {
196	INVAL_ITLB_IDLE, // 00
197	INVAL_ITLB_CHECK, // 01
198	INVAL_ITLB_INVAL, // 02
199	INVAL_ITLB_CLEAR, // 03
200	};
201
202	enum inval_dtlb_fsm_state_e {
203	INVAL_DTLB_IDLE, // 00
204	INVAL_DTLB_CHECK, // 01
205	INVAL_DTLB_INVAL, // 02
206	INVAL_DTLB_CLEAR, // 03
207	};
208
209	// TLB Mode ITLB / DTLB / ICACHE / DCACHE
210	enum {
211	ALL_DEACTIVE = 0x0000, // TLBs disactive caches disactive
212	INS_TLB_MASK = 0x8,
213	DATA_TLB_MASK = 0x4,
214	INS_CACHE_MASK = 0x2,
215	DATA_CACHE_MASK = 0x1,
216	};
217
218	// Error Type
219	enum mmu_error_type_e {
220	MMU_NONE = 0x0000, // None
221	MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 (non fatal error)
222	MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 (non fatal error)
223	MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode (user error)
224	MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (user error)
225	MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address (user error)
226	MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 (kernel error)
227	MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 (kernel error)
228	MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access (kernel error)
229	MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 (non fatal error)
230	MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 (non fatal error)
231	MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode (user error)
232	MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page (user error)
233	MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address (user error)
234	MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access (kernel error)
235	MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access (kernel error)
236	MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access (kernel error)
237	};
238
239	public:
240	sc_in<bool> p_clk;
241	sc_in<bool> p_resetn;
242	sc_in<bool> p_irq[iss_t::n_irq];
243	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
244	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
245	soclib::caba::VciTarget<vci_param> p_vci_tgt;
246
247	private:
248	// STRUCTURAL PARAMETERS
249	soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
250	const soclib::common::Segment m_segment;
251	iss_t m_iss;
252	const vci_srcid_t m_srcid_rw;
253	const vci_srcid_t m_srcid_c;
254
255	const size_t m_itlb_ways;
256	const size_t m_itlb_sets;
257
258	const size_t m_dtlb_ways;
259	const size_t m_dtlb_sets;
260
261	const size_t m_icache_ways;
262	const size_t m_icache_sets;
263	const size_t m_icache_yzmask;
264	const size_t m_icache_words;
265
266	const size_t m_dcache_ways;
267	const size_t m_dcache_sets;
268	const size_t m_dcache_yzmask;
269	const size_t m_dcache_words;
270
271	const size_t m_write_buf_size;
272	const size_t m_paddr_nbits;
273
274	// instruction and data vcache tlb instances
275	soclib::caba::GenericCcTlb<paddr_t> icache_tlb;
276	soclib::caba::GenericCcTlb<paddr_t> dcache_tlb;
277
278	sc_signal<vaddr_t> r_mmu_ptpr; // page table pointer register
279	sc_signal<int> r_mmu_mode; // tlb mode register
280	sc_signal<int> r_mmu_params; // mmu parameters register
281	sc_signal<int> r_mmu_release; // mmu release register
282	sc_signal<int> r_mmu_word_lo; // mmu misc data low
283	sc_signal<int> r_mmu_word_hi; // mmu mmu misc data hight
284
285	// DCACHE FSM REGISTERS
286	sc_signal<int> r_dcache_fsm; // state register
287	sc_signal<paddr_t> r_dcache_paddr_save; // physical address
288	sc_signal<data_t> r_dcache_wdata_save; // write data
289	sc_signal<data_t> r_dcache_rdata_save; // read data
290	sc_signal<type_t> r_dcache_type_save; // access type
291	sc_signal<vci_be_t> r_dcache_be_save; // byte enable
292	sc_signal<bool> r_dcache_cached_save; // used by the write buffer
293	sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of tlb miss
294	sc_signal<bool> r_dcache_dirty_save; // used for TLB dirty bit update
295	sc_signal<size_t> r_dcache_tlb_set_save; // used for TLB dirty bit update
296	sc_signal<size_t> r_dcache_tlb_way_save; // used for TLB dirty bit update
297	sc_signal<vaddr_t> r_dcache_id1_save; // used by the PT1 bypass
298	sc_signal<paddr_t> r_dcache_ptba_save; // used by the PT1 bypass
299	sc_signal<bool> r_dcache_ptba_ok; // used by the PT1 bypass
300	sc_signal<data_t> r_dcache_pte_update; // used for page table update
301	sc_signal<data_t> r_dcache_ppn_update; // used for physical page number update
302	sc_signal<tag_t> r_dcache_ppn_save; // used for speculative cache access
303	sc_signal<tag_t> r_dcache_vpn_save; // used for speculative cache access
304	sc_signal<bool> r_dtlb_translation_valid; // used for speculative address
305	sc_signal<bool> r_dcache_buf_unc_valid; // used for uncached read
306	sc_signal<bool> r_dcache_hit_p_save; // used to save hit_p in case BIS
307
308	sc_signal<data_t> r_dcache_error_type; // software visible register
309	sc_signal<vaddr_t> r_dcache_bad_vaddr; // software visible register
310
311	sc_signal<bool> r_dcache_miss_req; // used for cached read miss
312	sc_signal<bool> r_dcache_unc_req; // used for uncached read miss
313	sc_signal<bool> r_dcache_write_req; // used for write
314	sc_signal<bool> r_dcache_tlb_read_req; // used for tlb ptba or pte read
315
316	sc_signal<bool> r_dcache_llsc_reserved; // used for check address reserved
317	sc_signal<paddr_t> r_dcache_llsc_addr_save; // used for save llsc address
318
319	sc_signal<bool> r_dcache_tlb_ll_acc_req; // used for tlb access bit update
320	sc_signal<bool> r_dcache_tlb_sc_acc_req; // used for tlb access bit update
321	sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update
322	sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update
323	sc_signal<bool> r_dcache_sc_updt_dirty; // used for tlb dirty bit update
324	sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit
325	sc_signal<bool> r_dcache_xtn_req; // used for xtn write for ICACHE
326
327	bool *r_dcache_in_itlb; // indicates some words of dcache line in ins TLB
328	bool *r_dcache_in_dtlb; // indicates some words of dcache line in data TLB
329
330	// coherence registers
331	sc_signal<int> r_dcache_fsm_save; // state save register
332	sc_signal<size_t> r_dcache_way;
333	sc_signal<size_t> r_dcache_set;
334	sc_signal<bool> r_dcache_cleanup_req; // data cleanup request
335	sc_signal<paddr_t> r_dcache_cleanup_line; // data cleanup NLINE
336	sc_signal<bool> r_dcache_inval_rsp; // data cache invalidate
337
338	// ICACHE FSM REGISTERS
339	sc_signal<int> r_icache_fsm; // state register
340	sc_signal<paddr_t> r_icache_paddr_save; // physical address
341	sc_signal<vaddr_t> r_icache_id1_save; // used by the PT1 bypass
342	sc_signal<paddr_t> r_icache_ptba_save; // used by the PT1 bypass
343	sc_signal<bool> r_icache_ptba_ok; // used by the PT1 bypass
344	sc_signal<data_t> r_icache_pte_update; // used for page table update
345	sc_signal<tag_t> r_icache_ppn_save; // used for speculative cache access
346	sc_signal<tag_t> r_icache_vpn_save; // used for speculative cache access
347	sc_signal<bool> r_itlb_translation_valid; // used for speculative physical address
348	sc_signal<bool> r_icache_buf_unc_valid; // used for uncached read
349
350	sc_signal<data_t> r_icache_error_type; // software visible registers
351	sc_signal<vaddr_t> r_icache_bad_vaddr; // software visible registers
352
353	sc_signal<bool> r_icache_miss_req; // used for cached read miss
354	sc_signal<bool> r_icache_unc_req; // used for uncached read miss
355	sc_signal<bool> r_dcache_itlb_read_req; // used for tlb ptba or pte read
356
357	sc_signal<bool> r_dcache_itlb_ll_acc_req; // used for tlb access bit update
358	sc_signal<bool> r_dcache_itlb_sc_acc_req; // used for tlb access bit update
359
360	sc_signal<bool> r_itlb_read_dcache_req; // used for instruction tlb miss, request in data cache
361	sc_signal<bool> r_itlb_k_read_dcache; // used for instruction tlb miss, request in data cache
362	sc_signal<bool> r_itlb_acc_dcache_req; // used for itlb update access bit via dcache
363	sc_signal<bool> r_itlb_acc_redo_req; // used for itlb update access bit via dcache
364	sc_signal<bool> r_dcache_rsp_itlb_error; // used for data cache rsp error when itlb miss
365	sc_signal<data_t> r_dcache_rsp_itlb_miss; // used for dcache rsp data when itlb miss
366	sc_signal<data_t> r_dcache_rsp_itlb_ppn; // used for dcache rsp ppn when itlb miss
367	sc_signal<vaddr_t> r_icache_vaddr_req; // virtual address requested by the CPU
368
369	// coherence registers
370	sc_signal<int> r_icache_fsm_save; // state save register
371	sc_signal<size_t> r_icache_way;
372	sc_signal<size_t> r_icache_set;
373	sc_signal<bool> r_icache_cleanup_req; // ins cleanup request
374	sc_signal<paddr_t> r_icache_cleanup_line; // ins cleanup NLINE
375	sc_signal<bool> r_icache_inval_rsp; // ins cache invalidate
376
377	// VCI_CMD FSM REGISTERS
378	sc_signal<int> r_vci_cmd_fsm;
379	sc_signal<size_t> r_vci_cmd_min;
380	sc_signal<size_t> r_vci_cmd_max;
381	sc_signal<size_t> r_vci_cmd_cpt;
382
383	// VCI_RSP FSM REGISTERS
384	sc_signal<int> r_vci_rsp_fsm;
385	sc_signal<size_t> r_vci_rsp_cpt;
386	sc_signal<bool> r_vci_rsp_ins_error;
387	sc_signal<bool> r_vci_rsp_data_error;
388	sc_signal<bool> r_dcache_tlb_sc_fail;
389
390	data_t *r_icache_miss_buf;
391	data_t *r_dcache_miss_buf;
392
393	sc_signal<int> r_cleanup_cmd_fsm;
394	sc_signal<int> r_cleanup_rsp_fsm;
395
396	// VCI_TGT FSM REGISTERS
397	data_t *r_tgt_buf;
398	bool *r_tgt_val;
399
400	sc_signal<int> r_vci_tgt_fsm;
401	sc_signal<paddr_t> r_tgt_addr;
402	sc_signal<size_t> r_tgt_word;
403	sc_signal<bool> r_tgt_update;
404	sc_signal<vci_srcid_t> r_tgt_srcid;
405	sc_signal<vci_pktid_t> r_tgt_pktid;
406	sc_signal<vci_trdid_t> r_tgt_trdid;
407	sc_signal<vci_plen_t> r_tgt_plen;
408	sc_signal<bool> r_tgt_req;
409	sc_signal<bool> r_tgt_icache_req;
410	sc_signal<bool> r_tgt_dcache_req;
411	sc_signal<bool> r_tgt_icache_rsp;
412	sc_signal<bool> r_tgt_dcache_rsp;
413
414	// INVAL CHECK FSM
415	sc_signal<int> r_inval_itlb_fsm;
416	sc_signal<bool> r_dcache_itlb_inval_req;
417	sc_signal<paddr_t> r_dcache_itlb_inval_line;
418	sc_signal<bool> r_itlb_cc_check_end;
419	sc_signal<size_t> r_ccinval_itlb_way;
420	sc_signal<size_t> r_ccinval_itlb_set;
421	sc_signal<bool> r_icache_inval_tlb_rsp;
422	sc_signal<paddr_t> r_icache_tlb_nline;
423
424	sc_signal<int> r_inval_dtlb_fsm;
425	sc_signal<bool> r_dcache_dtlb_inval_req;
426	sc_signal<paddr_t> r_dcache_dtlb_inval_line;
427	sc_signal<bool> r_dtlb_cc_check_end;
428	sc_signal<size_t> r_ccinval_dtlb_way;
429	sc_signal<size_t> r_ccinval_dtlb_set;
430	sc_signal<bool> r_dcache_inval_tlb_rsp;
431	sc_signal<paddr_t> r_dcache_tlb_nline;
432
433	sc_signal<bool> r_dcache_itlb_cleanup_req;
434	sc_signal<paddr_t> r_dcache_itlb_cleanup_line;
435
436	sc_signal<bool> r_dcache_dtlb_cleanup_req;
437	sc_signal<paddr_t> r_dcache_dtlb_cleanup_line;
438
439	sc_signal<bool> r_itlb_inval_req;
440	sc_signal<bool> r_dcache_cc_check;
441
442	WriteBuffer<paddr_t> r_wbuf;
443	GenericCache<paddr_t> r_icache;
444	GenericCache<paddr_t> r_dcache;
445
446	// Activity counters
447	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
448	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
449	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
450	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
451
452	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
453	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
454	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
455	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
456
457	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
458	uint32_t m_cpt_total_cycles; // total number of cycles
459	uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen
460
461	// Cache activity counters
462	uint32_t m_cpt_read; // total number of read data
463	uint32_t m_cpt_write; // total number of write data
464	uint32_t m_cpt_data_miss; // number of read miss
465	uint32_t m_cpt_ins_miss; // number of instruction miss
466	uint32_t m_cpt_unc_read; // number of read uncached
467	uint32_t m_cpt_write_cached; // number of cached write
468	uint32_t m_cpt_ins_read; // number of instruction read
469
470	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
471	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
472	uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
473	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
474
475	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
476	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
477	uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
478	uint32_t m_cpt_write_transaction; // number of VCI write transactions
479	uint32_t m_cpt_icache_unc_transaction;
480
481	uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
482	uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
483	uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
484	uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
485	uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
486	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
487
488	// TLB activity counters
489	uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read
490	uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss
491	uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc
492	uint32_t m_cpt_data_tlb_read; // number of data tlb read
493	uint32_t m_cpt_data_tlb_miss; // number of data tlb miss
494	uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc
495	uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
496	uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
497	uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
498	uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line
499	uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line
500	uint32_t m_cpt_tlb_occup_dcache;
501
502	uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss
503	uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
504	uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
505	uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
506	uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
507	uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache
508	uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache
509
510	uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
511	uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions
512	uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions
513	uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
514	uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions
515	uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions
516	uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions
517	uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions
518
519	uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
520	uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions
521	uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions
522	uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
523	uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions
524	uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions
525	uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
526	uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
527
528	uint32_t m_cpt_cc_update_data; // number of coherence update data packets
529	uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets
530	uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets
531	uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets
532
533	uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets
534	uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets
535	uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets
536	uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets
537
538	uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
539	uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
540
541	uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions
542	uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions
543	uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions
544	uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions
545
546	uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate
547	uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate
548
549	uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate
550	uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate
551
552	protected:
553	SC_HAS_PROCESS(VciCcVCacheWrapper2V1);
554
555	public:
556	VciCcVCacheWrapper2V1(
557	sc_module_name insname,
558	int proc_id,
559	const soclib::common::MappingTable &mtp,
560	const soclib::common::MappingTable &mtc,
561	const soclib::common::IntTab &initiator_index_rw,
562	const soclib::common::IntTab &initiator_index_c,
563	const soclib::common::IntTab &target_index,
564	size_t itlb_ways,
565	size_t itlb_sets,
566	size_t dtlb_ways,
567	size_t dtlb_sets,
568	size_t icache_ways,
569	size_t icache_sets,
570	size_t icache_words,
571	size_t dcache_ways,
572	size_t dcache_sets,
573	size_t dcache_words,
574	size_t write_buf_size );
575
576	~VciCcVCacheWrapper2V1();
577
578	void print_cpi();
579	void print_stats();
580	void clear_stats();
581	void print_trace(size_t mode = 0);
582
583	private:
584	void transition();
585	void genMoore();
586
587	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
588	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
589	};
590
591	}}
592
593	#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H */
594
595	// Local Variables:
596	// tab-width: 4
597	// c-basic-offset: 4
598	// c-file-offsets:((innamespace . 0)(inline-open . 0))
599	// indent-tabs-mode: nil
600	// End:
601
602	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
603
604
605
606

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