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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 204

Last change on this file since 204 was 204, checked in by alain, 12 years ago
bugs fix
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1	/* -- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_SC_UPDT",
74	"DCACHE_TLB_SC_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_WRITE_TLB_DIRTY",
91	"DCACHE_WRITE_CACHE_DIRTY",
92	"DCACHE_WRITE_SC_WAIT",
93	"DCACHE_WRITE_UNC_WAIT",
94
95	"DCACHE_MISS_VICTIM",
96	"DCACHE_MISS_INVAL",
97	"DCACHE_MISS_INVAL_WAIT",
98	"DCACHE_MISS_WAIT",
99	"DCACHE_MISS_UPDT",
100
101	"DCACHE_UNC_WAIT",
102
103	"DCACHE_CC_CHECK",
104	"DCACHE_CC_INVAL",
105	"DCACHE_CC_UPDT",
106
107	"DCACHE_INVAL_TLB_SCAN",
108	};
109	const char *cmd_fsm_state_str[] = {
110	"CMD_IDLE",
111	"CMD_INS_MISS",
112	"CMD_INS_UNC",
113	"CMD_DATA_MISS",
114	"CMD_DATA_UNC",
115	"CMD_DATA_WRITE",
116	"CMD_DATA_SC",
117	};
118	const char *rsp_fsm_state_str[] = {
119	"RSP_IDLE",
120	"RSP_INS_MISS",
121	"RSP_INS_UNC",
122	"RSP_DATA_MISS",
123	"RSP_DATA_UNC",
124	"RSP_DATA_WRITE",
125	};
126	const char *cleanup_fsm_state_str[] = {
127	"CLEANUP_DATA_IDLE",
128	"CLEANUP_DATA_GO",
129	"CLEANUP_INS_IDLE",
130	"CLEANUP_INS_GO",
131	};
132	const char *tgt_fsm_state_str[] = {
133	"TGT_IDLE",
134	"TGT_UPDT_WORD",
135	"TGT_UPDT_DATA",
136	"TGT_REQ_BROADCAST",
137	"TGT_REQ_ICACHE",
138	"TGT_REQ_DCACHE",
139	"TGT_RSP_BROADCAST",
140	"TGT_RSP_ICACHE",
141	"TGT_RSP_DCACHE",
142	};
143	}
144
145	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
146
147	using soclib::common::uint32_log2;
148
149	/////////////////////////////////
150	tmpl(/**/)::VciCcVCacheWrapperV4(
151	sc_module_name name,
152	int proc_id,
153	const soclib::common::MappingTable &mtp,
154	const soclib::common::MappingTable &mtc,
155	const soclib::common::IntTab &initiator_index_d,
156	const soclib::common::IntTab &initiator_index_c,
157	const soclib::common::IntTab &target_index_d,
158	size_t itlb_ways,
159	size_t itlb_sets,
160	size_t dtlb_ways,
161	size_t dtlb_sets,
162	size_t icache_ways,
163	size_t icache_sets,
164	size_t icache_words,
165	size_t dcache_ways,
166	size_t dcache_sets,
167	size_t dcache_words,
168	size_t wbuf_nlines,
169	size_t wbuf_nwords,
170	uint32_t max_frozen_cycles,
171	uint32_t debug_start_cycle,
172	bool debug_ok)
173	: soclib::caba::BaseModule(name),
174
175	p_clk("clk"),
176	p_resetn("resetn"),
177	p_vci_ini_d("vci_ini_d"),
178	p_vci_ini_c("vci_ini_c"),
179	p_vci_tgt_c("vci_tgt_d"),
180
181	m_cacheability_table(mtp.getCacheabilityTable()),
182	m_segment(mtc.getSegment(target_index_d)),
183	m_srcid_d(mtp.indexForId(initiator_index_d)),
184	m_srcid_c(mtp.indexForId(initiator_index_c)),
185
186	m_itlb_ways(itlb_ways),
187	m_itlb_sets(itlb_sets),
188
189	m_dtlb_ways(dtlb_ways),
190	m_dtlb_sets(dtlb_sets),
191
192	m_icache_ways(icache_ways),
193	m_icache_sets(icache_sets),
194	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
195	m_icache_words(icache_words),
196
197	m_dcache_ways(dcache_ways),
198	m_dcache_sets(dcache_sets),
199	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
200	m_dcache_words(dcache_words),
201
202	m_proc_id(proc_id),
203
204	m_max_frozen_cycles(max_frozen_cycles),
205
206	m_paddr_nbits(vci_param::N),
207
208	m_debug_start_cycle(debug_start_cycle),
209	m_debug_ok(debug_ok),
210
211	r_mmu_ptpr("r_mmu_ptpr"),
212	r_mmu_mode("r_mmu_mode"),
213	r_mmu_word_lo("r_mmu_word_lo"),
214	r_mmu_word_hi("r_mmu_word_hi"),
215	r_mmu_ibvar("r_mmu_ibvar"),
216	r_mmu_dbvar("r_mmu_dbvar"),
217	r_mmu_ietr("r_mmu_ietr"),
218	r_mmu_detr("r_mmu_detr"),
219
220	r_icache_fsm("r_icache_fsm"),
221	r_icache_fsm_save("r_icache_fsm_save"),
222	r_icache_vci_paddr("r_icache_vci_paddr"),
223	r_icache_vaddr_save("r_icache_vaddr_save"),
224
225	r_icache_miss_way("r_icache_miss_way"),
226	r_icache_miss_set("r_icache_miss_set"),
227	r_icache_miss_word("r_icache_miss_word"),
228	r_icache_miss_inval("r_icache_miss_inval"),
229
230	r_icache_cc_way("r_icache_cc_way"),
231	r_icache_cc_set("r_icache_cc_set"),
232	r_icache_cc_word("r_icache_cc_word"),
233
234	r_icache_flush_count("r_icache_flush_count"),
235
236	r_icache_miss_req("r_icache_miss_req"),
237	r_icache_unc_req("r_icache_unc_req"),
238
239	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
240	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
241
242	r_icache_cleanup_req("r_icache_cleanup_req"),
243	r_icache_cleanup_line("r_icache_cleanup_line"),
244
245	r_dcache_fsm("r_dcache_fsm"),
246	r_dcache_fsm_save("r_dcache_fsm_save"),
247
248	r_dcache_p0_valid("r_dcache_p0_valid"),
249	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
250	r_dcache_p0_wdata("r_dcache_p0_wdata"),
251	r_dcache_p0_be("r_dcache_p0_be"),
252	r_dcache_p0_paddr("r_dcache_p0_paddr"),
253	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
254	r_dcache_p0_tlb_way("r_dcache_p0_tlb_way"),
255	r_dcache_p0_tlb_set("r_dcache_p0_tlb_set"),
256	r_dcache_p0_tlb_nline("r_dcache_p0_tlb_nline"),
257	r_dcache_p0_tlb_dirty("r_dcache_p0_tlb_dirty"),
258	r_dcache_p0_tlb_big("r_dcache_p0_tlb_big"),
259
260	r_dcache_p1_valid("r_dcache_p1_valid"),
261	r_dcache_p1_updt_cache("r_dcache_p1_updt_cache"),
262	r_dcache_p1_set_dirty("r_dcache_p1_set_dirty"),
263	r_dcache_p1_vaddr("r_dcache_p1_vaddr"),
264	r_dcache_p1_wdata("r_dcache_p1_wdata"),
265	r_dcache_p1_be("r_dcache_p1_be"),
266	r_dcache_p1_paddr("r_dcache_p1_paddr"),
267	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
268	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
269	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
270	r_dcache_p1_tlb_way("r_dcache_p1_tlb_way"),
271	r_dcache_p1_tlb_set("r_dcache_p1_tlb_set"),
272	r_dcache_p1_tlb_nline("r_dcache_p1_tlb_nline"),
273	r_dcache_p1_tlb_big("r_dcache_p1_tlb_big"),
274
275	r_dcache_p2_vaddr("r_dcache_p2_vaddr"),
276	r_dcache_p2_tlb_way("r_dcache_p2_tlb_way"),
277	r_dcache_p2_tlb_set("r_dcache_p2_tlb_set"),
278	r_dcache_p2_set_dirty("r_dcache_p2_set_dirty"),
279	r_dcache_p2_pte_paddr("r_dcache_p2_pte_paddr"),
280	r_dcache_p2_pte_way("r_dcache_p2_pte_way"),
281	r_dcache_p2_pte_set("r_dcache_p2_pte_set"),
282	r_dcache_p2_pte_word("r_dcache_p2_pte_word"),
283	r_dcache_p2_pte("r_dcache_p2_pte"),
284
285	r_dcache_vci_paddr("r_dcache_vci_paddr"),
286	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
287	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
288	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
289	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
290	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
291	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
292
293	r_dcache_xtn_way("r_dcache_xtn_way"),
294	r_dcache_xtn_set("r_dcache_xtn_set"),
295
296	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
297
298	r_dcache_miss_type("r_dcache_miss_type"),
299	r_dcache_miss_word("r_dcache_miss_word"),
300	r_dcache_miss_way("r_dcache_miss_way"),
301	r_dcache_miss_set("r_dcache_miss_set"),
302	r_dcache_miss_inval("r_dcache_miss_inval"),
303
304	r_dcache_cc_way("r_dcache_cc_way"),
305	r_dcache_cc_set("r_dcache_cc_set"),
306	r_dcache_cc_word("r_dcache_cc_word"),
307
308	r_dcache_flush_count("r_dcache_flush_count"),
309
310	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
311	r_dcache_tlb_ins("r_dcache_tlb_ins"),
312	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
313	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
314	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
315	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
316	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
317	r_dcache_tlb_way("r_dcache_tlb_way"),
318	r_dcache_tlb_set("r_dcache_tlb_set"),
319
320	r_dcache_ll_valid("r_dcache_ll_valid"),
321	r_dcache_ll_data("r_dcache_ll_data"),
322	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
323
324	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
325	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
326	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
327	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
328
329	r_dcache_xtn_req("r_dcache_xtn_req"),
330	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
331
332	r_dcache_cleanup_req("r_dcache_cleanup_req"),
333	r_dcache_cleanup_line("r_dcache_cleanup_line"),
334
335	r_vci_cmd_fsm("r_vci_cmd_fsm"),
336	r_vci_cmd_min("r_vci_cmd_min"),
337	r_vci_cmd_max("r_vci_cmd_max"),
338	r_vci_cmd_cpt("r_vci_cmd_cpt"),
339	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
340
341	r_vci_rsp_fsm("r_vci_rsp_fsm"),
342	r_vci_rsp_cpt("r_vci_rsp_cpt"),
343	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
344	r_vci_rsp_data_error("r_vci_rsp_data_error"),
345	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
346	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
347
348	r_cleanup_fsm("r_cleanup_fsm"),
349	r_cleanup_trdid("r_cleanup_trdid"),
350	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
351
352	r_tgt_fsm("r_tgt_fsm"),
353	r_tgt_paddr("r_tgt_paddr"),
354	r_tgt_word_count("r_tgt_word_count"),
355	r_tgt_word_min("r_tgt_word_min"),
356	r_tgt_word_max("r_tgt_word_max"),
357	r_tgt_update("r_tgt_update"),
358	r_tgt_update_data("r_tgt_update_data"),
359	r_tgt_srcid("r_tgt_srcid"),
360	r_tgt_pktid("r_tgt_pktid"),
361	r_tgt_trdid("r_tgt_trdid"),
362
363	r_tgt_icache_req("r_tgt_icache_req"),
364	r_tgt_dcache_req("r_tgt_dcache_req"),
365	r_tgt_icache_rsp("r_tgt_icache_rsp"),
366	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
367
368	r_iss(this->name(), proc_id),
369	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
370	r_icache("icache", icache_ways, icache_sets, icache_words),
371	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
372	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
373	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
374	{
375	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
376	"Need more PLEN bits.");
377
378	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
379	"Need more TRDID bits.");
380
381	assert( (icache_words == dcache_words) and
382	"icache_words and dcache_words parameters must be equal");
383
384	assert( (itlb_sets == dtlb_sets) and
385	"itlb_sets and dtlb_sets parameters must be etqual");
386
387	assert( (itlb_ways == dtlb_ways) and
388	"itlb_ways and dtlb_ways parameters must be etqual");
389
390	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
391	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
392	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
393	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
394	(uint32_log2(m_icache_words<<2));
395
396	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
397
398	r_tgt_buf = new uint32_t[dcache_words];
399	r_tgt_be = new vci_be_t[dcache_words];
400	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapperV4()
424	/////////////////////////////////////
425	{
426	delete [] r_tgt_be;
427	delete [] r_tgt_buf;
428	delete [] r_dcache_in_itlb;
429	delete [] r_dcache_in_dtlb;
430	}
431
432	////////////////////////
433	tmpl(void)::print_cpi()
434	////////////////////////
435	{
436	std::cout << name() << " CPI = "
437	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
438	}
439
440	////////////////////////////////////
441	tmpl(void)::print_trace(size_t mode)
442	////////////////////////////////////
443	{
444	// b0 : write buffer print trace
445	// b1 : write buffer verbose
446	// b2 : dcache print trace
447	// b3 : icache print trace
448
449	typename iss_t::InstructionRequest ireq;
450	typename iss_t::InstructionResponse irsp;
451	typename iss_t::DataRequest dreq;
452	typename iss_t::DataResponse drsp;
453
454	ireq.valid = m_ireq_valid;
455	ireq.addr = m_ireq_addr;
456	ireq.mode = m_ireq_mode;
457
458	irsp.valid = m_irsp_valid;
459	irsp.instruction = m_irsp_instruction;
460	irsp.error = m_irsp_error;
461
462	dreq.valid = m_dreq_valid;
463	dreq.addr = m_dreq_addr;
464	dreq.mode = m_dreq_mode;
465	dreq.type = m_dreq_type;
466	dreq.wdata = m_dreq_wdata;
467	dreq.be = m_dreq_be;
468
469	drsp.valid = m_drsp_valid;
470	drsp.rdata = m_drsp_rdata;
471	drsp.error = m_drsp_error;
472
473	std::cout << std::dec << "PROC " << name() << std::endl;
474
475	std::cout << " " << ireq << std::endl;
476	std::cout << " " << irsp << std::endl;
477	std::cout << " " << dreq << std::endl;
478	std::cout << " " << drsp << std::endl;
479
480	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
481	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
482	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
483	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
484	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
485	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
486	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
487	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
488	std::cout << std::endl;
489
490	if(mode & 0x1)
491	{
492	r_wbuf.printTrace((mode>>1)&1);
493	}
494	if(mode & 0x4)
495	{
496	std::cout << " Data cache" << std::endl;
497	r_dcache.printTrace();
498	}
499	if(mode & 0x8)
500	{
501	std::cout << " Instruction cache" << std::endl;
502	r_icache.printTrace();
503	}
504	}
505
506	//////////////////////////////////////////
507	tmpl(void)::cache_monitor( paddr_t addr )
508	//////////////////////////////////////////
509	{
510	size_t cache_way;
511	size_t cache_set;
512	size_t cache_word;
513	uint32_t cache_rdata;
514	bool cache_hit = r_dcache.read( addr,
515	&cache_rdata,
516	&cache_way,
517	&cache_set,
518	&cache_word );
519	if ( cache_hit != m_debug_previous_hit )
520	{
521	std::cout << "PROC " << name()
522	<< " cache change at cycle " << std::dec << m_cpt_total_cycles
523	<< " for adresse " << std::hex << addr
524	<< " / HIT = " << cache_hit << std::endl;
525	}
526	m_debug_previous_hit = cache_hit;
527	}
528
529
530
531	/*
532	////////////////////////
533	tmpl(void)::print_stats()
534	////////////////////////
535	{
536	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
537	std::cout << name() << std::endl
538	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
539	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
540	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
541	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
542	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
543	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
544	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
545	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
546	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
547	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
548	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
549	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
550	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
551	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
552	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
553	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
554	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
555	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
556	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
557	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
558	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
559	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
560	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
561	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
562	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
563	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
564	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
565	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
566	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
567	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
568	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
569	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
570	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
571	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
572	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
573	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
574	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
575	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
576	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
577	}
578
579	////////////////////////
580	tmpl(void)::clear_stats()
581	////////////////////////
582	{
583	m_cpt_dcache_data_read = 0;
584	m_cpt_dcache_data_write = 0;
585	m_cpt_dcache_dir_read = 0;
586	m_cpt_dcache_dir_write = 0;
587	m_cpt_icache_data_read = 0;
588	m_cpt_icache_data_write = 0;
589	m_cpt_icache_dir_read = 0;
590	m_cpt_icache_dir_write = 0;
591
592	m_cpt_frz_cycles = 0;
593	m_cpt_dcache_frz_cycles = 0;
594	m_cpt_total_cycles = 0;
595
596	m_cpt_read = 0;
597	m_cpt_write = 0;
598	m_cpt_data_miss = 0;
599	m_cpt_ins_miss = 0;
600	m_cpt_unc_read = 0;
601	m_cpt_write_cached = 0;
602	m_cpt_ins_read = 0;
603
604	m_cost_write_frz = 0;
605	m_cost_data_miss_frz = 0;
606	m_cost_unc_read_frz = 0;
607	m_cost_ins_miss_frz = 0;
608
609	m_cpt_imiss_transaction = 0;
610	m_cpt_dmiss_transaction = 0;
611	m_cpt_unc_transaction = 0;
612	m_cpt_write_transaction = 0;
613	m_cpt_icache_unc_transaction = 0;
614
615	m_cost_imiss_transaction = 0;
616	m_cost_dmiss_transaction = 0;
617	m_cost_unc_transaction = 0;
618	m_cost_write_transaction = 0;
619	m_cost_icache_unc_transaction = 0;
620	m_length_write_transaction = 0;
621
622	m_cpt_ins_tlb_read = 0;
623	m_cpt_ins_tlb_miss = 0;
624	m_cpt_ins_tlb_update_acc = 0;
625
626	m_cpt_data_tlb_read = 0;
627	m_cpt_data_tlb_miss = 0;
628	m_cpt_data_tlb_update_acc = 0;
629	m_cpt_data_tlb_update_dirty = 0;
630	m_cpt_ins_tlb_hit_dcache = 0;
631	m_cpt_data_tlb_hit_dcache = 0;
632	m_cpt_ins_tlb_occup_cache = 0;
633	m_cpt_data_tlb_occup_cache = 0;
634
635	m_cost_ins_tlb_miss_frz = 0;
636	m_cost_data_tlb_miss_frz = 0;
637	m_cost_ins_tlb_update_acc_frz = 0;
638	m_cost_data_tlb_update_acc_frz = 0;
639	m_cost_data_tlb_update_dirty_frz = 0;
640	m_cost_ins_tlb_occup_cache_frz = 0;
641	m_cost_data_tlb_occup_cache_frz = 0;
642
643	m_cpt_itlbmiss_transaction = 0;
644	m_cpt_itlb_ll_transaction = 0;
645	m_cpt_itlb_sc_transaction = 0;
646	m_cpt_dtlbmiss_transaction = 0;
647	m_cpt_dtlb_ll_transaction = 0;
648	m_cpt_dtlb_sc_transaction = 0;
649	m_cpt_dtlb_ll_dirty_transaction = 0;
650	m_cpt_dtlb_sc_dirty_transaction = 0;
651
652	m_cost_itlbmiss_transaction = 0;
653	m_cost_itlb_ll_transaction = 0;
654	m_cost_itlb_sc_transaction = 0;
655	m_cost_dtlbmiss_transaction = 0;
656	m_cost_dtlb_ll_transaction = 0;
657	m_cost_dtlb_sc_transaction = 0;
658	m_cost_dtlb_ll_dirty_transaction = 0;
659	m_cost_dtlb_sc_dirty_transaction = 0;
660
661	m_cpt_cc_update_data = 0;
662	m_cpt_cc_inval_ins = 0;
663	m_cpt_cc_inval_data = 0;
664	m_cpt_cc_broadcast = 0;
665
666	m_cost_updt_data_frz = 0;
667	m_cost_inval_ins_frz = 0;
668	m_cost_inval_data_frz = 0;
669	m_cost_broadcast_frz = 0;
670
671	m_cpt_cc_cleanup_data = 0;
672	m_cpt_cc_cleanup_ins = 0;
673	}
674
675	*/
676
677	/////////////////////////
678	tmpl(void)::transition()
679	/////////////////////////
680	{
681	if ( not p_resetn.read() )
682	{
683	r_iss.reset();
684	r_wbuf.reset();
685	r_icache.reset();
686	r_dcache.reset();
687	r_itlb.reset();
688	r_dtlb.reset();
689
690	r_dcache_fsm = DCACHE_IDLE;
691	r_icache_fsm = ICACHE_IDLE;
692	r_vci_cmd_fsm = CMD_IDLE;
693	r_vci_rsp_fsm = RSP_IDLE;
694	r_tgt_fsm = TGT_IDLE;
695	r_cleanup_fsm = CLEANUP_DATA_IDLE;
696
697	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
698	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
699
700
701	// Response FIFOs and cleanup buffer
702	r_vci_rsp_fifo_icache.init();
703	r_vci_rsp_fifo_dcache.init();
704	r_cleanup_buffer.reset();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CLEANUP FSMs
717	r_icache_cleanup_req = false;
718
719	// No pending write in pipeline
720	r_dcache_p0_valid = false;
721	r_dcache_p1_valid = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_sc_req = false;
727
728	// No uncacheable write pending
729	r_dcache_pending_unc_write = false;
730
731	// No LL reservation
732	r_dcache_ll_valid = false;
733
734	// No TLB inval requestis
735	r_dcache_itlb_inval_req = false;
736	r_dcache_dtlb_inval_req = false;
737
738	// No processor XTN request pending
739	r_dcache_xtn_req = false;
740
741	// No request from DCACHE FSM to CLEANUP FSMs
742	r_dcache_cleanup_req = false;
743
744	// No request from TGT FSM to ICACHE/DCACHE FSMs
745	r_tgt_icache_req = false;
746	r_tgt_dcache_req = false;
747
748	// No signalisation of a coherence request matching a pending miss
749	r_icache_miss_inval = false;
750	r_dcache_miss_inval = false;
751
752	// No signalisation of errors
753	r_vci_rsp_ins_error = false;
754	r_vci_rsp_data_error = false;
755
756	// Debug variables
757	m_debug_previous_hit = false;
758	m_debug_dcache_fsm = false;
759	m_debug_icache_fsm = false;
760	m_debug_cleanup_fsm = false;
761
762	/*
763	// activity counters
764	m_cpt_dcache_data_read = 0;
765	m_cpt_dcache_data_write = 0;
766	m_cpt_dcache_dir_read = 0;
767	m_cpt_dcache_dir_write = 0;
768	m_cpt_icache_data_read = 0;
769	m_cpt_icache_data_write = 0;
770	m_cpt_icache_dir_read = 0;
771	m_cpt_icache_dir_write = 0;
772
773	m_cpt_frz_cycles = 0;
774	m_cpt_dcache_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776
777	m_cpt_read = 0;
778	m_cpt_write = 0;
779	m_cpt_data_miss = 0;
780	m_cpt_ins_miss = 0;
781	m_cpt_unc_read = 0;
782	m_cpt_write_cached = 0;
783	m_cpt_ins_read = 0;
784
785	m_cost_write_frz = 0;
786	m_cost_data_miss_frz = 0;
787	m_cost_unc_read_frz = 0;
788	m_cost_ins_miss_frz = 0;
789
790	m_cpt_imiss_transaction = 0;
791	m_cpt_dmiss_transaction = 0;
792	m_cpt_unc_transaction = 0;
793	m_cpt_write_transaction = 0;
794	m_cpt_icache_unc_transaction = 0;
795
796	m_cost_imiss_transaction = 0;
797	m_cost_dmiss_transaction = 0;
798	m_cost_unc_transaction = 0;
799	m_cost_write_transaction = 0;
800	m_cost_icache_unc_transaction = 0;
801	m_length_write_transaction = 0;
802
803	m_cpt_ins_tlb_read = 0;
804	m_cpt_ins_tlb_miss = 0;
805	m_cpt_ins_tlb_update_acc = 0;
806
807	m_cpt_data_tlb_read = 0;
808	m_cpt_data_tlb_miss = 0;
809	m_cpt_data_tlb_update_acc = 0;
810	m_cpt_data_tlb_update_dirty = 0;
811	m_cpt_ins_tlb_hit_dcache = 0;
812	m_cpt_data_tlb_hit_dcache = 0;
813	m_cpt_ins_tlb_occup_cache = 0;
814	m_cpt_data_tlb_occup_cache = 0;
815
816	m_cost_ins_tlb_miss_frz = 0;
817	m_cost_data_tlb_miss_frz = 0;
818	m_cost_ins_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_acc_frz = 0;
820	m_cost_data_tlb_update_dirty_frz = 0;
821	m_cost_ins_tlb_occup_cache_frz = 0;
822	m_cost_data_tlb_occup_cache_frz = 0;
823
824	m_cpt_ins_tlb_inval = 0;
825	m_cpt_data_tlb_inval = 0;
826	m_cost_ins_tlb_inval_frz = 0;
827	m_cost_data_tlb_inval_frz = 0;
828
829	m_cpt_cc_update_data = 0;
830	m_cpt_cc_inval_ins = 0;
831	m_cpt_cc_inval_data = 0;
832	m_cpt_cc_broadcast = 0;
833
834	m_cost_updt_data_frz = 0;
835	m_cost_inval_ins_frz = 0;
836	m_cost_inval_data_frz = 0;
837	m_cost_broadcast_frz = 0;
838
839	m_cpt_cc_cleanup_data = 0;
840	m_cpt_cc_cleanup_ins = 0;
841
842	m_cpt_itlbmiss_transaction = 0;
843	m_cpt_itlb_ll_transaction = 0;
844	m_cpt_itlb_sc_transaction = 0;
845	m_cpt_dtlbmiss_transaction = 0;
846	m_cpt_dtlb_ll_transaction = 0;
847	m_cpt_dtlb_sc_transaction = 0;
848	m_cpt_dtlb_ll_dirty_transaction = 0;
849	m_cpt_dtlb_sc_dirty_transaction = 0;
850
851	m_cost_itlbmiss_transaction = 0;
852	m_cost_itlb_ll_transaction = 0;
853	m_cost_itlb_sc_transaction = 0;
854	m_cost_dtlbmiss_transaction = 0;
855	m_cost_dtlb_ll_transaction = 0;
856	m_cost_dtlb_sc_transaction = 0;
857	m_cost_dtlb_ll_dirty_transaction = 0;
858	m_cost_dtlb_sc_dirty_transaction = 0;
859
860	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
861	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
862	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
863	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
867
868	*/
869	return;
870	}
871
872	// Response FIFOs default values
873	bool vci_rsp_fifo_icache_get = false;
874	bool vci_rsp_fifo_icache_put = false;
875	uint32_t vci_rsp_fifo_icache_data = 0;
876
877	bool vci_rsp_fifo_dcache_get = false;
878	bool vci_rsp_fifo_dcache_put = false;
879	uint32_t vci_rsp_fifo_dcache_data = 0;
880
881	#ifdef INSTRUMENTATION
882	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
883	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
884	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
885	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
886	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
887	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
888	#endif
889
890	m_cpt_total_cycles++;
891
892	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
893	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
894	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
895
896	/////////////////////////////////////////////////////////////////////
897	// The TGT_FSM controls the following ressources:
898	// - r_tgt_fsm
899	// - r_tgt_buf[nwords]
900	// - r_tgt_be[nwords]
901	// - r_tgt_update
902	// - r_tgt_word_min
903	// - r_tgt_word_max
904	// - r_tgt_word_count
905	// - r_tgt_paddr
906	// - r_tgt_srcid
907	// - r_tgt_trdid
908	// - r_tgt_pktid
909	// - r_tgt_icache_req (set)
910	// - r_tgt_dcache_req (set)
911	//
912	// All VCI commands must be CMD_WRITE.
913	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
914	// It is a multicast request otherwise.
915	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
916	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
917	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
918	//
919	// For all types of coherence request, the line index (i.e. the Z & Y fields)
920	// is coded on 34 bits, and is contained in the WDATA and BE fields
921	// of the first VCI flit.
922	// - for a multicast invalidate or for a broadcast invalidate request
923	// the VCI packet length is 1 word.
924	// - for an update request the VCI packet length is (n+2) words.
925	// The WDATA field of the second VCI word contains the word index.
926	// The WDATA field of the n following words contains the values.
927	// - for all transaction types, the VCI response is one single word.
928	// In case of errors in the VCI command packet, the simulation
929	// is stopped with an error message.
930	//
931	// This FSM is NOT pipelined : It consumes a new coherence request
932	// on the VCI port only when the previous request is completed.
933	//
934	// The VCI_TGT FSM stores the external request arguments in the
935	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
936	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
937	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
938	// states. It waits the completion of the coherence request by polling the
939	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
940	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
941	// These two FSMs signal if a VCI answer must be send by setting
942	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
943	///////////////////////////////////////////////////////////////////////////////
944
945	switch( r_tgt_fsm.read() )
946	{
947	//////////////
948	case TGT_IDLE:
949	{
950	if ( p_vci_tgt_c.cmdval.read() )
951	{
952	paddr_t address = p_vci_tgt_c.address.read();
953
954	// command checking
955	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
956	{
957	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
958	std::cout << "the received VCI coherence command is not a write" << std::endl;
959	exit(0);
960	}
961
962	// address checking
963	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
964	{
965	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
966	std::cout << "out of segment VCI coherence command received" << std::endl;
967	exit(0);
968	}
969
970	r_tgt_srcid = p_vci_tgt_c.srcid.read();
971	r_tgt_trdid = p_vci_tgt_c.trdid.read();
972	r_tgt_pktid = p_vci_tgt_c.pktid.read();
973
974	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
975	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
976
977	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
978	{
979	if ( not p_vci_tgt_c.eop.read() )
980	{
981	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
982	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
983	exit(0);
984	}
985	r_tgt_update = false;
986	r_tgt_fsm = TGT_REQ_BROADCAST;
987
988	#ifdef INSTRUMENTATION
989	m_cpt_cc_broadcast++;
990	#endif
991	}
992	else // multi-update or multi-invalidate for data type
993	{
994	paddr_t cell = address - m_segment.baseAddress();
995
996	if (cell == 0) // invalidate data
997	{
998	if ( not p_vci_tgt_c.eop.read() )
999	{
1000	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1001	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1002	exit(0);
1003	}
1004	r_tgt_update = false;
1005	r_tgt_fsm = TGT_REQ_DCACHE;
1006
1007	#ifdef INSTRUMENTATION
1008	m_cpt_cc_inval_dcache++;
1009	#endif
1010	}
1011	else if (cell == 4) // invalidate instruction
1012	{
1013	if ( not p_vci_tgt_c.eop.read() )
1014	{
1015	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1016	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1017	exit(0);
1018	}
1019	r_tgt_update = false;
1020	r_tgt_fsm = TGT_REQ_ICACHE;
1021
1022	#ifdef INSTRUMENTATION
1023	m_cpt_cc_inval_icache++;
1024	#endif
1025	}
1026	else if (cell == 8) // update data
1027	{
1028	if ( p_vci_tgt_c.eop.read() )
1029	{
1030	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1031	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1032	exit(0);
1033	}
1034	r_tgt_update = true;
1035	r_tgt_update_data = true;
1036	r_tgt_fsm = TGT_UPDT_WORD;
1037
1038	#ifdef INSTRUMENTATION
1039	m_cpt_cc_update_dcache++;
1040	#endif
1041	}
1042	else // update instruction
1043	{
1044	if ( p_vci_tgt_c.eop.read() )
1045	{
1046	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1047	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1048	exit(0);
1049	}
1050	r_tgt_update = true;
1051	r_tgt_update_data = false;
1052	r_tgt_fsm = TGT_UPDT_WORD;
1053
1054	#ifdef INSTRUMENTATION
1055	m_cpt_cc_update_icache++;
1056	#endif
1057	}
1058	} // end if multi
1059	} // end if cmdval
1060	break;
1061	}
1062	///////////////////
1063	case TGT_UPDT_WORD: // first word index acquisition
1064	{
1065	if (p_vci_tgt_c.cmdval.read())
1066	{
1067	if ( p_vci_tgt_c.eop.read() )
1068	{
1069	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1070	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1071	exit(0);
1072	}
1073	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1074
1075	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1076	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1077	r_tgt_fsm = TGT_UPDT_DATA;
1078	}
1079	break;
1080	}
1081	///////////////////
1082	case TGT_UPDT_DATA:
1083	{
1084	if (p_vci_tgt_c.cmdval.read())
1085	{
1086	size_t word = r_tgt_word_count.read();
1087	if (word >= m_dcache_words)
1088	{
1089	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1090	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1091	exit(0);
1092	}
1093	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1094	r_tgt_be[word] = p_vci_tgt_c.be.read();
1095	r_tgt_word_count = word + 1;
1096
1097	if (p_vci_tgt_c.eop.read()) // last word
1098	{
1099	r_tgt_word_max = word;
1100	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1101	else r_tgt_fsm = TGT_REQ_ICACHE;
1102	}
1103	}
1104	break;
1105	}
1106	///////////////////////
1107	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1108	{
1109	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1110	{
1111	r_tgt_fsm = TGT_RSP_BROADCAST;
1112	r_tgt_icache_req = true;
1113	r_tgt_dcache_req = true;
1114	}
1115	break;
1116	}
1117	/////////////////////
1118	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1119	{
1120	if ( not r_tgt_icache_req.read() )
1121	{
1122	r_tgt_fsm = TGT_RSP_ICACHE;
1123	r_tgt_icache_req = true;
1124	}
1125	break;
1126	}
1127	////////////////////
1128	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1129	{
1130	if ( not r_tgt_dcache_req.read() )
1131	{
1132	r_tgt_fsm = TGT_RSP_DCACHE;
1133	r_tgt_dcache_req = true;
1134	}
1135	break;
1136	}
1137	///////////////////////
1138	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1139	// no response when r_tgt_*cache_rsp is false
1140	{
1141	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1142	{
1143	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1144	{
1145	if ( p_vci_tgt_c.rspack.read() )
1146	{
1147	// reset dcache first if activated
1148	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1149	else r_tgt_icache_rsp = false;
1150	}
1151	}
1152	else
1153	{
1154	r_tgt_fsm = TGT_IDLE;
1155	}
1156	}
1157	break;
1158	}
1159	////////////////////
1160	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1161	{
1162	// no response when r_tgt_icache_rsp is false
1163	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1164	{
1165	r_tgt_fsm = TGT_IDLE;
1166	r_tgt_icache_rsp = false;
1167	}
1168	break;
1169	}
1170	////////////////////
1171	case TGT_RSP_DCACHE:
1172	{
1173	// no response when r_tgt_dcache_rsp is false
1174	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1175	{
1176	r_tgt_fsm = TGT_IDLE;
1177	r_tgt_dcache_rsp = false;
1178	}
1179	break;
1180	}
1181	} // end switch TGT_FSM
1182
1183	/////////////////////////////////////////////////////////////////////
1184	// Get data and instruction requests from processor
1185	///////////////////////////////////////////////////////////////////////
1186
1187	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
1188	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
1189
1190	r_iss.getRequests(ireq, dreq);
1191
1192	////////////////////////////////////////////////////////////////////////////////////
1193	// ICACHE_FSM
1194	//
1195	// There is 9 conditions to exit the IDLE state:
1196	// One condition is a coherence request from TGT FSM :
1197	// - Coherence operation => ICACHE_CC_CHEK
1198	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1199	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1200	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1201	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1202	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1203	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1204	// three configurations corresponding to instruction processor requests :
1205	// - tlb miss => ICACHE_TLB_WAIT
1206	// - cacheable read miss => ICACHE_MISS_VICTIM
1207	// - uncacheable read miss => ICACHE_UNC_REQ
1208	//
1209	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1210	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1211	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1212	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1213	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1214	// The availability of the missing cache line is signaled by the response fifo,
1215	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1216	//
1217	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1218	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1219	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1220	// the response from the RSP FSM, through the response fifo. The missing instruction
1221	// is directly returned to processor in this state.
1222	//
1223	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1224	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1225	// and goes to the ICACHE_TLB_WAIT state.
1226	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1227	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1228	//
1229	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1230	// using the r_dcache_xtn_req flip-flop.
1231	// The request opcode and the address to be invalidated are transmitted
1232	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1233	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1234	// is completed.
1235	//
1236	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1237	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1238	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1239	////////////////////////////////////////////////////////////////////////////////////////
1240
1241	// The default value for irsp.valid is false
1242	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
1243
1244	switch( r_icache_fsm.read() )
1245	{
1246	/////////////////
1247	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1248	// by DCACHE FSM, and coherence requests with a fixed priority:
1249	// coherence > XTN > instruction
1250	// We access the itlb and dcache in parallel with the virtual address
1251	// for itlb, and with a speculative physical address for icache,
1252	// computed during the previous cycle.
1253	{
1254	// coherence request from the target FSM
1255	if ( r_tgt_icache_req.read() )
1256	{
1257	r_icache_fsm = ICACHE_CC_CHECK;
1258	r_icache_fsm_save = r_icache_fsm.read();
1259	break;
1260	}
1261
1262	// Decoding processor XTN requests sent by DCACHE FSM
1263	// These request are not executed in this IDLE state, because
1264	// they require access to icache or itlb, that are already accessed
1265	if ( r_dcache_xtn_req.read() )
1266	{
1267	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1268	{
1269	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1270	break;
1271	}
1272	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1273	{
1274	r_icache_flush_count = 0;
1275	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1276	break;
1277	}
1278	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1279	{
1280	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1281	break;
1282	}
1283	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1284	{
1285	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1286	break;
1287	}
1288	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1289	{
1290	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1291	(paddr_t)r_mmu_word_lo.read();
1292	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1293	break;
1294	}
1295	} // end if xtn_req
1296
1297	// processor request
1298	if ( ireq.valid )
1299	{
1300	bool cacheable;
1301	paddr_t paddr;
1302
1303	// We register processor request
1304	r_icache_vaddr_save = ireq.addr;
1305
1306	// speculative icache access (if cache activated)
1307	// we use the speculative PPN computed during the previous cycle
1308
1309	uint32_t cache_inst = 0;
1310	bool cache_hit = false;
1311
1312	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1313	{
1314	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1315	((paddr_t)ireq.addr & PAGE_K_MASK);
1316
1317	#ifdef INSTRUMENTATION
1318	m_cpt_icache_data_read++;
1319	m_cpt_icache_dir_read++;
1320	#endif
1321	cache_hit = r_icache.read( spc_paddr,
1322	&cache_inst );
1323	}
1324
1325	// systematic itlb access (if tlb activated)
1326	// we use the virtual address
1327
1328	paddr_t tlb_paddr;
1329	pte_info_t tlb_flags;
1330	size_t tlb_way;
1331	size_t tlb_set;
1332	paddr_t tlb_nline;
1333	bool tlb_hit = false;;
1334
1335	if ( r_mmu_mode.read() & INS_TLB_MASK )
1336	{
1337
1338	#ifdef INSTRUMENTATION
1339	m_cpt_itlb_read++;
1340	#endif
1341	tlb_hit = r_itlb.translate( ireq.addr,
1342	&tlb_paddr,
1343	&tlb_flags,
1344	&tlb_nline, // unused
1345	&tlb_way, // unused
1346	&tlb_set ); // unused
1347	}
1348
1349	// We compute cacheability, physical address and check access rights:
1350	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1351	// the physical address is obtained from the TLB, and the access rights are
1352	// defined by the U and X bits in the PTE.
1353	// - If MMU not activated : cacheability is defined by the segment table,
1354	// the physical address is equal to the virtual address (identity mapping)
1355	// and there is no access rights checking
1356
1357	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1358	{
1359	// cacheability
1360	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1361	else cacheable = m_cacheability_table[ireq.addr];
1362
1363	// physical address
1364	paddr = (paddr_t)ireq.addr;
1365	}
1366	else // itlb activated
1367	{
1368	if ( tlb_hit ) // tlb hit
1369	{
1370	// cacheability
1371	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1372	else cacheable = tlb_flags.c;
1373
1374	// physical address
1375	paddr = tlb_paddr;
1376
1377	// access rights checking
1378	if ( not tlb_flags.u && (ireq.mode == iss_t::MODE_USER) )
1379	{
1380	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1381	r_mmu_ibvar = ireq.addr;
1382	irsp.valid = true;
1383	irsp.error = true;
1384	irsp.instruction = 0;
1385	break;
1386	}
1387	else if ( not tlb_flags.x )
1388	{
1389	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1390	r_mmu_ibvar = ireq.addr;
1391	irsp.valid = true;
1392	irsp.error = true;
1393	irsp.instruction = 0;
1394	break;
1395	}
1396	}
1397	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1398	else
1399	{
1400
1401	#ifdef INSTRUMENTATION
1402	m_cpt_itlb_miss++;
1403	#endif
1404	r_icache_fsm = ICACHE_TLB_WAIT;
1405	r_icache_tlb_miss_req = true;
1406	break;
1407	}
1408	} // end if itlb activated
1409
1410	// physical address registration (for next cycle)
1411	r_icache_vci_paddr = paddr;
1412
1413	// We enter this section only in case of TLB hit:
1414	// Finally, we get the instruction depending on cacheability,
1415	// we send the response to processor, and compute next state
1416	if ( cacheable ) // cacheable read
1417	{
1418	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1419	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1420	{
1421
1422	#ifdef INSTRUMENTATION
1423	m_cpt_icache_spc_miss++;
1424	#endif
1425	// we return an invalid response and stay in IDLE state
1426	// the cache access will cost one extra cycle.
1427	break;
1428	}
1429
1430	if ( not cache_hit ) // cache miss
1431	{
1432	// in case of icache miss we send a request to CMD FSM, but we are
1433	// blocked in IDLE state if the previous cleanup is not completed
1434	if ( not r_icache_cleanup_req.read() )
1435	{
1436
1437	#ifdef INSTRUMENTATION
1438	m_cpt_icache_miss++;
1439	#endif
1440	r_icache_fsm = ICACHE_MISS_VICTIM;
1441	r_icache_miss_req = true;
1442	}
1443	break;
1444	}
1445	else // cache hit
1446	{
1447
1448	#ifdef INSTRUMENTATION
1449	m_cpt_ins_read++;
1450	#endif
1451	irsp.valid = true;
1452	irsp.instruction = cache_inst;
1453	}
1454	}
1455	else // non cacheable read
1456	{
1457	r_icache_unc_req = true;
1458	r_icache_fsm = ICACHE_UNC_WAIT;
1459	}
1460	} // end if ireq.valid
1461	break;
1462	}
1463	/////////////////////
1464	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1465	// the itlb is udated by the DCACHE FSM, as well as the
1466	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1467	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1468	// reset the r_icache_tlb_miss_req flip-flop
1469	// external coherence request are accepted in this state.
1470	{
1471	// external coherence request
1472	if ( r_tgt_icache_req.read() )
1473	{
1474	r_icache_fsm = ICACHE_CC_CHECK;
1475	r_icache_fsm_save = r_icache_fsm.read();
1476	break;
1477	}
1478
1479	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1480
1481	// DCACHE FSM signals response by reseting the request flip-flop
1482	if ( not r_icache_tlb_miss_req.read() )
1483	{
1484	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1485	{
1486	r_icache_tlb_rsp_error = false;
1487	irsp.error = true;
1488	irsp.valid = true;
1489	r_icache_fsm = ICACHE_IDLE;
1490	}
1491	else // tlb updated : return to IDLE state
1492	{
1493	r_icache_fsm = ICACHE_IDLE;
1494	}
1495	}
1496	break;
1497	}
1498	//////////////////////////
1499	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1500	{
1501	r_itlb.flush();
1502	r_dcache_xtn_req = false;
1503	r_icache_fsm = ICACHE_IDLE;
1504	break;
1505	}
1506	////////////////////////////
1507	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1508	// the r_icache_flush_count register as a slot counter.
1509	// We loop in this state until all slots have been visited.
1510	// A cleanup request is generated for each valid line
1511	// and we are blocked until the previous cleanup is completed
1512	{
1513	if ( not r_icache_cleanup_req.read() )
1514	{
1515	size_t way = r_icache_flush_count.read()/m_icache_sets;
1516	size_t set = r_icache_flush_count.read()%m_icache_sets;
1517	paddr_t nline;
1518	bool cleanup_req = r_icache.inval( way,
1519	set,
1520	&nline );
1521	if ( cleanup_req )
1522	{
1523	r_icache_cleanup_req = true;
1524	r_icache_cleanup_line = nline;
1525	}
1526	r_icache_flush_count = r_icache_flush_count.read() + 1;
1527	}
1528
1529	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1530	{
1531	r_dcache_xtn_req = false;
1532	r_icache_fsm = ICACHE_IDLE;
1533	}
1534	break;
1535	}
1536	//////////////////////////
1537	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1538	// stored in the r_dcache_p0_wdata register
1539	{
1540	r_itlb.inval(r_dcache_p0_wdata.read());
1541	r_dcache_xtn_req = false;
1542	r_icache_fsm = ICACHE_IDLE;
1543	break;
1544	}
1545	///////////////////////////////
1546	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1547	// requires 3 cycles (in case of hit on itlb and icache).
1548	// In this state, we access TLB to translate virtual address
1549	// stored in the r_dcache_p0_wdata register.
1550	{
1551	paddr_t paddr;
1552	bool hit;
1553
1554	// read physical address in TLB when MMU activated
1555	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1556	{
1557
1558	#ifdef INSTRUMENTATION
1559	m_cpt_itlb_read++;
1560	#endif
1561	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1562	&paddr);
1563	}
1564	else // itlb not activated
1565	{
1566	paddr = (paddr_t)r_dcache_p0_wdata.read();
1567	hit = true;
1568	}
1569
1570	if ( hit ) // continue the selective inval process
1571	{
1572	r_icache_vci_paddr = paddr;
1573	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1574	}
1575	else // miss : send a request to DCACHE FSM
1576	{
1577
1578	#ifdef INSTRUMENTATION
1579	m_cpt_itlb_miss++;
1580	#endif
1581	r_icache_tlb_miss_req = true;
1582	r_icache_fsm = ICACHE_TLB_WAIT;
1583	}
1584	break;
1585	}
1586	///////////////////////////////
1587	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1588	// require 2 cycles. In this state, we read dcache,
1589	// with address stored in r_icache_vci_paddr register.
1590	{
1591	uint32_t data;
1592	size_t way;
1593	size_t set;
1594	size_t word;
1595	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1596	&data,
1597	&way,
1598	&set,
1599	&word);
1600	if ( hit ) // inval to be done
1601	{
1602	r_icache_miss_way = way;
1603	r_icache_miss_set = set;
1604	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1605	}
1606	else // miss : acknowlege the XTN request and return
1607	{
1608	r_dcache_xtn_req = false;
1609	r_icache_fsm = ICACHE_IDLE;
1610	}
1611	break;
1612	}
1613	///////////////////////////////
1614	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1615	// We are blocked if the previous cleanup is not completed
1616	{
1617	paddr_t nline;
1618
1619	if ( not r_icache_cleanup_req.read() )
1620	{
1621	r_icache.inval( r_icache_miss_way.read(),
1622	r_icache_miss_set.read(),
1623	&nline );
1624
1625	// request cleanup
1626	r_icache_cleanup_req = true;
1627	r_icache_cleanup_line = nline;
1628	// acknowledge the XTN request and return
1629	r_dcache_xtn_req = false;
1630	r_icache_fsm = ICACHE_IDLE;
1631	}
1632	break;
1633	}
1634
1635	////////////////////////
1636	case ICACHE_MISS_VICTIM: // Selects a victim line
1637	// Set the r_icache_cleanup_req flip-flop
1638	// when the selected slot is not empty
1639	{
1640	if ( ireq.valid ) m_cost_ins_miss_frz++;
1641
1642	bool valid;
1643	size_t way;
1644	size_t set;
1645	paddr_t victim;
1646
1647	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1648	&victim,
1649	&way,
1650	&set);
1651	r_icache_miss_way = way;
1652	r_icache_miss_set = set;
1653
1654	if ( valid )
1655	{
1656	r_icache_cleanup_req = true;
1657	r_icache_cleanup_line = victim;
1658	r_icache_fsm = ICACHE_MISS_INVAL;
1659	}
1660	else
1661	{
1662	r_icache_fsm = ICACHE_MISS_WAIT;
1663	}
1664	break;
1665	}
1666	///////////////////////
1667	case ICACHE_MISS_INVAL: // invalidate the victim line
1668	{
1669	paddr_t nline;
1670
1671	r_icache.inval( r_icache_miss_way.read(),
1672	r_icache_miss_set.read(),
1673	&nline ); // unused
1674
1675	r_icache_fsm = ICACHE_MISS_WAIT;
1676	break;
1677	}
1678	//////////////////////
1679	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1680	{
1681	if ( ireq.valid ) m_cost_ins_miss_frz++;
1682
1683	// external coherence request
1684	if ( r_tgt_icache_req.read() )
1685	{
1686	r_icache_fsm = ICACHE_CC_CHECK;
1687	r_icache_fsm_save = r_icache_fsm.read();
1688	break;
1689	}
1690
1691	if ( r_vci_rsp_ins_error.read() ) // bus error
1692	{
1693	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1694	r_mmu_ibvar = r_icache_vaddr_save.read();
1695	irsp.valid = true;
1696	irsp.error = true;
1697	r_vci_rsp_ins_error = false;
1698	r_icache_fsm = ICACHE_IDLE;
1699	}
1700	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1701	{
1702	r_icache_miss_word = 0;
1703	r_icache_fsm = ICACHE_MISS_UPDT;
1704	}
1705	break;
1706	}
1707	//////////////////////
1708	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1709	{
1710	if ( ireq.valid ) m_cost_ins_miss_frz++;
1711
1712	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1713	{
1714	if ( r_icache_miss_inval ) // Matching coherence request
1715	// We pop the response FIFO, without updating the cache
1716	// We send a cleanup for the missing line at the last word
1717	// Blocked if the previous cleanup is not completed
1718	{
1719	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1720	{
1721	vci_rsp_fifo_icache_get = true;
1722	r_icache_miss_word = r_icache_miss_word.read() + 1;
1723	}
1724	else // last word
1725	{
1726	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1727	{
1728	vci_rsp_fifo_icache_get = true;
1729	r_icache_cleanup_req = true;
1730	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1731	r_icache_miss_inval = false;
1732	r_icache_fsm = ICACHE_IDLE;
1733	}
1734	}
1735	}
1736	else // No matching coherence request
1737	// We pop the FIFO and update the cache
1738	// We update the directory at the last word
1739	{
1740
1741	#ifdef INSTRUMENTATION
1742	m_cpt_icache_data_write++;
1743	#endif
1744	r_icache.write( r_icache_miss_way.read(),
1745	r_icache_miss_set.read(),
1746	r_icache_miss_word.read(),
1747	r_vci_rsp_fifo_icache.read() );
1748	vci_rsp_fifo_icache_get = true;
1749	r_icache_miss_word = r_icache_miss_word.read() + 1;
1750	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1751	{
1752
1753	#ifdef INSTRUMENTATION
1754	m_cpt_icache_dir_write++;
1755	#endif
1756	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1757	r_icache_miss_way.read(),
1758	r_icache_miss_set.read() );
1759	r_icache_fsm = ICACHE_IDLE;
1760	}
1761	}
1762	}
1763	break;
1764	}
1765	////////////////////
1766	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1767	//
1768	{
1769	// external coherence request
1770	if ( r_tgt_icache_req.read() )
1771	{
1772	r_icache_fsm = ICACHE_CC_CHECK;
1773	r_icache_fsm_save = r_icache_fsm.read();
1774	break;
1775	}
1776
1777	if ( r_vci_rsp_ins_error.read() ) // bus error
1778	{
1779	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1780	r_mmu_ibvar = ireq.addr;
1781	r_vci_rsp_ins_error = false;
1782	irsp.valid = true;
1783	irsp.error = true;
1784	r_icache_fsm = ICACHE_IDLE;
1785	}
1786	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1787	{
1788	vci_rsp_fifo_icache_get = true;
1789	r_icache_fsm = ICACHE_IDLE;
1790	if ( ireq.valid and (ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1791	{
1792	irsp.valid = true;
1793	irsp.instruction = r_vci_rsp_fifo_icache.read();
1794	}
1795	}
1796	break;
1797	}
1798	/////////////////////
1799	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1800	// handling coherence requests.
1801	// the return state is defined in r_icache_fsm_save.
1802	{
1803	paddr_t paddr = r_tgt_paddr.read();
1804	paddr_t mask = ~((m_icache_words<<2)-1);
1805
1806	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1807	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1808	{
1809	r_icache_miss_inval = true; // signaling the matching
1810	r_tgt_icache_req = false; // coherence request completed
1811	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1812	r_icache_fsm = r_icache_fsm_save.read();
1813	}
1814	else // no match
1815	{
1816
1817	#ifdef INSTRUMENTATION
1818	m_cpt_icache_dir_read++;
1819	#endif
1820	uint32_t inst;
1821	size_t way;
1822	size_t set;
1823	size_t word;
1824	bool hit = r_icache.read(paddr,
1825	&inst,
1826	&way,
1827	&set,
1828	&word);
1829	r_icache_cc_way = way;
1830	r_icache_cc_set = set;
1831
1832	if ( hit and r_tgt_update.read() ) // hit update
1833	{
1834	r_icache_fsm = ICACHE_CC_UPDT;
1835	r_icache_cc_word = r_tgt_word_min.read();
1836	}
1837	else if ( hit and not r_tgt_update.read() ) // hit inval
1838	{
1839	r_icache_fsm = ICACHE_CC_INVAL;
1840	}
1841	else // miss can happen
1842	{
1843	r_tgt_icache_req = false;
1844	r_tgt_icache_rsp = r_tgt_update.read();
1845	r_icache_fsm = r_icache_fsm_save.read();
1846	}
1847	}
1848	break;
1849	}
1850
1851	/////////////////////
1852	case ICACHE_CC_INVAL: // invalidate a cache line
1853	{
1854	paddr_t nline;
1855	r_icache.inval( r_icache_cc_way.read(),
1856	r_icache_cc_set.read(),
1857	&nline );
1858
1859	r_tgt_icache_req = false;
1860	r_tgt_icache_rsp = true;
1861	r_icache_fsm = r_icache_fsm_save.read();
1862	break;
1863	}
1864	////////////////////
1865	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1866	{
1867	size_t word = r_icache_cc_word.read();
1868	size_t way = r_icache_cc_way.read();
1869	size_t set = r_icache_cc_set.read();
1870
1871	r_icache.write( way,
1872	set,
1873	word,
1874	r_tgt_buf[word],
1875	r_tgt_be[word] );
1876
1877	r_icache_cc_word = word+1;
1878
1879	if ( word == r_tgt_word_max.read() ) // last word
1880	{
1881	r_tgt_icache_req = false;
1882	r_tgt_icache_rsp = true;
1883	r_icache_fsm = r_icache_fsm_save.read();
1884	}
1885	break;
1886	}
1887
1888	} // end switch r_icache_fsm
1889
1890	// save the IREQ and IRSP fields for the print_trace() function
1891	m_ireq_valid = ireq.valid;
1892	m_ireq_addr = ireq.addr;
1893	m_ireq_mode = ireq.mode;
1894
1895	m_irsp_valid = irsp.valid;
1896	m_irsp_instruction = irsp.instruction;
1897	m_irsp_error = irsp.error;
1898
1899	////////////////////////////////////////////////////////////////////////////////////
1900	// DCACHE FSM
1901	//
1902	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1903	// the cacheability, depending on the MMU mode.
1904	//
1905	// 1/ Coherence requests :
1906	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1907	// requesting a line invalidation or a line update.
1908	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1909	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1910	// goes to the CC_CHECK state to execute the requested action, and returns to the
1911	// pre-empted state.
1912	//
1913	// 2/ processor requests :
1914	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1915	// The IDLE state implements a three stages pipe-line to handle write bursts:
1916	// - The physical address is computed by dtlb in stage P0.
1917	// - The registration in wbuf and the dcache hit are computed in stage P1.
1918	// - The dcache update is done in stage P2.
1919	// A write operation can require a fourth stage if the dirty bit must be updated,
1920	// or if the TLBs must be cleared, but these "long write" operation requires
1921	// to exit the IDLE stage
1922	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1923	// (virtual address for itlb, and speculative physical address computed during
1924	// previous cycle for dcache) in order to return the data in one cycle for a read.
1925	// We just pay an extra cycle when the speculative access is illegal.
1926	//
1927	// 3/ Atomic instructions LL/SC
1928	// The LL/SC address can be cacheable or non cacheable.
1929	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1930	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1931	// memory controller.
1932	// - LL requests from the processor are transmitted as standard VCI
1933	// READ transactions (one word / one line, depending on the cacheability).
1934	// - SC requests from the processor are systematically transmitted to the
1935	// memory cache as COMPARE&swap requests (both the data value stored in the
1936	// r_dcache_ll_data register and the new value).
1937	//
1938	// 4/ Non cacheable access:
1939	// This component implement a strong order between non cacheable access
1940	// (read or write) : A new non cacheable VCI transaction starts only when
1941	// the previous non cacheable transaction is completed. Both cacheable and
1942	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1943	// a non cacheable write transaction posted in the write buffer by setting the
1944	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1945	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1946	// pending non cacheable write transaction completes).
1947	//
1948	// 5/ Error handling:
1949	// When the MMU is not activated, Read Bus Errors are synchronous events,
1950	// but Write Bus Errors are asynchronous events (processor is not frozen).
1951	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1952	// r_vci_rsp_data_error flip-flop, without writing any data in the
1953	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1954	// by the DCACHE FSM.
1955	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1956	// the asynchronous error using the setWriteBerr() method.
1957	// When the MMU is activated bus error are rare events, as the MMU
1958	// checks the physical address before the VCI transaction starts.
1959	////////////////////////////////////////////////////////////////////////////////////////
1960
1961	// The default value for drsp.valid is false
1962	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
1963
1964	switch ( r_dcache_fsm.read() )
1965	{
1966	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1967	// 1) Long write request (DCACHE FSM) => DCACHE_WRITE_***
1968	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1969	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1970	// 4) XTN request (processor) => DCACHE_XTN_*
1971	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1972	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1973	// 7) Uncacheable read (processor) => DCACHE_UNC_REQ
1974	// 8) SC access (processor) => DCACHE_SC
1975	// There is 4 configurations to access the cache,
1976	// depending on the pipe-line state, defined
1977	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1978	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1979	// V0 / V1 / Data / Directory / comment
1980	// 0 / 0 / read(A0) / read(A0) / read speculative access
1981	// 0 / 1 / write(A2) / nop / read request delayed
1982	// 1 / 0 / nop / read(A1) / read request delayed
1983	// 1 / 1 / write(A2) / read(A1) / read request delayed
1984	{
1985	////////////////////////////////////////////////////////////////////////////////
1986	// Handling P2 pipe-line stage
1987	// Inputs are r_dcache_p1_* registers.
1988	// Three actions are executed in this P2 stage:
1989	// - If r_dcache_p1_updt_cache is true, we update the local copy in dcache.
1990	// - If the modified cache line has copies in TLBs, we launch a TLB invalidate
1991	// operation, that is blocking for the processor, because we switch to
1992	// DCACHE_INVAL_TLB
1993	// - If the PTE dirty bit must be updated, we start a "long write", that is
1994	// blocking for the processor, because we switch to the DCACHE_WRITE_SET_DIRTY
1995
1996	bool long_write_set_dirty = false;
1997	bool tlb_inval_required = false;
1998
1999	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2000	{
2001	bool cache_updt = r_dcache_p1_updt_cache.read();
2002	size_t way = r_dcache_p1_cache_way.read();
2003	size_t set = r_dcache_p1_cache_set.read();
2004	size_t word = r_dcache_p1_cache_word.read();
2005	uint32_t wdata = r_dcache_p1_wdata.read();
2006	vci_be_t be = r_dcache_p1_be.read();
2007
2008	// update dcache if required
2009	if ( cache_updt )
2010	{
2011	r_dcache.write( way,
2012	set,
2013	word,
2014	wdata,
2015	be );
2016	#ifdef INSTRUMENTATION
2017	m_cpt_dcache_data_write++;
2018	#endif
2019	// cache update can require itlb & dtlb inval
2020	bool inval_itlb = false;
2021	bool inval_dtlb = false;
2022
2023	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
2024	{
2025	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
2026	inval_dtlb = true;
2027	}
2028	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
2029	{
2030	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
2031	inval_itlb = true;
2032	}
2033	if ( inval_itlb or inval_dtlb )
2034	{
2035	tlb_inval_required = true;
2036	r_dcache_itlb_inval_req = inval_itlb;
2037	r_dcache_dtlb_inval_req = inval_dtlb;
2038	r_dcache_tlb_inval_count = 0;
2039	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2));
2040	}
2041	} // end dcache update
2042
2043	// checking if dirty bit update is required
2044	if ( r_dcache_p1_set_dirty.read() )
2045	{
2046	long_write_set_dirty = true;
2047	r_dcache_p2_vaddr = r_dcache_p1_vaddr.read();
2048	r_dcache_p2_set_dirty = r_dcache_p1_set_dirty.read();
2049	r_dcache_p2_tlb_way = r_dcache_p1_tlb_way.read();
2050	r_dcache_p2_tlb_set = r_dcache_p1_tlb_set.read();
2051	// The PTE physical address is the concatenation of the nline value (from dtlb),
2052	// with the word index (obtained from the proper bits of the virtual address)
2053	if ( r_dcache_p1_tlb_big.read() ) // PTE1
2054	{
2055	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2)) \|
2056	(paddr_t)((r_dcache_p1_vaddr.read()>>19) & 0x3c);
2057	}
2058	else // PTE2
2059	{
2060	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2)) \|
2061	(paddr_t)((r_dcache_p1_vaddr.read()>>10) & 0x3c);
2062	}
2063	}
2064
2065	#if DEBUG_DCACHE
2066	if ( m_debug_dcache_fsm )
2067	{
2068	if ( cache_updt )
2069	std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec
2070	<< " / way = " << way
2071	<< " / set = " << set
2072	<< " / word = " << word << std::hex
2073	<< " / wdata = " << wdata
2074	<< " / be = " << be << std::endl;
2075	if ( long_write_set_dirty )
2076	std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required"
2077	<< " / pte_paddr = " << std::hex << r_dcache_p2_pte_paddr.read() << std::endl;
2078	}
2079	#endif
2080	} // end P2 stage
2081
2082	///////////////////////////////////////////////////////////////////////////
2083	// Handling P1 pipe-line stage
2084	// Inputs are r_dcache_p0_* registers.
2085	// - We must write into wbuf and test the hit in dcache.
2086	// If the write request is not cacheable, and there is a pending
2087	// non cacheable write, or if the write buffer is full, we break:
2088	// The P0 and P1 pipe-line stages are frozen until the write
2089	// request registration is possible, but the P2 stage is not frozen.
2090	// - The r_dcache_p1_valid bit activating the P2 pipe-line stage
2091	// must be computed at all cycles. The P2 stage must be activated
2092	// if there is local copy in dcache, or if the PTE dirty bit must be set.
2093
2094	if ( r_dcache_p0_valid.read() and not tlb_inval_required ) // P1 stage activated
2095	{
2096	// write not cacheable, and previous non cacheable write registered
2097	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2098	{
2099	r_dcache_p1_valid = false;
2100	break;
2101	}
2102
2103	// try a registration into write buffer
2104	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2105	r_dcache_p0_be.read(),
2106	r_dcache_p0_wdata.read(),
2107	r_dcache_p0_cacheable.read() );
2108	#ifdef INSTRUMENTATION
2109	m_cpt_wbuf_write++;
2110	#endif
2111	// write buffer full
2112	if ( not wok )
2113	{
2114	r_dcache_p1_valid = false;
2115	break;
2116	}
2117	// update the write_buffer state extension
2118	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2119
2120	// read directory to detect local copy
2121	size_t cache_way;
2122	size_t cache_set;
2123	size_t cache_word;
2124	bool local_copy;
2125	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2126	{
2127	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2128	&cache_way,
2129	&cache_set,
2130	&cache_word );
2131	#ifdef INSTRUMENTATION
2132	m_cpt_dcache_dir_read++;
2133	#endif
2134	}
2135	else
2136	{
2137	local_copy = false;
2138	}
2139
2140	// dirty bit update requested
2141	bool dirty_req = (r_mmu_mode.read() & DATA_TLB_MASK) and not r_dcache_p0_tlb_dirty.read();
2142
2143	// if there is a local copy or a dirty bit update requested
2144	if ( local_copy or dirty_req )
2145	{
2146	r_dcache_p1_valid = true;
2147	r_dcache_p1_set_dirty = dirty_req;
2148	r_dcache_p1_updt_cache = local_copy;
2149	r_dcache_p1_vaddr = r_dcache_p0_vaddr.read();
2150	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2151	r_dcache_p1_be = r_dcache_p0_be.read();
2152	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2153	r_dcache_p1_tlb_way = r_dcache_p0_tlb_way;
2154	r_dcache_p1_tlb_set = r_dcache_p0_tlb_set;
2155	r_dcache_p1_tlb_nline = r_dcache_p0_tlb_nline;
2156	r_dcache_p1_tlb_big = r_dcache_p0_tlb_big;
2157	r_dcache_p1_cache_way = cache_way;
2158	r_dcache_p1_cache_set = cache_set;
2159	r_dcache_p1_cache_word = cache_word;
2160	}
2161	else
2162	{
2163	r_dcache_p1_valid = false;
2164	}
2165	}
2166	else // P1 stage not activated
2167	{
2168	r_dcache_p1_valid = false;
2169	} // end P1 stage
2170
2171	/////////////////////////////////////////////////////////////////////////////
2172	// handling P0 pipe-line stage
2173	// This stage is controlling the DCACHE FSM state register:
2174	// - the TLB invalidate requests have the highest priority,
2175	// - then the long write requests,
2176	// - then the external coherence requests,
2177	// - then the itlb miss requests,
2178	// - and finally the processor requests.
2179	// A processor read request generate a dcache access using speculative PPN
2180	// only if the write pipe-line is empty. There is an unconditionnal access
2181	// to the dtlb, using virtual address from processor.
2182	// The r_dcache_p0_valid value must be computed at all cycles.
2183
2184	bool p0_valid = false; // default value
2185
2186	// TLB inval required
2187	if ( tlb_inval_required )
2188	{
2189	r_dcache_fsm_save = DCACHE_IDLE;
2190	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2191	}
2192
2193	// long write request
2194	else if ( long_write_set_dirty )
2195	{
2196	r_dcache_fsm = DCACHE_WRITE_TLB_DIRTY;
2197	}
2198
2199	// external coherence request
2200	else if ( r_tgt_dcache_req.read() )
2201	{
2202	r_dcache_fsm_save = DCACHE_IDLE;
2203	r_dcache_fsm = DCACHE_CC_CHECK;
2204	}
2205
2206	// itlb miss request
2207	else if ( r_icache_tlb_miss_req.read() )
2208	{
2209	r_dcache_tlb_ins = true;
2210	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2211	r_dcache_fsm = DCACHE_TLB_MISS;
2212	}
2213
2214	// processor request
2215	else if (dreq.valid )
2216	{
2217	// dcache access using speculative PPN only if pipe-line empty
2218	paddr_t cache_paddr;
2219	size_t cache_way;
2220	size_t cache_set;
2221	size_t cache_word;
2222	uint32_t cache_rdata;
2223	bool cache_hit;
2224
2225	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2226	not r_dcache_p0_valid.read() and
2227	not r_dcache_p1_valid.read() ) // pipe-line empty
2228	{
2229	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2230	((paddr_t)dreq.addr & PAGE_K_MASK);
2231
2232	cache_hit = r_dcache.read( cache_paddr,
2233	&cache_rdata,
2234	&cache_way,
2235	&cache_set,
2236	&cache_word );
2237	#ifdef INSTRUMENTATION
2238	m_cpt_dcache_dir_read++;
2239	m_cpt_dcache_data_read++;
2240	#endif
2241	}
2242	else
2243	{
2244	cache_hit = false;
2245	} // end dcache access
2246
2247	// systematic dtlb access using virtual address
2248
2249	paddr_t tlb_paddr;
2250	pte_info_t tlb_flags;
2251	size_t tlb_way;
2252	size_t tlb_set;
2253	paddr_t tlb_nline;
2254	bool tlb_hit;
2255
2256	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // TLB activated
2257	{
2258	tlb_hit = r_dtlb.translate( dreq.addr,
2259	&tlb_paddr,
2260	&tlb_flags,
2261	&tlb_nline,
2262	&tlb_way,
2263	&tlb_set );
2264	#ifdef INSTRUMENTATION
2265	m_cpt_dtlb_read++;
2266	#endif
2267	// register dtlb outputs
2268	r_dcache_p0_tlb_nline = tlb_nline;
2269	r_dcache_p0_tlb_way = tlb_way;
2270	r_dcache_p0_tlb_set = tlb_set;
2271	r_dcache_p0_tlb_dirty = tlb_flags.d;
2272	r_dcache_p0_tlb_big = tlb_flags.b;
2273	}
2274	else
2275	{
2276	tlb_hit = false;
2277	} // end dtlb access
2278
2279	// register the processor request
2280	r_dcache_p0_vaddr = dreq.addr;
2281	r_dcache_p0_be = dreq.be;
2282	r_dcache_p0_wdata = dreq.wdata;
2283
2284	// Handling READ XTN requests from processor
2285	// They are executed in this DCACHE_IDLE state.
2286	// The processor must not be in user mode
2287	if (dreq.type == iss_t::XTN_READ)
2288	{
2289	int xtn_opcode = (int)dreq.addr/4;
2290
2291	// checking processor mode:
2292	if (dreq.mode == iss_t::MODE_USER)
2293	{
2294	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2295	r_mmu_dbvar = dreq.addr;
2296	drsp.valid = true;
2297	drsp.error = true;
2298	r_dcache_fsm = DCACHE_IDLE;
2299	}
2300	else
2301	{
2302	switch( xtn_opcode )
2303	{
2304	case iss_t::XTN_INS_ERROR_TYPE:
2305	drsp.rdata = r_mmu_ietr.read();
2306	drsp.valid = true;
2307	break;
2308
2309	case iss_t::XTN_DATA_ERROR_TYPE:
2310	drsp.rdata = r_mmu_detr.read();
2311	drsp.valid = true;
2312	break;
2313
2314	case iss_t::XTN_INS_BAD_VADDR:
2315	drsp.rdata = r_mmu_ibvar.read();
2316	drsp.valid = true;
2317	break;
2318
2319	case iss_t::XTN_DATA_BAD_VADDR:
2320	drsp.rdata = r_mmu_dbvar.read();
2321	drsp.valid = true;
2322	break;
2323
2324	case iss_t::XTN_PTPR:
2325	drsp.rdata = r_mmu_ptpr.read();
2326	drsp.valid = true;
2327	break;
2328
2329	case iss_t::XTN_TLB_MODE:
2330	drsp.rdata = r_mmu_mode.read();
2331	drsp.valid = true;
2332	break;
2333
2334	case iss_t::XTN_MMU_PARAMS:
2335	drsp.rdata = r_mmu_params;
2336	drsp.valid = true;
2337	break;
2338
2339	case iss_t::XTN_MMU_RELEASE:
2340	drsp.rdata = r_mmu_release;
2341	drsp.valid = true;
2342	break;
2343
2344	case iss_t::XTN_MMU_WORD_LO:
2345	drsp.rdata = r_mmu_word_lo.read();
2346	drsp.valid = true;
2347	break;
2348
2349	case iss_t::XTN_MMU_WORD_HI:
2350	drsp.rdata = r_mmu_word_hi.read();
2351	drsp.valid = true;
2352	break;
2353
2354	default:
2355	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2356	r_mmu_dbvar = dreq.addr;
2357	drsp.valid = true;
2358	drsp.error = true;
2359	break;
2360	} // end switch xtn_opcode
2361	} // end else
2362	} // end if XTN_READ
2363
2364	// Handling WRITE XTN requests from processor.
2365	// They are not executed in this DCACHE_IDLE state,
2366	// if they require access to the caches or the TLBs
2367	// that are already accessed for speculative read.
2368	// Caches can be invalidated or flushed in user mode,
2369	// and the sync instruction can be executed in user mode
2370	else if (dreq.type == iss_t::XTN_WRITE)
2371	{
2372	int xtn_opcode = (int)dreq.addr/4;
2373	r_dcache_xtn_opcode = xtn_opcode;
2374
2375	// checking processor mode:
2376	if ( (dreq.mode == iss_t::MODE_USER) &&
2377	(xtn_opcode != iss_t:: XTN_SYNC) &&
2378	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2379	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2380	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2381	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2382	{
2383	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2384	r_mmu_dbvar = dreq.addr;
2385	drsp.valid = true;
2386	drsp.error = true;
2387	r_dcache_fsm = DCACHE_IDLE;
2388	}
2389	else
2390	{
2391	switch( xtn_opcode )
2392	{
2393	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2394	r_mmu_ptpr = dreq.wdata;
2395	r_dcache_xtn_req = true;
2396	r_dcache_fsm = DCACHE_XTN_SWITCH;
2397	break;
2398
2399	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2400	r_mmu_mode = dreq.wdata;
2401	drsp.valid = true;
2402	r_dcache_fsm = DCACHE_IDLE;
2403	break;
2404
2405	case iss_t::XTN_DTLB_INVAL: // dtlb access
2406	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2407	break;
2408
2409	case iss_t::XTN_ITLB_INVAL: // itlb access
2410	r_dcache_xtn_req = true;
2411	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2412	break;
2413
2414	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2415	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2416	break;
2417
2418	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2419	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2420	r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2421	(paddr_t)r_mmu_word_lo.read();
2422	break;
2423
2424	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2425	r_dcache_flush_count = 0;
2426	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2427	break;
2428
2429	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2430	r_dcache_xtn_req = true;
2431	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2432	break;
2433
2434	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2435	r_dcache_xtn_req = true;
2436	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2437	break;
2438
2439	case iss_t::XTN_ICACHE_FLUSH: // icache access
2440	r_dcache_xtn_req = true;
2441	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2442	break;
2443
2444	case iss_t::XTN_SYNC: // wait until write buffer empty
2445	r_dcache_fsm = DCACHE_XTN_SYNC;
2446	break;
2447
2448	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2449	r_mmu_word_lo = dreq.wdata;
2450	drsp.valid = true;
2451	r_dcache_fsm = DCACHE_IDLE;
2452	break;
2453
2454	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2455	r_mmu_word_hi = dreq.wdata;
2456	drsp.valid = true;
2457	r_dcache_fsm = DCACHE_IDLE;
2458	break;
2459
2460	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2461	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2462	drsp.valid = true;
2463	r_dcache_fsm = DCACHE_IDLE;
2464	break;
2465
2466	default:
2467	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2468	r_mmu_dbvar = dreq.addr;
2469	drsp.valid = true;
2470	drsp.error = true;
2471	r_dcache_fsm = DCACHE_IDLE;
2472	break;
2473	} // end switch xtn_opcode
2474	} // end else
2475	} // end if XTN_WRITE
2476
2477	// Handling read/write processor requests.
2478	// The dtlb and dcache can be activated or not.
2479	// We compute the physical address, the cacheability, and check processor request.
2480	// - If DTLB not activated : cacheability is defined by the segment table,
2481	// the physical address is equal to the virtual address (identity mapping)
2482	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2483	// the physical address is obtained from the TLB, and the U & W bits
2484	// of the PTE are checked.
2485	// The processor request is decoded only if the TLB is not activated or if
2486	// the virtual address hits in tLB and access rights are OK.
2487	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2488	else
2489	{
2490	bool valid_req = false;
2491	bool cacheable = false;
2492	paddr_t paddr = 0;
2493
2494	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2495	{
2496	valid_req = true;
2497
2498	// cacheability
2499	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2500	else cacheable = m_cacheability_table[dreq.addr];
2501
2502	// physical address
2503	paddr = (paddr_t)dreq.addr;
2504	}
2505	else // dtlb activated
2506	{
2507	if ( tlb_hit ) // tlb hit
2508	{
2509	// cacheability
2510	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2511	else cacheable = tlb_flags.c;
2512
2513	// access rights checking
2514	if ( not tlb_flags.u and (dreq.mode == iss_t::MODE_USER))
2515	{
2516	if ( (dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL) )
2517	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2518	else
2519	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2520
2521	r_mmu_dbvar = dreq.addr;
2522	drsp.valid = true;
2523	drsp.error = true;
2524	drsp.rdata = 0;
2525	}
2526	else if ( not tlb_flags.w and
2527	((dreq.type == iss_t::DATA_WRITE) or
2528	(dreq.type == iss_t::DATA_SC)) )
2529	{
2530	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2531	r_mmu_dbvar = dreq.addr;
2532	drsp.valid = true;
2533	drsp.error = true;
2534	drsp.rdata = 0;
2535	}
2536	else
2537	{
2538	valid_req = true;
2539	}
2540
2541	// physical address
2542	paddr = tlb_paddr;
2543	}
2544	else // tlb miss
2545	{
2546	r_dcache_tlb_vaddr = dreq.addr;
2547	r_dcache_tlb_ins = false;
2548	r_dcache_fsm = DCACHE_TLB_MISS;
2549	}
2550	} // end DTLB activated
2551
2552	if ( valid_req ) // processor request is valid
2553	{
2554	// physical address and cacheability registration
2555	r_dcache_p0_paddr = paddr;
2556	r_dcache_p0_cacheable = cacheable;
2557
2558	// READ or LL request
2559	// The read requests are taken only if the write pipe-line is empty.
2560	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2561	// If speculative access is KO we just pay one extra cycle.
2562	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2563	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2564	if ( ((dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL)) and
2565	not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2566	{
2567	if ( cacheable ) // cacheable read
2568	{
2569	// if the speculative access is illegal, we pay an extra cycle
2570	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2571	!= (paddr & ~PAGE_K_MASK))
2572	{
2573	#ifdef INSTRUMENTATION
2574	m_cpt_dcache_spec_miss++;
2575	#endif
2576	}
2577	// if cache miss, try to get the missing line
2578	else if ( not cache_hit )
2579	{
2580	#ifdef INSTRUMENTATION
2581	m_cpt_dcache_miss++;
2582	#endif
2583	// blocked in IDLE state if previous cleanup not completed
2584	if ( not r_dcache_cleanup_req.read() )
2585	{
2586	r_dcache_vci_paddr = paddr;
2587	r_dcache_vci_miss_req = true;
2588	r_dcache_miss_type = PROC_MISS;
2589	r_dcache_fsm = DCACHE_MISS_VICTIM;
2590	}
2591	}
2592	// if cache hit return the data
2593	else
2594	{
2595	#ifdef INSTRUMENTATION
2596	m_cpt_data_read++;
2597	#endif
2598	drsp.valid = true;
2599	drsp.rdata = cache_rdata;
2600	}
2601	}
2602	else // uncacheable read
2603	{
2604	r_dcache_vci_paddr = paddr;
2605	r_dcache_vci_unc_be = dreq.be;
2606	r_dcache_vci_unc_req = true;
2607	r_dcache_fsm = DCACHE_UNC_WAIT;
2608	}
2609
2610	// makes reservation in case of LL
2611	if ( dreq.type == iss_t::DATA_LL )
2612	{
2613	r_dcache_ll_valid = true;
2614	r_dcache_ll_data = cache_rdata;
2615	r_dcache_ll_vaddr = dreq.addr;
2616	}
2617	} // end READ or LL
2618
2619	// WRITE request:
2620	// The write request arguments have been registered.
2621	// The physical address has been computed and registered.
2622	// We acknowledge the processor request and activate the P1 pipeline stage.
2623	else if ( dreq.type == iss_t::DATA_WRITE )
2624	{
2625
2626	#ifdef INSTRUMENTATION
2627	m_cpt_data_write++;
2628	#endif
2629	p0_valid = true;
2630	drsp.valid = true;
2631	drsp.rdata = 0;
2632	} // end WRITE
2633
2634	// SC request:
2635	// - if a valid LL reservation (with the same address) is registered,
2636	// we request a SC transaction to CMD FSM and go to the DCACHE_UNC_WAIT state
2637	// that will directly return the response to the processor, and invalidate
2638	// the LL reservation. We don't check a possible write hit in dcache,
2639	// as the cache update is done by the coherence transaction...
2640	// - if there is no registerd LL, we just stay in IDLE state, invalidate
2641	// the LL reservation, and return 1 (atomic access failed)
2642	else if ( dreq.type == iss_t::DATA_SC )
2643	{
2644	#ifdef INSTRUMENTATION
2645	m_cpt_data_sc++;
2646	#endif
2647	// test if valid registered LL
2648	if ( r_dcache_ll_valid.read() and (r_dcache_ll_vaddr.read() == dreq.addr))
2649	{
2650	r_dcache_vci_paddr = paddr;
2651	r_dcache_vci_sc_req = true;
2652	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2653	r_dcache_vci_sc_new = dreq.wdata;
2654	r_dcache_fsm = DCACHE_UNC_WAIT;
2655	}
2656	else // no registered LL
2657	{
2658	drsp.valid = true;
2659	drsp.rdata = 1;
2660	r_dcache_ll_valid = false;
2661	}
2662	} // end SC
2663	} // end valid_req
2664	} // end if read/write request
2665	} // end P0 pipe stage
2666
2667	r_dcache_p0_valid = p0_valid;
2668	break;
2669	}
2670	/////////////////////
2671	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2672	// - Input arguments are r_dcache_tlb_vaddr & r_dcache_tlb_ins
2673	// - The sub-fsm access the dcache to find the missing TLB entry,
2674	// and activates the cache miss procedure in case of miss.
2675	// - It bypass the first level page table access if possible.
2676	// - It uses atomic access to update the R/L access bits
2677	// in the page table if required.
2678	// - It directly updates the itlb or dtlb, and writes into the
2679	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2680	{
2681	uint32_t ptba = 0;
2682	bool bypass;
2683	paddr_t paddr;
2684
2685	// evaluate bypass in order to skip first level page table access
2686	if ( r_dcache_tlb_ins.read() ) // itlb miss
2687	{
2688	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2689	}
2690	else // dtlb miss
2691	{
2692	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2693	}
2694
2695	if ( not bypass ) // Try to read the PTE1/PTD1 in dcache
2696	{
2697	paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2698	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2699	r_dcache_tlb_paddr = paddr;
2700	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2701	}
2702	else // Try to read the PTE2 in dcache
2703	{
2704	paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2705	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2706	r_dcache_tlb_paddr = paddr;
2707	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2708	}
2709
2710	#if DEBUG_DCACHE
2711	if ( m_debug_dcache_fsm )
2712	{
2713	if ( r_dcache_tlb_ins.read() )
2714	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss request:";
2715	else
2716	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss request:";
2717	std::cout << " vaddr = " << std::hex << r_dcache_tlb_vaddr.read()
2718	<< " / bypass = " << bypass
2719	<< " / PTE address = " << paddr << std::endl;
2720	}
2721	#endif
2722
2723	break;
2724	}
2725	/////////////////////////
2726	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2727	{
2728	uint32_t entry;
2729	size_t way;
2730	size_t set;
2731	size_t word;
2732
2733	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2734	&entry,
2735	&way,
2736	&set,
2737	&word );
2738	#ifdef INSTRUMENTATION
2739	m_cpt_dcache_data_read++;
2740	m_cpt_dcache_dir_read++;
2741	#endif
2742	if ( hit ) // hit in dcache
2743	{
2744	if ( not (entry & PTE_V_MASK) ) // unmapped
2745	{
2746	if ( r_dcache_tlb_ins.read() )
2747	{
2748	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2749	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2750	r_icache_tlb_miss_req = false;
2751	r_icache_tlb_rsp_error = true;
2752	}
2753	else
2754	{
2755	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2756	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2757	drsp.valid = true;
2758	drsp.error = true;
2759	}
2760	r_dcache_fsm = DCACHE_IDLE;
2761
2762	#if DEBUG_DCACHE
2763	if ( m_debug_dcache_fsm )
2764	{
2765	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2766	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2767	<< std::dec << " / way = " << way
2768	<< std::dec << " / set = " << set
2769	<< std::dec << " / word = " << word
2770	<< std::hex << " / PTE1 = " << entry << std::endl;
2771	}
2772	#endif
2773
2774	}
2775	else if( entry & PTE_T_MASK ) // PTD : access PT2
2776	{
2777	// register bypass
2778	if ( r_dcache_tlb_ins.read() ) // itlb
2779	{
2780	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2781	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2782	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2783	}
2784	else // dtlb
2785	{
2786	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2787	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2788	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2789	}
2790	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2791	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2792	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2793
2794	#if DEBUG_DCACHE
2795	if ( m_debug_dcache_fsm )
2796	{
2797	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2798	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2799	<< std::dec << " / way = " << way
2800	<< std::dec << " / set = " << set
2801	<< std::dec << " / word = " << word
2802	<< std::hex << " / PTD = " << entry << std::endl;
2803	}
2804	#endif
2805	}
2806	else // PTE1 : update the TLB
2807	{
2808	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
2809	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
2810	r_dcache_tlb_pte_flags = entry;
2811	r_dcache_tlb_cache_way = way;
2812	r_dcache_tlb_cache_set = set;
2813	r_dcache_tlb_cache_word = word;
2814	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2815
2816	#if DEBUG_DCACHE
2817	if ( m_debug_dcache_fsm )
2818	{
2819	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2820	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2821	<< std::dec << " / way = " << way
2822	<< std::dec << " / set = " << set
2823	<< std::dec << " / word = " << word
2824	<< std::hex << " / PTE1 = " << entry << std::endl;
2825	}
2826	#endif
2827	}
2828	}
2829	else // we must load the missing cache line in dcache
2830	{
2831	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2832	r_dcache_miss_type = PTE1_MISS;
2833	r_dcache_fsm = DCACHE_MISS_VICTIM;
2834	r_dcache_vci_miss_req = true;
2835
2836	#if DEBUG_DCACHE
2837	if ( m_debug_dcache_fsm )
2838	{
2839	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2840	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2841	}
2842	#endif
2843	}
2844	break;
2845	}
2846	////////////////////////////
2847	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2848	{
2849	size_t way;
2850	size_t set;
2851
2852	if ( r_dcache_tlb_ins.read() )
2853	{
2854	r_itlb.select( r_dcache_tlb_vaddr.read(),
2855	true, // PTE1
2856	&way,
2857	&set );
2858	#ifdef INSTRUMENTATION
2859	m_cpt_itlb_read++;
2860	#endif
2861	}
2862	else
2863	{
2864	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2865	true, // PTE1
2866	&way,
2867	&set );
2868	#ifdef INSTRUMENTATION
2869	m_cpt_dtlb_read++;
2870	#endif
2871	}
2872	r_dcache_tlb_way = way;
2873	r_dcache_tlb_set = set;
2874	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2875
2876	#if DEBUG_DCACHE
2877	if ( m_debug_dcache_fsm )
2878	{
2879	if ( r_dcache_tlb_ins.read() )
2880	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2881	else
2882	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2883	std::cout << " way = " << std::dec << way
2884	<< " / set = " << set << std::endl;
2885	}
2886	#endif
2887	break;
2888	}
2889	//////////////////////////
2890	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2891	// if L/R bit already set, exit the sub-fsm
2892	// if not, the page table must be updated
2893	{
2894	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2895	uint32_t pte = r_dcache_tlb_pte_flags.read();
2896	bool updt = false;
2897
2898	// test the access bits L/R, depending on the physical address locality
2899	// we must use the 10 MSB bits of the 19 bits PPN1 to obtain the target index
2900	// we must use the 10 MSB bits of the SRCID to obtain the local index
2901	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required
2902
2903	uint32_t target = (pte >> 9) & 0x3FF;
2904	uint32_t local = m_srcid_d >> 4;
2905
2906	if ( local == target ) // local_address
2907	{
2908	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2909	{
2910	updt = true;
2911	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2912	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
2913	}
2914	}
2915	else // remote address
2916	{
2917	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2918	{
2919	updt = true;
2920	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2921	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
2922	}
2923	}
2924
2925	// update TLB
2926	if ( r_dcache_tlb_ins.read() )
2927	{
2928	r_itlb.write( true, // 2M page
2929	pte,
2930	0, // argument unused for a PTE1
2931	r_dcache_tlb_vaddr.read(),
2932	r_dcache_tlb_way.read(),
2933	r_dcache_tlb_set.read(),
2934	nline );
2935	#ifdef INSTRUMENTATION
2936	m_cpt_itlb_write++;
2937	#endif
2938	}
2939	else
2940	{
2941	r_dtlb.write( true, // 2M page
2942	pte,
2943	0, // argument unused for a PTE1
2944	r_dcache_tlb_vaddr.read(),
2945	r_dcache_tlb_way.read(),
2946	r_dcache_tlb_set.read(),
2947	nline );
2948	#ifdef INSTRUMENTATION
2949	m_cpt_dtlb_write++;
2950	#endif
2951	}
2952	// next state
2953	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
2954	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
2955
2956	#if DEBUG_DCACHE
2957	if ( m_debug_dcache_fsm )
2958	{
2959	if ( r_dcache_tlb_ins.read() )
2960	{
2961	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB:";
2962	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
2963	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
2964	r_itlb.print();
2965	}
2966	else
2967	{
2968	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB:";
2969	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
2970	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
2971	r_dtlb.print();
2972	}
2973
2974	}
2975	#endif
2976	break;
2977	}
2978	/////////////////////////
2979	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
2980	{
2981	uint32_t pte_flags;
2982	uint32_t pte_ppn;
2983	size_t way;
2984	size_t set;
2985	size_t word;
2986
2987	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2988	&pte_flags,
2989	&pte_ppn,
2990	&way,
2991	&set,
2992	&word );
2993	#ifdef INSTRUMENTATION
2994	m_cpt_dcache_data_read++;
2995	m_cpt_dcache_dir_read++;
2996	#endif
2997	if ( hit ) // request hits in dcache
2998	{
2999	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3000	{
3001	if ( r_dcache_tlb_ins.read() )
3002	{
3003	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3004	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3005	r_icache_tlb_miss_req = false;
3006	r_icache_tlb_rsp_error = true;
3007	}
3008	else
3009	{
3010	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3011	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3012	drsp.valid = true;
3013	drsp.error = true;
3014	}
3015	r_dcache_fsm = DCACHE_IDLE;
3016
3017	#if DEBUG_DCACHE
3018	if ( m_debug_dcache_fsm )
3019	{
3020	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3021	<< " PTE_FLAGS = " << std::hex << pte_flags
3022	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3023	}
3024	#endif
3025	}
3026	else // mapped : update the TLB
3027	{
3028	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
3029	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
3030	r_dcache_tlb_pte_flags = pte_flags;
3031	r_dcache_tlb_pte_ppn = pte_ppn;
3032	r_dcache_tlb_cache_way = way;
3033	r_dcache_tlb_cache_set = set;
3034	r_dcache_tlb_cache_word = word;
3035	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3036
3037	#if DEBUG_DCACHE
3038	if ( m_debug_dcache_fsm )
3039	{
3040	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3041	<< " PTE_FLAGS = " << std::hex << pte_flags
3042	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3043	}
3044	#endif
3045	}
3046	}
3047	else // we must load the missing cache line in dcache
3048	{
3049	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3050	r_dcache_miss_type = PTE2_MISS;
3051	r_dcache_fsm = DCACHE_MISS_VICTIM;
3052	r_dcache_vci_miss_req = true;
3053
3054	#if DEBUG_DCACHE
3055	if ( m_debug_dcache_fsm )
3056	{
3057	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3058	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3059	}
3060	#endif
3061	}
3062	break;
3063	}
3064	////////////////////////////
3065	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3066	{
3067	size_t way;
3068	size_t set;
3069
3070	if ( r_dcache_tlb_ins.read() )
3071	{
3072	r_itlb.select( r_dcache_tlb_vaddr.read(),
3073	false, // PTE2
3074	&way,
3075	&set );
3076	#ifdef INSTRUMENTATION
3077	m_cpt_itlb_read++;
3078	#endif
3079	}
3080	else
3081	{
3082	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3083	false, // PTE2
3084	&way,
3085	&set );
3086	#ifdef INSTRUMENTATION
3087	m_cpt_dtlb_read++;
3088	#endif
3089	}
3090	r_dcache_tlb_way = way;
3091	r_dcache_tlb_set = set;
3092	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3093	break;
3094	}
3095	//////////////////////////
3096	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3097	// if L/R bit already set exit the sub-fsm
3098	// if not, the page table must be updated by an atomic access
3099	{
3100	paddr_t nline = r_dcache_p0_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3101	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3102	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3103	bool updt = false; // page table update required
3104
3105	// test the access bit L/R, depending on the physical address locality
3106	// we must use the 10 MSB bits of the 28 bits PPN2 to obtain the target cluster index
3107	// we must use the 10 MSB bits of the SRCID to obtain the local cluster index
3108	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required.
3109
3110	uint32_t target = (pte_ppn >> 18) & 0x3FF;
3111	uint32_t local = m_srcid_d >> 4;
3112
3113	if ( local == target ) // local address
3114	{
3115	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3116	{
3117	updt = true;
3118	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3119	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
3120	}
3121	}
3122	else // remote address
3123	{
3124	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3125	{
3126	updt = true;
3127	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3128	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
3129	}
3130	}
3131
3132	// update TLB for a PTE2
3133	if ( r_dcache_tlb_ins.read() )
3134	{
3135	r_itlb.write( false, // 2K page
3136	pte_flags,
3137	pte_ppn,
3138	r_dcache_tlb_vaddr.read(),
3139	r_dcache_tlb_way.read(),
3140	r_dcache_tlb_set.read(),
3141	nline );
3142	#ifdef INSTRUMENTATION
3143	m_cpt_itlb_write++;
3144	#endif
3145	}
3146	else
3147	{
3148	r_dtlb.write( false, // 2K page
3149	pte_flags,
3150	pte_ppn,
3151	r_dcache_tlb_vaddr.read(),
3152	r_dcache_tlb_way.read(),
3153	r_dcache_tlb_set.read(),
3154	nline );
3155	#ifdef INSTRUMENTATION
3156	m_cpt_dtlb_write++;
3157	#endif
3158	}
3159
3160	#if DEBUG_DCACHE
3161	if ( m_debug_dcache_fsm )
3162	{
3163	if ( r_dcache_tlb_ins.read() )
3164	{
3165	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB:";
3166	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3167	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3168	r_itlb.print();
3169	}
3170	else
3171	{
3172	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB:";
3173	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3174	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3175	r_dtlb.print();
3176	}
3177	}
3178	#endif
3179	// next state
3180	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
3181	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3182	break;
3183	}
3184	////////////////////////
3185	case DCACHE_TLB_SC_UPDT: // update the dcache after a tlb miss (L/R bit),
3186	// request a SC transaction to CMD FSM
3187	{
3188	#if DEBUG_DCACHE
3189	if ( m_debug_dcache_fsm )
3190	{
3191	std::cout << " <PROC.DCACHE_TLB_SC_UPDT> Update dcache: (L/R) bit" << std::endl;
3192	}
3193	#endif
3194	r_dcache.write(r_dcache_tlb_cache_way.read(),
3195	r_dcache_tlb_cache_set.read(),
3196	r_dcache_tlb_cache_word.read(),
3197	r_dcache_tlb_pte_flags.read());
3198	#ifdef INSTRUMENTATION
3199	m_cpt_dcache_data_write++;
3200	#endif
3201	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3202	r_dcache_vci_sc_req = true;
3203	r_dcache_fsm = DCACHE_TLB_SC_WAIT;
3204	break;
3205	}
3206	////////////////////////
3207	case DCACHE_TLB_SC_WAIT: // Waiting a response to SC transaction.
3208	// We consume the response in rsp FIFO,
3209	// and exit the sub-fsm, but we don't
3210	// analyse the response, because we don't
3211	// care if the L/R bit update is not done.
3212	// We must take the coherence requests because
3213	// there is a risk of dead-lock
3214
3215	{
3216	// external coherence request
3217	if ( r_tgt_dcache_req )
3218	{
3219	r_dcache_fsm = DCACHE_CC_CHECK;
3220	r_dcache_fsm_save = r_dcache_fsm;
3221	break;
3222	}
3223
3224	if ( r_vci_rsp_data_error.read() ) // bus error
3225	{
3226	std::cout << "BUS ERROR in DCACHE_TLB_SC_WAIT state" << std::endl;
3227	std::cout << "This should not happen in this state" << std::endl;
3228	exit(0);
3229	}
3230	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3231	{
3232	#if DEBUG_DCACHE
3233	if ( m_debug_dcache_fsm )
3234	{
3235	std::cout << " <PROC.DCACHE_TLB_SC_WAIT> SC response received" << std::endl;
3236	}
3237	#endif
3238	vci_rsp_fifo_dcache_get = true;
3239	r_dcache_fsm = DCACHE_TLB_RETURN;
3240	}
3241	break;
3242	}
3243	///////////////////////
3244	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3245	{
3246	#if DEBUG_DCACHE
3247	if ( m_debug_dcache_fsm )
3248	{
3249	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3250	}
3251	#endif
3252	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3253	r_dcache_fsm = DCACHE_IDLE;
3254	break;
3255	}
3256	///////////////////////
3257	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3258	{
3259	if ( not r_dcache_xtn_req.read() )
3260	{
3261	r_dtlb.flush();
3262	r_dcache_fsm = DCACHE_IDLE;
3263	drsp.valid = true;
3264	}
3265	break;
3266	}
3267	/////////////////////
3268	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3269	// The coherence request must be taken
3270	// as there is a risk of dead-lock
3271	{
3272	// external coherence request
3273	if ( r_tgt_dcache_req.read() )
3274	{
3275	r_dcache_fsm = DCACHE_CC_CHECK;
3276	r_dcache_fsm_save = DCACHE_XTN_SYNC;
3277	}
3278
3279	if ( r_wbuf.empty() )
3280	{
3281	drsp.valid = true;
3282	r_dcache_fsm = DCACHE_IDLE;
3283	}
3284	break;
3285	}
3286	////////////////////////
3287	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3288	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3289	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3290	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3291	{
3292	// external coherence request
3293	if ( r_tgt_dcache_req )
3294	{
3295	r_dcache_fsm = DCACHE_CC_CHECK;
3296	r_dcache_fsm_save = r_dcache_fsm;
3297	break;
3298	}
3299
3300	// itlb miss request
3301	if ( r_icache_tlb_miss_req.read() )
3302	{
3303	r_dcache_tlb_ins = true;
3304	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3305	r_dcache_fsm = DCACHE_TLB_MISS;
3306	break;
3307	}
3308
3309	// test if XTN request to icache completed
3310	if ( not r_dcache_xtn_req.read() )
3311	{
3312	r_dcache_fsm = DCACHE_IDLE;
3313	drsp.valid = true;
3314	}
3315	break;
3316	}
3317	/////////////////////////
3318	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3319	// the r_dcache_flush counter as a slot counter.
3320	// We loop in this state until all slots have been visited.
3321	// A cleanup request is generated for each valid line
3322	// and we are blocked until the previous cleanup is completed
3323	// Finally, both the itlb and dtlb are reset, because
3324	// all TLB entries (including global entries) must be invalidated.
3325	{
3326	if ( not r_dcache_cleanup_req )
3327	{
3328	paddr_t nline;
3329	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3330	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3331
3332	bool cleanup_req = r_dcache.inval( way,
3333	set,
3334	&nline );
3335	if ( cleanup_req )
3336	{
3337	r_dcache_cleanup_req = true;
3338	r_dcache_cleanup_line = nline;
3339	}
3340
3341	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3342
3343	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot
3344	{
3345	r_dtlb.reset(); // global entries are invalidated
3346	r_itlb.reset(); // global entries are invalidated
3347	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
3348	{
3349	r_dcache_in_itlb[line] = false;
3350	r_dcache_in_dtlb[line] = false;
3351	}
3352	r_dcache_fsm = DCACHE_IDLE;
3353	drsp.valid = true;
3354	}
3355	}
3356	break;
3357	}
3358	/////////////////////////
3359	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3360	{
3361	r_dtlb.inval(r_dcache_p0_wdata.read());
3362	r_dcache_fsm = DCACHE_IDLE;
3363	drsp.valid = true;
3364	break;
3365	}
3366	////////////////////////////
3367	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3368	// requires 3 cycles: access tlb, read cache, inval cache
3369	// we compute the physical address in this state
3370	{
3371	paddr_t paddr;
3372	bool hit;
3373
3374	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3375	{
3376	#ifdef INSTRUMENTATION
3377	m_cpt_dtlb_read++;
3378	#endif
3379	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3380	&paddr );
3381	}
3382	else // dtlb not activated
3383	{
3384	paddr = (paddr_t)r_dcache_p0_wdata.read();
3385	hit = true;
3386	}
3387
3388	if ( hit ) // tlb hit
3389	{
3390	r_dcache_p0_paddr = paddr;
3391	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3392	}
3393	else // tlb miss
3394	{
3395	#ifdef INSTRUMENTATION
3396	m_cpt_dtlb_miss++;
3397	#endif
3398	r_dcache_tlb_ins = false; // dtlb
3399	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3400	r_dcache_fsm = DCACHE_TLB_MISS;
3401	}
3402	break;
3403	}
3404	////////////////////////////
3405	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3406	// requires 2 cycles: read cache / inval cache
3407	// In this state we read dcache.
3408	{
3409	uint32_t data;
3410	size_t way;
3411	size_t set;
3412	size_t word;
3413	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3414	&data,
3415	&way,
3416	&set,
3417	&word );
3418	#ifdef INSTRUMENTATION
3419	m_cpt_dcache_data_read++;
3420	m_cpt_dcache_dir_read++;
3421	#endif
3422	if ( hit ) // inval to be done
3423	{
3424	r_dcache_xtn_way = way;
3425	r_dcache_xtn_set = set;
3426	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3427	}
3428	else // miss : nothing to do
3429	{
3430	r_dcache_fsm = DCACHE_IDLE;
3431	drsp.valid = true;
3432	}
3433	break;
3434	}
3435	////////////////////////////
3436	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line & cleanup
3437	// Blocked if previous cleanup not completed
3438	// Test if itlb or dtlb inval is required
3439	{
3440	if ( not r_dcache_cleanup_req.read() )
3441	{
3442	paddr_t nline;
3443	size_t way = r_dcache_xtn_way.read();
3444	size_t set = r_dcache_xtn_set.read();
3445	bool inval_itlb = false;
3446	bool inval_dtlb = false;
3447
3448	r_icache.inval( way,
3449	set,
3450	&nline );
3451
3452	// request cleanup
3453	r_dcache_cleanup_req = true;
3454	r_dcache_cleanup_line = nline;
3455
3456	// possible itlb & dtlb invalidate requests
3457
3458	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
3459	{
3460	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3461	inval_dtlb = true;
3462	}
3463	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
3464	{
3465	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3466	inval_itlb = true;
3467	}
3468
3469	// no valid response until itlb & dtlb invalidated
3470	if ( inval_itlb or inval_dtlb )
3471	{
3472	r_dcache_itlb_inval_req = inval_itlb;
3473	r_dcache_dtlb_inval_req = inval_dtlb;
3474	r_dcache_tlb_inval_line = nline;
3475	r_dcache_tlb_inval_count = 0;
3476	r_dcache_fsm_save = DCACHE_XTN_DC_INVAL_END;
3477	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3478	}
3479	else
3480	{
3481	r_dcache_fsm = DCACHE_IDLE;
3482	drsp.valid = true;
3483	}
3484	}
3485	break;
3486	}
3487	//////////////////////////////
3488	case DCACHE_XTN_DC_INVAL_END: // waiting completion of itlb and dtlb invalidate
3489	{
3490	r_dcache_fsm = DCACHE_IDLE;
3491	drsp.valid = true;
3492	break;
3493	}
3494	////////////////////////
3495	case DCACHE_MISS_VICTIM: // Selects a victim line
3496	// Set the r_dcache_cleanup_req flip-flop
3497	// when the selected slot is not empty
3498	{
3499	bool valid;
3500	size_t way;
3501	size_t set;
3502	paddr_t victim;
3503
3504	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3505	&victim,
3506	&way,
3507	&set );
3508	r_dcache_miss_way = way;
3509	r_dcache_miss_set = set;
3510
3511	if ( valid )
3512	{
3513	r_dcache_cleanup_req = true;
3514	r_dcache_cleanup_line = victim;
3515	r_dcache_fsm = DCACHE_MISS_INVAL;
3516	}
3517	else
3518	{
3519	r_dcache_fsm = DCACHE_MISS_WAIT;
3520	}
3521
3522	#if DEBUG_DCACHE
3523	if ( m_debug_dcache_fsm )
3524	{
3525	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:"
3526	<< " / way = " << way
3527	<< " / set = " << set
3528	<< " / valid = " << valid
3529	<< " / line = " << std::hex << victim << std::endl;
3530	}
3531	#endif
3532	break;
3533	}
3534	///////////////////////
3535	case DCACHE_MISS_INVAL: // invalidate the victim line
3536	// and possibly request itlb or dtlb invalidate
3537	{
3538	paddr_t nline;
3539	size_t way = r_dcache_miss_way.read();
3540	size_t set = r_dcache_miss_set.read();
3541
3542	r_dcache.inval( way,
3543	set,
3544	&nline );
3545
3546	// if itlb & dtlb invalidate are required
3547	// the miss response is not handled before invalidate completed
3548	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3549	( r_dcache_in_itlb[way*m_dcache_sets+set] or
3550	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
3551	{
3552	r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3553	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
3554	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3555	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
3556	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3557	r_dcache_fsm = DCACHE_MISS_INVAL_WAIT;
3558	}
3559	else
3560	{
3561	r_dcache_fsm = DCACHE_MISS_WAIT;
3562	}
3563	break;
3564	}
3565	////////////////////////////
3566	case DCACHE_MISS_INVAL_WAIT: // waiting completion of itlb / dtlb invalidate
3567	{
3568	if ( (not r_dcache_itlb_inval_req.read()) or (not r_dcache_dtlb_inval_req.read()) )
3569	{
3570	r_dcache_fsm = DCACHE_MISS_WAIT;
3571	}
3572	break;
3573	}
3574	//////////////////////
3575	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3576	// This state is in charge of error signaling
3577	// There is 5 types of error depending on the requester
3578	{
3579	// external coherence request
3580	if ( r_tgt_dcache_req )
3581	{
3582	r_dcache_fsm = DCACHE_CC_CHECK;
3583	r_dcache_fsm_save = r_dcache_fsm;
3584	break;
3585	}
3586
3587	if ( r_vci_rsp_data_error.read() ) // bus error
3588	{
3589	switch ( r_dcache_miss_type.read() )
3590	{
3591	case PROC_MISS:
3592	{
3593	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3594	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3595	drsp.valid = true;
3596	drsp.error = true;
3597	r_dcache_fsm = DCACHE_IDLE;
3598	break;
3599	}
3600	case PTE1_MISS:
3601	{
3602	if ( r_dcache_tlb_ins.read() )
3603	{
3604	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3605	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3606	r_icache_tlb_miss_req = false;
3607	r_icache_tlb_rsp_error = true;
3608	}
3609	else
3610	{
3611	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3612	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3613	drsp.valid = true;
3614	drsp.error = true;
3615	}
3616	r_dcache_fsm = DCACHE_IDLE;
3617	break;
3618	}
3619	case PTE2_MISS:
3620	{
3621	if ( r_dcache_tlb_ins.read() )
3622	{
3623	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3624	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3625	r_icache_tlb_miss_req = false;
3626	r_icache_tlb_rsp_error = true;
3627	}
3628	else
3629	{
3630	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3631	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3632	drsp.valid = true;
3633	drsp.error = true;
3634	}
3635	r_dcache_fsm = DCACHE_IDLE;
3636	break;
3637	}
3638	} // end switch type
3639	r_vci_rsp_data_error = false;
3640	}
3641	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3642	{
3643	r_dcache_miss_word = 0;
3644	r_dcache_fsm = DCACHE_MISS_UPDT;
3645	}
3646	break;
3647	}
3648	//////////////////////
3649	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3650	// returns the response depending on the miss type
3651	{
3652	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3653	{
3654	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3655	// pop the FIFO, without cache update
3656	// send a cleanup for the missing line
3657	// if the previous cleanup is completed
3658	{
3659	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3660	{
3661	vci_rsp_fifo_dcache_get = true;
3662	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3663	}
3664	else // last word
3665	{
3666	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3667	{
3668	vci_rsp_fifo_dcache_get = true;
3669	r_dcache_cleanup_req = true;
3670	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3671	(uint32_log2(m_dcache_words)+2);
3672	r_dcache_miss_inval = false;
3673	r_dcache_fsm = DCACHE_IDLE;
3674	}
3675	}
3676	}
3677	else // No matching coherence request
3678	// pop the FIFO and update the cache
3679	// update the directory at the last word
3680	// send a response to ICACHE FSM
3681	// in case of itlb miss
3682	{
3683
3684	#ifdef INSTRUMENTATION
3685	m_cpt_dcache_data_write++;
3686	#endif
3687	r_dcache.write( r_dcache_miss_way.read(),
3688	r_dcache_miss_set.read(),
3689	r_dcache_miss_word.read(),
3690	r_vci_rsp_fifo_dcache.read());
3691
3692	vci_rsp_fifo_dcache_get = true;
3693	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3694
3695	// if last word, update directory, set in_itlb & in_dtlb bits
3696	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3697	{
3698
3699	#ifdef INSTRUMENTATION
3700	m_cpt_dcache_dir_write++;
3701	#endif
3702	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3703	r_dcache_miss_way.read(),
3704	r_dcache_miss_set.read() );
3705
3706	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3707	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3708	else r_dcache_fsm = DCACHE_IDLE;
3709	}
3710	}
3711
3712	#if DEBUG_DCACHE
3713	if ( m_debug_dcache_fsm )
3714	{
3715	if ( r_dcache_miss_inval.read() )
3716	{
3717	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3718	{
3719	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3720	<< " pop the FIFO, don't update the cache" << std::endl;
3721	}
3722	else
3723	{
3724	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3725	<< " last word : send a cleanup request " << std::endl;
3726	}
3727	}
3728	else
3729	{
3730	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3731	<< " address = " << r_dcache_vci_paddr.read()
3732	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3733	<< " / way = " << r_dcache_miss_way.read()
3734	<< " / set = " << r_dcache_miss_set.read()
3735	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3736	}
3737	}
3738	#endif
3739
3740	} // end if rok
3741	break;
3742	}
3743	/////////////////////
3744	case DCACHE_UNC_WAIT:
3745	{
3746	// external coherence request
3747	if ( r_tgt_dcache_req.read() )
3748	{
3749	r_dcache_fsm = DCACHE_CC_CHECK;
3750	r_dcache_fsm_save = r_dcache_fsm;
3751	break;
3752	}
3753
3754	if ( r_vci_rsp_data_error.read() ) // bus error
3755	{
3756	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3757	r_mmu_dbvar = dreq.addr;
3758	r_vci_rsp_data_error = false;
3759	drsp.error = true;
3760	drsp.valid = true;
3761	r_dcache_fsm = DCACHE_IDLE;
3762	break;
3763	}
3764	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3765	{
3766	vci_rsp_fifo_dcache_get = true;
3767	r_dcache_fsm = DCACHE_IDLE;
3768	// we acknowledge the processor request if it has not been modified
3769	if ( dreq.valid and (dreq.addr == r_dcache_p0_vaddr.read()) )
3770	{
3771	drsp.valid = true;
3772	drsp.rdata = r_vci_rsp_fifo_dcache.read();
3773	}
3774	}
3775	break;
3776	}
3777	////////////////////////////
3778	case DCACHE_WRITE_TLB_DIRTY: // set PTE dirty bit in dtlb
3779	// and get PTE in dcache
3780	{
3781	// set dirty bit in dtlb
3782	r_dtlb.set_dirty( r_dcache_p2_tlb_way.read(),
3783	r_dcache_p2_tlb_set.read() );
3784
3785	// get PTE in dcache
3786	uint32_t pte = 0;
3787	size_t way;
3788	size_t set;
3789	size_t word;
3790	bool hit = r_dcache.read( r_dcache_p2_pte_paddr.read(),
3791	&pte,
3792	&way,
3793	&set,
3794	&word );
3795	#ifdef INSTRUMENTATION
3796	m_cpt_dcache_data_read++;
3797	m_cpt_dcache_dir_read++;
3798	#endif;
3799
3800	#if DEBUG_DCACHE
3801	if ( m_debug_dcache_fsm )
3802	{
3803	std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set dirty bit in dtlb:" << std::dec
3804	<< " / tlb_way = " << r_dcache_p2_tlb_way.read()
3805	<< " / tlb_set = " << r_dcache_p2_tlb_set.read() << std::endl;
3806	r_dtlb.print();
3807	std::cout << " Get PTE in dcache:" << std::hex
3808	<< " paddr = " << r_dcache_p2_pte_paddr.read()
3809	<< " / PTE = " << pte << std::dec
3810	<< " / dcache_way = " << way
3811	<< " / dcache_set = " << set << std::endl;
3812	}
3813	#endif
3814	assert( hit and "error in DCACHE_WRITE_TLB_DIRTY: the PTE should be in dcache" );
3815
3816	r_dcache_p2_pte_way = way; // register pte way in dcache
3817	r_dcache_p2_pte_set = set; // register pte set in dcache;
3818	r_dcache_p2_pte_word = word; // register pte word in dcache;
3819	r_dcache_p2_pte = pte; // register pte value
3820	r_dcache_fsm = DCACHE_WRITE_CACHE_DIRTY;
3821	break;
3822	}
3823	//////////////////////////////
3824	case DCACHE_WRITE_CACHE_DIRTY: // set PTE dirty bit in dcache
3825	// request SC tranansaction to CMD FSM
3826	{
3827	// set PTE dirty bit in dcache
3828	r_dcache.write( r_dcache_p2_pte_way.read(),
3829	r_dcache_p2_pte_set.read(),
3830	r_dcache_p2_pte_word.read(),
3831	r_dcache_p2_pte.read() \| PTE_D_MASK,
3832	0xF );
3833
3834	#ifdef INSTRUMENTATION
3835	m_cpt_dcache_data_write++;
3836	#endif
3837
3838	#if DEBUG_DCACHE
3839	if ( m_debug_dcache_fsm )
3840	{
3841	std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache"
3842	<< " / way = " << r_dcache_p2_pte_way.read()
3843	<< " / set = " << r_dcache_p2_pte_set.read()
3844	<< " / word = " << r_dcache_p2_pte_word.read() << std::endl;
3845	std::cout << " Request SC transaction"
3846	<< " / address = " << "bloup"
3847	<< " / old = " << r_dcache_p2_pte.read()
3848	<< " / new = " << (r_dcache_p2_pte.read() \| PTE_D_MASK) << std::endl;
3849	}
3850	#endif
3851	// request sc transaction to CMD_FSM
3852	r_dcache_vci_sc_req = true;
3853	r_dcache_vci_sc_old = r_dcache_p2_pte.read();
3854	r_dcache_vci_sc_new = r_dcache_p2_pte.read() \| PTE_D_MASK;
3855	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3856	break;
3857	}
3858	//////////////////////////
3859	case DCACHE_WRITE_SC_WAIT: // wait completion of SC
3860	// if atomic, write completed : return to IDLE state
3861	// else, makes an uncacheable read to retry the SC
3862	{
3863	// external coherence request
3864	if ( r_tgt_dcache_req )
3865	{
3866	r_dcache_fsm = DCACHE_CC_CHECK;
3867	r_dcache_fsm_save = r_dcache_fsm;
3868	break;
3869	}
3870
3871	if ( r_vci_rsp_data_error.read() ) // bus error
3872	{
3873	r_mmu_detr = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3874	r_mmu_dbvar = r_dcache_p2_vaddr;
3875	drsp.valid = true;
3876	drsp.error = true;
3877	r_dcache_fsm = DCACHE_IDLE;
3878	break;
3879	}
3880	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3881	{
3882	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // atomic
3883	{
3884	drsp.valid = true; // acknowledge the initial write
3885	r_dcache_fsm = DCACHE_IDLE;
3886	}
3887	else
3888	{
3889	r_dcache_vci_paddr = r_dcache_p2_pte_paddr;
3890	r_dcache_vci_unc_req = true;
3891	r_dcache_vci_unc_be = 0xF;
3892	r_dcache_fsm = DCACHE_WRITE_UNC_WAIT;
3893	}
3894	}
3895	break;
3896	}
3897	///////////////////////////
3898	case DCACHE_WRITE_UNC_WAIT: // wait completion of uncacheable read
3899	// in case of success we retry a SC request to
3900	// set the dirty bit in the PTE
3901	{
3902	// external coherence request
3903	if ( r_tgt_dcache_req )
3904	{
3905	r_dcache_fsm = DCACHE_CC_CHECK;
3906	r_dcache_fsm_save = r_dcache_fsm;
3907	break;
3908	}
3909
3910	if ( r_vci_rsp_data_error.read() ) // bus error
3911	{
3912	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3913	r_mmu_dbvar = r_dcache_p2_vaddr;
3914	drsp.valid = true;
3915	drsp.error = true;
3916	r_dcache_fsm = DCACHE_IDLE;
3917	break;
3918	}
3919	if ( r_vci_rsp_fifo_dcache.rok() ) // PTE available
3920	{
3921	r_dcache_vci_sc_req = true;
3922	r_dcache_vci_sc_old = r_vci_rsp_fifo_dcache.read();
3923	r_dcache_vci_sc_new = r_vci_rsp_fifo_dcache.read() \| PTE_D_MASK;
3924	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3925	}
3926	break;
3927	}
3928	/////////////////////
3929	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
3930	// handling coherence requests.
3931	// If there is a matching pending miss on the modified cache
3932	// line this is signaled in the r_dcache_miss inval flip-flop.
3933	// If the updated (or invalidated) cache line has copies in TLBs
3934	// these TLB copies are invalidated.
3935	// The return state is defined in r_dcache_fsm_save
3936	{
3937	paddr_t paddr = r_tgt_paddr.read();
3938	paddr_t mask = ~((m_dcache_words<<2)-1);
3939
3940
3941	if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and
3942	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
3943	{
3944	r_dcache_miss_inval = true; // signaling the match
3945	r_tgt_dcache_req = false; // coherence request completed
3946	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
3947	r_dcache_fsm = r_dcache_fsm_save;
3948
3949	#if DEBUG_DCACHE
3950	if ( m_debug_dcache_fsm )
3951	{
3952	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
3953	<< " address = " << std::hex << paddr << std::endl;
3954	}
3955	#endif
3956
3957	}
3958	else // no match
3959	{
3960	uint32_t rdata;
3961	size_t way;
3962	size_t set;
3963	size_t word;
3964
3965	bool hit = r_dcache.read(paddr,
3966	&rdata, // unused
3967	&way,
3968	&set,
3969	&word); // unused
3970	#ifdef INSTRUMENTATION
3971	m_cpt_dcache_data_read++;
3972	m_cpt_dcache_dir_read++;
3973	#endif
3974	r_dcache_cc_way = way;
3975	r_dcache_cc_set = set;
3976
3977	if ( hit and r_tgt_update.read() ) // hit update
3978	{
3979	r_dcache_fsm = DCACHE_CC_UPDT;
3980	r_dcache_cc_word = r_tgt_word_min.read();
3981	}
3982	else if ( hit and not r_tgt_update.read() ) // hit inval
3983	{
3984	r_dcache_fsm = DCACHE_CC_INVAL;
3985	}
3986	else // miss can happen
3987	{
3988	r_tgt_dcache_req = false;
3989	r_tgt_dcache_rsp = r_tgt_update.read();
3990	r_dcache_fsm = r_dcache_fsm_save.read();
3991	}
3992
3993	#if DEBUG_DCACHE
3994	if ( m_debug_dcache_fsm )
3995	{
3996
3997	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
3998	<< " address = " << std::hex << paddr << std::dec;
3999	if ( hit )
4000	{
4001	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4002	}
4003	else
4004	{
4005	std::cout << " / MISS" << std::endl;
4006	}
4007	}
4008	#endif
4009
4010	}
4011	break;
4012	}
4013	/////////////////////
4014	case DCACHE_CC_INVAL: // invalidate one cache line
4015	// and test possible copies in TLBs
4016	{
4017	paddr_t nline;
4018	size_t way = r_dcache_cc_way.read();
4019	size_t set = r_dcache_cc_set.read();
4020	bool inval_itlb = false;
4021	bool inval_dtlb = false;
4022
4023	r_dcache.inval( way,
4024	set,
4025	&nline );
4026
4027	// possible itlb & dtlb invalidate requests
4028
4029	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
4030	{
4031	r_dtlb.reset_bypass(nline);
4032	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4033	inval_dtlb = true;
4034	}
4035	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
4036	{
4037	r_itlb.reset_bypass(nline);
4038	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4039	inval_itlb = true;
4040	}
4041
4042	if ( inval_itlb or inval_dtlb ) // no valid response until itlb / dtlb invalidated
4043	{
4044	r_dcache_itlb_inval_req = inval_itlb;
4045	r_dcache_dtlb_inval_req = inval_dtlb;
4046	r_dcache_tlb_inval_line = nline;
4047	r_dcache_tlb_inval_count = 0;
4048	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4049	}
4050	else
4051	{
4052	r_tgt_dcache_rsp = true;
4053	r_tgt_dcache_req = false;
4054	r_dcache_fsm = r_dcache_fsm_save.read();
4055	}
4056
4057	#if DEBUG_DCACHE
4058	if ( m_debug_dcache_fsm )
4059	{
4060	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line :" << std::dec
4061	<< " way = " << way
4062	<< " / set = " << set;
4063	if ( inval_itlb ) std::cout << " / itlb inval required";
4064	if ( inval_dtlb ) std::cout << " / dtlb inval required";
4065	std::cout << std::endl;
4066	}
4067	#endif
4068
4069	break;
4070	}
4071	///////////////////
4072	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4073	// and test possible copies in TLBs
4074	{
4075	size_t word = r_dcache_cc_word.read();
4076	size_t way = r_dcache_cc_way.read();
4077	size_t set = r_dcache_cc_set.read();
4078	bool inval_itlb = false;
4079	bool inval_dtlb = false;
4080	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4081
4082	r_dcache.write( way,
4083	set,
4084	word,
4085	r_tgt_buf[word],
4086	r_tgt_be[word] );
4087	#ifdef INSTRUMENTATION
4088	m_cpt_dcache_data_write++;
4089	#endif
4090	r_dcache_cc_word = word + 1;
4091
4092	if ( word == r_tgt_word_max.read() ) // last word
4093	{
4094	// possible itlb & dtlb invalidate requests
4095
4096	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
4097	{
4098	r_dtlb.reset_bypass(nline);
4099	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4100	inval_dtlb = true;
4101	}
4102	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[way*m_dcache_sets+set] )
4103	{
4104	r_itlb.reset_bypass(nline);
4105	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4106	inval_itlb = true;
4107	}
4108
4109	if ( inval_itlb or inval_dtlb ) // no valid response until itlb / dtlb invalidated
4110	{
4111	r_dcache_itlb_inval_req = inval_itlb;
4112	r_dcache_dtlb_inval_req = inval_dtlb;
4113	r_dcache_tlb_inval_line = nline;
4114	r_dcache_tlb_inval_count = 0;
4115	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4116	}
4117	else
4118	{
4119	r_tgt_dcache_rsp = true;
4120	r_tgt_dcache_req = false;
4121	r_dcache_fsm = r_dcache_fsm_save.read();
4122	}
4123	}
4124
4125	#if DEBUG_DCACHE
4126	if ( m_debug_dcache_fsm )
4127	{
4128	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec
4129	<< " way = " << way
4130	<< " / set = " << set
4131	<< " / word = " << word
4132	<< " / value = " << std::hex << r_tgt_buf[word];
4133	if ( inval_itlb ) std::cout << " / itlb inval required";
4134	if ( inval_dtlb ) std::cout << " / dtlb inval required";
4135	std::cout << std::endl;
4136	}
4137	#endif
4138
4139	break;
4140	}
4141	///////////////////////////
4142	case DCACHE_INVAL_TLB_SCAN: // scan sequencially all TLB entries for both ITLB & DTLB
4143	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4144	// and (m_itlb_ways == m_dtlb_ways)
4145	// Caution : we enter this state when a DCACHE line is modified,
4146	// and there is a copy in itlb or dtlb.
4147	// It can be caused by a coherence transaction, a XTN inval
4148	// or a WRITE hit. Input arguments are:
4149	// - r_dcache_tlb_inval_line
4150	// - r_dcache_tlb_inval_count
4151	// - r_dcache_itlb_inval_req
4152	// - r_dcache_dtlb_inval_req
4153	// - r_dcache_fsm_save
4154	{
4155	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4156	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4157	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4158
4159	if ( r_dcache_itlb_inval_req.read() )
4160	{
4161	bool ok = r_itlb.inval( line,
4162	way,
4163	set );
4164	#if DEBUG_DCACHE
4165	if ( m_debug_dcache_fsm and ok )
4166	{
4167	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4168	<< " line = " << line << std::dec
4169	<< " / set = " << set
4170	<< " / way = " << way << std::endl;
4171	r_itlb.print();
4172	}
4173	#endif
4174	}
4175
4176	if ( r_dcache_dtlb_inval_req.read() )
4177	{
4178	bool ok = r_dtlb.inval( line,
4179	way,
4180	set );
4181	#if DEBUG_DCACHE
4182	if ( m_debug_dcache_fsm and ok )
4183	{
4184	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4185	<< " line = " << line << std::dec
4186	<< " / set = " << set
4187	<< " / way = " << way << std::endl;
4188	r_dtlb.print();
4189	}
4190	#endif
4191	}
4192
4193	// return to the calling state when TLB inval completed
4194	if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) )
4195	{
4196	if ( r_dcache_fsm_save.read() != DCACHE_XTN_DC_INVAL_END ) // not an XTN inval
4197	{
4198	r_tgt_dcache_rsp = true;
4199	r_tgt_dcache_req = false;
4200	}
4201	r_dcache_dtlb_inval_req = false;
4202	r_dcache_itlb_inval_req = false;
4203	r_dcache_fsm = r_dcache_fsm_save.read();
4204	}
4205	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4206	}
4207	} // end switch r_dcache_fsm
4208
4209
4210	//////////////////// save DREQ and DRSP fields for print_trace() ////////////////
4211	m_dreq_valid = dreq.valid;
4212	m_dreq_addr = dreq.addr;
4213	m_dreq_mode = dreq.mode;
4214	m_dreq_type = dreq.type;
4215	m_dreq_wdata = dreq.wdata;
4216	m_dreq_be = dreq.be;
4217
4218	m_drsp_valid = drsp.valid;
4219	m_drsp_rdata = drsp.rdata;
4220	m_drsp_error = drsp.error;
4221
4222	///////////////// wbuf update //////////////////////////////////////////////////////
4223	r_wbuf.update();
4224
4225	/////////// test processor frozen /////////////////////////////////////////////
4226	// The simulation exit if the number of consecutive frozen cycles
4227	// is larger than the m_max_frozen_cycles (constructor parameter)
4228	if ( (ireq.valid and not irsp.valid) or (dreq.valid and not drsp.valid) )
4229	{
4230	m_cpt_frz_cycles++; // used for instrumentation
4231	m_cpt_stop_simulation++; // used for debug
4232	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4233	{
4234	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4235	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4236	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4237	<< std::endl;
4238	exit(1);
4239	}
4240	}
4241	else
4242	{
4243	m_cpt_stop_simulation = 0;
4244	}
4245
4246	/////////// execute one iss cycle /////////////////////////////////
4247	{
4248	uint32_t it = 0;
4249	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4250	r_iss.executeNCycles(1, irsp, drsp, it);
4251	}
4252
4253	////////////////////////////////////////////////////////////////////////////
4254	// The VCI_CMD FSM controls the following ressources:
4255	// - r_vci_cmd_fsm
4256	// - r_vci_cmd_min
4257	// - r_vci_cmd_max
4258	// - r_vci_cmd_cpt
4259	// - r_vci_cmd_imiss_prio
4260	// - wbuf (reset)
4261	// - r_icache_miss_req (reset)
4262	// - r_icache_unc_req (reset)
4263	// - r_dcache_vci_miss_req (reset)
4264	// - r_dcache_vci_unc_req (reset)
4265	// - r_dcache_vci_sc_req (reset)
4266	//
4267	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4268	// There is 6 request types, with the following priorities :
4269	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4270	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4271	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4272	// 4 - Instruction Uncachable : r_icache_unc_req
4273	// 5 - Data Write : r_wbuf.rok()
4274	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4275	//
4276	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4277	// and the VCI_RSP_FSM are fully desynchronized.
4278	//
4279	// VCI formats:
4280	// According to the VCI advanced specification, all read requests packets
4281	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4282	// are one word packets.
4283	// For write burst packets, all words are in the same cache line,
4284	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4285	// The sc command packet implements actually a compare-and-swap mechanism
4286	// and the packet contains two flits.
4287	////////////////////////////////////////////////////////////////////////////////////
4288
4289	switch ( r_vci_cmd_fsm.read() )
4290	{
4291	//////////////
4292	case CMD_IDLE:
4293	{
4294	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4295	// to check a possible pending write on the same cache line.
4296	// As there is only one possible access per cycle to write buffer, we implement
4297	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4298
4299	size_t wbuf_min;
4300	size_t wbuf_max;
4301
4302	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4303	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4304	bool icache_miss_req = r_icache_miss_req.read()
4305	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4306
4307	// 1 - Data Read Miss
4308	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4309	{
4310	r_vci_cmd_fsm = CMD_DATA_MISS;
4311	r_dcache_vci_miss_req = false;
4312	r_vci_cmd_imiss_prio = true;
4313	// m_cpt_dmiss_transaction++;
4314	}
4315	// 2 - Data Read Uncachable
4316	else if ( r_dcache_vci_unc_req.read() )
4317	{
4318	r_vci_cmd_fsm = CMD_DATA_UNC;
4319	r_dcache_vci_unc_req = false;
4320	// m_cpt_dunc_transaction++;
4321	}
4322	// 3 - Instruction Miss
4323	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4324	{
4325	r_vci_cmd_fsm = CMD_INS_MISS;
4326	r_icache_miss_req = false;
4327	r_vci_cmd_imiss_prio = false;
4328	// m_cpt_imiss_transaction++;
4329	}
4330	// 4 - Instruction Uncachable
4331	else if ( r_icache_unc_req.read() )
4332	{
4333	r_vci_cmd_fsm = CMD_INS_UNC;
4334	r_icache_unc_req = false;
4335	// m_cpt_iunc_transaction++;
4336	}
4337	// 5 - Data Write
4338	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4339	{
4340	r_vci_cmd_fsm = CMD_DATA_WRITE;
4341	r_vci_cmd_cpt = wbuf_min;
4342	r_vci_cmd_min = wbuf_min;
4343	r_vci_cmd_max = wbuf_max;
4344	// m_cpt_write_transaction++;
4345	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4346	}
4347	// 6 - Data Store Conditionnal
4348	else if ( r_dcache_vci_sc_req.read() )
4349	{
4350	r_vci_cmd_fsm = CMD_DATA_SC;
4351	r_dcache_vci_sc_req = false;
4352	r_vci_cmd_cpt = 0;
4353	// m_cpt_sc_transaction++;
4354	}
4355	break;
4356	}
4357	////////////////////
4358	case CMD_DATA_WRITE:
4359	{
4360	if ( p_vci_ini_d.cmdack.read() )
4361	{
4362	// m_conso_wbuf_read++;
4363	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4364	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4365	{
4366	r_vci_cmd_fsm = CMD_IDLE ;
4367	r_wbuf.sent() ;
4368	}
4369	}
4370	break;
4371	}
4372	/////////////////
4373	case CMD_DATA_SC:
4374	{
4375	// The SC VCI command contains two flits
4376	if ( p_vci_ini_d.cmdack.read() )
4377	{
4378	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4379	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4380	}
4381	break;
4382	}
4383	//////////////////
4384	case CMD_INS_MISS:
4385	case CMD_INS_UNC:
4386	case CMD_DATA_MISS:
4387	case CMD_DATA_UNC:
4388	{
4389	// all read VCI commands contain one single flit
4390	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4391	break;
4392	}
4393
4394	} // end switch r_vci_cmd_fsm
4395
4396	//////////////////////////////////////////////////////////////////////////
4397	// The VCI_RSP FSM controls the following ressources:
4398	// - r_vci_rsp_fsm:
4399	// - r_vci_rsp_fifo_icache (push)
4400	// - r_vci_rsp_fifo_dcache (push)
4401	// - r_vci_rsp_data_error (set)
4402	// - r_vci_rsp_ins_error (set)
4403	// - r_vci_rsp_cpt
4404	//
4405	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4406	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4407	// to identify the transactions.
4408	//
4409	// VCI vormat:
4410	// This component checks the response packet length and accepts only
4411	// single word packets for write response packets.
4412	//
4413	// Error handling:
4414	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4415	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4416	// flip_flop and the error is signaled by the DCACHE FSM.
4417	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4418	// flip_flop and the error is signaled by the ICACHE FSM.
4419	// In case of Cleanup Error, the simulation stops with an error message...
4420	//////////////////////////////////////////////////////////////////////////
4421
4422	switch ( r_vci_rsp_fsm.read() )
4423	{
4424	//////////////
4425	case RSP_IDLE:
4426	{
4427	if ( p_vci_ini_d.rspval.read() )
4428	{
4429	r_vci_rsp_cpt = 0;
4430
4431	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4432	{
4433	r_vci_rsp_fsm = RSP_DATA_WRITE;
4434	}
4435	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4436	{
4437	r_vci_rsp_fsm = RSP_INS_MISS;
4438	}
4439	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4440	{
4441	r_vci_rsp_fsm = RSP_INS_UNC;
4442	}
4443	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4444	{
4445	r_vci_rsp_fsm = RSP_DATA_MISS;
4446	}
4447	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4448	{
4449	r_vci_rsp_fsm = RSP_DATA_UNC;
4450	}
4451	else
4452	{
4453	assert(false and "Unexpected VCI response");
4454	}
4455	}
4456	break;
4457	}
4458	//////////////////
4459	case RSP_INS_MISS:
4460	{
4461	if ( p_vci_ini_d.rspval.read() )
4462	{
4463	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4464	{
4465	r_vci_rsp_ins_error = true;
4466	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4467	}
4468	else // no error reported
4469	{
4470	if ( r_vci_rsp_fifo_icache.wok() )
4471	{
4472	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4473	"The VCI response packet for instruction miss is too long" );
4474
4475	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4476	vci_rsp_fifo_icache_put = true,
4477	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4478	if ( p_vci_ini_d.reop.read() )
4479	{
4480	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4481	"The VCI response packet for instruction miss is too short");
4482
4483	r_vci_rsp_fsm = RSP_IDLE;
4484	}
4485	}
4486	}
4487	}
4488	break;
4489	}
4490	/////////////////
4491	case RSP_INS_UNC:
4492	{
4493	if (p_vci_ini_d.rspval.read() )
4494	{
4495	assert( p_vci_ini_d.reop.read() and
4496	"illegal VCI response packet for uncachable instruction");
4497
4498	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4499	{
4500	r_vci_rsp_ins_error = true;
4501	r_vci_rsp_fsm = RSP_IDLE;
4502	}
4503	else // no error reported
4504	{
4505	if ( r_vci_rsp_fifo_icache.wok())
4506	{
4507	vci_rsp_fifo_icache_put = true;
4508	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4509	r_vci_rsp_fsm = RSP_IDLE;
4510	}
4511	}
4512	}
4513	break;
4514	}
4515	///////////////////
4516	case RSP_DATA_MISS:
4517	{
4518	if ( p_vci_ini_d.rspval.read() )
4519	{
4520	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4521	{
4522	r_vci_rsp_data_error = true;
4523	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4524	}
4525	else // no error reported
4526	{
4527	if ( r_vci_rsp_fifo_dcache.wok() )
4528	{
4529	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4530	"The VCI response packet for data miss is too long");
4531
4532	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4533	vci_rsp_fifo_dcache_put = true,
4534	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4535	if ( p_vci_ini_d.reop.read() )
4536	{
4537	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4538	"The VCI response packet for data miss is too short");
4539
4540	r_vci_rsp_fsm = RSP_IDLE;
4541	}
4542	}
4543	}
4544	}
4545	break;
4546	}
4547	//////////////////
4548	case RSP_DATA_UNC:
4549	{
4550	if (p_vci_ini_d.rspval.read() )
4551	{
4552	assert( p_vci_ini_d.reop.read() and
4553	"illegal VCI response packet for uncachable read data");
4554
4555	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4556	{
4557	r_vci_rsp_data_error = true;
4558	r_vci_rsp_fsm = RSP_IDLE;
4559	}
4560	else // no error reported
4561	{
4562	if ( r_vci_rsp_fifo_dcache.wok())
4563	{
4564	vci_rsp_fifo_dcache_put = true;
4565	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4566	r_vci_rsp_fsm = RSP_IDLE;
4567	}
4568	}
4569	}
4570	break;
4571	}
4572	////////////////////
4573	case RSP_DATA_WRITE:
4574	{
4575	if (p_vci_ini_d.rspval.read())
4576	{
4577	assert( p_vci_ini_d.reop.read() and
4578	"a VCI response packet must contain one flit for a write transaction");
4579
4580	r_vci_rsp_fsm = RSP_IDLE;
4581	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4582	bool cacheable = r_wbuf.completed(wbuf_index);
4583	if ( not cacheable ) r_dcache_pending_unc_write = false;
4584	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4585	}
4586	break;
4587	}
4588	} // end switch r_vci_rsp_fsm
4589
4590	////////////////////////////////////////////////////////////////////////////////
4591	// The CLEANUP FSM send the cleanup commands on the coherence network,
4592	// and supports simultaneous cleanup transactions, but two simultaneous
4593	// transactions mut address different cache lines.
4594	// Therefore, the line number is registered in an associative
4595	// registration buffer (Content Adressable Memory) by the CLEANUP FSM,
4596	// and the corresponding slot (identified by the VCI TRDID field) is cleared
4597	// when the cleanup transaction response is received.
4598	// It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
4599	// with a round robin priority, and can support up to 4 simultaneous
4600	// cleanup transactions (4 slots in the registration buffer).
4601	// The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
4602	// when the command has been sent.
4603	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4604	// - if data cleanup : TRDID = 2*index + 0
4605	// - if instruction cleanup : TRDID = 2*index + 1
4606	////////////////////////////////////////////////////////////////////////////
4607
4608	switch ( r_cleanup_fsm.read() )
4609	{
4610	///////////////////////
4611	case CLEANUP_DATA_IDLE: // dcache has highest priority
4612	{
4613	size_t index = 0;
4614	bool ok;
4615	if ( r_dcache_cleanup_req.read() ) // dcache request
4616	{
4617	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4618	&index );
4619	if ( ok ) // successful registration
4620	{
4621	r_cleanup_fsm = CLEANUP_DATA_GO;
4622	r_cleanup_trdid = index<<1;
4623	}
4624	}
4625	else if ( r_icache_cleanup_req.read() ) // icache request
4626	{
4627	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4628	&index );
4629	if ( ok ) // successful registration
4630	{
4631	r_cleanup_fsm = CLEANUP_INS_GO;
4632	r_cleanup_trdid = (index<<1) + 1;
4633	}
4634	}
4635	break;
4636	}
4637	//////////////////////
4638	case CLEANUP_INS_IDLE: // icache has highest priority
4639	{
4640	size_t index = 0;
4641	bool ok;
4642	if ( r_icache_cleanup_req.read() ) // icache request
4643	{
4644	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4645	&index );
4646	if ( ok ) // successful registration
4647	{
4648	r_cleanup_fsm = CLEANUP_INS_GO;
4649	r_cleanup_trdid = (index<<1) + 1;
4650	}
4651	}
4652	else if ( r_dcache_cleanup_req.read() ) // dcache request
4653	{
4654	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4655	&index );
4656	if ( ok ) // successful registration
4657	{
4658	r_cleanup_fsm = CLEANUP_DATA_GO;
4659	r_cleanup_trdid = index<<1;
4660	}
4661	}
4662	break;
4663	}
4664	/////////////////////
4665	case CLEANUP_DATA_GO:
4666	{
4667	if ( p_vci_ini_c.cmdack.read() )
4668	{
4669	r_dcache_cleanup_req = false;
4670	r_cleanup_fsm = CLEANUP_INS_IDLE;
4671
4672	#if DEBUG_CLEANUP
4673	if ( m_debug_cleanup_fsm )
4674	{
4675	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4676	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4677	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4678	}
4679	#endif
4680	}
4681	}
4682	////////////////////////
4683	case CLEANUP_INS_GO:
4684	{
4685	if ( p_vci_ini_c.cmdack.read() )
4686	{
4687	r_icache_cleanup_req = false;
4688	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4689
4690	#if DEBUG_CLEANUP
4691	if ( m_debug_cleanup_fsm )
4692	{
4693	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4694	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4695	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4696	}
4697	#endif
4698	}
4699	}
4700	} // end switch CLEANUP FSM
4701
4702	//////////////// Handling cleanup responses //////////////////
4703	if ( p_vci_ini_c.rspval.read() ) // valid response
4704	{
4705	r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
4706	}
4707
4708	///////////////// Response FIFOs update //////////////////////
4709	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4710	vci_rsp_fifo_icache_put,
4711	vci_rsp_fifo_icache_data);
4712
4713	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4714	vci_rsp_fifo_dcache_put,
4715	vci_rsp_fifo_dcache_data);
4716	} // end transition()
4717
4718	///////////////////////
4719	tmpl(void)::genMoore()
4720	///////////////////////
4721	{
4722	////////////////////////////////////////////////////////////////
4723	// VCI initiator command on the coherence network (cleanup)
4724	// it depends on the CLEANUP FSM state
4725
4726	paddr_t address;
4727
4728	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4729	address = r_dcache_cleanup_line.read()m_dcache_words4;
4730	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4731	address = r_icache_cleanup_line.read()m_icache_words4;
4732	else
4733	address = 0;
4734
4735	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4736	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4737	p_vci_ini_c.address = address;
4738	p_vci_ini_c.wdata = 0;
4739	p_vci_ini_c.be = 0xF;
4740	p_vci_ini_c.plen = 4;
4741	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4742	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4743	p_vci_ini_c.pktid = 0;
4744	p_vci_ini_c.srcid = m_srcid_c;
4745	p_vci_ini_c.cons = false;
4746	p_vci_ini_c.wrap = false;
4747	p_vci_ini_c.contig = false;
4748	p_vci_ini_c.clen = 0;
4749	p_vci_ini_c.cfixed = false;
4750	p_vci_ini_c.eop = true;
4751
4752	/////////////////////////////////////////////////////////////////
4753	// VCI initiator response on the coherence network (cleanup)
4754	// We always consume the response, and we don't use it.
4755
4756	p_vci_ini_c.rspack = true;
4757
4758	/////////////////////////////////////////////////////////////////
4759	// VCI initiator command on the direct network
4760	// it depends on the CMD FSM state
4761
4762	p_vci_ini_d.pktid = 0;
4763	p_vci_ini_d.srcid = m_srcid_d;
4764	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4765	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4766	p_vci_ini_d.wrap = false;
4767	p_vci_ini_d.clen = 0;
4768	p_vci_ini_d.cfixed = false;
4769
4770	switch ( r_vci_cmd_fsm.read() ) {
4771
4772	case CMD_IDLE:
4773	p_vci_ini_d.cmdval = false;
4774	p_vci_ini_d.address = 0;
4775	p_vci_ini_d.wdata = 0;
4776	p_vci_ini_d.be = 0;
4777	p_vci_ini_d.trdid = 0;
4778	p_vci_ini_d.plen = 0;
4779	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4780	p_vci_ini_d.eop = false;
4781	break;
4782
4783	case CMD_INS_MISS:
4784	p_vci_ini_d.cmdval = true;
4785	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4786	p_vci_ini_d.wdata = 0;
4787	p_vci_ini_d.be = 0xF;
4788	p_vci_ini_d.trdid = TYPE_INS_MISS;
4789	p_vci_ini_d.plen = m_icache_words<<2;
4790	p_vci_ini_d.cmd = vci_param::CMD_READ;
4791	p_vci_ini_d.eop = true;
4792	break;
4793
4794	case CMD_INS_UNC:
4795	p_vci_ini_d.cmdval = true;
4796	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4797	p_vci_ini_d.wdata = 0;
4798	p_vci_ini_d.be = 0xF;
4799	p_vci_ini_d.trdid = TYPE_INS_UNC;
4800	p_vci_ini_d.plen = 4;
4801	p_vci_ini_d.cmd = vci_param::CMD_READ;
4802	p_vci_ini_d.eop = true;
4803	break;
4804
4805	case CMD_DATA_MISS:
4806	p_vci_ini_d.cmdval = true;
4807	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4808	p_vci_ini_d.wdata = 0;
4809	p_vci_ini_d.be = 0xF;
4810	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4811	p_vci_ini_d.plen = m_dcache_words << 2;
4812	p_vci_ini_d.cmd = vci_param::CMD_READ;
4813	p_vci_ini_d.eop = true;
4814	break;
4815
4816	case CMD_DATA_UNC:
4817	p_vci_ini_d.cmdval = true;
4818	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4819	p_vci_ini_d.wdata = 0;
4820	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4821	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4822	p_vci_ini_d.plen = 4;
4823	p_vci_ini_d.cmd = vci_param::CMD_READ;
4824	p_vci_ini_d.eop = true;
4825	break;
4826
4827	case CMD_DATA_WRITE:
4828	p_vci_ini_d.cmdval = true;
4829	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4830	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4831	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4832	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4833	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4834	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4835	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4836	break;
4837
4838	case CMD_DATA_SC:
4839	p_vci_ini_d.cmdval = true;
4840	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4841	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4842	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4843	p_vci_ini_d.be = 0xF;
4844	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4845	p_vci_ini_d.plen = 8;
4846	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4847	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4848	break;
4849	} // end switch r_vci_cmd_fsm
4850
4851	//////////////////////////////////////////////////////////
4852	// VCI initiator response on the direct network
4853	// it depends on the VCI RSP state
4854
4855	switch (r_vci_rsp_fsm.read() )
4856	{
4857	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4858	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4859	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4860	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4861	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4862	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4863	} // end switch r_vci_rsp_fsm
4864
4865	////////////////////////////////////////////////////////////////
4866	// VCI target command and response on the coherence network
4867	switch ( r_tgt_fsm.read() )
4868	{
4869	case TGT_IDLE:
4870	case TGT_UPDT_WORD:
4871	case TGT_UPDT_DATA:
4872	p_vci_tgt_c.cmdack = true;
4873	p_vci_tgt_c.rspval = false;
4874	break;
4875
4876	case TGT_RSP_BROADCAST:
4877	p_vci_tgt_c.cmdack = false;
4878	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4879	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4880	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4881	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4882	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4883	p_vci_tgt_c.rdata = 0;
4884	p_vci_tgt_c.rerror = 0;
4885	p_vci_tgt_c.reop = true;
4886	break;
4887
4888	case TGT_RSP_ICACHE:
4889	p_vci_tgt_c.cmdack = false;
4890	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4891	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4892	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4893	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4894	p_vci_tgt_c.rdata = 0;
4895	p_vci_tgt_c.rerror = 0;
4896	p_vci_tgt_c.reop = true;
4897	break;
4898
4899	case TGT_RSP_DCACHE:
4900	p_vci_tgt_c.cmdack = false;
4901	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4902	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4903	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4904	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4905	p_vci_tgt_c.rdata = 0;
4906	p_vci_tgt_c.rerror = 0;
4907	p_vci_tgt_c.reop = true;
4908	break;
4909
4910	case TGT_REQ_BROADCAST:
4911	case TGT_REQ_ICACHE:
4912	case TGT_REQ_DCACHE:
4913	p_vci_tgt_c.cmdack = false;
4914	p_vci_tgt_c.rspval = false;
4915	break;
4916
4917	} // end switch TGT_FSM
4918	} // end genMoore
4919
4920	}}
4921
4922	// Local Variables:
4923	// tab-width: 4
4924	// c-basic-offset: 4
4925	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4926	// indent-tabs-mode: nil
4927	// End:
4928
4929	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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