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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 205

Last change on this file since 205 was 205, checked in by alain, 12 years ago
bug fixing
File size: 190.4 KB

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1	/* -- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_TLB_SET",
91	"DCACHE_DIRTY_CACHE_SET",
92	"DCACHE_DIRTY_SC_WAIT",
93	"DCACHE_DIRTY_UNC_WAIT",
94
95	"DCACHE_MISS_VICTIM",
96	"DCACHE_MISS_INVAL",
97	"DCACHE_MISS_INVAL_WAIT",
98	"DCACHE_MISS_WAIT",
99	"DCACHE_MISS_UPDT",
100
101	"DCACHE_UNC_WAIT",
102	"DCACHE_SC_WAIT",
103
104	"DCACHE_CC_CHECK",
105	"DCACHE_CC_INVAL",
106	"DCACHE_CC_UPDT",
107
108	"DCACHE_INVAL_TLB_SCAN",
109	};
110	const char *cmd_fsm_state_str[] = {
111	"CMD_IDLE",
112	"CMD_INS_MISS",
113	"CMD_INS_UNC",
114	"CMD_DATA_MISS",
115	"CMD_DATA_UNC",
116	"CMD_DATA_WRITE",
117	"CMD_DATA_SC",
118	};
119	const char *rsp_fsm_state_str[] = {
120	"RSP_IDLE",
121	"RSP_INS_MISS",
122	"RSP_INS_UNC",
123	"RSP_DATA_MISS",
124	"RSP_DATA_UNC",
125	"RSP_DATA_WRITE",
126	};
127	const char *cleanup_fsm_state_str[] = {
128	"CLEANUP_DATA_IDLE",
129	"CLEANUP_DATA_GO",
130	"CLEANUP_INS_IDLE",
131	"CLEANUP_INS_GO",
132	};
133	const char *tgt_fsm_state_str[] = {
134	"TGT_IDLE",
135	"TGT_UPDT_WORD",
136	"TGT_UPDT_DATA",
137	"TGT_REQ_BROADCAST",
138	"TGT_REQ_ICACHE",
139	"TGT_REQ_DCACHE",
140	"TGT_RSP_BROADCAST",
141	"TGT_RSP_ICACHE",
142	"TGT_RSP_DCACHE",
143	};
144	}
145
146	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
147
148	using soclib::common::uint32_log2;
149
150	/////////////////////////////////
151	tmpl(/**/)::VciCcVCacheWrapperV4(
152	sc_module_name name,
153	int proc_id,
154	const soclib::common::MappingTable &mtp,
155	const soclib::common::MappingTable &mtc,
156	const soclib::common::IntTab &initiator_index_d,
157	const soclib::common::IntTab &initiator_index_c,
158	const soclib::common::IntTab &target_index_d,
159	size_t itlb_ways,
160	size_t itlb_sets,
161	size_t dtlb_ways,
162	size_t dtlb_sets,
163	size_t icache_ways,
164	size_t icache_sets,
165	size_t icache_words,
166	size_t dcache_ways,
167	size_t dcache_sets,
168	size_t dcache_words,
169	size_t wbuf_nlines,
170	size_t wbuf_nwords,
171	uint32_t max_frozen_cycles,
172	uint32_t debug_start_cycle,
173	bool debug_ok)
174	: soclib::caba::BaseModule(name),
175
176	p_clk("clk"),
177	p_resetn("resetn"),
178	p_vci_ini_d("vci_ini_d"),
179	p_vci_ini_c("vci_ini_c"),
180	p_vci_tgt_c("vci_tgt_d"),
181
182	m_cacheability_table(mtp.getCacheabilityTable()),
183	m_segment(mtc.getSegment(target_index_d)),
184	m_srcid_d(mtp.indexForId(initiator_index_d)),
185	m_srcid_c(mtp.indexForId(initiator_index_c)),
186
187	m_itlb_ways(itlb_ways),
188	m_itlb_sets(itlb_sets),
189
190	m_dtlb_ways(dtlb_ways),
191	m_dtlb_sets(dtlb_sets),
192
193	m_icache_ways(icache_ways),
194	m_icache_sets(icache_sets),
195	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
196	m_icache_words(icache_words),
197
198	m_dcache_ways(dcache_ways),
199	m_dcache_sets(dcache_sets),
200	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
201	m_dcache_words(dcache_words),
202
203	m_proc_id(proc_id),
204
205	m_max_frozen_cycles(max_frozen_cycles),
206
207	m_paddr_nbits(vci_param::N),
208
209	m_debug_start_cycle(debug_start_cycle),
210	m_debug_ok(debug_ok),
211
212	r_mmu_ptpr("r_mmu_ptpr"),
213	r_mmu_mode("r_mmu_mode"),
214	r_mmu_word_lo("r_mmu_word_lo"),
215	r_mmu_word_hi("r_mmu_word_hi"),
216	r_mmu_ibvar("r_mmu_ibvar"),
217	r_mmu_dbvar("r_mmu_dbvar"),
218	r_mmu_ietr("r_mmu_ietr"),
219	r_mmu_detr("r_mmu_detr"),
220
221	r_icache_fsm("r_icache_fsm"),
222	r_icache_fsm_save("r_icache_fsm_save"),
223	r_icache_vci_paddr("r_icache_vci_paddr"),
224	r_icache_vaddr_save("r_icache_vaddr_save"),
225
226	r_icache_miss_way("r_icache_miss_way"),
227	r_icache_miss_set("r_icache_miss_set"),
228	r_icache_miss_word("r_icache_miss_word"),
229	r_icache_miss_inval("r_icache_miss_inval"),
230
231	r_icache_cc_way("r_icache_cc_way"),
232	r_icache_cc_set("r_icache_cc_set"),
233	r_icache_cc_word("r_icache_cc_word"),
234
235	r_icache_flush_count("r_icache_flush_count"),
236
237	r_icache_miss_req("r_icache_miss_req"),
238	r_icache_unc_req("r_icache_unc_req"),
239
240	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
241	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
242
243	r_icache_cleanup_req("r_icache_cleanup_req"),
244	r_icache_cleanup_line("r_icache_cleanup_line"),
245
246	r_dcache_fsm("r_dcache_fsm"),
247	r_dcache_fsm_save("r_dcache_fsm_save"),
248
249	r_dcache_p0_valid("r_dcache_p0_valid"),
250	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
251	r_dcache_p0_wdata("r_dcache_p0_wdata"),
252	r_dcache_p0_be("r_dcache_p0_be"),
253	r_dcache_p0_paddr("r_dcache_p0_paddr"),
254	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
255	r_dcache_p0_tlb_way("r_dcache_p0_tlb_way"),
256	r_dcache_p0_tlb_set("r_dcache_p0_tlb_set"),
257	r_dcache_p0_tlb_nline("r_dcache_p0_tlb_nline"),
258	r_dcache_p0_tlb_dirty("r_dcache_p0_tlb_dirty"),
259	r_dcache_p0_tlb_big("r_dcache_p0_tlb_big"),
260
261	r_dcache_p1_valid("r_dcache_p1_valid"),
262	r_dcache_p1_updt_cache("r_dcache_p1_updt_cache"),
263	r_dcache_p1_set_dirty("r_dcache_p1_set_dirty"),
264	r_dcache_p1_vaddr("r_dcache_p1_vaddr"),
265	r_dcache_p1_wdata("r_dcache_p1_wdata"),
266	r_dcache_p1_be("r_dcache_p1_be"),
267	r_dcache_p1_paddr("r_dcache_p1_paddr"),
268	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
269	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
270	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
271	r_dcache_p1_tlb_way("r_dcache_p1_tlb_way"),
272	r_dcache_p1_tlb_set("r_dcache_p1_tlb_set"),
273	r_dcache_p1_tlb_nline("r_dcache_p1_tlb_nline"),
274	r_dcache_p1_tlb_big("r_dcache_p1_tlb_big"),
275
276	r_dcache_p2_way("r_dcache_p2_way"),
277	r_dcache_p2_set("r_dcache_p2_set"),
278	r_dcache_p2_word("r_dcache_p2_word"),
279	r_dcache_p2_pte_paddr("r_dcache_p2_pte_paddr"),
280	r_dcache_p2_pte_value("r_dcache_p2_pte_value"),
281	r_dcache_p2_type_sc("r_dcache_p2_type_sc"),
282	r_dcache_p2_sc_success("r_dcache_p2_sc_success"),
283
284	r_dcache_vci_paddr("r_dcache_vci_paddr"),
285	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
286	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
287	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
290	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
291
292	r_dcache_xtn_way("r_dcache_xtn_way"),
293	r_dcache_xtn_set("r_dcache_xtn_set"),
294
295	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
296
297	r_dcache_miss_type("r_dcache_miss_type"),
298	r_dcache_miss_word("r_dcache_miss_word"),
299	r_dcache_miss_way("r_dcache_miss_way"),
300	r_dcache_miss_set("r_dcache_miss_set"),
301	r_dcache_miss_inval("r_dcache_miss_inval"),
302
303	r_dcache_cc_way("r_dcache_cc_way"),
304	r_dcache_cc_set("r_dcache_cc_set"),
305	r_dcache_cc_word("r_dcache_cc_word"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
310	r_dcache_tlb_ins("r_dcache_tlb_ins"),
311	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
312	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
313	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
314	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
315	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
316	r_dcache_tlb_way("r_dcache_tlb_way"),
317	r_dcache_tlb_set("r_dcache_tlb_set"),
318
319	r_dcache_ll_valid("r_dcache_ll_valid"),
320	r_dcache_ll_data("r_dcache_ll_data"),
321	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
322
323	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
324	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
325	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
326	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
327
328	r_dcache_xtn_req("r_dcache_xtn_req"),
329	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
330
331	r_dcache_cleanup_req("r_dcache_cleanup_req"),
332	r_dcache_cleanup_line("r_dcache_cleanup_line"),
333
334	r_vci_cmd_fsm("r_vci_cmd_fsm"),
335	r_vci_cmd_min("r_vci_cmd_min"),
336	r_vci_cmd_max("r_vci_cmd_max"),
337	r_vci_cmd_cpt("r_vci_cmd_cpt"),
338	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
339
340	r_vci_rsp_fsm("r_vci_rsp_fsm"),
341	r_vci_rsp_cpt("r_vci_rsp_cpt"),
342	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
343	r_vci_rsp_data_error("r_vci_rsp_data_error"),
344	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
345	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
346
347	r_cleanup_fsm("r_cleanup_fsm"),
348	r_cleanup_trdid("r_cleanup_trdid"),
349	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
350
351	r_tgt_fsm("r_tgt_fsm"),
352	r_tgt_paddr("r_tgt_paddr"),
353	r_tgt_word_count("r_tgt_word_count"),
354	r_tgt_word_min("r_tgt_word_min"),
355	r_tgt_word_max("r_tgt_word_max"),
356	r_tgt_update("r_tgt_update"),
357	r_tgt_update_data("r_tgt_update_data"),
358	r_tgt_srcid("r_tgt_srcid"),
359	r_tgt_pktid("r_tgt_pktid"),
360	r_tgt_trdid("r_tgt_trdid"),
361
362	r_tgt_icache_req("r_tgt_icache_req"),
363	r_tgt_dcache_req("r_tgt_dcache_req"),
364	r_tgt_icache_rsp("r_tgt_icache_rsp"),
365	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
366
367	r_iss(this->name(), proc_id),
368	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
369	r_icache("icache", icache_ways, icache_sets, icache_words),
370	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
371	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
372	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
373	{
374	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
375	"Need more PLEN bits.");
376
377	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
378	"Need more TRDID bits.");
379
380	assert( (icache_words == dcache_words) and
381	"icache_words and dcache_words parameters must be equal");
382
383	assert( (itlb_sets == dtlb_sets) and
384	"itlb_sets and dtlb_sets parameters must be etqual");
385
386	assert( (itlb_ways == dtlb_ways) and
387	"itlb_ways and dtlb_ways parameters must be etqual");
388
389	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
390	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
391	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
392	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
393	(uint32_log2(m_icache_words<<2));
394
395	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
396
397	r_tgt_buf = new uint32_t[dcache_words];
398	r_tgt_be = new vci_be_t[dcache_words];
399	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
400	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
401
402	SC_METHOD(transition);
403	dont_initialize();
404	sensitive << p_clk.pos();
405
406	SC_METHOD(genMoore);
407	dont_initialize();
408	sensitive << p_clk.neg();
409
410	typename iss_t::CacheInfo cache_info;
411	cache_info.has_mmu = true;
412	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
413	cache_info.icache_assoc = icache_ways;
414	cache_info.icache_n_lines = icache_sets;
415	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
416	cache_info.dcache_assoc = dcache_ways;
417	cache_info.dcache_n_lines = dcache_sets;
418	r_iss.setCacheInfo(cache_info);
419	}
420
421	/////////////////////////////////////
422	tmpl(/**/)::~VciCcVCacheWrapperV4()
423	/////////////////////////////////////
424	{
425	delete [] r_tgt_be;
426	delete [] r_tgt_buf;
427	delete [] r_dcache_in_itlb;
428	delete [] r_dcache_in_dtlb;
429	}
430
431	////////////////////////
432	tmpl(void)::print_cpi()
433	////////////////////////
434	{
435	std::cout << name() << " CPI = "
436	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
437	}
438
439	////////////////////////////////////
440	tmpl(void)::print_trace(size_t mode)
441	////////////////////////////////////
442	{
443	// b0 : write buffer trace
444	// b1 : write buffer verbose
445	// b2 : dcache trace
446	// b3 : icache trace
447	// b4 : dtlb trace
448	// b5 : itlb trace
449
450	std::cout << std::dec << "PROC " << name() << std::endl;
451
452	std::cout << " " << m_ireq << std::endl;
453	std::cout << " " << m_irsp << std::endl;
454	std::cout << " " << m_dreq << std::endl;
455	std::cout << " " << m_drsp << std::endl;
456
457	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
458	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
459	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
460	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
461	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
462	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
463	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
464	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
465	std::cout << std::endl;
466
467	if(mode & 0x01)
468	{
469	r_wbuf.printTrace((mode>>1)&1);
470	}
471	if(mode & 0x04)
472	{
473	std::cout << " Data Cache" << std::endl;
474	r_dcache.printTrace();
475	}
476	if(mode & 0x08)
477	{
478	std::cout << " Instruction Cache" << std::endl;
479	r_icache.printTrace();
480	}
481	if(mode & 0x10)
482	{
483	std::cout << " Data TLB" << std::endl;
484	r_dtlb.printTrace();
485	}
486	if(mode & 0x20)
487	{
488	std::cout << " Instruction TLB" << std::endl;
489	r_itlb.printTrace();
490	}
491	}
492
493	//////////////////////////////////////////
494	tmpl(void)::cache_monitor( paddr_t addr )
495	//////////////////////////////////////////
496	{
497	size_t cache_way;
498	size_t cache_set;
499	size_t cache_word;
500	uint32_t cache_rdata;
501	bool cache_hit = r_dcache.read( addr,
502	&cache_rdata,
503	&cache_way,
504	&cache_set,
505	&cache_word );
506	if ( cache_hit != m_debug_previous_hit )
507	{
508	std::cout << "PROC " << name()
509	<< " cache change at cycle " << std::dec << m_cpt_total_cycles
510	<< " for adresse " << std::hex << addr
511	<< " / HIT = " << cache_hit << std::endl;
512	}
513	m_debug_previous_hit = cache_hit;
514	}
515
516
517
518	/*
519	////////////////////////
520	tmpl(void)::print_stats()
521	////////////////////////
522	{
523	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
524	std::cout << name() << std::endl
525	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
526	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
527	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
528	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
529	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
530	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
531	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
532	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
533	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
534	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
535	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
536	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
537	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
538	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
539	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
540	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
541	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
542	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
543	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
544	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
545	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
546	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
547	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
548	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
549	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
550	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
551	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
552	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
553	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
554	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
555	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
556	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
557	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
558	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
559	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
560	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
561	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
562	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
563	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
564	}
565
566	////////////////////////
567	tmpl(void)::clear_stats()
568	////////////////////////
569	{
570	m_cpt_dcache_data_read = 0;
571	m_cpt_dcache_data_write = 0;
572	m_cpt_dcache_dir_read = 0;
573	m_cpt_dcache_dir_write = 0;
574	m_cpt_icache_data_read = 0;
575	m_cpt_icache_data_write = 0;
576	m_cpt_icache_dir_read = 0;
577	m_cpt_icache_dir_write = 0;
578
579	m_cpt_frz_cycles = 0;
580	m_cpt_dcache_frz_cycles = 0;
581	m_cpt_total_cycles = 0;
582
583	m_cpt_read = 0;
584	m_cpt_write = 0;
585	m_cpt_data_miss = 0;
586	m_cpt_ins_miss = 0;
587	m_cpt_unc_read = 0;
588	m_cpt_write_cached = 0;
589	m_cpt_ins_read = 0;
590
591	m_cost_write_frz = 0;
592	m_cost_data_miss_frz = 0;
593	m_cost_unc_read_frz = 0;
594	m_cost_ins_miss_frz = 0;
595
596	m_cpt_imiss_transaction = 0;
597	m_cpt_dmiss_transaction = 0;
598	m_cpt_unc_transaction = 0;
599	m_cpt_write_transaction = 0;
600	m_cpt_icache_unc_transaction = 0;
601
602	m_cost_imiss_transaction = 0;
603	m_cost_dmiss_transaction = 0;
604	m_cost_unc_transaction = 0;
605	m_cost_write_transaction = 0;
606	m_cost_icache_unc_transaction = 0;
607	m_length_write_transaction = 0;
608
609	m_cpt_ins_tlb_read = 0;
610	m_cpt_ins_tlb_miss = 0;
611	m_cpt_ins_tlb_update_acc = 0;
612
613	m_cpt_data_tlb_read = 0;
614	m_cpt_data_tlb_miss = 0;
615	m_cpt_data_tlb_update_acc = 0;
616	m_cpt_data_tlb_update_dirty = 0;
617	m_cpt_ins_tlb_hit_dcache = 0;
618	m_cpt_data_tlb_hit_dcache = 0;
619	m_cpt_ins_tlb_occup_cache = 0;
620	m_cpt_data_tlb_occup_cache = 0;
621
622	m_cost_ins_tlb_miss_frz = 0;
623	m_cost_data_tlb_miss_frz = 0;
624	m_cost_ins_tlb_update_acc_frz = 0;
625	m_cost_data_tlb_update_acc_frz = 0;
626	m_cost_data_tlb_update_dirty_frz = 0;
627	m_cost_ins_tlb_occup_cache_frz = 0;
628	m_cost_data_tlb_occup_cache_frz = 0;
629
630	m_cpt_itlbmiss_transaction = 0;
631	m_cpt_itlb_ll_transaction = 0;
632	m_cpt_itlb_sc_transaction = 0;
633	m_cpt_dtlbmiss_transaction = 0;
634	m_cpt_dtlb_ll_transaction = 0;
635	m_cpt_dtlb_sc_transaction = 0;
636	m_cpt_dtlb_ll_dirty_transaction = 0;
637	m_cpt_dtlb_sc_dirty_transaction = 0;
638
639	m_cost_itlbmiss_transaction = 0;
640	m_cost_itlb_ll_transaction = 0;
641	m_cost_itlb_sc_transaction = 0;
642	m_cost_dtlbmiss_transaction = 0;
643	m_cost_dtlb_ll_transaction = 0;
644	m_cost_dtlb_sc_transaction = 0;
645	m_cost_dtlb_ll_dirty_transaction = 0;
646	m_cost_dtlb_sc_dirty_transaction = 0;
647
648	m_cpt_cc_update_data = 0;
649	m_cpt_cc_inval_ins = 0;
650	m_cpt_cc_inval_data = 0;
651	m_cpt_cc_broadcast = 0;
652
653	m_cost_updt_data_frz = 0;
654	m_cost_inval_ins_frz = 0;
655	m_cost_inval_data_frz = 0;
656	m_cost_broadcast_frz = 0;
657
658	m_cpt_cc_cleanup_data = 0;
659	m_cpt_cc_cleanup_ins = 0;
660	}
661
662	*/
663
664	/////////////////////////
665	tmpl(void)::transition()
666	/////////////////////////
667	{
668	if ( not p_resetn.read() )
669	{
670	r_iss.reset();
671	r_wbuf.reset();
672	r_icache.reset();
673	r_dcache.reset();
674	r_itlb.reset();
675	r_dtlb.reset();
676
677	r_dcache_fsm = DCACHE_IDLE;
678	r_icache_fsm = ICACHE_IDLE;
679	r_vci_cmd_fsm = CMD_IDLE;
680	r_vci_rsp_fsm = RSP_IDLE;
681	r_tgt_fsm = TGT_IDLE;
682	r_cleanup_fsm = CLEANUP_DATA_IDLE;
683
684	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
685	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
686
687
688	// Response FIFOs and cleanup buffer
689	r_vci_rsp_fifo_icache.init();
690	r_vci_rsp_fifo_dcache.init();
691	r_cleanup_buffer.reset();
692
693	// ICACHE & DCACHE activated
694	r_mmu_mode = 0x3;
695
696	// No request from ICACHE FSM to CMD FSM
697	r_icache_miss_req = false;
698	r_icache_unc_req = false;
699
700	// No request from ICACHE_FSM to DCACHE FSM
701	r_icache_tlb_miss_req = false;
702
703	// No request from ICACHE_FSM to CLEANUP FSMs
704	r_icache_cleanup_req = false;
705
706	// No pending write in pipeline
707	r_dcache_p0_valid = false;
708	r_dcache_p1_valid = false;
709
710	// No request from DCACHE_FSM to CMD_FSM
711	r_dcache_vci_miss_req = false;
712	r_dcache_vci_unc_req = false;
713	r_dcache_vci_sc_req = false;
714
715	// No uncacheable write pending
716	r_dcache_pending_unc_write = false;
717
718	// No LL reservation
719	r_dcache_ll_valid = false;
720
721	// No TLB inval requestis
722	r_dcache_itlb_inval_req = false;
723	r_dcache_dtlb_inval_req = false;
724
725	// No processor XTN request pending
726	r_dcache_xtn_req = false;
727
728	// No request from DCACHE FSM to CLEANUP FSMs
729	r_dcache_cleanup_req = false;
730
731	// No request from TGT FSM to ICACHE/DCACHE FSMs
732	r_tgt_icache_req = false;
733	r_tgt_dcache_req = false;
734
735	// No signalisation of a coherence request matching a pending miss
736	r_icache_miss_inval = false;
737	r_dcache_miss_inval = false;
738
739	// No signalisation of errors
740	r_vci_rsp_ins_error = false;
741	r_vci_rsp_data_error = false;
742
743	// Debug variables
744	m_debug_previous_hit = false;
745	m_debug_dcache_fsm = false;
746	m_debug_icache_fsm = false;
747	m_debug_cleanup_fsm = false;
748
749	/*
750	// activity counters
751	m_cpt_dcache_data_read = 0;
752	m_cpt_dcache_data_write = 0;
753	m_cpt_dcache_dir_read = 0;
754	m_cpt_dcache_dir_write = 0;
755	m_cpt_icache_data_read = 0;
756	m_cpt_icache_data_write = 0;
757	m_cpt_icache_dir_read = 0;
758	m_cpt_icache_dir_write = 0;
759
760	m_cpt_frz_cycles = 0;
761	m_cpt_dcache_frz_cycles = 0;
762	m_cpt_total_cycles = 0;
763
764	m_cpt_read = 0;
765	m_cpt_write = 0;
766	m_cpt_data_miss = 0;
767	m_cpt_ins_miss = 0;
768	m_cpt_unc_read = 0;
769	m_cpt_write_cached = 0;
770	m_cpt_ins_read = 0;
771
772	m_cost_write_frz = 0;
773	m_cost_data_miss_frz = 0;
774	m_cost_unc_read_frz = 0;
775	m_cost_ins_miss_frz = 0;
776
777	m_cpt_imiss_transaction = 0;
778	m_cpt_dmiss_transaction = 0;
779	m_cpt_unc_transaction = 0;
780	m_cpt_write_transaction = 0;
781	m_cpt_icache_unc_transaction = 0;
782
783	m_cost_imiss_transaction = 0;
784	m_cost_dmiss_transaction = 0;
785	m_cost_unc_transaction = 0;
786	m_cost_write_transaction = 0;
787	m_cost_icache_unc_transaction = 0;
788	m_length_write_transaction = 0;
789
790	m_cpt_ins_tlb_read = 0;
791	m_cpt_ins_tlb_miss = 0;
792	m_cpt_ins_tlb_update_acc = 0;
793
794	m_cpt_data_tlb_read = 0;
795	m_cpt_data_tlb_miss = 0;
796	m_cpt_data_tlb_update_acc = 0;
797	m_cpt_data_tlb_update_dirty = 0;
798	m_cpt_ins_tlb_hit_dcache = 0;
799	m_cpt_data_tlb_hit_dcache = 0;
800	m_cpt_ins_tlb_occup_cache = 0;
801	m_cpt_data_tlb_occup_cache = 0;
802
803	m_cost_ins_tlb_miss_frz = 0;
804	m_cost_data_tlb_miss_frz = 0;
805	m_cost_ins_tlb_update_acc_frz = 0;
806	m_cost_data_tlb_update_acc_frz = 0;
807	m_cost_data_tlb_update_dirty_frz = 0;
808	m_cost_ins_tlb_occup_cache_frz = 0;
809	m_cost_data_tlb_occup_cache_frz = 0;
810
811	m_cpt_ins_tlb_inval = 0;
812	m_cpt_data_tlb_inval = 0;
813	m_cost_ins_tlb_inval_frz = 0;
814	m_cost_data_tlb_inval_frz = 0;
815
816	m_cpt_cc_update_data = 0;
817	m_cpt_cc_inval_ins = 0;
818	m_cpt_cc_inval_data = 0;
819	m_cpt_cc_broadcast = 0;
820
821	m_cost_updt_data_frz = 0;
822	m_cost_inval_ins_frz = 0;
823	m_cost_inval_data_frz = 0;
824	m_cost_broadcast_frz = 0;
825
826	m_cpt_cc_cleanup_data = 0;
827	m_cpt_cc_cleanup_ins = 0;
828
829	m_cpt_itlbmiss_transaction = 0;
830	m_cpt_itlb_ll_transaction = 0;
831	m_cpt_itlb_sc_transaction = 0;
832	m_cpt_dtlbmiss_transaction = 0;
833	m_cpt_dtlb_ll_transaction = 0;
834	m_cpt_dtlb_sc_transaction = 0;
835	m_cpt_dtlb_ll_dirty_transaction = 0;
836	m_cpt_dtlb_sc_dirty_transaction = 0;
837
838	m_cost_itlbmiss_transaction = 0;
839	m_cost_itlb_ll_transaction = 0;
840	m_cost_itlb_sc_transaction = 0;
841	m_cost_dtlbmiss_transaction = 0;
842	m_cost_dtlb_ll_transaction = 0;
843	m_cost_dtlb_sc_transaction = 0;
844	m_cost_dtlb_ll_dirty_transaction = 0;
845	m_cost_dtlb_sc_dirty_transaction = 0;
846
847	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
848	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
849	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
850	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
851	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
852	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
853	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
854
855	*/
856	return;
857	}
858
859	// Response FIFOs default values
860	bool vci_rsp_fifo_icache_get = false;
861	bool vci_rsp_fifo_icache_put = false;
862	uint32_t vci_rsp_fifo_icache_data = 0;
863
864	bool vci_rsp_fifo_dcache_get = false;
865	bool vci_rsp_fifo_dcache_put = false;
866	uint32_t vci_rsp_fifo_dcache_data = 0;
867
868	#ifdef INSTRUMENTATION
869	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
870	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
871	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
872	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
873	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
874	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
875	#endif
876
877	m_cpt_total_cycles++;
878
879	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
880	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
881	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
882
883	/////////////////////////////////////////////////////////////////////
884	// The TGT_FSM controls the following ressources:
885	// - r_tgt_fsm
886	// - r_tgt_buf[nwords]
887	// - r_tgt_be[nwords]
888	// - r_tgt_update
889	// - r_tgt_word_min
890	// - r_tgt_word_max
891	// - r_tgt_word_count
892	// - r_tgt_paddr
893	// - r_tgt_srcid
894	// - r_tgt_trdid
895	// - r_tgt_pktid
896	// - r_tgt_icache_req (set)
897	// - r_tgt_dcache_req (set)
898	//
899	// All VCI commands must be CMD_WRITE.
900	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
901	// It is a multicast request otherwise.
902	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
903	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
904	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
905	//
906	// For all types of coherence request, the line index (i.e. the Z & Y fields)
907	// is coded on 34 bits, and is contained in the WDATA and BE fields
908	// of the first VCI flit.
909	// - for a multicast invalidate or for a broadcast invalidate request
910	// the VCI packet length is 1 word.
911	// - for an update request the VCI packet length is (n+2) words.
912	// The WDATA field of the second VCI word contains the word index.
913	// The WDATA field of the n following words contains the values.
914	// - for all transaction types, the VCI response is one single word.
915	// In case of errors in the VCI command packet, the simulation
916	// is stopped with an error message.
917	//
918	// This FSM is NOT pipelined : It consumes a new coherence request
919	// on the VCI port only when the previous request is completed.
920	//
921	// The VCI_TGT FSM stores the external request arguments in the
922	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
923	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
924	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
925	// states. It waits the completion of the coherence request by polling the
926	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
927	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
928	// These two FSMs signal if a VCI answer must be send by setting
929	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
930	///////////////////////////////////////////////////////////////////////////////
931
932	switch( r_tgt_fsm.read() )
933	{
934	//////////////
935	case TGT_IDLE:
936	{
937	if ( p_vci_tgt_c.cmdval.read() )
938	{
939	paddr_t address = p_vci_tgt_c.address.read();
940
941	// command checking
942	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
943	{
944	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
945	std::cout << "the received VCI coherence command is not a write" << std::endl;
946	exit(0);
947	}
948
949	// address checking
950	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
951	{
952	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
953	std::cout << "out of segment VCI coherence command received" << std::endl;
954	exit(0);
955	}
956
957	r_tgt_srcid = p_vci_tgt_c.srcid.read();
958	r_tgt_trdid = p_vci_tgt_c.trdid.read();
959	r_tgt_pktid = p_vci_tgt_c.pktid.read();
960
961	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
962	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
963
964	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
965	{
966	if ( not p_vci_tgt_c.eop.read() )
967	{
968	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
969	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
970	exit(0);
971	}
972	r_tgt_update = false;
973	r_tgt_fsm = TGT_REQ_BROADCAST;
974
975	#ifdef INSTRUMENTATION
976	m_cpt_cc_broadcast++;
977	#endif
978	}
979	else // multi-update or multi-invalidate for data type
980	{
981	paddr_t cell = address - m_segment.baseAddress();
982
983	if (cell == 0) // invalidate data
984	{
985	if ( not p_vci_tgt_c.eop.read() )
986	{
987	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
988	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
989	exit(0);
990	}
991	r_tgt_update = false;
992	r_tgt_fsm = TGT_REQ_DCACHE;
993
994	#ifdef INSTRUMENTATION
995	m_cpt_cc_inval_dcache++;
996	#endif
997	}
998	else if (cell == 4) // invalidate instruction
999	{
1000	if ( not p_vci_tgt_c.eop.read() )
1001	{
1002	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1003	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1004	exit(0);
1005	}
1006	r_tgt_update = false;
1007	r_tgt_fsm = TGT_REQ_ICACHE;
1008
1009	#ifdef INSTRUMENTATION
1010	m_cpt_cc_inval_icache++;
1011	#endif
1012	}
1013	else if (cell == 8) // update data
1014	{
1015	if ( p_vci_tgt_c.eop.read() )
1016	{
1017	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1018	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1019	exit(0);
1020	}
1021	r_tgt_update = true;
1022	r_tgt_update_data = true;
1023	r_tgt_fsm = TGT_UPDT_WORD;
1024
1025	#ifdef INSTRUMENTATION
1026	m_cpt_cc_update_dcache++;
1027	#endif
1028	}
1029	else // update instruction
1030	{
1031	if ( p_vci_tgt_c.eop.read() )
1032	{
1033	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1034	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1035	exit(0);
1036	}
1037	r_tgt_update = true;
1038	r_tgt_update_data = false;
1039	r_tgt_fsm = TGT_UPDT_WORD;
1040
1041	#ifdef INSTRUMENTATION
1042	m_cpt_cc_update_icache++;
1043	#endif
1044	}
1045	} // end if multi
1046	} // end if cmdval
1047	break;
1048	}
1049	///////////////////
1050	case TGT_UPDT_WORD: // first word index acquisition
1051	{
1052	if (p_vci_tgt_c.cmdval.read())
1053	{
1054	if ( p_vci_tgt_c.eop.read() )
1055	{
1056	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1057	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1058	exit(0);
1059	}
1060	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1061
1062	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1063	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1064	r_tgt_fsm = TGT_UPDT_DATA;
1065	}
1066	break;
1067	}
1068	///////////////////
1069	case TGT_UPDT_DATA:
1070	{
1071	if (p_vci_tgt_c.cmdval.read())
1072	{
1073	size_t word = r_tgt_word_count.read();
1074	if (word >= m_dcache_words)
1075	{
1076	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1077	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1078	exit(0);
1079	}
1080	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1081	r_tgt_be[word] = p_vci_tgt_c.be.read();
1082	r_tgt_word_count = word + 1;
1083
1084	if (p_vci_tgt_c.eop.read()) // last word
1085	{
1086	r_tgt_word_max = word;
1087	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1088	else r_tgt_fsm = TGT_REQ_ICACHE;
1089	}
1090	}
1091	break;
1092	}
1093	///////////////////////
1094	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1095	{
1096	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1097	{
1098	r_tgt_fsm = TGT_RSP_BROADCAST;
1099	r_tgt_icache_req = true;
1100	r_tgt_dcache_req = true;
1101	}
1102	break;
1103	}
1104	/////////////////////
1105	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1106	{
1107	if ( not r_tgt_icache_req.read() )
1108	{
1109	r_tgt_fsm = TGT_RSP_ICACHE;
1110	r_tgt_icache_req = true;
1111	}
1112	break;
1113	}
1114	////////////////////
1115	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1116	{
1117	if ( not r_tgt_dcache_req.read() )
1118	{
1119	r_tgt_fsm = TGT_RSP_DCACHE;
1120	r_tgt_dcache_req = true;
1121	}
1122	break;
1123	}
1124	///////////////////////
1125	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1126	// no response when r_tgt_*cache_rsp is false
1127	{
1128	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1129	{
1130	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1131	{
1132	if ( p_vci_tgt_c.rspack.read() )
1133	{
1134	// reset dcache first if activated
1135	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1136	else r_tgt_icache_rsp = false;
1137	}
1138	}
1139	else
1140	{
1141	r_tgt_fsm = TGT_IDLE;
1142	}
1143	}
1144	break;
1145	}
1146	////////////////////
1147	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1148	{
1149	// no response when r_tgt_icache_rsp is false
1150	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1151	{
1152	r_tgt_fsm = TGT_IDLE;
1153	r_tgt_icache_rsp = false;
1154	}
1155	break;
1156	}
1157	////////////////////
1158	case TGT_RSP_DCACHE:
1159	{
1160	// no response when r_tgt_dcache_rsp is false
1161	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1162	{
1163	r_tgt_fsm = TGT_IDLE;
1164	r_tgt_dcache_rsp = false;
1165	}
1166	break;
1167	}
1168	} // end switch TGT_FSM
1169
1170	/////////////////////////////////////////////////////////////////////
1171	// Get data and instruction requests from processor
1172	///////////////////////////////////////////////////////////////////////
1173
1174	r_iss.getRequests(m_ireq, m_dreq);
1175
1176	////////////////////////////////////////////////////////////////////////////////////
1177	// ICACHE_FSM
1178	//
1179	// There is 9 conditions to exit the IDLE state:
1180	// One condition is a coherence request from TGT FSM :
1181	// - Coherence operation => ICACHE_CC_CHEK
1182	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1183	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1184	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1185	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1186	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1187	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1188	// three configurations corresponding to instruction processor requests :
1189	// - tlb miss => ICACHE_TLB_WAIT
1190	// - cacheable read miss => ICACHE_MISS_VICTIM
1191	// - uncacheable read miss => ICACHE_UNC_REQ
1192	//
1193	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1194	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1195	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1196	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1197	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1198	// The availability of the missing cache line is signaled by the response fifo,
1199	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1200	//
1201	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1202	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1203	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1204	// the response from the RSP FSM, through the response fifo. The missing instruction
1205	// is directly returned to processor in this state.
1206	//
1207	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1208	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1209	// and goes to the ICACHE_TLB_WAIT state.
1210	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1211	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1212	//
1213	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1214	// using the r_dcache_xtn_req flip-flop.
1215	// The request opcode and the address to be invalidated are transmitted
1216	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1217	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1218	// is completed.
1219	//
1220	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1221	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1222	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1223	////////////////////////////////////////////////////////////////////////////////////////
1224
1225	// default value for m_irsp.valid
1226	m_irsp.valid = false;
1227
1228	switch( r_icache_fsm.read() )
1229	{
1230	/////////////////
1231	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1232	// by DCACHE FSM, and coherence requests with a fixed priority:
1233	// coherence > XTN > instruction
1234	// We access the itlb and dcache in parallel with the virtual address
1235	// for itlb, and with a speculative physical address for icache,
1236	// computed during the previous cycle.
1237	{
1238	// coherence request from the target FSM
1239	if ( r_tgt_icache_req.read() )
1240	{
1241	r_icache_fsm = ICACHE_CC_CHECK;
1242	r_icache_fsm_save = r_icache_fsm.read();
1243	break;
1244	}
1245
1246	// Decoding processor XTN requests sent by DCACHE FSM
1247	// These request are not executed in this IDLE state, because
1248	// they require access to icache or itlb, that are already accessed
1249	if ( r_dcache_xtn_req.read() )
1250	{
1251	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1252	{
1253	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1254	break;
1255	}
1256	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1257	{
1258	r_icache_flush_count = 0;
1259	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1260	break;
1261	}
1262	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1263	{
1264	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1265	break;
1266	}
1267	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1268	{
1269	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1270	break;
1271	}
1272	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1273	{
1274	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1275	(paddr_t)r_mmu_word_lo.read();
1276	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1277	break;
1278	}
1279	} // end if xtn_req
1280
1281	// processor request
1282	if ( m_ireq.valid )
1283	{
1284	bool cacheable;
1285	paddr_t paddr;
1286
1287	// We register processor request
1288	r_icache_vaddr_save = m_ireq.addr;
1289
1290	// speculative icache access (if cache activated)
1291	// we use the speculative PPN computed during the previous cycle
1292
1293	uint32_t cache_inst = 0;
1294	bool cache_hit = false;
1295
1296	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1297	{
1298	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1299	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1300
1301	#ifdef INSTRUMENTATION
1302	m_cpt_icache_data_read++;
1303	m_cpt_icache_dir_read++;
1304	#endif
1305	cache_hit = r_icache.read( spc_paddr,
1306	&cache_inst );
1307	}
1308
1309	// systematic itlb access (if tlb activated)
1310	// we use the virtual address
1311
1312	paddr_t tlb_paddr;
1313	pte_info_t tlb_flags;
1314	size_t tlb_way;
1315	size_t tlb_set;
1316	paddr_t tlb_nline;
1317	bool tlb_hit = false;;
1318
1319	if ( r_mmu_mode.read() & INS_TLB_MASK )
1320	{
1321
1322	#ifdef INSTRUMENTATION
1323	m_cpt_itlb_read++;
1324	#endif
1325	tlb_hit = r_itlb.translate( m_ireq.addr,
1326	&tlb_paddr,
1327	&tlb_flags,
1328	&tlb_nline, // unused
1329	&tlb_way, // unused
1330	&tlb_set ); // unused
1331	}
1332
1333	// We compute cacheability, physical address and check access rights:
1334	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1335	// the physical address is obtained from the TLB, and the access rights are
1336	// defined by the U and X bits in the PTE.
1337	// - If MMU not activated : cacheability is defined by the segment table,
1338	// the physical address is equal to the virtual address (identity mapping)
1339	// and there is no access rights checking
1340
1341	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1342	{
1343	// cacheability
1344	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1345	else cacheable = m_cacheability_table[m_ireq.addr];
1346
1347	// physical address
1348	paddr = (paddr_t)m_ireq.addr;
1349	}
1350	else // itlb activated
1351	{
1352	if ( tlb_hit ) // tlb hit
1353	{
1354	// cacheability
1355	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1356	else cacheable = tlb_flags.c;
1357
1358	// physical address
1359	paddr = tlb_paddr;
1360
1361	// access rights checking
1362	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1363	{
1364	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1365	r_mmu_ibvar = m_ireq.addr;
1366	m_irsp.valid = true;
1367	m_irsp.error = true;
1368	m_irsp.instruction = 0;
1369	break;
1370	}
1371	else if ( not tlb_flags.x )
1372	{
1373	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1374	r_mmu_ibvar = m_ireq.addr;
1375	m_irsp.valid = true;
1376	m_irsp.error = true;
1377	m_irsp.instruction = 0;
1378	break;
1379	}
1380	}
1381	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1382	else
1383	{
1384
1385	#ifdef INSTRUMENTATION
1386	m_cpt_itlb_miss++;
1387	#endif
1388	r_icache_fsm = ICACHE_TLB_WAIT;
1389	r_icache_tlb_miss_req = true;
1390	break;
1391	}
1392	} // end if itlb activated
1393
1394	// physical address registration (for next cycle)
1395	r_icache_vci_paddr = paddr;
1396
1397	// We enter this section only in case of TLB hit:
1398	// Finally, we get the instruction depending on cacheability,
1399	// we send the response to processor, and compute next state
1400	if ( cacheable ) // cacheable read
1401	{
1402	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1403	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1404	{
1405
1406	#ifdef INSTRUMENTATION
1407	m_cpt_icache_spc_miss++;
1408	#endif
1409	// we return an invalid response and stay in IDLE state
1410	// the cache access will cost one extra cycle.
1411	break;
1412	}
1413
1414	if ( not cache_hit ) // cache miss
1415	{
1416	// in case of icache miss we send a request to CMD FSM, but we are
1417	// blocked in IDLE state if the previous cleanup is not completed
1418	if ( not r_icache_cleanup_req.read() )
1419	{
1420
1421	#ifdef INSTRUMENTATION
1422	m_cpt_icache_miss++;
1423	#endif
1424	r_icache_fsm = ICACHE_MISS_VICTIM;
1425	r_icache_miss_req = true;
1426	}
1427	break;
1428	}
1429	else // cache hit
1430	{
1431
1432	#ifdef INSTRUMENTATION
1433	m_cpt_ins_read++;
1434	#endif
1435	m_irsp.valid = true;
1436	m_irsp.instruction = cache_inst;
1437	}
1438	}
1439	else // non cacheable read
1440	{
1441	r_icache_unc_req = true;
1442	r_icache_fsm = ICACHE_UNC_WAIT;
1443	}
1444	} // end if m_ireq.valid
1445	break;
1446	}
1447	/////////////////////
1448	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1449	// the itlb is udated by the DCACHE FSM, as well as the
1450	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1451	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1452	// reset the r_icache_tlb_miss_req flip-flop
1453	// external coherence request are accepted in this state.
1454	{
1455	// external coherence request
1456	if ( r_tgt_icache_req.read() )
1457	{
1458	r_icache_fsm = ICACHE_CC_CHECK;
1459	r_icache_fsm_save = r_icache_fsm.read();
1460	break;
1461	}
1462
1463	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1464
1465	// DCACHE FSM signals response by reseting the request flip-flop
1466	if ( not r_icache_tlb_miss_req.read() )
1467	{
1468	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1469	{
1470	r_icache_tlb_rsp_error = false;
1471	m_irsp.error = true;
1472	m_irsp.valid = true;
1473	r_icache_fsm = ICACHE_IDLE;
1474	}
1475	else // tlb updated : return to IDLE state
1476	{
1477	r_icache_fsm = ICACHE_IDLE;
1478	}
1479	}
1480	break;
1481	}
1482	//////////////////////////
1483	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1484	{
1485	r_itlb.flush();
1486	r_dcache_xtn_req = false;
1487	r_icache_fsm = ICACHE_IDLE;
1488	break;
1489	}
1490	////////////////////////////
1491	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1492	// the r_icache_flush_count register as a slot counter.
1493	// We loop in this state until all slots have been visited.
1494	// A cleanup request is generated for each valid line
1495	// and we are blocked until the previous cleanup is completed
1496	{
1497	if ( not r_icache_cleanup_req.read() )
1498	{
1499	size_t way = r_icache_flush_count.read()/m_icache_sets;
1500	size_t set = r_icache_flush_count.read()%m_icache_sets;
1501	paddr_t nline;
1502	bool cleanup_req = r_icache.inval( way,
1503	set,
1504	&nline );
1505	if ( cleanup_req )
1506	{
1507	r_icache_cleanup_req = true;
1508	r_icache_cleanup_line = nline;
1509	}
1510	r_icache_flush_count = r_icache_flush_count.read() + 1;
1511	}
1512
1513	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1514	{
1515	r_dcache_xtn_req = false;
1516	r_icache_fsm = ICACHE_IDLE;
1517	}
1518	break;
1519	}
1520	//////////////////////////
1521	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1522	// stored in the r_dcache_p0_wdata register
1523	{
1524	r_itlb.inval(r_dcache_p0_wdata.read());
1525	r_dcache_xtn_req = false;
1526	r_icache_fsm = ICACHE_IDLE;
1527	break;
1528	}
1529	///////////////////////////////
1530	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1531	// requires 3 cycles (in case of hit on itlb and icache).
1532	// In this state, we access TLB to translate virtual address
1533	// stored in the r_dcache_p0_wdata register.
1534	{
1535	paddr_t paddr;
1536	bool hit;
1537
1538	// read physical address in TLB when MMU activated
1539	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1540	{
1541
1542	#ifdef INSTRUMENTATION
1543	m_cpt_itlb_read++;
1544	#endif
1545	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1546	&paddr);
1547	}
1548	else // itlb not activated
1549	{
1550	paddr = (paddr_t)r_dcache_p0_wdata.read();
1551	hit = true;
1552	}
1553
1554	if ( hit ) // continue the selective inval process
1555	{
1556	r_icache_vci_paddr = paddr;
1557	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1558	}
1559	else // miss : send a request to DCACHE FSM
1560	{
1561
1562	#ifdef INSTRUMENTATION
1563	m_cpt_itlb_miss++;
1564	#endif
1565	r_icache_tlb_miss_req = true;
1566	r_icache_fsm = ICACHE_TLB_WAIT;
1567	}
1568	break;
1569	}
1570	///////////////////////////////
1571	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1572	// require 2 cycles. In this state, we read dcache,
1573	// with address stored in r_icache_vci_paddr register.
1574	{
1575	uint32_t data;
1576	size_t way;
1577	size_t set;
1578	size_t word;
1579	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1580	&data,
1581	&way,
1582	&set,
1583	&word);
1584	if ( hit ) // inval to be done
1585	{
1586	r_icache_miss_way = way;
1587	r_icache_miss_set = set;
1588	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1589	}
1590	else // miss : acknowlege the XTN request and return
1591	{
1592	r_dcache_xtn_req = false;
1593	r_icache_fsm = ICACHE_IDLE;
1594	}
1595	break;
1596	}
1597	///////////////////////////////
1598	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1599	// We are blocked if the previous cleanup is not completed
1600	{
1601	paddr_t nline;
1602
1603	if ( not r_icache_cleanup_req.read() )
1604	{
1605	r_icache.inval( r_icache_miss_way.read(),
1606	r_icache_miss_set.read(),
1607	&nline );
1608
1609	// request cleanup
1610	r_icache_cleanup_req = true;
1611	r_icache_cleanup_line = nline;
1612	// acknowledge the XTN request and return
1613	r_dcache_xtn_req = false;
1614	r_icache_fsm = ICACHE_IDLE;
1615	}
1616	break;
1617	}
1618
1619	////////////////////////
1620	case ICACHE_MISS_VICTIM: // Selects a victim line
1621	// Set the r_icache_cleanup_req flip-flop
1622	// when the selected slot is not empty
1623	{
1624	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1625
1626	bool valid;
1627	size_t way;
1628	size_t set;
1629	paddr_t victim;
1630
1631	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1632	&victim,
1633	&way,
1634	&set);
1635	r_icache_miss_way = way;
1636	r_icache_miss_set = set;
1637
1638	if ( valid )
1639	{
1640	r_icache_cleanup_req = true;
1641	r_icache_cleanup_line = victim;
1642	r_icache_fsm = ICACHE_MISS_INVAL;
1643	}
1644	else
1645	{
1646	r_icache_fsm = ICACHE_MISS_WAIT;
1647	}
1648	break;
1649	}
1650	///////////////////////
1651	case ICACHE_MISS_INVAL: // invalidate the victim line
1652	{
1653	paddr_t nline;
1654
1655	r_icache.inval( r_icache_miss_way.read(),
1656	r_icache_miss_set.read(),
1657	&nline ); // unused
1658
1659	r_icache_fsm = ICACHE_MISS_WAIT;
1660	break;
1661	}
1662	//////////////////////
1663	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1664	{
1665	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1666
1667	// external coherence request
1668	if ( r_tgt_icache_req.read() )
1669	{
1670	r_icache_fsm = ICACHE_CC_CHECK;
1671	r_icache_fsm_save = r_icache_fsm.read();
1672	break;
1673	}
1674
1675	if ( r_vci_rsp_ins_error.read() ) // bus error
1676	{
1677	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1678	r_mmu_ibvar = r_icache_vaddr_save.read();
1679	m_irsp.valid = true;
1680	m_irsp.error = true;
1681	r_vci_rsp_ins_error = false;
1682	r_icache_fsm = ICACHE_IDLE;
1683	}
1684	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1685	{
1686	r_icache_miss_word = 0;
1687	r_icache_fsm = ICACHE_MISS_UPDT;
1688	}
1689	break;
1690	}
1691	//////////////////////
1692	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1693	{
1694	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1695
1696	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1697	{
1698	if ( r_icache_miss_inval ) // Matching coherence request
1699	// We pop the response FIFO, without updating the cache
1700	// We send a cleanup for the missing line at the last word
1701	// Blocked if the previous cleanup is not completed
1702	{
1703	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1704	{
1705	vci_rsp_fifo_icache_get = true;
1706	r_icache_miss_word = r_icache_miss_word.read() + 1;
1707	}
1708	else // last word
1709	{
1710	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1711	{
1712	vci_rsp_fifo_icache_get = true;
1713	r_icache_cleanup_req = true;
1714	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1715	r_icache_miss_inval = false;
1716	r_icache_fsm = ICACHE_IDLE;
1717	}
1718	}
1719	}
1720	else // No matching coherence request
1721	// We pop the FIFO and update the cache
1722	// We update the directory at the last word
1723	{
1724
1725	#ifdef INSTRUMENTATION
1726	m_cpt_icache_data_write++;
1727	#endif
1728	r_icache.write( r_icache_miss_way.read(),
1729	r_icache_miss_set.read(),
1730	r_icache_miss_word.read(),
1731	r_vci_rsp_fifo_icache.read() );
1732	vci_rsp_fifo_icache_get = true;
1733	r_icache_miss_word = r_icache_miss_word.read() + 1;
1734	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1735	{
1736
1737	#ifdef INSTRUMENTATION
1738	m_cpt_icache_dir_write++;
1739	#endif
1740	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1741	r_icache_miss_way.read(),
1742	r_icache_miss_set.read() );
1743	r_icache_fsm = ICACHE_IDLE;
1744	}
1745	}
1746	}
1747	break;
1748	}
1749	////////////////////
1750	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1751	//
1752	{
1753	// external coherence request
1754	if ( r_tgt_icache_req.read() )
1755	{
1756	r_icache_fsm = ICACHE_CC_CHECK;
1757	r_icache_fsm_save = r_icache_fsm.read();
1758	break;
1759	}
1760
1761	if ( r_vci_rsp_ins_error.read() ) // bus error
1762	{
1763	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1764	r_mmu_ibvar = m_ireq.addr;
1765	r_vci_rsp_ins_error = false;
1766	m_irsp.valid = true;
1767	m_irsp.error = true;
1768	r_icache_fsm = ICACHE_IDLE;
1769	}
1770	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1771	{
1772	vci_rsp_fifo_icache_get = true;
1773	r_icache_fsm = ICACHE_IDLE;
1774	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1775	{
1776	m_irsp.valid = true;
1777	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1778	}
1779	}
1780	break;
1781	}
1782	/////////////////////
1783	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1784	// handling coherence requests.
1785	// the return state is defined in r_icache_fsm_save.
1786	{
1787	paddr_t paddr = r_tgt_paddr.read();
1788	paddr_t mask = ~((m_icache_words<<2)-1);
1789
1790	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1791	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1792	{
1793	r_icache_miss_inval = true; // signaling the matching
1794	r_tgt_icache_req = false; // coherence request completed
1795	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1796	r_icache_fsm = r_icache_fsm_save.read();
1797	}
1798	else // no match
1799	{
1800
1801	#ifdef INSTRUMENTATION
1802	m_cpt_icache_dir_read++;
1803	#endif
1804	uint32_t inst;
1805	size_t way;
1806	size_t set;
1807	size_t word;
1808	bool hit = r_icache.read(paddr,
1809	&inst,
1810	&way,
1811	&set,
1812	&word);
1813	r_icache_cc_way = way;
1814	r_icache_cc_set = set;
1815
1816	if ( hit and r_tgt_update.read() ) // hit update
1817	{
1818	r_icache_fsm = ICACHE_CC_UPDT;
1819	r_icache_cc_word = r_tgt_word_min.read();
1820	}
1821	else if ( hit and not r_tgt_update.read() ) // hit inval
1822	{
1823	r_icache_fsm = ICACHE_CC_INVAL;
1824	}
1825	else // miss can happen
1826	{
1827	r_tgt_icache_req = false;
1828	r_tgt_icache_rsp = r_tgt_update.read();
1829	r_icache_fsm = r_icache_fsm_save.read();
1830	}
1831	}
1832	break;
1833	}
1834
1835	/////////////////////
1836	case ICACHE_CC_INVAL: // invalidate a cache line
1837	{
1838	paddr_t nline;
1839	r_icache.inval( r_icache_cc_way.read(),
1840	r_icache_cc_set.read(),
1841	&nline );
1842
1843	r_tgt_icache_req = false;
1844	r_tgt_icache_rsp = true;
1845	r_icache_fsm = r_icache_fsm_save.read();
1846	break;
1847	}
1848	////////////////////
1849	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1850	{
1851	size_t word = r_icache_cc_word.read();
1852	size_t way = r_icache_cc_way.read();
1853	size_t set = r_icache_cc_set.read();
1854
1855	r_icache.write( way,
1856	set,
1857	word,
1858	r_tgt_buf[word],
1859	r_tgt_be[word] );
1860
1861	r_icache_cc_word = word+1;
1862
1863	if ( word == r_tgt_word_max.read() ) // last word
1864	{
1865	r_tgt_icache_req = false;
1866	r_tgt_icache_rsp = true;
1867	r_icache_fsm = r_icache_fsm_save.read();
1868	}
1869	break;
1870	}
1871
1872	} // end switch r_icache_fsm
1873
1874	////////////////////////////////////////////////////////////////////////////////////
1875	// DCACHE FSM
1876	//
1877	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1878	// the cacheability, depending on the MMU mode.
1879	//
1880	// 1/ Coherence requests :
1881	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1882	// requesting a line invalidation or a line update.
1883	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1884	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1885	// goes to the CC_CHECK state to execute the requested action, and returns to the
1886	// pre-empted state.
1887	//
1888	// 2/ TLB miss
1889	// The page tables can be cacheable.
1890	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1891	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1892	// this sub-fsm implement the table-walk...
1893	//
1894	// 3/ processor requests :
1895	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1896	// The IDLE state implements a three stages pipe-line to handle write bursts:
1897	// - The physical address is computed by dtlb in stage P0.
1898	// - The registration in wbuf and the dcache hit are computed in stage P1.
1899	// - The dcache update is done in stage P2.
1900	// A write operation can require a "long write" operation (if the PTE dirty bit
1901	// must be updated) handled by a dedicated sub-fsm (DCACHE_DIRTY_TLB_SET state).
1902	// If a PTE is modified, the both te itlb and dtlb are selectively, but sequencially
1903	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1904	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1905	// (virtual address for itlb, and speculative physical address computed during
1906	// previous cycle for dcache) in order to return the data in one cycle for a read.
1907	// We just pay an extra cycle when the speculative access is failing.
1908	//
1909	// 4/ Atomic instructions LL/SC
1910	// The LL/SC address can be cacheable or non cacheable.
1911	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1912	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1913	// memory controller.
1914	// - LL requests from the processor are transmitted as standard VCI
1915	// READ transactions (one word / one line, depending on the cacheability).
1916	// - SC requests from the processor are systematically transmitted to the
1917	// memory cache as Compare&swap requests (both the data value stored in the
1918	// r_dcache_ll_data register and the new value).
1919	// The cache is not updated, as this is done in case of success by the
1920	// coherence transaction.
1921	// If rqired, the dirty bit is updated in PTE by a "long write".
1922	//
1923	// 5/ Non cacheable access:
1924	// This component implement a strong order between non cacheable access
1925	// (read or write) : A new non cacheable VCI transaction starts only when
1926	// the previous non cacheable transaction is completed. Both cacheable and
1927	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1928	// a non cacheable write transaction posted in the write buffer by setting the
1929	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1930	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1931	// pending non cacheable write transaction completes).
1932	//
1933	// 6/ Error handling:
1934	// When the MMU is not activated, Read Bus Errors are synchronous events,
1935	// but Write Bus Errors are asynchronous events (processor is not frozen).
1936	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1937	// r_vci_rsp_data_error flip-flop, without writing any data in the
1938	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1939	// by the DCACHE FSM.
1940	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1941	// the asynchronous error using the setWriteBerr() method.
1942	// When the MMU is activated bus error are rare events, as the MMU
1943	// checks the physical address before the VCI transaction starts.
1944	////////////////////////////////////////////////////////////////////////////////////////
1945
1946	// default value for m_drsp.valid
1947	m_drsp.valid = false;
1948
1949	switch ( r_dcache_fsm.read() )
1950	{
1951	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1952	// 1) Long write request (DCACHE FSM) => DCACHE_DIRTY_***
1953	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1954	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1955	// 4) XTN request (processor) => DCACHE_XTN_*
1956	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1957	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1958	// 7) Uncacheable read (processor) => DCACHE_UNC_REQ
1959	// 8) SC access (processor) => DCACHE_SC
1960	// There is 4 configurations to access the cache,
1961	// depending on the pipe-line state, defined
1962	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1963	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1964	// V0 / V1 / Data / Directory / comment
1965	// 0 / 0 / read(A0) / read(A0) / read speculative access
1966	// 0 / 1 / write(A2) / nop / read request delayed
1967	// 1 / 0 / nop / read(A1) / read request delayed
1968	// 1 / 1 / write(A2) / read(A1) / read request delayed
1969	{
1970	////////////////////////////////////////////////////////////////////////////////
1971	// Handling P2 pipe-line stage
1972	// Inputs are r_dcache_p1_* registers.
1973	// Three actions are executed in this P2 stage:
1974	// - If r_dcache_p1_updt_cache is true, we update the local copy in dcache.
1975	// - If the modified cache line has copies in TLBs, we launch a TLB invalidate
1976	// operation, that is blocking for the processor, because we switch to
1977	// DCACHE_INVAL_TLB
1978	// - If the PTE dirty bit must be updated, we start a "long write", that is
1979	// blocking for the processor, because we switch to the DCACHE_DIRTY_SET_DIRTY
1980
1981	bool long_write_set_dirty = false; // default value
1982	bool tlb_inval_required = false; // default value
1983
1984	if ( r_dcache_p1_valid.read() ) // P2 stage activated
1985	{
1986	bool cache_updt = r_dcache_p1_updt_cache.read();
1987	size_t way = r_dcache_p1_cache_way.read();
1988	size_t set = r_dcache_p1_cache_set.read();
1989	size_t word = r_dcache_p1_cache_word.read();
1990	uint32_t wdata = r_dcache_p1_wdata.read();
1991	vci_be_t be = r_dcache_p1_be.read();
1992
1993	// update dcache if required
1994	if ( cache_updt )
1995	{
1996	r_dcache.write( way,
1997	set,
1998	word,
1999	wdata,
2000	be );
2001	#ifdef INSTRUMENTATION
2002	m_cpt_dcache_data_write++;
2003	#endif
2004	// cache update can require itlb & dtlb inval
2005	bool inval_itlb = false;
2006	bool inval_dtlb = false;
2007
2008	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
2009	{
2010	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
2011	inval_dtlb = true;
2012	}
2013	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
2014	{
2015	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
2016	inval_itlb = true;
2017	}
2018	if ( inval_itlb or inval_dtlb )
2019	{
2020	tlb_inval_required = true;
2021	r_dcache_itlb_inval_req = inval_itlb;
2022	r_dcache_dtlb_inval_req = inval_dtlb;
2023	r_dcache_tlb_inval_count = 0;
2024	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2));
2025	}
2026	} // end dcache update
2027
2028	// checking if dirty bit update is required
2029	if ( r_dcache_p1_set_dirty.read() )
2030	{
2031	long_write_set_dirty = true;
2032	r_dcache_p2_way = r_dcache_p1_tlb_way.read();
2033	r_dcache_p2_set = r_dcache_p1_tlb_set.read();
2034	// The PTE physical address is the concatenation of the nline value (from dtlb),
2035	// with the word index (obtained from the proper bits of the virtual address)
2036	if ( r_dcache_p1_tlb_big.read() ) // PTE1
2037	{
2038	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2)) \|
2039	(paddr_t)((r_dcache_p1_vaddr.read()>>19) & 0x3c);
2040	}
2041	else // PTE2
2042	{
2043	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2)) \|
2044	(paddr_t)((r_dcache_p1_vaddr.read()>>9) & 0x38);
2045	}
2046	}
2047
2048	#if DEBUG_DCACHE
2049	if ( m_debug_dcache_fsm )
2050	{
2051	if ( cache_updt )
2052	std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec
2053	<< " / way = " << way
2054	<< " / set = " << set
2055	<< " / word = " << word << std::hex
2056	<< " / wdata = " << wdata
2057	<< " / be = " << be << std::endl;
2058	if ( long_write_set_dirty )
2059	std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required"
2060	<< " / pte_paddr = " << std::hex << r_dcache_p2_pte_paddr.read() << std::endl;
2061	}
2062	#endif
2063	} // end P2 stage
2064
2065	///////////////////////////////////////////////////////////////////////////
2066	// Handling P1 pipe-line stage
2067	// Inputs are r_dcache_p0_* registers.
2068	// - We must write into wbuf and test the hit in dcache.
2069	// If the write request is not cacheable, and there is a pending
2070	// non cacheable write, or if the write buffer is full, we break:
2071	// The P0 and P1 pipe-line stages are frozen until the write
2072	// request registration is possible, but the P2 stage is not frozen.
2073	// - The r_dcache_p1_valid bit activating the P2 pipe-line stage
2074	// must be computed at all cycles. The P2 stage must be activated
2075	// if there is local copy in dcache, or if the PTE dirty bit must be set.
2076
2077	if ( r_dcache_p0_valid.read() and not tlb_inval_required ) // P1 stage activated
2078	{
2079	// write not cacheable, and previous non cacheable write registered
2080	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2081	{
2082	r_dcache_p1_valid = false;
2083	break;
2084	}
2085
2086	// try a registration into write buffer
2087	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2088	r_dcache_p0_be.read(),
2089	r_dcache_p0_wdata.read(),
2090	r_dcache_p0_cacheable.read() );
2091	#ifdef INSTRUMENTATION
2092	m_cpt_wbuf_write++;
2093	#endif
2094	// write buffer full
2095	if ( not wok )
2096	{
2097	r_dcache_p1_valid = false;
2098	break;
2099	}
2100	// update the write_buffer state extension
2101	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2102
2103	// read directory to detect local copy
2104	size_t cache_way;
2105	size_t cache_set;
2106	size_t cache_word;
2107	bool local_copy;
2108	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2109	{
2110	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2111	&cache_way,
2112	&cache_set,
2113	&cache_word );
2114	#ifdef INSTRUMENTATION
2115	m_cpt_dcache_dir_read++;
2116	#endif
2117	}
2118	else
2119	{
2120	local_copy = false;
2121	}
2122
2123	// dirty bit update requested
2124	bool dirty_req = (r_mmu_mode.read() & DATA_TLB_MASK) and not r_dcache_p0_tlb_dirty.read();
2125
2126	// if there is a local copy or a dirty bit update requested
2127	if ( local_copy or dirty_req )
2128	{
2129	r_dcache_p1_valid = true;
2130	r_dcache_p1_set_dirty = dirty_req;
2131	r_dcache_p1_updt_cache = local_copy;
2132	r_dcache_p1_vaddr = r_dcache_p0_vaddr.read();
2133	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2134	r_dcache_p1_be = r_dcache_p0_be.read();
2135	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2136	r_dcache_p1_tlb_way = r_dcache_p0_tlb_way;
2137	r_dcache_p1_tlb_set = r_dcache_p0_tlb_set;
2138	r_dcache_p1_tlb_nline = r_dcache_p0_tlb_nline;
2139	r_dcache_p1_tlb_big = r_dcache_p0_tlb_big;
2140	r_dcache_p1_cache_way = cache_way;
2141	r_dcache_p1_cache_set = cache_set;
2142	r_dcache_p1_cache_word = cache_word;
2143	}
2144	else
2145	{
2146	r_dcache_p1_valid = false;
2147	}
2148	}
2149	else // P1 stage not activated
2150	{
2151	r_dcache_p1_valid = false;
2152	} // end P1 stage
2153
2154	/////////////////////////////////////////////////////////////////////////////
2155	// handling P0 pipe-line stage
2156	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2157	// The r_dcache_p0_valid flip-flop is only set in case of WRITE request.
2158	// - the TLB invalidate requests have the highest priority,
2159	// - then the long write requests,
2160	// - then the external coherence requests,
2161	// - then the itlb miss requests,
2162	// - and finally the processor requests.
2163	// If dtlb is activated, there is an unconditionnal access to dtlb,
2164	// for address translation.
2165	// 1) A processor WRITE request enters the three stage pipe-line (handled
2166	// by the IDLE state), and can be completed by a "long write" if the
2167	// PTE dirty bit must be updated in dtb, dcache and RAM.
2168	// 2) A processor READ request generate a simultaneouss access to
2169	// both dcache data and dcache directoty, using speculative PPN, but
2170	// is delayed if the write pipe-line is not empty.
2171	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2172	// DCACHE_MISS_WAIT states.
2173	// 3) A processor LL request is handled as a READ request.
2174	// 4) A processor SC request is delayed until the write pipe-line is empty.
2175	// A VCI SC transaction is launched, and we wait the VCI response in
2176	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2177	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2178	// The data is not modified in dcache, as it will be done by the
2179	// coherence transaction.
2180
2181	// TLB inval required
2182	if ( tlb_inval_required )
2183	{
2184	r_dcache_fsm_save = DCACHE_IDLE;
2185	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2186	r_dcache_p0_valid = false;
2187	}
2188
2189	// long write request
2190	else if ( long_write_set_dirty )
2191	{
2192	r_dcache_fsm = DCACHE_DIRTY_TLB_SET;
2193	r_dcache_p0_valid = false;
2194	}
2195
2196	// external coherence request
2197	else if ( r_tgt_dcache_req.read() )
2198	{
2199	r_dcache_fsm_save = DCACHE_IDLE;
2200	r_dcache_fsm = DCACHE_CC_CHECK;
2201	r_dcache_p0_valid = false;
2202	}
2203
2204	// itlb miss request
2205	else if ( r_icache_tlb_miss_req.read() )
2206	{
2207	r_dcache_tlb_ins = true;
2208	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2209	r_dcache_fsm = DCACHE_TLB_MISS;
2210	r_dcache_p0_valid = false;
2211	}
2212
2213	// processor request
2214	else if ( m_dreq.valid )
2215	{
2216	// dcache access using speculative PPN only if pipe-line empty
2217	paddr_t cache_paddr;
2218	size_t cache_way;
2219	size_t cache_set;
2220	size_t cache_word;
2221	uint32_t cache_rdata;
2222	bool cache_hit;
2223
2224	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2225	not r_dcache_p0_valid.read() and
2226	not r_dcache_p1_valid.read() ) // pipe-line empty
2227	{
2228	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2229	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2230
2231	cache_hit = r_dcache.read( cache_paddr,
2232	&cache_rdata,
2233	&cache_way,
2234	&cache_set,
2235	&cache_word );
2236	#ifdef INSTRUMENTATION
2237	m_cpt_dcache_dir_read++;
2238	m_cpt_dcache_data_read++;
2239	#endif
2240	}
2241	else
2242	{
2243	cache_hit = false;
2244	} // end dcache access
2245
2246	// systematic dtlb access using virtual address
2247
2248	paddr_t tlb_paddr;
2249	pte_info_t tlb_flags;
2250	size_t tlb_way;
2251	size_t tlb_set;
2252	paddr_t tlb_nline;
2253	bool tlb_hit;
2254
2255	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // TLB activated
2256	{
2257	tlb_hit = r_dtlb.translate( m_dreq.addr,
2258	&tlb_paddr,
2259	&tlb_flags,
2260	&tlb_nline,
2261	&tlb_way,
2262	&tlb_set );
2263	#ifdef INSTRUMENTATION
2264	m_cpt_dtlb_read++;
2265	#endif
2266	// register dtlb outputs
2267	r_dcache_p0_tlb_nline = tlb_nline;
2268	r_dcache_p0_tlb_way = tlb_way;
2269	r_dcache_p0_tlb_set = tlb_set;
2270	r_dcache_p0_tlb_dirty = tlb_flags.d;
2271	r_dcache_p0_tlb_big = tlb_flags.b;
2272	}
2273	else
2274	{
2275	tlb_hit = false;
2276	} // end dtlb access
2277
2278	// register the processor request
2279	r_dcache_p0_vaddr = m_dreq.addr;
2280	r_dcache_p0_be = m_dreq.be;
2281	r_dcache_p0_wdata = m_dreq.wdata;
2282
2283	// Handling READ XTN requests from processor
2284	// They are executed in this DCACHE_IDLE state.
2285	// The processor must not be in user mode
2286	if (m_dreq.type == iss_t::XTN_READ)
2287	{
2288	int xtn_opcode = (int)m_dreq.addr/4;
2289
2290	// checking processor mode:
2291	if (m_dreq.mode == iss_t::MODE_USER)
2292	{
2293	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2294	r_mmu_dbvar = m_dreq.addr;
2295	m_drsp.valid = true;
2296	m_drsp.error = true;
2297	r_dcache_fsm = DCACHE_IDLE;
2298	}
2299	else
2300	{
2301	switch( xtn_opcode )
2302	{
2303	case iss_t::XTN_INS_ERROR_TYPE:
2304	m_drsp.rdata = r_mmu_ietr.read();
2305	m_drsp.valid = true;
2306	break;
2307
2308	case iss_t::XTN_DATA_ERROR_TYPE:
2309	m_drsp.rdata = r_mmu_detr.read();
2310	m_drsp.valid = true;
2311	break;
2312
2313	case iss_t::XTN_INS_BAD_VADDR:
2314	m_drsp.rdata = r_mmu_ibvar.read();
2315	m_drsp.valid = true;
2316	break;
2317
2318	case iss_t::XTN_DATA_BAD_VADDR:
2319	m_drsp.rdata = r_mmu_dbvar.read();
2320	m_drsp.valid = true;
2321	break;
2322
2323	case iss_t::XTN_PTPR:
2324	m_drsp.rdata = r_mmu_ptpr.read();
2325	m_drsp.valid = true;
2326	break;
2327
2328	case iss_t::XTN_TLB_MODE:
2329	m_drsp.rdata = r_mmu_mode.read();
2330	m_drsp.valid = true;
2331	break;
2332
2333	case iss_t::XTN_MMU_PARAMS:
2334	m_drsp.rdata = r_mmu_params;
2335	m_drsp.valid = true;
2336	break;
2337
2338	case iss_t::XTN_MMU_RELEASE:
2339	m_drsp.rdata = r_mmu_release;
2340	m_drsp.valid = true;
2341	break;
2342
2343	case iss_t::XTN_MMU_WORD_LO:
2344	m_drsp.rdata = r_mmu_word_lo.read();
2345	m_drsp.valid = true;
2346	break;
2347
2348	case iss_t::XTN_MMU_WORD_HI:
2349	m_drsp.rdata = r_mmu_word_hi.read();
2350	m_drsp.valid = true;
2351	break;
2352
2353	default:
2354	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2355	r_mmu_dbvar = m_dreq.addr;
2356	m_drsp.valid = true;
2357	m_drsp.error = true;
2358	break;
2359	} // end switch xtn_opcode
2360	} // end else
2361	r_dcache_p0_valid = false;
2362	} // end if XTN_READ
2363
2364	// Handling WRITE XTN requests from processor.
2365	// They are not executed in this DCACHE_IDLE state,
2366	// if they require access to the caches or the TLBs
2367	// that are already accessed for speculative read.
2368	// Caches can be invalidated or flushed in user mode,
2369	// and the sync instruction can be executed in user mode
2370	else if (m_dreq.type == iss_t::XTN_WRITE)
2371	{
2372	int xtn_opcode = (int)m_dreq.addr/4;
2373	r_dcache_xtn_opcode = xtn_opcode;
2374
2375	// checking processor mode:
2376	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2377	(xtn_opcode != iss_t:: XTN_SYNC) &&
2378	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2379	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2380	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2381	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2382	{
2383	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2384	r_mmu_dbvar = m_dreq.addr;
2385	m_drsp.valid = true;
2386	m_drsp.error = true;
2387	r_dcache_fsm = DCACHE_IDLE;
2388	}
2389	else
2390	{
2391	switch( xtn_opcode )
2392	{
2393	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2394	r_mmu_ptpr = m_dreq.wdata;
2395	r_dcache_xtn_req = true;
2396	r_dcache_fsm = DCACHE_XTN_SWITCH;
2397	break;
2398
2399	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2400	r_mmu_mode = m_dreq.wdata;
2401	m_drsp.valid = true;
2402	r_dcache_fsm = DCACHE_IDLE;
2403	break;
2404
2405	case iss_t::XTN_DTLB_INVAL: // dtlb access
2406	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2407	break;
2408
2409	case iss_t::XTN_ITLB_INVAL: // itlb access
2410	r_dcache_xtn_req = true;
2411	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2412	break;
2413
2414	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2415	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2416	break;
2417
2418	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2419	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2420	r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2421	(paddr_t)r_mmu_word_lo.read();
2422	break;
2423
2424	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2425	r_dcache_flush_count = 0;
2426	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2427	break;
2428
2429	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2430	r_dcache_xtn_req = true;
2431	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2432	break;
2433
2434	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2435	r_dcache_xtn_req = true;
2436	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2437	break;
2438
2439	case iss_t::XTN_ICACHE_FLUSH: // icache access
2440	r_dcache_xtn_req = true;
2441	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2442	break;
2443
2444	case iss_t::XTN_SYNC: // wait until write buffer empty
2445	r_dcache_fsm = DCACHE_XTN_SYNC;
2446	break;
2447
2448	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2449	r_mmu_word_lo = m_dreq.wdata;
2450	m_drsp.valid = true;
2451	r_dcache_fsm = DCACHE_IDLE;
2452	break;
2453
2454	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2455	r_mmu_word_hi = m_dreq.wdata;
2456	m_drsp.valid = true;
2457	r_dcache_fsm = DCACHE_IDLE;
2458	break;
2459
2460	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2461	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2462	m_drsp.valid = true;
2463	r_dcache_fsm = DCACHE_IDLE;
2464	break;
2465
2466	default:
2467	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2468	r_mmu_dbvar = m_dreq.addr;
2469	m_drsp.valid = true;
2470	m_drsp.error = true;
2471	r_dcache_fsm = DCACHE_IDLE;
2472	break;
2473	} // end switch xtn_opcode
2474	} // end else
2475	r_dcache_p0_valid = false;
2476	} // end if XTN_WRITE
2477
2478	// Handling read/write/ll/sc processor requests.
2479	// The dtlb and dcache can be activated or not.
2480	// We compute the physical address, the cacheability, and check processor request.
2481	// - If DTLB not activated : cacheability is defined by the segment table,
2482	// the physical address is equal to the virtual address (identity mapping)
2483	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2484	// the physical address is obtained from the TLB, and the U & W bits
2485	// of the PTE are checked.
2486	// The processor request is decoded only if the TLB is not activated or if
2487	// the virtual address hits in tLB and access rights are OK.
2488	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2489	else
2490	{
2491	bool valid_req = false;
2492	bool cacheable = false;
2493	paddr_t paddr = 0;
2494
2495	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2496	{
2497	valid_req = true;
2498
2499	// cacheability
2500	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2501	else cacheable = m_cacheability_table[m_dreq.addr];
2502
2503	// physical address
2504	paddr = (paddr_t)m_dreq.addr;
2505	}
2506	else // dtlb activated
2507	{
2508	if ( tlb_hit ) // tlb hit
2509	{
2510	// cacheability
2511	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2512	else cacheable = tlb_flags.c;
2513
2514	// access rights checking
2515	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2516	{
2517	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2518	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2519	else
2520	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2521
2522	r_mmu_dbvar = m_dreq.addr;
2523	m_drsp.valid = true;
2524	m_drsp.error = true;
2525	m_drsp.rdata = 0;
2526	}
2527	else if ( not tlb_flags.w and
2528	((m_dreq.type == iss_t::DATA_WRITE) or
2529	(m_dreq.type == iss_t::DATA_SC)) )
2530	{
2531	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2532	r_mmu_dbvar = m_dreq.addr;
2533	m_drsp.valid = true;
2534	m_drsp.error = true;
2535	m_drsp.rdata = 0;
2536	}
2537	else
2538	{
2539	valid_req = true;
2540	}
2541
2542	// physical address
2543	paddr = tlb_paddr;
2544	}
2545	else // tlb miss
2546	{
2547	r_dcache_tlb_vaddr = m_dreq.addr;
2548	r_dcache_tlb_ins = false;
2549	r_dcache_fsm = DCACHE_TLB_MISS;
2550	}
2551	} // end DTLB activated
2552
2553	if ( valid_req ) // processor request is valid after TLB check
2554	{
2555	// physical address and cacheability registration
2556	r_dcache_p0_paddr = paddr;
2557	r_dcache_p0_cacheable = cacheable;
2558
2559	// READ or LL request
2560	// The read requests are taken only if the write pipe-line is empty.
2561	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2562	// If speculative access is KO we just pay one extra cycle.
2563	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2564	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2565	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2566	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2567	{
2568	if ( cacheable ) // cacheable read
2569	{
2570	// if the speculative access is illegal, we pay an extra cycle
2571	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2572	!= (paddr & ~PAGE_K_MASK))
2573	{
2574	#ifdef INSTRUMENTATION
2575	m_cpt_dcache_spec_miss++;
2576	#endif
2577	}
2578	// if cache miss, try to get the missing line
2579	else if ( not cache_hit )
2580	{
2581	#ifdef INSTRUMENTATION
2582	m_cpt_dcache_miss++;
2583	#endif
2584	// blocked in IDLE state if previous cleanup not completed
2585	if ( not r_dcache_cleanup_req.read() )
2586	{
2587	r_dcache_vci_paddr = paddr;
2588	r_dcache_vci_miss_req = true;
2589	r_dcache_miss_type = PROC_MISS;
2590	r_dcache_fsm = DCACHE_MISS_VICTIM;
2591	}
2592	}
2593	// if cache hit return the data
2594	else
2595	{
2596	#ifdef INSTRUMENTATION
2597	m_cpt_data_read++;
2598	#endif
2599	m_drsp.valid = true;
2600	m_drsp.rdata = cache_rdata;
2601	}
2602	}
2603	else // uncacheable read
2604	{
2605	r_dcache_vci_paddr = paddr;
2606	r_dcache_vci_unc_be = m_dreq.be;
2607	r_dcache_vci_unc_req = true;
2608	r_dcache_fsm = DCACHE_UNC_WAIT;
2609	}
2610
2611	// makes reservation in case of LL
2612	if ( m_dreq.type == iss_t::DATA_LL )
2613	{
2614	r_dcache_ll_valid = true;
2615	r_dcache_ll_data = cache_rdata;
2616	r_dcache_ll_vaddr = m_dreq.addr;
2617	}
2618	r_dcache_p0_valid = false;
2619	} // end READ or LL
2620
2621	// WRITE request:
2622	// The write request arguments have been registered in r_dcache_p0 registers.
2623	// The physical address has been computed and registered.
2624	// We acknowledge the processor request and activate the P1 pipeline stage.
2625	else if ( m_dreq.type == iss_t::DATA_WRITE )
2626	{
2627
2628	#ifdef INSTRUMENTATION
2629	m_cpt_data_write++;
2630	#endif
2631	m_drsp.valid = true;
2632	m_drsp.rdata = 0;
2633	r_dcache_p0_valid = true;
2634	} // end WRITE
2635
2636	// SC request:
2637	// The SC requests are taken only if the write pipe-line is empty.
2638	// - if a valid LL reservation (with the same address) is registered,
2639	// we request a SC transaction to CMD FSM and go to the DCACHE_SC_WAIT state
2640	// that will directly return the response to the processor, invalidate
2641	// the LL reservation, and set the Dirty bit if required.
2642	// We don't check a possible write hit in dcache, as the cache update
2643	// is done by the coherence transaction...
2644	// - if there is no valid registered LL, we just stay in IDLE state,
2645	// and return 1 (atomic access failed)
2646	else if ( ( m_dreq.type == iss_t::DATA_SC )
2647	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2648	{
2649
2650	#ifdef INSTRUMENTATION
2651	m_cpt_data_sc++;
2652	#endif
2653	// test if valid registered LL
2654	if ( r_dcache_ll_valid.read() and (r_dcache_ll_vaddr.read() == m_dreq.addr))
2655	{
2656	r_dcache_vci_paddr = paddr;
2657	r_dcache_vci_sc_req = true;
2658	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2659	r_dcache_vci_sc_new = m_dreq.wdata;
2660	r_dcache_fsm = DCACHE_SC_WAIT;
2661	}
2662	else // no registered LL
2663	{
2664
2665	m_drsp.valid = true;
2666	m_drsp.rdata = 1;
2667	r_dcache_ll_valid = false;
2668	}
2669	r_dcache_p0_valid = false;
2670	} // end SC
2671	else
2672	{
2673	r_dcache_p0_valid = false;
2674	}
2675	} // end valid_req
2676	else
2677	{
2678	r_dcache_p0_valid = false;
2679	}
2680	} // end if read/write/ll/sc request
2681	} // end dreq.valid
2682	else
2683	{
2684	r_dcache_p0_valid = false;
2685	} // end P0 pipe stage
2686	break;
2687	}
2688	/////////////////////
2689	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2690	// Input arguments are:
2691	// - r_dcache_tlb_vaddr
2692	// - r_dcache_tlb_ins (true when itlb miss)
2693	// The sub-fsm access the dcache to find the missing TLB entry,
2694	// and activates the cache miss procedure in case of miss.
2695	// It bypass the first level page table access if possible.
2696	// It uses atomic access to update the R/L access bits
2697	// in the page table if required.
2698	// It directly updates the itlb or dtlb, and writes into the
2699	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2700	{
2701	uint32_t ptba = 0;
2702	bool bypass;
2703	paddr_t pte_paddr;
2704
2705	// evaluate bypass in order to skip first level page table access
2706	if ( r_dcache_tlb_ins.read() ) // itlb miss
2707	{
2708	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2709	}
2710	else // dtlb miss
2711	{
2712	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2713	}
2714
2715	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2716	{
2717	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2718	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2719	r_dcache_tlb_paddr = pte_paddr;
2720	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2721	}
2722	else // Try to read PTE2 in dcache
2723	{
2724	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2725	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2726	r_dcache_tlb_paddr = pte_paddr;
2727	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2728	}
2729
2730	#if DEBUG_DCACHE
2731	if ( m_debug_dcache_fsm )
2732	{
2733	if ( r_dcache_tlb_ins.read() )
2734	{
2735	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2736	}
2737	else
2738	{
2739	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2740	}
2741	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2742	<< " / BYPASS = " << bypass
2743	<< " / PTE_ADR = " << pte_paddr << std::endl;
2744	}
2745	#endif
2746
2747	break;
2748	}
2749	/////////////////////////
2750	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2751	{
2752	uint32_t entry;
2753	size_t way;
2754	size_t set;
2755	size_t word;
2756
2757	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2758	&entry,
2759	&way,
2760	&set,
2761	&word );
2762	#ifdef INSTRUMENTATION
2763	m_cpt_dcache_data_read++;
2764	m_cpt_dcache_dir_read++;
2765	#endif
2766	if ( hit ) // hit in dcache
2767	{
2768	if ( not (entry & PTE_V_MASK) ) // unmapped
2769	{
2770	if ( r_dcache_tlb_ins.read() )
2771	{
2772	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2773	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2774	r_icache_tlb_miss_req = false;
2775	r_icache_tlb_rsp_error = true;
2776	}
2777	else
2778	{
2779	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2780	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2781	m_drsp.valid = true;
2782	m_drsp.error = true;
2783	}
2784	r_dcache_fsm = DCACHE_IDLE;
2785
2786	#if DEBUG_DCACHE
2787	if ( m_debug_dcache_fsm )
2788	{
2789	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2790	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2791	<< std::dec << " / way = " << way
2792	<< std::dec << " / set = " << set
2793	<< std::dec << " / word = " << word
2794	<< std::hex << " / PTE1 = " << entry << std::endl;
2795	}
2796	#endif
2797
2798	}
2799	else if( entry & PTE_T_MASK ) // PTD : access PT2
2800	{
2801	// register bypass
2802	if ( r_dcache_tlb_ins.read() ) // itlb
2803	{
2804	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2805	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2806	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2807	}
2808	else // dtlb
2809	{
2810	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2811	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2812	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2813	}
2814	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2815	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2816	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2817
2818	#if DEBUG_DCACHE
2819	if ( m_debug_dcache_fsm )
2820	{
2821	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2822	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2823	<< std::dec << " / way = " << way
2824	<< std::dec << " / set = " << set
2825	<< std::dec << " / word = " << word
2826	<< std::hex << " / PTD = " << entry << std::endl;
2827	}
2828	#endif
2829	}
2830	else // PTE1 : update the TLB
2831	{
2832	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
2833	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
2834	r_dcache_tlb_pte_flags = entry;
2835	r_dcache_tlb_cache_way = way;
2836	r_dcache_tlb_cache_set = set;
2837	r_dcache_tlb_cache_word = word;
2838	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2839
2840	#if DEBUG_DCACHE
2841	if ( m_debug_dcache_fsm )
2842	{
2843	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2844	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2845	<< std::dec << " / way = " << way
2846	<< std::dec << " / set = " << set
2847	<< std::dec << " / word = " << word
2848	<< std::hex << " / PTE1 = " << entry << std::endl;
2849	}
2850	#endif
2851	}
2852	}
2853	else // we must load the missing cache line in dcache
2854	{
2855	r_dcache_vci_miss_req = true;
2856	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2857	r_dcache_miss_type = PTE1_MISS;
2858	r_dcache_fsm = DCACHE_MISS_VICTIM;
2859
2860	#if DEBUG_DCACHE
2861	if ( m_debug_dcache_fsm )
2862	{
2863	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2864	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2865	}
2866	#endif
2867	}
2868	break;
2869	}
2870	////////////////////////////
2871	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2872	{
2873	size_t way;
2874	size_t set;
2875
2876	if ( r_dcache_tlb_ins.read() )
2877	{
2878	r_itlb.select( r_dcache_tlb_vaddr.read(),
2879	true, // PTE1
2880	&way,
2881	&set );
2882	#ifdef INSTRUMENTATION
2883	m_cpt_itlb_read++;
2884	#endif
2885	}
2886	else
2887	{
2888	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2889	true, // PTE1
2890	&way,
2891	&set );
2892	#ifdef INSTRUMENTATION
2893	m_cpt_dtlb_read++;
2894	#endif
2895	}
2896	r_dcache_tlb_way = way;
2897	r_dcache_tlb_set = set;
2898	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2899
2900	#if DEBUG_DCACHE
2901	if ( m_debug_dcache_fsm )
2902	{
2903	if ( r_dcache_tlb_ins.read() )
2904	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2905	else
2906	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2907	std::cout << " way = " << std::dec << way
2908	<< " / set = " << set << std::endl;
2909	}
2910	#endif
2911	break;
2912	}
2913	//////////////////////////
2914	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2915	// if L/R bit already set, exit the sub-fsm
2916	// if not, the page table must be updated
2917	{
2918	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2919	uint32_t pte = r_dcache_tlb_pte_flags.read();
2920	bool updt = false;
2921	bool local = true;
2922
2923	// We should compute the access locality:
2924	// The PPN MSB bits define the destination cluster index.
2925	// The m_srcid_d MSB bits define the source cluster index.
2926	// The number of bits to compare depends on the number of clusters,
2927	// and can be obtained in the mapping table.
2928	// As long as this computation is not done, all access are local.
2929
2930	if ( local ) // local access
2931	{
2932	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2933	{
2934	updt = true;
2935	r_dcache_vci_sc_old = pte;
2936	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2937	pte = pte \| PTE_L_MASK;
2938	}
2939	}
2940	else // remote access
2941	{
2942	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2943	{
2944	updt = true;
2945	r_dcache_vci_sc_old = pte;
2946	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2947	pte = pte \| PTE_R_MASK;
2948	}
2949	}
2950
2951	// update TLB
2952	if ( r_dcache_tlb_ins.read() )
2953	{
2954	r_itlb.write( true, // 2M page
2955	pte,
2956	0, // argument unused for a PTE1
2957	r_dcache_tlb_vaddr.read(),
2958	r_dcache_tlb_way.read(),
2959	r_dcache_tlb_set.read(),
2960	nline );
2961	#ifdef INSTRUMENTATION
2962	m_cpt_itlb_write++;
2963	#endif
2964	}
2965	else
2966	{
2967	r_dtlb.write( true, // 2M page
2968	pte,
2969	0, // argument unused for a PTE1
2970	r_dcache_tlb_vaddr.read(),
2971	r_dcache_tlb_way.read(),
2972	r_dcache_tlb_set.read(),
2973	nline );
2974	#ifdef INSTRUMENTATION
2975	m_cpt_dtlb_write++;
2976	#endif
2977	}
2978	// next state
2979	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
2980	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
2981
2982	#if DEBUG_DCACHE
2983	if ( m_debug_dcache_fsm )
2984	{
2985	if ( r_dcache_tlb_ins.read() )
2986	{
2987	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
2988	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
2989	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2990	r_itlb.printTrace();
2991	}
2992	else
2993	{
2994	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
2995	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
2996	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2997	r_dtlb.printTrace();
2998	}
2999
3000	}
3001	#endif
3002	break;
3003	}
3004	/////////////////////////
3005	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3006	{
3007	uint32_t pte_flags;
3008	uint32_t pte_ppn;
3009	size_t way;
3010	size_t set;
3011	size_t word;
3012
3013	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3014	&pte_flags,
3015	&pte_ppn,
3016	&way,
3017	&set,
3018	&word );
3019	#ifdef INSTRUMENTATION
3020	m_cpt_dcache_data_read++;
3021	m_cpt_dcache_dir_read++;
3022	#endif
3023	if ( hit ) // request hits in dcache
3024	{
3025	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3026	{
3027	if ( r_dcache_tlb_ins.read() )
3028	{
3029	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3030	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3031	r_icache_tlb_miss_req = false;
3032	r_icache_tlb_rsp_error = true;
3033	}
3034	else
3035	{
3036	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3037	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3038	m_drsp.valid = true;
3039	m_drsp.error = true;
3040	}
3041	r_dcache_fsm = DCACHE_IDLE;
3042
3043	#if DEBUG_DCACHE
3044	if ( m_debug_dcache_fsm )
3045	{
3046	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3047	<< " PTE_FLAGS = " << std::hex << pte_flags
3048	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3049	}
3050	#endif
3051	}
3052	else // mapped : update the TLB
3053	{
3054	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
3055	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
3056	r_dcache_tlb_pte_flags = pte_flags;
3057	r_dcache_tlb_pte_ppn = pte_ppn;
3058	r_dcache_tlb_cache_way = way;
3059	r_dcache_tlb_cache_set = set;
3060	r_dcache_tlb_cache_word = word;
3061	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3062
3063	#if DEBUG_DCACHE
3064	if ( m_debug_dcache_fsm )
3065	{
3066	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3067	<< " PTE_FLAGS = " << std::hex << pte_flags
3068	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3069	}
3070	#endif
3071	}
3072	}
3073	else // we must load the missing cache line in dcache
3074	{
3075	r_dcache_fsm = DCACHE_MISS_VICTIM;
3076	r_dcache_vci_miss_req = true;
3077	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3078	r_dcache_miss_type = PTE2_MISS;
3079
3080	#if DEBUG_DCACHE
3081	if ( m_debug_dcache_fsm )
3082	{
3083	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3084	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3085	}
3086	#endif
3087	}
3088	break;
3089	}
3090	////////////////////////////
3091	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3092	{
3093	size_t way;
3094	size_t set;
3095
3096	if ( r_dcache_tlb_ins.read() )
3097	{
3098	r_itlb.select( r_dcache_tlb_vaddr.read(),
3099	false, // PTE2
3100	&way,
3101	&set );
3102	#ifdef INSTRUMENTATION
3103	m_cpt_itlb_read++;
3104	#endif
3105	}
3106	else
3107	{
3108	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3109	false, // PTE2
3110	&way,
3111	&set );
3112	#ifdef INSTRUMENTATION
3113	m_cpt_dtlb_read++;
3114	#endif
3115	}
3116
3117	#if DEBUG_DCACHE
3118	if ( m_debug_dcache_fsm )
3119	{
3120	if ( r_dcache_tlb_ins.read() )
3121	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3122	else
3123	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3124	std::cout << " way = " << std::dec << way
3125	<< " / set = " << set << std::endl;
3126	}
3127	#endif
3128	r_dcache_tlb_way = way;
3129	r_dcache_tlb_set = set;
3130	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3131	break;
3132	}
3133	//////////////////////////
3134	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3135	// if L/R bit already set, exit the sub-fsm
3136	// if not, the page table must be updated by an atomic access
3137	{
3138	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3139	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3140	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3141	bool updt = false;
3142	bool local = true;
3143
3144	// We should compute the access locality:
3145	// The PPN MSB bits define the destination cluster index.
3146	// The m_srcid_d MSB bits define the source cluster index.
3147	// The number of bits to compare depends on the number of clusters,
3148	// and can be obtained in the mapping table.
3149	// As long as this computation is not done, all access are local.
3150
3151	if ( local ) // local access
3152	{
3153	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3154	{
3155	updt = true;
3156	r_dcache_vci_sc_old = pte_flags;
3157	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3158	pte_flags = pte_flags \| PTE_L_MASK;
3159	}
3160	}
3161	else // remote access
3162	{
3163	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3164	{
3165	updt = true;
3166	r_dcache_vci_sc_old = pte_flags;
3167	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3168	pte_flags = pte_flags \| PTE_R_MASK;
3169	}
3170	}
3171
3172	// update TLB for a PTE2
3173	if ( r_dcache_tlb_ins.read() )
3174	{
3175	r_itlb.write( false, // 4K page
3176	pte_flags,
3177	pte_ppn,
3178	r_dcache_tlb_vaddr.read(),
3179	r_dcache_tlb_way.read(),
3180	r_dcache_tlb_set.read(),
3181	nline );
3182	#ifdef INSTRUMENTATION
3183	m_cpt_itlb_write++;
3184	#endif
3185	}
3186	else
3187	{
3188	r_dtlb.write( false, // 4K page
3189	pte_flags,
3190	pte_ppn,
3191	r_dcache_tlb_vaddr.read(),
3192	r_dcache_tlb_way.read(),
3193	r_dcache_tlb_set.read(),
3194	nline );
3195	#ifdef INSTRUMENTATION
3196	m_cpt_dtlb_write++;
3197	#endif
3198	}
3199
3200	#if DEBUG_DCACHE
3201	if ( m_debug_dcache_fsm )
3202	{
3203	if ( r_dcache_tlb_ins.read() )
3204	{
3205	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3206	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3207	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3208	r_itlb.printTrace();
3209	}
3210	else
3211	{
3212	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3213	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3214	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3215	r_dtlb.printTrace();
3216	}
3217	}
3218	#endif
3219	// next state
3220	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3221	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3222	break;
3223	}
3224	////////////////////////
3225	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3226	// request a SC transaction to CMD FSM
3227	{
3228	#if DEBUG_DCACHE
3229	if ( m_debug_dcache_fsm )
3230	{
3231	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3232	}
3233	#endif
3234	r_dcache.write(r_dcache_tlb_cache_way.read(),
3235	r_dcache_tlb_cache_set.read(),
3236	r_dcache_tlb_cache_word.read(),
3237	r_dcache_tlb_pte_flags.read());
3238	#ifdef INSTRUMENTATION
3239	m_cpt_dcache_data_write++;
3240	#endif
3241	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3242	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3243	r_dcache_vci_sc_req = true;
3244	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3245	break;
3246	}
3247	////////////////////////
3248	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3249	// We consume the response in rsp FIFO,
3250	// and exit the sub-fsm, but we don't
3251	// analyse the response, because we don't
3252	// care if the L/R bit update is not done.
3253	// We must take the coherence requests because
3254	// there is a risk of dead-lock
3255
3256	{
3257	// external coherence request
3258	if ( r_tgt_dcache_req )
3259	{
3260	r_dcache_fsm = DCACHE_CC_CHECK;
3261	r_dcache_fsm_save = r_dcache_fsm;
3262	break;
3263	}
3264
3265	if ( r_vci_rsp_data_error.read() ) // bus error
3266	{
3267	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3268	std::cout << "This should not happen in this state" << std::endl;
3269	exit(0);
3270	}
3271	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3272	{
3273	#if DEBUG_DCACHE
3274	if ( m_debug_dcache_fsm )
3275	{
3276	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3277	}
3278	#endif
3279	vci_rsp_fifo_dcache_get = true;
3280	r_dcache_fsm = DCACHE_TLB_RETURN;
3281	}
3282	break;
3283	}
3284	///////////////////////
3285	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3286	{
3287	#if DEBUG_DCACHE
3288	if ( m_debug_dcache_fsm )
3289	{
3290	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3291	}
3292	#endif
3293	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3294	r_dcache_fsm = DCACHE_IDLE;
3295	break;
3296	}
3297	///////////////////////
3298	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3299	{
3300	if ( not r_dcache_xtn_req.read() )
3301	{
3302	r_dtlb.flush();
3303	r_dcache_fsm = DCACHE_IDLE;
3304	m_drsp.valid = true;
3305	}
3306	break;
3307	}
3308	/////////////////////
3309	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3310	// The coherence request must be taken
3311	// as there is a risk of dead-lock
3312	{
3313	// external coherence request
3314	if ( r_tgt_dcache_req.read() )
3315	{
3316	r_dcache_fsm = DCACHE_CC_CHECK;
3317	r_dcache_fsm_save = DCACHE_XTN_SYNC;
3318	}
3319
3320	if ( r_wbuf.empty() )
3321	{
3322	m_drsp.valid = true;
3323	r_dcache_fsm = DCACHE_IDLE;
3324	}
3325	break;
3326	}
3327	////////////////////////
3328	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3329	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3330	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3331	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3332	{
3333	// external coherence request
3334	if ( r_tgt_dcache_req )
3335	{
3336	r_dcache_fsm = DCACHE_CC_CHECK;
3337	r_dcache_fsm_save = r_dcache_fsm;
3338	break;
3339	}
3340
3341	// itlb miss request
3342	if ( r_icache_tlb_miss_req.read() )
3343	{
3344	r_dcache_tlb_ins = true;
3345	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3346	r_dcache_fsm = DCACHE_TLB_MISS;
3347	break;
3348	}
3349
3350	// test if XTN request to icache completed
3351	if ( not r_dcache_xtn_req.read() )
3352	{
3353	r_dcache_fsm = DCACHE_IDLE;
3354	m_drsp.valid = true;
3355	}
3356	break;
3357	}
3358	/////////////////////////
3359	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3360	// the r_dcache_flush counter as a slot counter.
3361	// We loop in this state until all slots have been visited.
3362	// A cleanup request is generated for each valid line
3363	// and we are blocked until the previous cleanup is completed
3364	// Finally, both the itlb and dtlb are reset, because
3365	// all TLB entries (including global entries) must be invalidated.
3366	{
3367	if ( not r_dcache_cleanup_req )
3368	{
3369	paddr_t nline;
3370	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3371	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3372
3373	bool cleanup_req = r_dcache.inval( way,
3374	set,
3375	&nline );
3376	if ( cleanup_req )
3377	{
3378	r_dcache_cleanup_req = true;
3379	r_dcache_cleanup_line = nline;
3380	}
3381
3382	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3383
3384	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot
3385	{
3386	r_dtlb.reset(); // global entries are invalidated
3387	r_itlb.reset(); // global entries are invalidated
3388	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
3389	{
3390	r_dcache_in_itlb[line] = false;
3391	r_dcache_in_dtlb[line] = false;
3392	}
3393	r_dcache_fsm = DCACHE_IDLE;
3394	m_drsp.valid = true;
3395	}
3396	}
3397	break;
3398	}
3399	/////////////////////////
3400	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3401	{
3402	r_dtlb.inval(r_dcache_p0_wdata.read());
3403	r_dcache_fsm = DCACHE_IDLE;
3404	m_drsp.valid = true;
3405	break;
3406	}
3407	////////////////////////////
3408	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3409	// requires 3 cycles: access tlb, read cache, inval cache
3410	// we compute the physical address in this state
3411	{
3412	paddr_t paddr;
3413	bool hit;
3414
3415	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3416	{
3417	#ifdef INSTRUMENTATION
3418	m_cpt_dtlb_read++;
3419	#endif
3420	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3421	&paddr );
3422	}
3423	else // dtlb not activated
3424	{
3425	paddr = (paddr_t)r_dcache_p0_wdata.read();
3426	hit = true;
3427	}
3428
3429	if ( hit ) // tlb hit
3430	{
3431	r_dcache_p0_paddr = paddr;
3432	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3433	}
3434	else // tlb miss
3435	{
3436	#ifdef INSTRUMENTATION
3437	m_cpt_dtlb_miss++;
3438	#endif
3439	r_dcache_tlb_ins = false; // dtlb
3440	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3441	r_dcache_fsm = DCACHE_TLB_MISS;
3442	}
3443	break;
3444	}
3445	////////////////////////////
3446	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3447	// requires 2 cycles: read cache / inval cache
3448	// In this state we read dcache.
3449	{
3450	uint32_t data;
3451	size_t way;
3452	size_t set;
3453	size_t word;
3454	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3455	&data,
3456	&way,
3457	&set,
3458	&word );
3459	#ifdef INSTRUMENTATION
3460	m_cpt_dcache_data_read++;
3461	m_cpt_dcache_dir_read++;
3462	#endif
3463	if ( hit ) // inval to be done
3464	{
3465	r_dcache_xtn_way = way;
3466	r_dcache_xtn_set = set;
3467	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3468	}
3469	else // miss : nothing to do
3470	{
3471	r_dcache_fsm = DCACHE_IDLE;
3472	m_drsp.valid = true;
3473	}
3474	break;
3475	}
3476	////////////////////////////
3477	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line & cleanup
3478	// Blocked if previous cleanup not completed
3479	// Test if itlb or dtlb inval is required
3480	{
3481	if ( not r_dcache_cleanup_req.read() )
3482	{
3483	paddr_t nline;
3484	size_t way = r_dcache_xtn_way.read();
3485	size_t set = r_dcache_xtn_set.read();
3486	bool inval_itlb = false;
3487	bool inval_dtlb = false;
3488
3489	r_icache.inval( way,
3490	set,
3491	&nline );
3492
3493	// request cleanup
3494	r_dcache_cleanup_req = true;
3495	r_dcache_cleanup_line = nline;
3496
3497	// possible itlb & dtlb invalidate requests
3498
3499	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
3500	{
3501	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3502	inval_dtlb = true;
3503	}
3504	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
3505	{
3506	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3507	inval_itlb = true;
3508	}
3509
3510	// no valid response until itlb & dtlb invalidated
3511	if ( inval_itlb or inval_dtlb )
3512	{
3513	r_dcache_itlb_inval_req = inval_itlb;
3514	r_dcache_dtlb_inval_req = inval_dtlb;
3515	r_dcache_tlb_inval_line = nline;
3516	r_dcache_tlb_inval_count = 0;
3517	r_dcache_fsm_save = DCACHE_XTN_DC_INVAL_END;
3518	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3519	}
3520	else
3521	{
3522	r_dcache_fsm = DCACHE_IDLE;
3523	m_drsp.valid = true;
3524	}
3525	}
3526	break;
3527	}
3528	//////////////////////////////
3529	case DCACHE_XTN_DC_INVAL_END: // waiting completion of itlb and dtlb invalidate
3530	{
3531	r_dcache_fsm = DCACHE_IDLE;
3532	m_drsp.valid = true;
3533	break;
3534	}
3535	////////////////////////
3536	case DCACHE_MISS_VICTIM: // Selects a victim line
3537	// Set the r_dcache_cleanup_req flip-flop
3538	// when the selected slot is not empty
3539	{
3540	bool valid;
3541	size_t way;
3542	size_t set;
3543	paddr_t victim;
3544
3545	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3546	&victim,
3547	&way,
3548	&set );
3549	r_dcache_miss_way = way;
3550	r_dcache_miss_set = set;
3551
3552	if ( valid )
3553	{
3554	r_dcache_cleanup_req = true;
3555	r_dcache_cleanup_line = victim;
3556	r_dcache_fsm = DCACHE_MISS_INVAL;
3557	}
3558	else
3559	{
3560	r_dcache_fsm = DCACHE_MISS_WAIT;
3561	}
3562
3563	#if DEBUG_DCACHE
3564	if ( m_debug_dcache_fsm )
3565	{
3566	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:"
3567	<< " / way = " << way
3568	<< " / set = " << set
3569	<< " / valid = " << valid
3570	<< " / line = " << std::hex << victim << std::endl;
3571	}
3572	#endif
3573	break;
3574	}
3575	///////////////////////
3576	case DCACHE_MISS_INVAL: // invalidate the victim line
3577	// and possibly request itlb or dtlb invalidate
3578	{
3579	paddr_t nline;
3580	size_t way = r_dcache_miss_way.read();
3581	size_t set = r_dcache_miss_set.read();
3582
3583	r_dcache.inval( way,
3584	set,
3585	&nline );
3586
3587	// if itlb & dtlb invalidate are required
3588	// the miss response is not handled before invalidate completed
3589	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3590	( r_dcache_in_itlb[way*m_dcache_sets+set] or
3591	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
3592	{
3593	r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3594	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
3595	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3596	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
3597	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3598	r_dcache_fsm = DCACHE_MISS_INVAL_WAIT;
3599	}
3600	else
3601	{
3602	r_dcache_fsm = DCACHE_MISS_WAIT;
3603	}
3604	break;
3605	}
3606	////////////////////////////
3607	case DCACHE_MISS_INVAL_WAIT: // waiting completion of itlb / dtlb invalidate
3608	{
3609	if ( (not r_dcache_itlb_inval_req.read()) or (not r_dcache_dtlb_inval_req.read()) )
3610	{
3611	r_dcache_fsm = DCACHE_MISS_WAIT;
3612	}
3613	break;
3614	}
3615	//////////////////////
3616	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3617	// This state is in charge of error signaling
3618	// There is 5 types of error depending on the requester
3619	{
3620	// external coherence request
3621	if ( r_tgt_dcache_req )
3622	{
3623	r_dcache_fsm = DCACHE_CC_CHECK;
3624	r_dcache_fsm_save = r_dcache_fsm;
3625	break;
3626	}
3627
3628	if ( r_vci_rsp_data_error.read() ) // bus error
3629	{
3630	switch ( r_dcache_miss_type.read() )
3631	{
3632	case PROC_MISS:
3633	{
3634	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3635	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3636	m_drsp.valid = true;
3637	m_drsp.error = true;
3638	r_dcache_fsm = DCACHE_IDLE;
3639	break;
3640	}
3641	case PTE1_MISS:
3642	{
3643	if ( r_dcache_tlb_ins.read() )
3644	{
3645	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3646	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3647	r_icache_tlb_miss_req = false;
3648	r_icache_tlb_rsp_error = true;
3649	}
3650	else
3651	{
3652	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3653	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3654	m_drsp.valid = true;
3655	m_drsp.error = true;
3656	}
3657	r_dcache_fsm = DCACHE_IDLE;
3658	break;
3659	}
3660	case PTE2_MISS:
3661	{
3662	if ( r_dcache_tlb_ins.read() )
3663	{
3664	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3665	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3666	r_icache_tlb_miss_req = false;
3667	r_icache_tlb_rsp_error = true;
3668	}
3669	else
3670	{
3671	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3672	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3673	m_drsp.valid = true;
3674	m_drsp.error = true;
3675	}
3676	r_dcache_fsm = DCACHE_IDLE;
3677	break;
3678	}
3679	} // end switch type
3680	r_vci_rsp_data_error = false;
3681	}
3682	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3683	{
3684	r_dcache_miss_word = 0;
3685	r_dcache_fsm = DCACHE_MISS_UPDT;
3686	}
3687	break;
3688	}
3689	//////////////////////
3690	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3691	// returns the response depending on the miss type
3692	{
3693	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3694	{
3695	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3696	// pop the FIFO, without cache update
3697	// send a cleanup for the missing line
3698	// if the previous cleanup is completed
3699	{
3700	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3701	{
3702	vci_rsp_fifo_dcache_get = true;
3703	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3704	}
3705	else // last word
3706	{
3707	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3708	{
3709	vci_rsp_fifo_dcache_get = true;
3710	r_dcache_cleanup_req = true;
3711	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3712	(uint32_log2(m_dcache_words)+2);
3713	r_dcache_miss_inval = false;
3714	r_dcache_fsm = DCACHE_IDLE;
3715	}
3716	}
3717	}
3718	else // No matching coherence request
3719	// pop the FIFO and update the cache
3720	// update the directory at the last word
3721	// send a response to ICACHE FSM
3722	// in case of itlb miss
3723	{
3724
3725	#ifdef INSTRUMENTATION
3726	m_cpt_dcache_data_write++;
3727	#endif
3728	r_dcache.write( r_dcache_miss_way.read(),
3729	r_dcache_miss_set.read(),
3730	r_dcache_miss_word.read(),
3731	r_vci_rsp_fifo_dcache.read());
3732
3733	vci_rsp_fifo_dcache_get = true;
3734	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3735
3736	// if last word, update directory, set in_itlb & in_dtlb bits
3737	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3738	{
3739
3740	#ifdef INSTRUMENTATION
3741	m_cpt_dcache_dir_write++;
3742	#endif
3743	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3744	r_dcache_miss_way.read(),
3745	r_dcache_miss_set.read() );
3746
3747	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3748	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3749	else r_dcache_fsm = DCACHE_IDLE;
3750	}
3751	}
3752
3753	#if DEBUG_DCACHE
3754	if ( m_debug_dcache_fsm )
3755	{
3756	if ( r_dcache_miss_inval.read() )
3757	{
3758	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3759	{
3760	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3761	<< " pop the FIFO, don't update the cache" << std::endl;
3762	}
3763	else
3764	{
3765	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3766	<< " last word : send a cleanup request " << std::endl;
3767	}
3768	}
3769	else
3770	{
3771	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3772	<< " address = " << r_dcache_vci_paddr.read()
3773	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3774	<< " / way = " << r_dcache_miss_way.read()
3775	<< " / set = " << r_dcache_miss_set.read()
3776	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3777	}
3778	}
3779	#endif
3780
3781	} // end if rok
3782	break;
3783	}
3784	/////////////////////
3785	case DCACHE_UNC_WAIT:
3786	{
3787	// external coherence request
3788	if ( r_tgt_dcache_req.read() )
3789	{
3790	r_dcache_fsm = DCACHE_CC_CHECK;
3791	r_dcache_fsm_save = r_dcache_fsm;
3792	break;
3793	}
3794
3795	if ( r_vci_rsp_data_error.read() ) // bus error
3796	{
3797	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3798	r_mmu_dbvar = m_dreq.addr;
3799	r_vci_rsp_data_error = false;
3800	m_drsp.error = true;
3801	m_drsp.valid = true;
3802	r_dcache_fsm = DCACHE_IDLE;
3803	break;
3804	}
3805	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3806	{
3807	vci_rsp_fifo_dcache_get = true;
3808	r_dcache_fsm = DCACHE_IDLE;
3809	// we acknowledge the processor request if it has not been modified
3810	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3811	{
3812	m_drsp.valid = true;
3813	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3814	}
3815	}
3816	break;
3817	}
3818	////////////////////
3819	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3820	// a long write is launched if dirty bit must be set
3821	{
3822	// external coherence request
3823	if ( r_tgt_dcache_req.read() )
3824	{
3825	r_dcache_fsm = DCACHE_CC_CHECK;
3826	r_dcache_fsm_save = r_dcache_fsm;
3827	break;
3828	}
3829
3830	if ( r_vci_rsp_data_error.read() ) // bus error
3831	{
3832	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3833	r_mmu_dbvar = m_dreq.addr;
3834	r_vci_rsp_data_error = false;
3835	m_drsp.error = true;
3836	m_drsp.valid = true;
3837	r_dcache_fsm = DCACHE_IDLE;
3838	break;
3839	}
3840	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3841	{
3842	bool sc_success = (r_vci_rsp_fifo_dcache.read() == 0);
3843	vci_rsp_fifo_dcache_get = true;
3844
3845	if ( sc_success and not r_dcache_p0_tlb_dirty.read() ) // Dirty bit must be set
3846	{
3847	// The PTE physical address is the concatenation of the nline value (from dtlb),
3848	// with the word index (obtained from the proper bits of the virtual address)
3849	if ( r_dcache_p0_tlb_big.read() ) // PTE1
3850	{
3851	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p0_tlb_nline.read()*(m_dcache_words<<2)) \|
3852	(paddr_t)((r_dcache_p0_vaddr.read()>>19) & 0x3c);
3853	}
3854	else // PTE2
3855	{
3856	r_dcache_p2_pte_paddr = (paddr_t)(r_dcache_p0_tlb_nline.read()*(m_dcache_words<<2)) \|
3857	(paddr_t)((r_dcache_p0_vaddr.read()>>9) & 0x38);
3858	}
3859	r_dcache_p2_sc_success = sc_success;
3860	r_dcache_p2_way = r_dcache_p0_tlb_way.read();
3861	r_dcache_p2_set = r_dcache_p0_tlb_set.read();
3862	r_dcache_fsm = DCACHE_DIRTY_TLB_SET;
3863
3864	}
3865	else
3866	{
3867	m_drsp.valid = true;
3868	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3869	r_dcache_fsm = DCACHE_IDLE;
3870	}
3871	}
3872	break;
3873	}
3874	//////////////////////////
3875	case DCACHE_DIRTY_TLB_SET: // Enter this sub_fsm in case of long write:
3876	// - in case of WRITE request (r_dcache_p2_type_sc == false)
3877	// - in case of SC request (r_dcache_p2_type_sc == true)
3878	// Inputs arguments are:
3879	// - r_dcache_p2_way,
3880	// - r_dcache_p2_set,
3881	// - r_dcache_p2_pte_paddr,
3882	// - r_dcache_p2_type_sc,
3883	// - r_dcache_p2_sc_success,
3884	// In this first state, we set PTE dirty bit in dtlb
3885	// and get PTE in dcache
3886	{
3887	// set dirty bit in dtlb
3888	r_dtlb.set_dirty( r_dcache_p2_way.read(),
3889	r_dcache_p2_set.read() );
3890
3891	// get PTE in dcache
3892	uint32_t pte = 0;
3893	size_t way;
3894	size_t set;
3895	size_t word;
3896	bool hit = r_dcache.read( r_dcache_p2_pte_paddr.read(),
3897	&pte,
3898	&way,
3899	&set,
3900	&word );
3901	#ifdef INSTRUMENTATION
3902	m_cpt_dcache_data_read++;
3903	m_cpt_dcache_dir_read++;
3904	#endif;
3905
3906	#if DEBUG_DCACHE
3907	if ( m_debug_dcache_fsm )
3908	{
3909	std::cout << " <PROC.DCACHE_DIRTY_TLB_SET> Set dirty bit in dtlb:" << std::dec
3910	<< " / tlb_set = " << r_dcache_p2_set.read()
3911	<< " / tlb_way = " << r_dcache_p2_way.read() << std::endl;
3912	r_dtlb.printTrace();
3913	std::cout << " and get PTE in dcache" << std::hex
3914	<< " / PADDR = " << r_dcache_p2_pte_paddr.read()
3915	<< " / PTE = " << pte << std::dec
3916	<< " / set = " << set
3917	<< " / way = " << way << std::endl;
3918	}
3919	#endif
3920	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3921
3922	r_dcache_p2_way = way; // register pte way in dcache
3923	r_dcache_p2_set = set; // register pte set in dcache;
3924	r_dcache_p2_word = word; // register pte word in dcache;
3925	r_dcache_p2_pte_value = pte; // register pte value
3926	r_dcache_fsm = DCACHE_DIRTY_CACHE_SET;
3927	break;
3928	}
3929	////////////////////////////
3930	case DCACHE_DIRTY_CACHE_SET: // set PTE dirty bit in dcache
3931	// request SC tranansaction to CMD FSM
3932	{
3933	// set PTE dirty bit in dcache
3934	r_dcache.write( r_dcache_p2_way.read(),
3935	r_dcache_p2_set.read(),
3936	r_dcache_p2_word.read(),
3937	r_dcache_p2_pte_value.read() \| PTE_D_MASK,
3938	0xF );
3939
3940	#ifdef INSTRUMENTATION
3941	m_cpt_dcache_data_write++;
3942	#endif
3943	// request sc transaction to CMD_FSM
3944	r_dcache_vci_sc_req = true;
3945	r_dcache_vci_paddr = r_dcache_p2_pte_paddr.read();
3946	r_dcache_vci_sc_old = r_dcache_p2_pte_value.read();
3947	r_dcache_vci_sc_new = r_dcache_p2_pte_value.read() \| PTE_D_MASK;
3948	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3949
3950	#if DEBUG_DCACHE
3951	if ( m_debug_dcache_fsm )
3952	{
3953	std::cout << " <PROC.DCACHE_DIRTY_CACHE_SET> Set PTE dirty bit in dcache"
3954	<< " / way = " << r_dcache_p2_way.read()
3955	<< " / set = " << r_dcache_p2_set.read()
3956	<< " / word = " << r_dcache_p2_word.read() << std::endl;
3957	std::cout << " and request SC transaction for dirty bit update"
3958	<< " / address = " << r_dcache_p2_pte_paddr.read()
3959	<< " / old = " << r_dcache_p2_pte_value.read()
3960	<< " / new = " << (r_dcache_p2_pte_value.read() \| PTE_D_MASK) << std::endl;
3961	}
3962	#endif
3963	break;
3964	}
3965	//////////////////////////
3966	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3967	// if atomic, write completed : return to IDLE state
3968	// else, read the mofified PTE to retry the SC
3969	{
3970	// external coherence request
3971	if ( r_tgt_dcache_req )
3972	{
3973	r_dcache_fsm = DCACHE_CC_CHECK;
3974	r_dcache_fsm_save = r_dcache_fsm;
3975	break;
3976	}
3977
3978	if ( r_vci_rsp_data_error.read() ) // bus error
3979	{
3980	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3981	std::cout << "This should not happen in this state" << std::endl;
3982	exit(0);
3983	}
3984	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3985	{
3986	vci_rsp_fifo_dcache_get = true;
3987	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
3988	{
3989	if ( r_dcache_p2_type_sc.read() ) // long write for SC request
3990	{
3991	m_drsp.valid = true;
3992	m_drsp.rdata = ( r_dcache_p2_sc_success.read() ? 0 : 1 );
3993	r_dcache_fsm = DCACHE_IDLE;
3994	}
3995	else // long write for WRITE request
3996	{
3997	r_dcache_fsm = DCACHE_IDLE;
3998	}
3999	}
4000	else // retry if dirty bit update failed
4001	{
4002	r_dcache_vci_paddr = r_dcache_p2_pte_paddr;
4003	r_dcache_vci_unc_req = true;
4004	r_dcache_vci_unc_be = 0xF;
4005	r_dcache_fsm = DCACHE_DIRTY_UNC_WAIT;
4006	}
4007	}
4008	break;
4009	}
4010	///////////////////////////
4011	case DCACHE_DIRTY_UNC_WAIT: // wait completion of PTE read
4012	// and retry a SC request to
4013	// set the dirty bit in the PTE
4014	{
4015	// external coherence request
4016	if ( r_tgt_dcache_req )
4017	{
4018	r_dcache_fsm = DCACHE_CC_CHECK;
4019	r_dcache_fsm_save = r_dcache_fsm;
4020	break;
4021	}
4022
4023	if ( r_vci_rsp_data_error.read() ) // bus error
4024	{
4025	std::cout << "BUS ERROR in DCACHE_DIRTY_UNC_WAIT state" << std::endl;
4026	std::cout << "This should not happen in this state" << std::endl;
4027	exit(0);
4028	}
4029	if ( r_vci_rsp_fifo_dcache.rok() ) // PTE available
4030	{
4031	r_dcache_vci_sc_req = true;
4032	r_dcache_vci_sc_old = r_vci_rsp_fifo_dcache.read();
4033	r_dcache_vci_sc_new = r_vci_rsp_fifo_dcache.read() \| PTE_D_MASK;
4034	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
4035	}
4036	break;
4037	}
4038	/////////////////////
4039	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4040	// handling coherence requests.
4041	// If there is a matching pending miss on the modified cache
4042	// line this is signaled in the r_dcache_miss inval flip-flop.
4043	// If the updated (or invalidated) cache line has copies in TLBs
4044	// these TLB copies are invalidated.
4045	// The return state is defined in r_dcache_fsm_save
4046	{
4047	paddr_t paddr = r_tgt_paddr.read();
4048	paddr_t mask = ~((m_dcache_words<<2)-1);
4049
4050
4051	if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and
4052	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4053	{
4054	r_dcache_miss_inval = true; // signaling the match
4055	r_tgt_dcache_req = false; // coherence request completed
4056	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4057	r_dcache_fsm = r_dcache_fsm_save;
4058
4059	#if DEBUG_DCACHE
4060	if ( m_debug_dcache_fsm )
4061	{
4062	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4063	<< " address = " << std::hex << paddr << std::endl;
4064	}
4065	#endif
4066
4067	}
4068	else // no match
4069	{
4070	uint32_t rdata;
4071	size_t way;
4072	size_t set;
4073	size_t word;
4074
4075	bool hit = r_dcache.read(paddr,
4076	&rdata, // unused
4077	&way,
4078	&set,
4079	&word); // unused
4080	#ifdef INSTRUMENTATION
4081	m_cpt_dcache_data_read++;
4082	m_cpt_dcache_dir_read++;
4083	#endif
4084	r_dcache_cc_way = way;
4085	r_dcache_cc_set = set;
4086
4087	if ( hit and r_tgt_update.read() ) // hit update
4088	{
4089	r_dcache_fsm = DCACHE_CC_UPDT;
4090	r_dcache_cc_word = r_tgt_word_min.read();
4091	}
4092	else if ( hit and not r_tgt_update.read() ) // hit inval
4093	{
4094	r_dcache_fsm = DCACHE_CC_INVAL;
4095	}
4096	else // miss can happen
4097	{
4098	r_tgt_dcache_req = false;
4099	r_tgt_dcache_rsp = r_tgt_update.read();
4100	r_dcache_fsm = r_dcache_fsm_save.read();
4101	}
4102
4103	#if DEBUG_DCACHE
4104	if ( m_debug_dcache_fsm )
4105	{
4106
4107	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4108	<< " address = " << std::hex << paddr << std::dec;
4109	if ( hit )
4110	{
4111	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4112	}
4113	else
4114	{
4115	std::cout << " / MISS" << std::endl;
4116	}
4117	}
4118	#endif
4119
4120	}
4121	break;
4122	}
4123	/////////////////////
4124	case DCACHE_CC_INVAL: // invalidate one cache line
4125	// and test possible copies in TLBs
4126	{
4127	paddr_t nline;
4128	size_t way = r_dcache_cc_way.read();
4129	size_t set = r_dcache_cc_set.read();
4130	bool inval_itlb = false;
4131	bool inval_dtlb = false;
4132
4133	r_dcache.inval( way,
4134	set,
4135	&nline );
4136
4137	// possible itlb & dtlb invalidate requests
4138
4139	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
4140	{
4141	r_dtlb.reset_bypass(nline);
4142	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4143	inval_dtlb = true;
4144	}
4145	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[m_dcache_sets*way+set] )
4146	{
4147	r_itlb.reset_bypass(nline);
4148	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4149	inval_itlb = true;
4150	}
4151
4152	if ( inval_itlb or inval_dtlb ) // no valid response until itlb / dtlb invalidated
4153	{
4154	r_dcache_itlb_inval_req = inval_itlb;
4155	r_dcache_dtlb_inval_req = inval_dtlb;
4156	r_dcache_tlb_inval_line = nline;
4157	r_dcache_tlb_inval_count = 0;
4158	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4159	}
4160	else
4161	{
4162	r_tgt_dcache_rsp = true;
4163	r_tgt_dcache_req = false;
4164	r_dcache_fsm = r_dcache_fsm_save.read();
4165	}
4166
4167	#if DEBUG_DCACHE
4168	if ( m_debug_dcache_fsm )
4169	{
4170	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line :" << std::dec
4171	<< " way = " << way
4172	<< " / set = " << set;
4173	if ( inval_itlb ) std::cout << " / itlb inval required";
4174	if ( inval_dtlb ) std::cout << " / dtlb inval required";
4175	std::cout << std::endl;
4176	}
4177	#endif
4178
4179	break;
4180	}
4181	///////////////////
4182	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4183	// and test possible copies in TLBs
4184	{
4185	size_t word = r_dcache_cc_word.read();
4186	size_t way = r_dcache_cc_way.read();
4187	size_t set = r_dcache_cc_set.read();
4188	bool inval_itlb = false;
4189	bool inval_dtlb = false;
4190	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4191
4192	r_dcache.write( way,
4193	set,
4194	word,
4195	r_tgt_buf[word],
4196	r_tgt_be[word] );
4197	#ifdef INSTRUMENTATION
4198	m_cpt_dcache_data_write++;
4199	#endif
4200	r_dcache_cc_word = word + 1;
4201
4202	if ( word == r_tgt_word_max.read() ) // last word
4203	{
4204	// possible itlb & dtlb invalidate requests
4205
4206	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and r_dcache_in_dtlb[way*m_dcache_sets+set] )
4207	{
4208	r_dtlb.reset_bypass(nline);
4209	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4210	inval_dtlb = true;
4211	}
4212	if ( (r_mmu_mode.read() & INS_TLB_MASK) and r_dcache_in_itlb[way*m_dcache_sets+set] )
4213	{
4214	r_itlb.reset_bypass(nline);
4215	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4216	inval_itlb = true;
4217	}
4218
4219	if ( inval_itlb or inval_dtlb ) // no valid response until itlb / dtlb invalidated
4220	{
4221	r_dcache_itlb_inval_req = inval_itlb;
4222	r_dcache_dtlb_inval_req = inval_dtlb;
4223	r_dcache_tlb_inval_line = nline;
4224	r_dcache_tlb_inval_count = 0;
4225	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4226	}
4227	else
4228	{
4229	r_tgt_dcache_rsp = true;
4230	r_tgt_dcache_req = false;
4231	r_dcache_fsm = r_dcache_fsm_save.read();
4232	}
4233	}
4234
4235	#if DEBUG_DCACHE
4236	if ( m_debug_dcache_fsm )
4237	{
4238	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec
4239	<< " way = " << way
4240	<< " / set = " << set
4241	<< " / word = " << word
4242	<< " / value = " << std::hex << r_tgt_buf[word];
4243	if ( inval_itlb ) std::cout << " / itlb inval required";
4244	if ( inval_dtlb ) std::cout << " / dtlb inval required";
4245	std::cout << std::endl;
4246	}
4247	#endif
4248
4249	break;
4250	}
4251	///////////////////////////
4252	case DCACHE_INVAL_TLB_SCAN: // scan sequencially all TLB entries for both ITLB & DTLB
4253	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4254	// and (m_itlb_ways == m_dtlb_ways)
4255	// Caution : we enter this state when a DCACHE line is modified,
4256	// and there is a copy in itlb or dtlb.
4257	// It can be caused by a coherence transaction, a XTN inval
4258	// or a WRITE hit. Input arguments are:
4259	// - r_dcache_tlb_inval_line
4260	// - r_dcache_tlb_inval_count
4261	// - r_dcache_itlb_inval_req
4262	// - r_dcache_dtlb_inval_req
4263	// - r_dcache_fsm_save
4264	{
4265	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4266	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4267	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4268
4269	if ( r_dcache_itlb_inval_req.read() )
4270	{
4271	bool ok = r_itlb.inval( line,
4272	way,
4273	set );
4274	#if DEBUG_DCACHE
4275	if ( m_debug_dcache_fsm and ok )
4276	{
4277	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4278	<< " line = " << line << std::dec
4279	<< " / set = " << set
4280	<< " / way = " << way << std::endl;
4281	r_itlb.printTrace();
4282	}
4283	#endif
4284	}
4285
4286	if ( r_dcache_dtlb_inval_req.read() )
4287	{
4288	bool ok = r_dtlb.inval( line,
4289	way,
4290	set );
4291	#if DEBUG_DCACHE
4292	if ( m_debug_dcache_fsm and ok )
4293	{
4294	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4295	<< " line = " << line << std::dec
4296	<< " / set = " << set
4297	<< " / way = " << way << std::endl;
4298	r_dtlb.printTrace();
4299	}
4300	#endif
4301	}
4302
4303	// return to the calling state when TLB inval completed
4304	if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) )
4305	{
4306	if ( r_dcache_fsm_save.read() != DCACHE_XTN_DC_INVAL_END ) // not an XTN inval
4307	{
4308	r_tgt_dcache_rsp = true;
4309	r_tgt_dcache_req = false;
4310	}
4311	r_dcache_dtlb_inval_req = false;
4312	r_dcache_itlb_inval_req = false;
4313	r_dcache_fsm = r_dcache_fsm_save.read();
4314	}
4315	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4316	}
4317	} // end switch r_dcache_fsm
4318
4319	///////////////// wbuf update //////////////////////////////////////////////////////
4320	r_wbuf.update();
4321
4322	//////////////// test processor frozen /////////////////////////////////////////////
4323	// The simulation exit if the number of consecutive frozen cycles
4324	// is larger than the m_max_frozen_cycles (constructor parameter)
4325	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4326	{
4327	m_cpt_frz_cycles++; // used for instrumentation
4328	m_cpt_stop_simulation++; // used for debug
4329	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4330	{
4331	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4332	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4333	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4334	<< std::endl;
4335	exit(1);
4336	}
4337	}
4338	else
4339	{
4340	m_cpt_stop_simulation = 0;
4341	}
4342
4343	/////////// execute one iss cycle /////////////////////////////////
4344	{
4345	uint32_t it = 0;
4346	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4347	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4348	}
4349
4350	////////////////////////////////////////////////////////////////////////////
4351	// The VCI_CMD FSM controls the following ressources:
4352	// - r_vci_cmd_fsm
4353	// - r_vci_cmd_min
4354	// - r_vci_cmd_max
4355	// - r_vci_cmd_cpt
4356	// - r_vci_cmd_imiss_prio
4357	// - wbuf (reset)
4358	// - r_icache_miss_req (reset)
4359	// - r_icache_unc_req (reset)
4360	// - r_dcache_vci_miss_req (reset)
4361	// - r_dcache_vci_unc_req (reset)
4362	// - r_dcache_vci_sc_req (reset)
4363	//
4364	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4365	// There is 6 request types, with the following priorities :
4366	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4367	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4368	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4369	// 4 - Instruction Uncachable : r_icache_unc_req
4370	// 5 - Data Write : r_wbuf.rok()
4371	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4372	//
4373	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4374	// and the VCI_RSP_FSM are fully desynchronized.
4375	//
4376	// VCI formats:
4377	// According to the VCI advanced specification, all read requests packets
4378	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4379	// are one word packets.
4380	// For write burst packets, all words are in the same cache line,
4381	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4382	// The sc command packet implements actually a compare-and-swap mechanism
4383	// and the packet contains two flits.
4384	////////////////////////////////////////////////////////////////////////////////////
4385
4386	switch ( r_vci_cmd_fsm.read() )
4387	{
4388	//////////////
4389	case CMD_IDLE:
4390	{
4391	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4392	// to check a possible pending write on the same cache line.
4393	// As there is only one possible access per cycle to write buffer, we implement
4394	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4395
4396	size_t wbuf_min;
4397	size_t wbuf_max;
4398
4399	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4400	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4401	bool icache_miss_req = r_icache_miss_req.read()
4402	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4403
4404	// 1 - Data Read Miss
4405	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4406	{
4407	r_vci_cmd_fsm = CMD_DATA_MISS;
4408	r_dcache_vci_miss_req = false;
4409	r_vci_cmd_imiss_prio = true;
4410	// m_cpt_dmiss_transaction++;
4411	}
4412	// 2 - Data Read Uncachable
4413	else if ( r_dcache_vci_unc_req.read() )
4414	{
4415	r_vci_cmd_fsm = CMD_DATA_UNC;
4416	r_dcache_vci_unc_req = false;
4417	// m_cpt_dunc_transaction++;
4418	}
4419	// 3 - Instruction Miss
4420	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4421	{
4422	r_vci_cmd_fsm = CMD_INS_MISS;
4423	r_icache_miss_req = false;
4424	r_vci_cmd_imiss_prio = false;
4425	// m_cpt_imiss_transaction++;
4426	}
4427	// 4 - Instruction Uncachable
4428	else if ( r_icache_unc_req.read() )
4429	{
4430	r_vci_cmd_fsm = CMD_INS_UNC;
4431	r_icache_unc_req = false;
4432	// m_cpt_iunc_transaction++;
4433	}
4434	// 5 - Data Write
4435	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4436	{
4437	r_vci_cmd_fsm = CMD_DATA_WRITE;
4438	r_vci_cmd_cpt = wbuf_min;
4439	r_vci_cmd_min = wbuf_min;
4440	r_vci_cmd_max = wbuf_max;
4441	// m_cpt_write_transaction++;
4442	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4443	}
4444	// 6 - Data Store Conditionnal
4445	else if ( r_dcache_vci_sc_req.read() )
4446	{
4447	r_vci_cmd_fsm = CMD_DATA_SC;
4448	r_dcache_vci_sc_req = false;
4449	r_vci_cmd_cpt = 0;
4450	// m_cpt_sc_transaction++;
4451	}
4452	break;
4453	}
4454	////////////////////
4455	case CMD_DATA_WRITE:
4456	{
4457	if ( p_vci_ini_d.cmdack.read() )
4458	{
4459	// m_conso_wbuf_read++;
4460	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4461	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4462	{
4463	r_vci_cmd_fsm = CMD_IDLE ;
4464	r_wbuf.sent() ;
4465	}
4466	}
4467	break;
4468	}
4469	/////////////////
4470	case CMD_DATA_SC:
4471	{
4472	// The SC VCI command contains two flits
4473	if ( p_vci_ini_d.cmdack.read() )
4474	{
4475	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4476	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4477	}
4478	break;
4479	}
4480	//////////////////
4481	case CMD_INS_MISS:
4482	case CMD_INS_UNC:
4483	case CMD_DATA_MISS:
4484	case CMD_DATA_UNC:
4485	{
4486	// all read VCI commands contain one single flit
4487	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4488	break;
4489	}
4490
4491	} // end switch r_vci_cmd_fsm
4492
4493	//////////////////////////////////////////////////////////////////////////
4494	// The VCI_RSP FSM controls the following ressources:
4495	// - r_vci_rsp_fsm:
4496	// - r_vci_rsp_fifo_icache (push)
4497	// - r_vci_rsp_fifo_dcache (push)
4498	// - r_vci_rsp_data_error (set)
4499	// - r_vci_rsp_ins_error (set)
4500	// - r_vci_rsp_cpt
4501	//
4502	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4503	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4504	// to identify the transactions.
4505	//
4506	// VCI vormat:
4507	// This component checks the response packet length and accepts only
4508	// single word packets for write response packets.
4509	//
4510	// Error handling:
4511	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4512	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4513	// flip_flop and the error is signaled by the DCACHE FSM.
4514	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4515	// flip_flop and the error is signaled by the ICACHE FSM.
4516	// In case of Cleanup Error, the simulation stops with an error message...
4517	//////////////////////////////////////////////////////////////////////////
4518
4519	switch ( r_vci_rsp_fsm.read() )
4520	{
4521	//////////////
4522	case RSP_IDLE:
4523	{
4524	if ( p_vci_ini_d.rspval.read() )
4525	{
4526	r_vci_rsp_cpt = 0;
4527
4528	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4529	{
4530	r_vci_rsp_fsm = RSP_DATA_WRITE;
4531	}
4532	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4533	{
4534	r_vci_rsp_fsm = RSP_INS_MISS;
4535	}
4536	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4537	{
4538	r_vci_rsp_fsm = RSP_INS_UNC;
4539	}
4540	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4541	{
4542	r_vci_rsp_fsm = RSP_DATA_MISS;
4543	}
4544	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4545	{
4546	r_vci_rsp_fsm = RSP_DATA_UNC;
4547	}
4548	else
4549	{
4550	assert(false and "Unexpected VCI response");
4551	}
4552	}
4553	break;
4554	}
4555	//////////////////
4556	case RSP_INS_MISS:
4557	{
4558	if ( p_vci_ini_d.rspval.read() )
4559	{
4560	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4561	{
4562	r_vci_rsp_ins_error = true;
4563	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4564	}
4565	else // no error reported
4566	{
4567	if ( r_vci_rsp_fifo_icache.wok() )
4568	{
4569	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4570	"The VCI response packet for instruction miss is too long" );
4571
4572	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4573	vci_rsp_fifo_icache_put = true,
4574	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4575	if ( p_vci_ini_d.reop.read() )
4576	{
4577	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4578	"The VCI response packet for instruction miss is too short");
4579
4580	r_vci_rsp_fsm = RSP_IDLE;
4581	}
4582	}
4583	}
4584	}
4585	break;
4586	}
4587	/////////////////
4588	case RSP_INS_UNC:
4589	{
4590	if (p_vci_ini_d.rspval.read() )
4591	{
4592	assert( p_vci_ini_d.reop.read() and
4593	"illegal VCI response packet for uncachable instruction");
4594
4595	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4596	{
4597	r_vci_rsp_ins_error = true;
4598	r_vci_rsp_fsm = RSP_IDLE;
4599	}
4600	else // no error reported
4601	{
4602	if ( r_vci_rsp_fifo_icache.wok())
4603	{
4604	vci_rsp_fifo_icache_put = true;
4605	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4606	r_vci_rsp_fsm = RSP_IDLE;
4607	}
4608	}
4609	}
4610	break;
4611	}
4612	///////////////////
4613	case RSP_DATA_MISS:
4614	{
4615	if ( p_vci_ini_d.rspval.read() )
4616	{
4617	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4618	{
4619	r_vci_rsp_data_error = true;
4620	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4621	}
4622	else // no error reported
4623	{
4624	if ( r_vci_rsp_fifo_dcache.wok() )
4625	{
4626	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4627	"The VCI response packet for data miss is too long");
4628
4629	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4630	vci_rsp_fifo_dcache_put = true,
4631	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4632	if ( p_vci_ini_d.reop.read() )
4633	{
4634	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4635	"The VCI response packet for data miss is too short");
4636
4637	r_vci_rsp_fsm = RSP_IDLE;
4638	}
4639	}
4640	}
4641	}
4642	break;
4643	}
4644	//////////////////
4645	case RSP_DATA_UNC:
4646	{
4647	if (p_vci_ini_d.rspval.read() )
4648	{
4649	assert( p_vci_ini_d.reop.read() and
4650	"illegal VCI response packet for uncachable read data");
4651
4652	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4653	{
4654	r_vci_rsp_data_error = true;
4655	r_vci_rsp_fsm = RSP_IDLE;
4656	}
4657	else // no error reported
4658	{
4659	if ( r_vci_rsp_fifo_dcache.wok())
4660	{
4661	vci_rsp_fifo_dcache_put = true;
4662	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4663	r_vci_rsp_fsm = RSP_IDLE;
4664	}
4665	}
4666	}
4667	break;
4668	}
4669	////////////////////
4670	case RSP_DATA_WRITE:
4671	{
4672	if (p_vci_ini_d.rspval.read())
4673	{
4674	assert( p_vci_ini_d.reop.read() and
4675	"a VCI response packet must contain one flit for a write transaction");
4676
4677	r_vci_rsp_fsm = RSP_IDLE;
4678	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4679	bool cacheable = r_wbuf.completed(wbuf_index);
4680	if ( not cacheable ) r_dcache_pending_unc_write = false;
4681	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4682	}
4683	break;
4684	}
4685	} // end switch r_vci_rsp_fsm
4686
4687	////////////////////////////////////////////////////////////////////////////////
4688	// The CLEANUP FSM send the cleanup commands on the coherence network,
4689	// and supports simultaneous cleanup transactions, but two simultaneous
4690	// transactions mut address different cache lines.
4691	// Therefore, the line number is registered in an associative
4692	// registration buffer (Content Adressable Memory) by the CLEANUP FSM,
4693	// and the corresponding slot (identified by the VCI TRDID field) is cleared
4694	// when the cleanup transaction response is received.
4695	// It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
4696	// with a round robin priority, and can support up to 4 simultaneous
4697	// cleanup transactions (4 slots in the registration buffer).
4698	// The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
4699	// when the command has been sent.
4700	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4701	// - if data cleanup : TRDID = 2*index + 0
4702	// - if instruction cleanup : TRDID = 2*index + 1
4703	////////////////////////////////////////////////////////////////////////////
4704
4705	switch ( r_cleanup_fsm.read() )
4706	{
4707	///////////////////////
4708	case CLEANUP_DATA_IDLE: // dcache has highest priority
4709	{
4710	size_t index = 0;
4711	bool ok;
4712	if ( r_dcache_cleanup_req.read() ) // dcache request
4713	{
4714	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4715	&index );
4716	if ( ok ) // successful registration
4717	{
4718	r_cleanup_fsm = CLEANUP_DATA_GO;
4719	r_cleanup_trdid = index<<1;
4720	}
4721	}
4722	else if ( r_icache_cleanup_req.read() ) // icache request
4723	{
4724	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4725	&index );
4726	if ( ok ) // successful registration
4727	{
4728	r_cleanup_fsm = CLEANUP_INS_GO;
4729	r_cleanup_trdid = (index<<1) + 1;
4730	}
4731	}
4732	break;
4733	}
4734	//////////////////////
4735	case CLEANUP_INS_IDLE: // icache has highest priority
4736	{
4737	size_t index = 0;
4738	bool ok;
4739	if ( r_icache_cleanup_req.read() ) // icache request
4740	{
4741	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4742	&index );
4743	if ( ok ) // successful registration
4744	{
4745	r_cleanup_fsm = CLEANUP_INS_GO;
4746	r_cleanup_trdid = (index<<1) + 1;
4747	}
4748	}
4749	else if ( r_dcache_cleanup_req.read() ) // dcache request
4750	{
4751	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4752	&index );
4753	if ( ok ) // successful registration
4754	{
4755	r_cleanup_fsm = CLEANUP_DATA_GO;
4756	r_cleanup_trdid = index<<1;
4757	}
4758	}
4759	break;
4760	}
4761	/////////////////////
4762	case CLEANUP_DATA_GO:
4763	{
4764	if ( p_vci_ini_c.cmdack.read() )
4765	{
4766	r_dcache_cleanup_req = false;
4767	r_cleanup_fsm = CLEANUP_INS_IDLE;
4768
4769	#if DEBUG_CLEANUP
4770	if ( m_debug_cleanup_fsm )
4771	{
4772	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4773	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4774	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4775	}
4776	#endif
4777	}
4778	}
4779	////////////////////////
4780	case CLEANUP_INS_GO:
4781	{
4782	if ( p_vci_ini_c.cmdack.read() )
4783	{
4784	r_icache_cleanup_req = false;
4785	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4786
4787	#if DEBUG_CLEANUP
4788	if ( m_debug_cleanup_fsm )
4789	{
4790	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4791	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4792	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4793	}
4794	#endif
4795	}
4796	}
4797	} // end switch CLEANUP FSM
4798
4799	//////////////// Handling cleanup responses //////////////////
4800	if ( p_vci_ini_c.rspval.read() ) // valid response
4801	{
4802	r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
4803	}
4804
4805	///////////////// Response FIFOs update //////////////////////
4806	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4807	vci_rsp_fifo_icache_put,
4808	vci_rsp_fifo_icache_data);
4809
4810	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4811	vci_rsp_fifo_dcache_put,
4812	vci_rsp_fifo_dcache_data);
4813	} // end transition()
4814
4815	///////////////////////
4816	tmpl(void)::genMoore()
4817	///////////////////////
4818	{
4819	////////////////////////////////////////////////////////////////
4820	// VCI initiator command on the coherence network (cleanup)
4821	// it depends on the CLEANUP FSM state
4822
4823	paddr_t address;
4824
4825	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4826	address = r_dcache_cleanup_line.read()m_dcache_words4;
4827	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4828	address = r_icache_cleanup_line.read()m_icache_words4;
4829	else
4830	address = 0;
4831
4832	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4833	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4834	p_vci_ini_c.address = address;
4835	p_vci_ini_c.wdata = 0;
4836	p_vci_ini_c.be = 0xF;
4837	p_vci_ini_c.plen = 4;
4838	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4839	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4840	p_vci_ini_c.pktid = 0;
4841	p_vci_ini_c.srcid = m_srcid_c;
4842	p_vci_ini_c.cons = false;
4843	p_vci_ini_c.wrap = false;
4844	p_vci_ini_c.contig = false;
4845	p_vci_ini_c.clen = 0;
4846	p_vci_ini_c.cfixed = false;
4847	p_vci_ini_c.eop = true;
4848
4849	/////////////////////////////////////////////////////////////////
4850	// VCI initiator response on the coherence network (cleanup)
4851	// We always consume the response, and we don't use it.
4852
4853	p_vci_ini_c.rspack = true;
4854
4855	/////////////////////////////////////////////////////////////////
4856	// VCI initiator command on the direct network
4857	// it depends on the CMD FSM state
4858
4859	p_vci_ini_d.pktid = 0;
4860	p_vci_ini_d.srcid = m_srcid_d;
4861	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4862	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4863	p_vci_ini_d.wrap = false;
4864	p_vci_ini_d.clen = 0;
4865	p_vci_ini_d.cfixed = false;
4866
4867	switch ( r_vci_cmd_fsm.read() ) {
4868
4869	case CMD_IDLE:
4870	p_vci_ini_d.cmdval = false;
4871	p_vci_ini_d.address = 0;
4872	p_vci_ini_d.wdata = 0;
4873	p_vci_ini_d.be = 0;
4874	p_vci_ini_d.trdid = 0;
4875	p_vci_ini_d.plen = 0;
4876	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4877	p_vci_ini_d.eop = false;
4878	break;
4879
4880	case CMD_INS_MISS:
4881	p_vci_ini_d.cmdval = true;
4882	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4883	p_vci_ini_d.wdata = 0;
4884	p_vci_ini_d.be = 0xF;
4885	p_vci_ini_d.trdid = TYPE_INS_MISS;
4886	p_vci_ini_d.plen = m_icache_words<<2;
4887	p_vci_ini_d.cmd = vci_param::CMD_READ;
4888	p_vci_ini_d.eop = true;
4889	break;
4890
4891	case CMD_INS_UNC:
4892	p_vci_ini_d.cmdval = true;
4893	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4894	p_vci_ini_d.wdata = 0;
4895	p_vci_ini_d.be = 0xF;
4896	p_vci_ini_d.trdid = TYPE_INS_UNC;
4897	p_vci_ini_d.plen = 4;
4898	p_vci_ini_d.cmd = vci_param::CMD_READ;
4899	p_vci_ini_d.eop = true;
4900	break;
4901
4902	case CMD_DATA_MISS:
4903	p_vci_ini_d.cmdval = true;
4904	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4905	p_vci_ini_d.wdata = 0;
4906	p_vci_ini_d.be = 0xF;
4907	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4908	p_vci_ini_d.plen = m_dcache_words << 2;
4909	p_vci_ini_d.cmd = vci_param::CMD_READ;
4910	p_vci_ini_d.eop = true;
4911	break;
4912
4913	case CMD_DATA_UNC:
4914	p_vci_ini_d.cmdval = true;
4915	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4916	p_vci_ini_d.wdata = 0;
4917	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4918	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4919	p_vci_ini_d.plen = 4;
4920	p_vci_ini_d.cmd = vci_param::CMD_READ;
4921	p_vci_ini_d.eop = true;
4922	break;
4923
4924	case CMD_DATA_WRITE:
4925	p_vci_ini_d.cmdval = true;
4926	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4927	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4928	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4929	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4930	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4931	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4932	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4933	break;
4934
4935	case CMD_DATA_SC:
4936	p_vci_ini_d.cmdval = true;
4937	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4938	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4939	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4940	p_vci_ini_d.be = 0xF;
4941	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4942	p_vci_ini_d.plen = 8;
4943	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4944	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4945	break;
4946	} // end switch r_vci_cmd_fsm
4947
4948	//////////////////////////////////////////////////////////
4949	// VCI initiator response on the direct network
4950	// it depends on the VCI RSP state
4951
4952	switch (r_vci_rsp_fsm.read() )
4953	{
4954	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4955	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4956	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4957	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4958	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4959	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4960	} // end switch r_vci_rsp_fsm
4961
4962	////////////////////////////////////////////////////////////////
4963	// VCI target command and response on the coherence network
4964	switch ( r_tgt_fsm.read() )
4965	{
4966	case TGT_IDLE:
4967	case TGT_UPDT_WORD:
4968	case TGT_UPDT_DATA:
4969	p_vci_tgt_c.cmdack = true;
4970	p_vci_tgt_c.rspval = false;
4971	break;
4972
4973	case TGT_RSP_BROADCAST:
4974	p_vci_tgt_c.cmdack = false;
4975	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4976	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4977	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4978	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4979	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4980	p_vci_tgt_c.rdata = 0;
4981	p_vci_tgt_c.rerror = 0;
4982	p_vci_tgt_c.reop = true;
4983	break;
4984
4985	case TGT_RSP_ICACHE:
4986	p_vci_tgt_c.cmdack = false;
4987	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4988	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4989	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4990	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4991	p_vci_tgt_c.rdata = 0;
4992	p_vci_tgt_c.rerror = 0;
4993	p_vci_tgt_c.reop = true;
4994	break;
4995
4996	case TGT_RSP_DCACHE:
4997	p_vci_tgt_c.cmdack = false;
4998	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4999	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5000	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5001	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5002	p_vci_tgt_c.rdata = 0;
5003	p_vci_tgt_c.rerror = 0;
5004	p_vci_tgt_c.reop = true;
5005	break;
5006
5007	case TGT_REQ_BROADCAST:
5008	case TGT_REQ_ICACHE:
5009	case TGT_REQ_DCACHE:
5010	p_vci_tgt_c.cmdack = false;
5011	p_vci_tgt_c.rspval = false;
5012	break;
5013
5014	} // end switch TGT_FSM
5015	} // end genMoore
5016
5017	}}
5018
5019	// Local Variables:
5020	// tab-width: 4
5021	// c-basic-offset: 4
5022	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5023	// indent-tabs-mode: nil
5024	// End:
5025
5026	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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