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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 233

Last change on this file since 233 was 233, checked in by alain, 12 years ago
Fixing a bug in the DCACHE_IDLE state: The coherence request were not taken in case of blocking write caused by write buffer full. This is a dead-lock case.
File size: 188.5 KB

Line
1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtd,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_c,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	uint32_t max_frozen_cycles,
169	uint32_t debug_start_cycle,
170	bool debug_ok)
171	: soclib::caba::BaseModule(name),
172
173	p_clk("clk"),
174	p_resetn("resetn"),
175	p_vci_ini_d("vci_ini_d"),
176	p_vci_ini_c("vci_ini_c"),
177	p_vci_tgt_c("vci_tgt_d"),
178
179	m_cacheability_table(mtd.getCacheabilityTable()),
180	m_segment(mtc.getSegment(target_index_c)),
181	m_srcid_d(mtd.indexForId(initiator_index_d)),
182	m_srcid_c(mtc.indexForId(initiator_index_c)),
183
184	m_itlb_ways(itlb_ways),
185	m_itlb_sets(itlb_sets),
186
187	m_dtlb_ways(dtlb_ways),
188	m_dtlb_sets(dtlb_sets),
189
190	m_icache_ways(icache_ways),
191	m_icache_sets(icache_sets),
192	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
193	m_icache_words(icache_words),
194
195	m_dcache_ways(dcache_ways),
196	m_dcache_sets(dcache_sets),
197	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
198	m_dcache_words(dcache_words),
199
200	m_proc_id(proc_id),
201
202	m_max_frozen_cycles(max_frozen_cycles),
203
204	m_paddr_nbits(vci_param::N),
205
206	m_debug_start_cycle(debug_start_cycle),
207	m_debug_ok(debug_ok),
208
209	r_mmu_ptpr("r_mmu_ptpr"),
210	r_mmu_mode("r_mmu_mode"),
211	r_mmu_word_lo("r_mmu_word_lo"),
212	r_mmu_word_hi("r_mmu_word_hi"),
213	r_mmu_ibvar("r_mmu_ibvar"),
214	r_mmu_dbvar("r_mmu_dbvar"),
215	r_mmu_ietr("r_mmu_ietr"),
216	r_mmu_detr("r_mmu_detr"),
217
218	r_icache_fsm("r_icache_fsm"),
219	r_icache_fsm_save("r_icache_fsm_save"),
220
221	r_icache_vci_paddr("r_icache_vci_paddr"),
222	r_icache_vaddr_save("r_icache_vaddr_save"),
223
224	r_icache_miss_way("r_icache_miss_way"),
225	r_icache_miss_set("r_icache_miss_set"),
226	r_icache_miss_word("r_icache_miss_word"),
227	r_icache_miss_inval("r_icache_miss_inval"),
228
229	r_icache_cc_way("r_icache_cc_way"),
230	r_icache_cc_set("r_icache_cc_set"),
231	r_icache_cc_word("r_icache_cc_word"),
232
233	r_icache_flush_count("r_icache_flush_count"),
234
235	r_icache_miss_req("r_icache_miss_req"),
236	r_icache_unc_req("r_icache_unc_req"),
237
238	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
239	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
240
241	r_icache_cleanup_req("r_icache_cleanup_req"),
242	r_icache_cleanup_line("r_icache_cleanup_line"),
243
244	r_dcache_fsm("r_dcache_fsm"),
245	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
246	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
247
248	r_dcache_p0_valid("r_dcache_p0_valid"),
249	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
250	r_dcache_p0_wdata("r_dcache_p0_wdata"),
251	r_dcache_p0_be("r_dcache_p0_be"),
252	r_dcache_p0_paddr("r_dcache_p0_paddr"),
253	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
254
255	r_dcache_p1_valid("r_dcache_p1_valid"),
256	r_dcache_p1_wdata("r_dcache_p1_wdata"),
257	r_dcache_p1_be("r_dcache_p1_be"),
258	r_dcache_p1_paddr("r_dcache_p1_paddr"),
259	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
260	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
261	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
262
263	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
264	r_dcache_dirty_way("r_dcache_dirty_way"),
265	r_dcache_dirty_set("r_dcache_dirty_set"),
266
267	r_dcache_vci_paddr("r_dcache_vci_paddr"),
268	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
269	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
270	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
271	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
272	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
273	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
274
275	r_dcache_xtn_way("r_dcache_xtn_way"),
276	r_dcache_xtn_set("r_dcache_xtn_set"),
277
278	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
279
280	r_dcache_miss_type("r_dcache_miss_type"),
281	r_dcache_miss_word("r_dcache_miss_word"),
282	r_dcache_miss_way("r_dcache_miss_way"),
283	r_dcache_miss_set("r_dcache_miss_set"),
284	r_dcache_miss_inval("r_dcache_miss_inval"),
285
286	r_dcache_cc_way("r_dcache_cc_way"),
287	r_dcache_cc_set("r_dcache_cc_set"),
288	r_dcache_cc_word("r_dcache_cc_word"),
289
290	r_dcache_flush_count("r_dcache_flush_count"),
291
292	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
293	r_dcache_tlb_ins("r_dcache_tlb_ins"),
294	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
295	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
296	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
297	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
298	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
299	r_dcache_tlb_way("r_dcache_tlb_way"),
300	r_dcache_tlb_set("r_dcache_tlb_set"),
301
302	r_dcache_ll_valid("r_dcache_ll_valid"),
303	r_dcache_ll_data("r_dcache_ll_data"),
304	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
305
306	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
307	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
308
309	r_dcache_xtn_req("r_dcache_xtn_req"),
310	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
311
312	r_dcache_cleanup_req("r_dcache_cleanup_req"),
313	r_dcache_cleanup_line("r_dcache_cleanup_line"),
314
315	r_vci_cmd_fsm("r_vci_cmd_fsm"),
316	r_vci_cmd_min("r_vci_cmd_min"),
317	r_vci_cmd_max("r_vci_cmd_max"),
318	r_vci_cmd_cpt("r_vci_cmd_cpt"),
319	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
320
321	r_vci_rsp_fsm("r_vci_rsp_fsm"),
322	r_vci_rsp_cpt("r_vci_rsp_cpt"),
323	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
324	r_vci_rsp_data_error("r_vci_rsp_data_error"),
325	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
326	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
327
328	r_cleanup_fsm("r_cleanup_fsm"),
329	r_cleanup_trdid("r_cleanup_trdid"),
330	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
331
332	r_tgt_fsm("r_tgt_fsm"),
333	r_tgt_paddr("r_tgt_paddr"),
334	r_tgt_word_count("r_tgt_word_count"),
335	r_tgt_word_min("r_tgt_word_min"),
336	r_tgt_word_max("r_tgt_word_max"),
337	r_tgt_update("r_tgt_update"),
338	r_tgt_update_data("r_tgt_update_data"),
339	r_tgt_srcid("r_tgt_srcid"),
340	r_tgt_pktid("r_tgt_pktid"),
341	r_tgt_trdid("r_tgt_trdid"),
342
343	r_tgt_icache_req("r_tgt_icache_req"),
344	r_tgt_dcache_req("r_tgt_dcache_req"),
345	r_tgt_icache_rsp("r_tgt_icache_rsp"),
346	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
347
348	r_iss(this->name(), proc_id),
349	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
350	r_icache("icache", icache_ways, icache_sets, icache_words),
351	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
352	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
353	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
354	{
355	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
356	"Need more PLEN bits.");
357
358	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
359	"Need more TRDID bits.");
360
361	assert( (icache_words == dcache_words) and
362	"icache_words and dcache_words parameters must be equal");
363
364	assert( (itlb_sets == dtlb_sets) and
365	"itlb_sets and dtlb_sets parameters must be etqual");
366
367	assert( (itlb_ways == dtlb_ways) and
368	"itlb_ways and dtlb_ways parameters must be etqual");
369
370	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
371	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
372	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
373	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
374	(uint32_log2(m_icache_words<<2));
375
376	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
377
378	r_tgt_buf = new uint32_t[dcache_words];
379	r_tgt_be = new vci_be_t[dcache_words];
380	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
381	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
382
383	SC_METHOD(transition);
384	dont_initialize();
385	sensitive << p_clk.pos();
386
387	SC_METHOD(genMoore);
388	dont_initialize();
389	sensitive << p_clk.neg();
390
391	typename iss_t::CacheInfo cache_info;
392	cache_info.has_mmu = true;
393	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
394	cache_info.icache_assoc = icache_ways;
395	cache_info.icache_n_lines = icache_sets;
396	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
397	cache_info.dcache_assoc = dcache_ways;
398	cache_info.dcache_n_lines = dcache_sets;
399	r_iss.setCacheInfo(cache_info);
400	}
401
402	/////////////////////////////////////
403	tmpl(/**/)::~VciCcVCacheWrapperV4()
404	/////////////////////////////////////
405	{
406	delete [] r_tgt_be;
407	delete [] r_tgt_buf;
408	delete [] r_dcache_in_tlb;
409	delete [] r_dcache_contains_ptd;
410	}
411
412	////////////////////////
413	tmpl(void)::print_cpi()
414	////////////////////////
415	{
416	std::cout << name() << " CPI = "
417	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
418	}
419
420	////////////////////////////////////
421	tmpl(void)::print_trace(size_t mode)
422	////////////////////////////////////
423	{
424	// b0 : write buffer trace
425	// b1 : write buffer verbose
426	// b2 : dcache trace
427	// b3 : icache trace
428	// b4 : dtlb trace
429	// b5 : itlb trace
430
431	std::cout << std::dec << "PROC " << name() << std::endl;
432
433	std::cout << " " << m_ireq << std::endl;
434	std::cout << " " << m_irsp << std::endl;
435	std::cout << " " << m_dreq << std::endl;
436	std::cout << " " << m_drsp << std::endl;
437
438	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
439	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
440	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
441	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
442	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
443	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
444	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
445	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
446	std::cout << std::endl;
447
448	if(mode & 0x01)
449	{
450	r_wbuf.printTrace((mode>>1)&1);
451	}
452	if(mode & 0x04)
453	{
454	std::cout << " Data Cache" << std::endl;
455	r_dcache.printTrace();
456	}
457	if(mode & 0x08)
458	{
459	std::cout << " Instruction Cache" << std::endl;
460	r_icache.printTrace();
461	}
462	if(mode & 0x10)
463	{
464	std::cout << " Data TLB" << std::endl;
465	r_dtlb.printTrace();
466	}
467	if(mode & 0x20)
468	{
469	std::cout << " Instruction TLB" << std::endl;
470	r_itlb.printTrace();
471	}
472	}
473
474	//////////////////////////////////////////
475	tmpl(void)::cache_monitor( paddr_t addr )
476	//////////////////////////////////////////
477	{
478	size_t cache_way;
479	size_t cache_set;
480	size_t cache_word;
481	uint32_t cache_rdata;
482	bool cache_hit = r_dcache.read_neutral( addr,
483	&cache_rdata,
484	&cache_way,
485	&cache_set,
486	&cache_word );
487	bool icache_hit = r_icache.read_neutral( addr,
488	&cache_rdata,
489	&cache_way,
490	&cache_set,
491	&cache_word );
492	if ( cache_hit != m_debug_previous_hit )
493	{
494	std::cout << "PROC " << name()
495	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
496	<< " for adresse " << std::hex << addr
497	<< " / HIT = " << std::dec << cache_hit << std::endl;
498	m_debug_previous_hit = cache_hit;
499	}
500	if ( icache_hit != m_idebug_previous_hit )
501	{
502	std::cout << "PROC " << name()
503	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
504	<< " for adresse " << std::hex << addr
505	<< " / HIT = " << icache_hit << std::endl;
506	m_idebug_previous_hit = icache_hit;
507	}
508	}
509
510	/*
511	////////////////////////
512	tmpl(void)::print_stats()
513	////////////////////////
514	{
515	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
516	std::cout << name() << std::endl
517	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
518	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
519	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
520	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
521	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
522	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
523	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
524	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
525	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
526	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
527	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
528	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
529	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
530	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
531	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
532	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
533	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
534	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
535	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
536	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
537	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
538	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
539	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
540	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
541	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
542	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
543	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
544	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
545	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
546	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
547	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
548	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
549	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
550	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
551	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
552	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
553	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
554	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
555	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
556	}
557
558	////////////////////////
559	tmpl(void)::clear_stats()
560	////////////////////////
561	{
562	m_cpt_dcache_data_read = 0;
563	m_cpt_dcache_data_write = 0;
564	m_cpt_dcache_dir_read = 0;
565	m_cpt_dcache_dir_write = 0;
566	m_cpt_icache_data_read = 0;
567	m_cpt_icache_data_write = 0;
568	m_cpt_icache_dir_read = 0;
569	m_cpt_icache_dir_write = 0;
570
571	m_cpt_frz_cycles = 0;
572	m_cpt_dcache_frz_cycles = 0;
573	m_cpt_total_cycles = 0;
574
575	m_cpt_read = 0;
576	m_cpt_write = 0;
577	m_cpt_data_miss = 0;
578	m_cpt_ins_miss = 0;
579	m_cpt_unc_read = 0;
580	m_cpt_write_cached = 0;
581	m_cpt_ins_read = 0;
582
583	m_cost_write_frz = 0;
584	m_cost_data_miss_frz = 0;
585	m_cost_unc_read_frz = 0;
586	m_cost_ins_miss_frz = 0;
587
588	m_cpt_imiss_transaction = 0;
589	m_cpt_dmiss_transaction = 0;
590	m_cpt_unc_transaction = 0;
591	m_cpt_write_transaction = 0;
592	m_cpt_icache_unc_transaction = 0;
593
594	m_cost_imiss_transaction = 0;
595	m_cost_dmiss_transaction = 0;
596	m_cost_unc_transaction = 0;
597	m_cost_write_transaction = 0;
598	m_cost_icache_unc_transaction = 0;
599	m_length_write_transaction = 0;
600
601	m_cpt_ins_tlb_read = 0;
602	m_cpt_ins_tlb_miss = 0;
603	m_cpt_ins_tlb_update_acc = 0;
604
605	m_cpt_data_tlb_read = 0;
606	m_cpt_data_tlb_miss = 0;
607	m_cpt_data_tlb_update_acc = 0;
608	m_cpt_data_tlb_update_dirty = 0;
609	m_cpt_ins_tlb_hit_dcache = 0;
610	m_cpt_data_tlb_hit_dcache = 0;
611	m_cpt_ins_tlb_occup_cache = 0;
612	m_cpt_data_tlb_occup_cache = 0;
613
614	m_cost_ins_tlb_miss_frz = 0;
615	m_cost_data_tlb_miss_frz = 0;
616	m_cost_ins_tlb_update_acc_frz = 0;
617	m_cost_data_tlb_update_acc_frz = 0;
618	m_cost_data_tlb_update_dirty_frz = 0;
619	m_cost_ins_tlb_occup_cache_frz = 0;
620	m_cost_data_tlb_occup_cache_frz = 0;
621
622	m_cpt_itlbmiss_transaction = 0;
623	m_cpt_itlb_ll_transaction = 0;
624	m_cpt_itlb_sc_transaction = 0;
625	m_cpt_dtlbmiss_transaction = 0;
626	m_cpt_dtlb_ll_transaction = 0;
627	m_cpt_dtlb_sc_transaction = 0;
628	m_cpt_dtlb_ll_dirty_transaction = 0;
629	m_cpt_dtlb_sc_dirty_transaction = 0;
630
631	m_cost_itlbmiss_transaction = 0;
632	m_cost_itlb_ll_transaction = 0;
633	m_cost_itlb_sc_transaction = 0;
634	m_cost_dtlbmiss_transaction = 0;
635	m_cost_dtlb_ll_transaction = 0;
636	m_cost_dtlb_sc_transaction = 0;
637	m_cost_dtlb_ll_dirty_transaction = 0;
638	m_cost_dtlb_sc_dirty_transaction = 0;
639
640	m_cpt_cc_update_data = 0;
641	m_cpt_cc_inval_ins = 0;
642	m_cpt_cc_inval_data = 0;
643	m_cpt_cc_broadcast = 0;
644
645	m_cost_updt_data_frz = 0;
646	m_cost_inval_ins_frz = 0;
647	m_cost_inval_data_frz = 0;
648	m_cost_broadcast_frz = 0;
649
650	m_cpt_cc_cleanup_data = 0;
651	m_cpt_cc_cleanup_ins = 0;
652	}
653
654	*/
655
656	/////////////////////////
657	tmpl(void)::transition()
658	/////////////////////////
659	{
660	if ( not p_resetn.read() )
661	{
662	r_iss.reset();
663	r_wbuf.reset();
664	r_icache.reset();
665	r_dcache.reset();
666	r_itlb.reset();
667	r_dtlb.reset();
668
669	r_dcache_fsm = DCACHE_IDLE;
670	r_icache_fsm = ICACHE_IDLE;
671	r_vci_cmd_fsm = CMD_IDLE;
672	r_vci_rsp_fsm = RSP_IDLE;
673	r_tgt_fsm = TGT_IDLE;
674	r_cleanup_fsm = CLEANUP_DATA_IDLE;
675
676	// reset dcache directory extension
677	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
678	{
679	r_dcache_in_tlb[i] = false;
680	r_dcache_contains_ptd[i] = false;
681	}
682
683	// Response FIFOs and cleanup buffer
684	r_vci_rsp_fifo_icache.init();
685	r_vci_rsp_fifo_dcache.init();
686	r_cleanup_buffer.reset();
687
688	// ICACHE & DCACHE activated
689	r_mmu_mode = 0x3;
690
691	// No request from ICACHE FSM to CMD FSM
692	r_icache_miss_req = false;
693	r_icache_unc_req = false;
694
695	// No request from ICACHE_FSM to DCACHE FSM
696	r_icache_tlb_miss_req = false;
697
698	// No request from ICACHE_FSM to CLEANUP FSMs
699	r_icache_cleanup_req = false;
700
701	// No pending write in pipeline
702	r_dcache_p0_valid = false;
703	r_dcache_p1_valid = false;
704
705	// No request from DCACHE_FSM to CMD_FSM
706	r_dcache_vci_miss_req = false;
707	r_dcache_vci_unc_req = false;
708	r_dcache_vci_sc_req = false;
709
710	// No uncacheable write pending
711	r_dcache_pending_unc_write = false;
712
713	// No LL reservation
714	r_dcache_ll_valid = false;
715
716	// No processor XTN request pending
717	r_dcache_xtn_req = false;
718
719	// No request from DCACHE FSM to CLEANUP FSMs
720	r_dcache_cleanup_req = false;
721
722	// No request from TGT FSM to ICACHE/DCACHE FSMs
723	r_tgt_icache_req = false;
724	r_tgt_dcache_req = false;
725
726	// No signalisation of a coherence request matching a pending miss
727	r_icache_miss_inval = false;
728	r_dcache_miss_inval = false;
729
730	// No signalisation of errors
731	r_vci_rsp_ins_error = false;
732	r_vci_rsp_data_error = false;
733
734	// Debug variables
735	m_debug_previous_hit = false;
736	m_idebug_previous_hit = false;
737	m_debug_dcache_fsm = false;
738	m_debug_icache_fsm = false;
739	m_debug_cleanup_fsm = false;
740
741	// activity counters
742	m_cpt_dcache_data_read = 0;
743	m_cpt_dcache_data_write = 0;
744	m_cpt_dcache_dir_read = 0;
745	m_cpt_dcache_dir_write = 0;
746	m_cpt_icache_data_read = 0;
747	m_cpt_icache_data_write = 0;
748	m_cpt_icache_dir_read = 0;
749	m_cpt_icache_dir_write = 0;
750
751	m_cpt_frz_cycles = 0;
752	m_cpt_total_cycles = 0;
753	m_cpt_stop_simulation = 0;
754
755	m_cpt_data_miss = 0;
756	m_cpt_ins_miss = 0;
757	m_cpt_unc_read = 0;
758	m_cpt_write_cached = 0;
759	m_cpt_ins_read = 0;
760
761	m_cost_write_frz = 0;
762	m_cost_data_miss_frz = 0;
763	m_cost_unc_read_frz = 0;
764	m_cost_ins_miss_frz = 0;
765
766	m_cpt_imiss_transaction = 0;
767	m_cpt_dmiss_transaction = 0;
768	m_cpt_unc_transaction = 0;
769	m_cpt_write_transaction = 0;
770	m_cpt_icache_unc_transaction = 0;
771
772	m_cost_imiss_transaction = 0;
773	m_cost_dmiss_transaction = 0;
774	m_cost_unc_transaction = 0;
775	m_cost_write_transaction = 0;
776	m_cost_icache_unc_transaction = 0;
777	m_length_write_transaction = 0;
778
779	m_cpt_ins_tlb_read = 0;
780	m_cpt_ins_tlb_miss = 0;
781	m_cpt_ins_tlb_update_acc = 0;
782
783	m_cpt_data_tlb_read = 0;
784	m_cpt_data_tlb_miss = 0;
785	m_cpt_data_tlb_update_acc = 0;
786	m_cpt_data_tlb_update_dirty = 0;
787	m_cpt_ins_tlb_hit_dcache = 0;
788	m_cpt_data_tlb_hit_dcache = 0;
789	m_cpt_ins_tlb_occup_cache = 0;
790	m_cpt_data_tlb_occup_cache = 0;
791
792	m_cost_ins_tlb_miss_frz = 0;
793	m_cost_data_tlb_miss_frz = 0;
794	m_cost_ins_tlb_update_acc_frz = 0;
795	m_cost_data_tlb_update_acc_frz = 0;
796	m_cost_data_tlb_update_dirty_frz = 0;
797	m_cost_ins_tlb_occup_cache_frz = 0;
798	m_cost_data_tlb_occup_cache_frz = 0;
799
800	m_cpt_ins_tlb_inval = 0;
801	m_cpt_data_tlb_inval = 0;
802	m_cost_ins_tlb_inval_frz = 0;
803	m_cost_data_tlb_inval_frz = 0;
804
805	m_cpt_cc_broadcast = 0;
806
807	m_cost_updt_data_frz = 0;
808	m_cost_inval_ins_frz = 0;
809	m_cost_inval_data_frz = 0;
810	m_cost_broadcast_frz = 0;
811
812	m_cpt_cc_cleanup_data = 0;
813	m_cpt_cc_cleanup_ins = 0;
814
815	m_cpt_itlbmiss_transaction = 0;
816	m_cpt_itlb_ll_transaction = 0;
817	m_cpt_itlb_sc_transaction = 0;
818	m_cpt_dtlbmiss_transaction = 0;
819	m_cpt_dtlb_ll_transaction = 0;
820	m_cpt_dtlb_sc_transaction = 0;
821	m_cpt_dtlb_ll_dirty_transaction = 0;
822	m_cpt_dtlb_sc_dirty_transaction = 0;
823
824	m_cost_itlbmiss_transaction = 0;
825	m_cost_itlb_ll_transaction = 0;
826	m_cost_itlb_sc_transaction = 0;
827	m_cost_dtlbmiss_transaction = 0;
828	m_cost_dtlb_ll_transaction = 0;
829	m_cost_dtlb_sc_transaction = 0;
830	m_cost_dtlb_ll_dirty_transaction = 0;
831	m_cost_dtlb_sc_dirty_transaction = 0;
832	/*
833	m_cpt_dcache_frz_cycles = 0;
834	m_cpt_read = 0;
835	m_cpt_write = 0;
836	m_cpt_cc_update_data = 0;
837	m_cpt_cc_inval_ins = 0;
838	m_cpt_cc_inval_data = 0;
839	*/
840
841	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
842	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
843	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
844	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
845	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
846	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
847	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
848
849	return;
850	}
851
852	// Response FIFOs default values
853	bool vci_rsp_fifo_icache_get = false;
854	bool vci_rsp_fifo_icache_put = false;
855	uint32_t vci_rsp_fifo_icache_data = 0;
856
857	bool vci_rsp_fifo_dcache_get = false;
858	bool vci_rsp_fifo_dcache_put = false;
859	uint32_t vci_rsp_fifo_dcache_data = 0;
860
861	#ifdef INSTRUMENTATION
862	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
863	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
864	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
865	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
866	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
867	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
868	#endif
869
870	m_cpt_total_cycles++;
871
872	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
873	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
874	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
875
876	/////////////////////////////////////////////////////////////////////
877	// The TGT_FSM controls the following ressources:
878	// - r_tgt_fsm
879	// - r_tgt_buf[nwords]
880	// - r_tgt_be[nwords]
881	// - r_tgt_update
882	// - r_tgt_word_min
883	// - r_tgt_word_max
884	// - r_tgt_word_count
885	// - r_tgt_paddr
886	// - r_tgt_srcid
887	// - r_tgt_trdid
888	// - r_tgt_pktid
889	// - r_tgt_icache_req (set)
890	// - r_tgt_dcache_req (set)
891	//
892	// All VCI commands must be CMD_WRITE.
893	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
894	// It is a multicast request otherwise.
895	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
896	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
897	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
898	//
899	// For all types of coherence request, the line index (i.e. the Z & Y fields)
900	// is coded on 34 bits, and is contained in the WDATA and BE fields
901	// of the first VCI flit.
902	// - for a multicast invalidate or for a broadcast invalidate request
903	// the VCI packet length is 1 word.
904	// - for an update request the VCI packet length is (n+2) words.
905	// The WDATA field of the second VCI word contains the word index.
906	// The WDATA field of the n following words contains the values.
907	// - for all transaction types, the VCI response is one single word.
908	// In case of errors in the VCI command packet, the simulation
909	// is stopped with an error message.
910	//
911	// This FSM is NOT pipelined : It consumes a new coherence request
912	// on the VCI port only when the previous request is completed.
913	//
914	// The VCI_TGT FSM stores the external request arguments in the
915	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
916	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
917	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
918	// states. It waits the completion of the coherence request by polling the
919	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
920	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
921	// These two FSMs signal if a VCI answer must be send by setting
922	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
923	///////////////////////////////////////////////////////////////////////////////
924
925	switch( r_tgt_fsm.read() )
926	{
927	//////////////
928	case TGT_IDLE:
929	{
930	if ( p_vci_tgt_c.cmdval.read() )
931	{
932	paddr_t address = p_vci_tgt_c.address.read();
933
934	// command checking
935	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
936	{
937	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
938	std::cout << "the received VCI coherence command is not a write" << std::endl;
939	exit(0);
940	}
941
942	// address checking
943	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
944	{
945	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
946	std::cout << "out of segment VCI coherence command received" << std::endl;
947	exit(0);
948	}
949
950	r_tgt_srcid = p_vci_tgt_c.srcid.read();
951	r_tgt_trdid = p_vci_tgt_c.trdid.read();
952	r_tgt_pktid = p_vci_tgt_c.pktid.read();
953
954	if (sizeof(paddr_t) <= 32) {
955	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
956	r_tgt_paddr =
957	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
958	} else {
959	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
960	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
961	}
962
963	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
964	{
965	if ( not p_vci_tgt_c.eop.read() )
966	{
967	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
968	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
969	exit(0);
970	}
971	r_tgt_update = false;
972	r_tgt_fsm = TGT_REQ_BROADCAST;
973
974	#ifdef INSTRUMENTATION
975	m_cpt_cc_broadcast++;
976	#endif
977	}
978	else // multi-update or multi-invalidate for data type
979	{
980	paddr_t cell = address - m_segment.baseAddress();
981
982	if (cell == 0) // invalidate data
983	{
984	if ( not p_vci_tgt_c.eop.read() )
985	{
986	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
987	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
988	exit(0);
989	}
990	r_tgt_update = false;
991	r_tgt_fsm = TGT_REQ_DCACHE;
992
993	#ifdef INSTRUMENTATION
994	m_cpt_cc_inval_dcache++;
995	#endif
996	}
997	else if (cell == 4) // invalidate instruction
998	{
999	if ( not p_vci_tgt_c.eop.read() )
1000	{
1001	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1002	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1003	exit(0);
1004	}
1005	r_tgt_update = false;
1006	r_tgt_fsm = TGT_REQ_ICACHE;
1007
1008	#ifdef INSTRUMENTATION
1009	m_cpt_cc_inval_icache++;
1010	#endif
1011	}
1012	else if (cell == 8) // update data
1013	{
1014	if ( p_vci_tgt_c.eop.read() )
1015	{
1016	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1017	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1018	exit(0);
1019	}
1020	r_tgt_update = true;
1021	r_tgt_update_data = true;
1022	r_tgt_fsm = TGT_UPDT_WORD;
1023
1024	#ifdef INSTRUMENTATION
1025	m_cpt_cc_update_dcache++;
1026	#endif
1027	}
1028	else // update instruction
1029	{
1030	if ( p_vci_tgt_c.eop.read() )
1031	{
1032	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1033	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1034	exit(0);
1035	}
1036	r_tgt_update = true;
1037	r_tgt_update_data = false;
1038	r_tgt_fsm = TGT_UPDT_WORD;
1039
1040	#ifdef INSTRUMENTATION
1041	m_cpt_cc_update_icache++;
1042	#endif
1043	}
1044	} // end if multi
1045	} // end if cmdval
1046	break;
1047	}
1048	///////////////////
1049	case TGT_UPDT_WORD: // first word index acquisition
1050	{
1051	if (p_vci_tgt_c.cmdval.read())
1052	{
1053	if ( p_vci_tgt_c.eop.read() )
1054	{
1055	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1056	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1057	exit(0);
1058	}
1059	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1060
1061	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1062	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1063	r_tgt_fsm = TGT_UPDT_DATA;
1064	}
1065	break;
1066	}
1067	///////////////////
1068	case TGT_UPDT_DATA:
1069	{
1070	if (p_vci_tgt_c.cmdval.read())
1071	{
1072	size_t word = r_tgt_word_count.read();
1073	if (word >= m_dcache_words)
1074	{
1075	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1076	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1077	exit(0);
1078	}
1079	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1080	r_tgt_be[word] = p_vci_tgt_c.be.read();
1081	r_tgt_word_count = word + 1;
1082
1083	if (p_vci_tgt_c.eop.read()) // last word
1084	{
1085	r_tgt_word_max = word;
1086	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1087	else r_tgt_fsm = TGT_REQ_ICACHE;
1088	}
1089	}
1090	break;
1091	}
1092	///////////////////////
1093	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1094	{
1095	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1096	{
1097	r_tgt_fsm = TGT_RSP_BROADCAST;
1098	r_tgt_icache_req = true;
1099	r_tgt_dcache_req = true;
1100	}
1101	break;
1102	}
1103	/////////////////////
1104	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1105	{
1106	if ( not r_tgt_icache_req.read() )
1107	{
1108	r_tgt_fsm = TGT_RSP_ICACHE;
1109	r_tgt_icache_req = true;
1110	}
1111	break;
1112	}
1113	////////////////////
1114	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1115	{
1116	if ( not r_tgt_dcache_req.read() )
1117	{
1118	r_tgt_fsm = TGT_RSP_DCACHE;
1119	r_tgt_dcache_req = true;
1120	}
1121	break;
1122	}
1123	///////////////////////
1124	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1125	// no response when r_tgt_*cache_rsp is false
1126	{
1127	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1128	{
1129	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1130	{
1131	if ( p_vci_tgt_c.rspack.read() )
1132	{
1133	// reset dcache first if activated
1134	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1135	else r_tgt_icache_rsp = false;
1136	}
1137	}
1138	else
1139	{
1140	r_tgt_fsm = TGT_IDLE;
1141	}
1142	}
1143	break;
1144	}
1145	////////////////////
1146	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1147	{
1148	// no response when r_tgt_icache_rsp is false
1149	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1150	{
1151	r_tgt_fsm = TGT_IDLE;
1152	r_tgt_icache_rsp = false;
1153	}
1154	break;
1155	}
1156	////////////////////
1157	case TGT_RSP_DCACHE:
1158	{
1159	// no response when r_tgt_dcache_rsp is false
1160	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1161	{
1162	r_tgt_fsm = TGT_IDLE;
1163	r_tgt_dcache_rsp = false;
1164	}
1165	break;
1166	}
1167	} // end switch TGT_FSM
1168
1169	/////////////////////////////////////////////////////////////////////
1170	// Get data and instruction requests from processor
1171	///////////////////////////////////////////////////////////////////////
1172
1173	r_iss.getRequests(m_ireq, m_dreq);
1174
1175	////////////////////////////////////////////////////////////////////////////////////
1176	// ICACHE_FSM
1177	//
1178	// There is 9 conditions to exit the IDLE state:
1179	// One condition is a coherence request from TGT FSM :
1180	// - Coherence operation => ICACHE_CC_CHEK
1181	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1182	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1183	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1184	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1185	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1186	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1187	// three configurations corresponding to instruction processor requests :
1188	// - tlb miss => ICACHE_TLB_WAIT
1189	// - cacheable read miss => ICACHE_MISS_VICTIM
1190	// - uncacheable read miss => ICACHE_UNC_REQ
1191	//
1192	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1193	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1194	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1195	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1196	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1197	// The availability of the missing cache line is signaled by the response fifo,
1198	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1199	//
1200	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1201	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1202	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1203	// the response from the RSP FSM, through the response fifo. The missing instruction
1204	// is directly returned to processor in this state.
1205	//
1206	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1207	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1208	// and goes to the ICACHE_TLB_WAIT state.
1209	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1210	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1211	//
1212	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1213	// using the r_dcache_xtn_req flip-flop.
1214	// The request opcode and the address to be invalidated are transmitted
1215	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1216	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1217	// is completed.
1218	//
1219	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1220	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1221	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1222	////////////////////////////////////////////////////////////////////////////////////////
1223
1224	// default value for m_irsp
1225	m_irsp.valid = false;
1226	m_irsp.error = false;
1227	m_irsp.instruction = 0;
1228
1229	switch( r_icache_fsm.read() )
1230	{
1231	/////////////////
1232	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1233	// by DCACHE FSM, and coherence requests with a fixed priority:
1234	// coherence > XTN > instruction
1235	// We access the itlb and dcache in parallel with the virtual address
1236	// for itlb, and with a speculative physical address for icache,
1237	// computed during the previous cycle.
1238	{
1239	// coherence request from the target FSM
1240	if ( r_tgt_icache_req.read() )
1241	{
1242	r_icache_fsm = ICACHE_CC_CHECK;
1243	r_icache_fsm_save = r_icache_fsm.read();
1244	break;
1245	}
1246
1247	// Decoding processor XTN requests sent by DCACHE FSM
1248	// These request are not executed in this IDLE state, because
1249	// they require access to icache or itlb, that are already accessed
1250	if ( r_dcache_xtn_req.read() )
1251	{
1252	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1253	{
1254	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1255	break;
1256	}
1257	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1258	{
1259	r_icache_flush_count = 0;
1260	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1261	break;
1262	}
1263	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1264	{
1265	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1266	break;
1267	}
1268	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1269	{
1270	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1271	break;
1272	}
1273	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1274	{
1275	if (sizeof(paddr_t) <= 32) {
1276	assert(r_mmu_word_hi.read() == 0 &&
1277	"high bits should be 0 for 32bit paddr");
1278	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1279	} else {
1280	r_icache_vci_paddr =
1281	(paddr_t)r_mmu_word_hi.read() << 32 \|
1282	(paddr_t)r_mmu_word_lo.read();
1283	}
1284	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1285	break;
1286	}
1287	} // end if xtn_req
1288
1289	// processor request
1290	if ( m_ireq.valid )
1291	{
1292	bool cacheable;
1293	paddr_t paddr;
1294
1295	// We register processor request
1296	r_icache_vaddr_save = m_ireq.addr;
1297
1298	// speculative icache access (if cache activated)
1299	// we use the speculative PPN computed during the previous cycle
1300
1301	uint32_t cache_inst = 0;
1302	bool cache_hit = false;
1303
1304	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1305	{
1306	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1307	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1308
1309	#ifdef INSTRUMENTATION
1310	m_cpt_icache_data_read++;
1311	m_cpt_icache_dir_read++;
1312	#endif
1313	cache_hit = r_icache.read( spc_paddr,
1314	&cache_inst );
1315	}
1316
1317	// systematic itlb access (if tlb activated)
1318	// we use the virtual address
1319
1320	paddr_t tlb_paddr;
1321	pte_info_t tlb_flags;
1322	size_t tlb_way;
1323	size_t tlb_set;
1324	paddr_t tlb_nline;
1325	bool tlb_hit = false;;
1326
1327	if ( r_mmu_mode.read() & INS_TLB_MASK )
1328	{
1329
1330	#ifdef INSTRUMENTATION
1331	m_cpt_itlb_read++;
1332	#endif
1333	tlb_hit = r_itlb.translate( m_ireq.addr,
1334	&tlb_paddr,
1335	&tlb_flags,
1336	&tlb_nline, // unused
1337	&tlb_way, // unused
1338	&tlb_set ); // unused
1339	}
1340
1341	// We compute cacheability, physical address and check access rights:
1342	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1343	// the physical address is obtained from the TLB, and the access rights are
1344	// defined by the U and X bits in the PTE.
1345	// - If MMU not activated : cacheability is defined by the segment table,
1346	// the physical address is equal to the virtual address (identity mapping)
1347	// and there is no access rights checking
1348
1349	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1350	{
1351	// cacheability
1352	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1353	else cacheable = m_cacheability_table[m_ireq.addr];
1354
1355	// physical address
1356	paddr = (paddr_t)m_ireq.addr;
1357	}
1358	else // itlb activated
1359	{
1360	if ( tlb_hit ) // tlb hit
1361	{
1362	// cacheability
1363	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1364	else cacheable = tlb_flags.c;
1365
1366	// physical address
1367	paddr = tlb_paddr;
1368
1369	// access rights checking
1370	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1371	{
1372	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1373	r_mmu_ibvar = m_ireq.addr;
1374	m_irsp.valid = true;
1375	m_irsp.error = true;
1376	m_irsp.instruction = 0;
1377	break;
1378	}
1379	else if ( not tlb_flags.x )
1380	{
1381	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1382	r_mmu_ibvar = m_ireq.addr;
1383	m_irsp.valid = true;
1384	m_irsp.error = true;
1385	m_irsp.instruction = 0;
1386	break;
1387	}
1388	}
1389	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1390	else
1391	{
1392
1393	#ifdef INSTRUMENTATION
1394	m_cpt_itlb_miss++;
1395	#endif
1396	r_icache_fsm = ICACHE_TLB_WAIT;
1397	r_icache_tlb_miss_req = true;
1398	break;
1399	}
1400	} // end if itlb activated
1401
1402	// physical address registration (for next cycle)
1403	r_icache_vci_paddr = paddr;
1404
1405	// We enter this section only in case of TLB hit:
1406	// Finally, we get the instruction depending on cacheability,
1407	// we send the response to processor, and compute next state
1408	if ( cacheable ) // cacheable read
1409	{
1410	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1411	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1412	{
1413
1414	#ifdef INSTRUMENTATION
1415	m_cpt_icache_spc_miss++;
1416	#endif
1417	// we return an invalid response and stay in IDLE state
1418	// the cache access will cost one extra cycle.
1419	break;
1420	}
1421
1422	if ( not cache_hit ) // cache miss
1423	{
1424
1425	#ifdef INSTRUMENTATION
1426	m_cpt_icache_miss++;
1427	#endif
1428	r_icache_fsm = ICACHE_MISS_VICTIM;
1429	r_icache_miss_req = true;
1430	}
1431	else // cache hit
1432	{
1433
1434	#ifdef INSTRUMENTATION
1435	m_cpt_ins_read++;
1436	#endif
1437	m_irsp.valid = true;
1438	m_irsp.instruction = cache_inst;
1439	}
1440	}
1441	else // non cacheable read
1442	{
1443	r_icache_unc_req = true;
1444	r_icache_fsm = ICACHE_UNC_WAIT;
1445	}
1446	} // end if m_ireq.valid
1447	break;
1448	}
1449	/////////////////////
1450	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1451	// the itlb is udated by the DCACHE FSM, as well as the
1452	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1453	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1454	// reset the r_icache_tlb_miss_req flip-flop
1455	// external coherence request are accepted in this state.
1456	{
1457	// external coherence request
1458	if ( r_tgt_icache_req.read() )
1459	{
1460	r_icache_fsm = ICACHE_CC_CHECK;
1461	r_icache_fsm_save = r_icache_fsm.read();
1462	break;
1463	}
1464
1465	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1466
1467	// DCACHE FSM signals response by reseting the request flip-flop
1468	if ( not r_icache_tlb_miss_req.read() )
1469	{
1470	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1471	{
1472	r_icache_tlb_rsp_error = false;
1473	m_irsp.error = true;
1474	m_irsp.valid = true;
1475	r_icache_fsm = ICACHE_IDLE;
1476	}
1477	else // tlb updated : return to IDLE state
1478	{
1479	r_icache_fsm = ICACHE_IDLE;
1480	}
1481	}
1482	break;
1483	}
1484	//////////////////////////
1485	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1486	{
1487	r_itlb.flush();
1488	r_dcache_xtn_req = false;
1489	r_icache_fsm = ICACHE_IDLE;
1490	break;
1491	}
1492	////////////////////////////
1493	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1494	// the r_icache_flush_count register as a slot counter.
1495	// We loop in this state until all slots have been visited.
1496	// A cleanup request is generated for each valid line
1497	// and we are blocked until the previous cleanup is completed
1498	{
1499	if ( not r_icache_cleanup_req.read() )
1500	{
1501	size_t way = r_icache_flush_count.read()/m_icache_sets;
1502	size_t set = r_icache_flush_count.read()%m_icache_sets;
1503	paddr_t nline;
1504	bool cleanup_req = r_icache.inval( way,
1505	set,
1506	&nline );
1507	if ( cleanup_req )
1508	{
1509	r_icache_cleanup_req = true;
1510	r_icache_cleanup_line = nline;
1511	}
1512	r_icache_flush_count = r_icache_flush_count.read() + 1;
1513	}
1514
1515	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1516	{
1517	r_dcache_xtn_req = false;
1518	r_icache_fsm = ICACHE_IDLE;
1519	}
1520	break;
1521	}
1522	//////////////////////////
1523	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1524	// stored in the r_dcache_p0_wdata register
1525	{
1526	r_itlb.inval(r_dcache_p0_wdata.read());
1527	r_dcache_xtn_req = false;
1528	r_icache_fsm = ICACHE_IDLE;
1529	break;
1530	}
1531	///////////////////////////////
1532	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1533	// requires 3 cycles (in case of hit on itlb and icache).
1534	// In this state, we access TLB to translate virtual address
1535	// stored in the r_dcache_p0_wdata register.
1536	{
1537	paddr_t paddr;
1538	bool hit;
1539
1540	// read physical address in TLB when MMU activated
1541	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1542	{
1543
1544	#ifdef INSTRUMENTATION
1545	m_cpt_itlb_read++;
1546	#endif
1547	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1548	&paddr);
1549	}
1550	else // itlb not activated
1551	{
1552	paddr = (paddr_t)r_dcache_p0_wdata.read();
1553	hit = true;
1554	}
1555
1556	if ( hit ) // continue the selective inval process
1557	{
1558	r_icache_vci_paddr = paddr;
1559	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1560	}
1561	else // miss : send a request to DCACHE FSM
1562	{
1563
1564	#ifdef INSTRUMENTATION
1565	m_cpt_itlb_miss++;
1566	#endif
1567	r_icache_tlb_miss_req = true;
1568	r_icache_fsm = ICACHE_TLB_WAIT;
1569	}
1570	break;
1571	}
1572	///////////////////////////////
1573	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1574	// require 2 cycles. In this state, we read dcache,
1575	// with address stored in r_icache_vci_paddr register.
1576	{
1577	uint32_t data;
1578	size_t way;
1579	size_t set;
1580	size_t word;
1581	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1582	&data,
1583	&way,
1584	&set,
1585	&word);
1586	if ( hit ) // inval to be done
1587	{
1588	r_icache_miss_way = way;
1589	r_icache_miss_set = set;
1590	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1591	}
1592	else // miss : acknowlege the XTN request and return
1593	{
1594	r_dcache_xtn_req = false;
1595	r_icache_fsm = ICACHE_IDLE;
1596	}
1597	break;
1598	}
1599	///////////////////////////////
1600	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1601	// We are blocked if the previous cleanup is not completed
1602	{
1603	paddr_t nline;
1604
1605	if ( not r_icache_cleanup_req.read() )
1606	{
1607	bool hit;
1608	hit = r_icache.inval( r_icache_miss_way.read(),
1609	r_icache_miss_set.read(),
1610	&nline );
1611	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1612
1613	// request cleanup
1614	r_icache_cleanup_req = true;
1615	r_icache_cleanup_line = nline;
1616	// acknowledge the XTN request and return
1617	r_dcache_xtn_req = false;
1618	r_icache_fsm = ICACHE_IDLE;
1619	}
1620	break;
1621	}
1622
1623	////////////////////////
1624	case ICACHE_MISS_VICTIM: // Selects a victim line
1625	// Set the r_icache_cleanup_req flip-flop
1626	// when the selected slot is not empty
1627	{
1628	m_cost_ins_miss_frz++;
1629
1630	size_t index; // unused
1631	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1632	if ( not hit and not r_icache_cleanup_req.read() )
1633	{
1634	bool valid;
1635	size_t way;
1636	size_t set;
1637	paddr_t victim;
1638
1639	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1640	&victim,
1641	&way,
1642	&set);
1643	r_icache_miss_way = way;
1644	r_icache_miss_set = set;
1645
1646	if ( valid )
1647	{
1648	r_icache_cleanup_req = true;
1649	r_icache_cleanup_line = victim;
1650	r_icache_fsm = ICACHE_MISS_INVAL;
1651	}
1652	else
1653	{
1654	r_icache_fsm = ICACHE_MISS_WAIT;
1655	}
1656	}
1657	break;
1658	}
1659	///////////////////////
1660	case ICACHE_MISS_INVAL: // invalidate the victim line
1661	{
1662	paddr_t nline;
1663	bool hit;
1664
1665	hit = r_icache.inval( r_icache_miss_way.read(),
1666	r_icache_miss_set.read(),
1667	&nline ); // unused
1668	assert(hit && "selected way/set line should be in icache");
1669
1670	r_icache_fsm = ICACHE_MISS_WAIT;
1671	break;
1672	}
1673	//////////////////////
1674	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1675	{
1676	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1677
1678	// external coherence request
1679	if ( r_tgt_icache_req.read() )
1680	{
1681	r_icache_fsm = ICACHE_CC_CHECK;
1682	r_icache_fsm_save = r_icache_fsm.read();
1683	break;
1684	}
1685
1686	if ( r_vci_rsp_ins_error.read() ) // bus error
1687	{
1688	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1689	r_mmu_ibvar = r_icache_vaddr_save.read();
1690	m_irsp.valid = true;
1691	m_irsp.error = true;
1692	r_vci_rsp_ins_error = false;
1693	r_icache_fsm = ICACHE_IDLE;
1694	}
1695	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1696	{
1697	r_icache_miss_word = 0;
1698	r_icache_fsm = ICACHE_MISS_UPDT;
1699	}
1700	break;
1701	}
1702	//////////////////////
1703	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1704	{
1705	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1706
1707	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1708	{
1709	if ( r_icache_miss_inval ) // Matching coherence request
1710	// We pop the response FIFO, without updating the cache
1711	// We send a cleanup for the missing line at the last word
1712	// Blocked if the previous cleanup is not completed
1713	{
1714	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1715	{
1716	vci_rsp_fifo_icache_get = true;
1717	r_icache_miss_word = r_icache_miss_word.read() + 1;
1718	}
1719	else // last word
1720	{
1721	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1722	{
1723	vci_rsp_fifo_icache_get = true;
1724	r_icache_cleanup_req = true;
1725	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1726	r_icache_miss_inval = false;
1727	r_icache_fsm = ICACHE_IDLE;
1728	}
1729	}
1730	}
1731	else // No matching coherence request
1732	// We pop the FIFO and update the cache
1733	// We update the directory at the last word
1734	{
1735
1736	#ifdef INSTRUMENTATION
1737	m_cpt_icache_data_write++;
1738	#endif
1739	r_icache.write( r_icache_miss_way.read(),
1740	r_icache_miss_set.read(),
1741	r_icache_miss_word.read(),
1742	r_vci_rsp_fifo_icache.read() );
1743	vci_rsp_fifo_icache_get = true;
1744	r_icache_miss_word = r_icache_miss_word.read() + 1;
1745	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1746	{
1747
1748	#ifdef INSTRUMENTATION
1749	m_cpt_icache_dir_write++;
1750	#endif
1751	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1752	r_icache_miss_way.read(),
1753	r_icache_miss_set.read() );
1754	r_icache_fsm = ICACHE_IDLE;
1755	}
1756	}
1757	}
1758	break;
1759	}
1760	////////////////////
1761	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1762	//
1763	{
1764	// external coherence request
1765	if ( r_tgt_icache_req.read() )
1766	{
1767	r_icache_fsm = ICACHE_CC_CHECK;
1768	r_icache_fsm_save = r_icache_fsm.read();
1769	break;
1770	}
1771
1772	if ( r_vci_rsp_ins_error.read() ) // bus error
1773	{
1774	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1775	r_mmu_ibvar = m_ireq.addr;
1776	r_vci_rsp_ins_error = false;
1777	m_irsp.valid = true;
1778	m_irsp.error = true;
1779	r_icache_fsm = ICACHE_IDLE;
1780	}
1781	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1782	{
1783	vci_rsp_fifo_icache_get = true;
1784	r_icache_fsm = ICACHE_IDLE;
1785	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1786	{
1787	m_irsp.valid = true;
1788	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1789	}
1790	}
1791	break;
1792	}
1793	/////////////////////
1794	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1795	// handling coherence requests.
1796	// the return state is defined in r_icache_fsm_save.
1797	{
1798	paddr_t paddr = r_tgt_paddr.read();
1799	paddr_t mask = ~((m_icache_words<<2)-1);
1800
1801	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1802	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1803	{
1804	r_icache_miss_inval = true; // signaling the matching
1805	r_tgt_icache_req = false; // coherence request completed
1806	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1807	r_icache_fsm = r_icache_fsm_save.read();
1808	}
1809	else // no match
1810	{
1811
1812	#ifdef INSTRUMENTATION
1813	m_cpt_icache_dir_read++;
1814	#endif
1815	uint32_t inst;
1816	size_t way;
1817	size_t set;
1818	size_t word;
1819	bool hit = r_icache.read(paddr,
1820	&inst,
1821	&way,
1822	&set,
1823	&word);
1824	r_icache_cc_way = way;
1825	r_icache_cc_set = set;
1826
1827	if ( hit and r_tgt_update.read() ) // hit update
1828	{
1829	r_icache_fsm = ICACHE_CC_UPDT;
1830	r_icache_cc_word = r_tgt_word_min.read();
1831	}
1832	else if ( hit and not r_tgt_update.read() ) // hit inval
1833	{
1834	r_icache_fsm = ICACHE_CC_INVAL;
1835	}
1836	else // miss can happen
1837	{
1838	r_tgt_icache_req = false;
1839	r_tgt_icache_rsp = r_tgt_update.read();
1840	r_icache_fsm = r_icache_fsm_save.read();
1841	}
1842	}
1843	break;
1844	}
1845
1846	/////////////////////
1847	case ICACHE_CC_INVAL: // invalidate a cache line
1848	{
1849	paddr_t nline;
1850	bool hit;
1851	hit = r_icache.inval( r_icache_cc_way.read(),
1852	r_icache_cc_set.read(),
1853	&nline );
1854	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1855	r_tgt_icache_req = false;
1856	r_tgt_icache_rsp = true;
1857	r_icache_fsm = r_icache_fsm_save.read();
1858	break;
1859	}
1860	////////////////////
1861	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1862	{
1863	size_t word = r_icache_cc_word.read();
1864	size_t way = r_icache_cc_way.read();
1865	size_t set = r_icache_cc_set.read();
1866
1867	r_icache.write( way,
1868	set,
1869	word,
1870	r_tgt_buf[word],
1871	r_tgt_be[word] );
1872
1873	r_icache_cc_word = word+1;
1874
1875	if ( word == r_tgt_word_max.read() ) // last word
1876	{
1877	r_tgt_icache_req = false;
1878	r_tgt_icache_rsp = true;
1879	r_icache_fsm = r_icache_fsm_save.read();
1880	}
1881	break;
1882	}
1883
1884	} // end switch r_icache_fsm
1885
1886	////////////////////////////////////////////////////////////////////////////////////
1887	// DCACHE FSM
1888	//
1889	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1890	// the cacheability, depending on the MMU mode.
1891	//
1892	// 1/ Coherence requests :
1893	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1894	// requesting a line invalidation or a line update.
1895	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1896	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1897	// goes to the CC_CHECK state to execute the requested action, and returns to the
1898	// pre-empted state.
1899	//
1900	// 2/ TLB miss
1901	// The page tables can be cacheable.
1902	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1903	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1904	// this sub-fsm implement the table-walk...
1905	//
1906	// 3/ processor requests :
1907	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1908	// The IDLE state implements a three stages pipe-line to handle write bursts:
1909	// - The physical address is computed by dtlb in stage P0.
1910	// - The registration in wbuf and the dcache hit are computed in stage P1.
1911	// - The dcache update is done in stage P2.
1912	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1913	// that is done (before handling the processor request) by a dedicated sub-fsm
1914	// (DCACHE_DIRTY_TLB_SET state).
1915	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1916	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1917	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1918	// (virtual address for itlb, and speculative physical address computed during
1919	// previous cycle for dcache) in order to return the data in one cycle for a READ
1920	// request. We just pay an extra cycle when the speculative access is failing.
1921	//
1922	// 4/ Atomic instructions LL/SC
1923	// The LL/SC address can be cacheable or non cacheable.
1924	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1925	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1926	// memory controller.
1927	// - LL requests from the processor are transmitted as standard VCI
1928	// READ transactions (one word / one line, depending on the cacheability).
1929	// - SC requests from the processor are systematically transmitted to the
1930	// memory cache as Compare&swap requests (both the data value stored in the
1931	// r_dcache_ll_data register and the new value).
1932	// The cache is not updated, as this is done in case of success by the
1933	// coherence transaction.
1934	//
1935	// 5/ Non cacheable access:
1936	// This component implement a strong order between non cacheable access
1937	// (read or write) : A new non cacheable VCI transaction starts only when
1938	// the previous non cacheable transaction is completed. Both cacheable and
1939	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1940	// a non cacheable write transaction posted in the write buffer by setting the
1941	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1942	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1943	// pending non cacheable write transaction completes).
1944	//
1945	// 6/ Error handling:
1946	// When the MMU is not activated, Read Bus Errors are synchronous events,
1947	// but Write Bus Errors are asynchronous events (processor is not frozen).
1948	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1949	// r_vci_rsp_data_error flip-flop, without writing any data in the
1950	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1951	// by the DCACHE FSM.
1952	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1953	// the asynchronous error using the setWriteBerr() method.
1954	// When the MMU is activated bus error are rare events, as the MMU
1955	// checks the physical address before the VCI transaction starts.
1956	////////////////////////////////////////////////////////////////////////////////////////
1957
1958	// default value for m_drsp
1959	m_drsp.valid = false;
1960	m_drsp.error = false;
1961	m_drsp.rdata = 0;
1962
1963	switch ( r_dcache_fsm.read() )
1964	{
1965	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1966	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1967	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1968	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1969	// 4) XTN request (processor) => DCACHE_XTN_*
1970	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1971	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1972	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1973	// 8) SC access (processor) => DCACHE_SC_WAIT
1974	//
1975	// The dtlb is unconditionally accessed to translate the
1976	// virtual adress from processor.
1977	//
1978	// There is 4 configurations to access the cache,
1979	// depending on the pipe-line state, defined
1980	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1981	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1982	// V0 / V1 / Data / Directory / comment
1983	// 0 / 0 / read(A0) / read(A0) / read speculative access
1984	// 0 / 1 / write(A2) / nop / read request delayed
1985	// 1 / 0 / nop / read(A1) / read request delayed
1986	// 1 / 1 / write(A2) / read(A1) / read request delayed
1987	{
1988	bool tlb_inval_required = false;
1989	bool write_pipe_frozen = false;
1990
1991	////////////////////////////////////////////////////////////////////////////////
1992	// Handling P2 pipe-line stage
1993	// Inputs are r_dcache_p1_* registers.
1994	// If r_dcache_p1_valid is true, we update the local copy in dcache.
1995	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
1996	// operation, going to DCACHE_INVAL_TLB_SCAN state.
1997
1998	if ( r_dcache_p1_valid.read() ) // P2 stage activated
1999	{
2000	size_t way = r_dcache_p1_cache_way.read();
2001	size_t set = r_dcache_p1_cache_set.read();
2002	size_t word = r_dcache_p1_cache_word.read();
2003	uint32_t wdata = r_dcache_p1_wdata.read();
2004	vci_be_t be = r_dcache_p1_be.read();
2005
2006	r_dcache.write( way,
2007	set,
2008	word,
2009	wdata,
2010	be );
2011	#ifdef INSTRUMENTATION
2012	m_cpt_dcache_data_write++;
2013	#endif
2014	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2015	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2016	{
2017	tlb_inval_required = true;
2018	r_dcache_tlb_inval_count = 0;
2019	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2020	(uint32_log2(m_dcache_words<<2));
2021	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2022	}
2023	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2024	{
2025	r_itlb.reset();
2026	r_dtlb.reset();
2027	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2028	}
2029
2030	#if DEBUG_DCACHE
2031	if ( m_debug_dcache_fsm )
2032	{
2033	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2034	<< " / WAY = " << way
2035	<< " / SET = " << set
2036	<< " / WORD = " << word << std::hex
2037	<< " / DATA = " << wdata
2038	<< " / BE = " << be << std::endl;
2039	}
2040	#endif
2041	} // end P2 stage
2042
2043	///////////////////////////////////////////////////////////////////////////
2044	// Handling P1 pipe-line stage
2045	// Inputs are r_dcache_p0_* registers.
2046	// We must write into wbuf and test the hit in dcache.
2047	// If the write request is non cacheable, and there is a pending
2048	// non cacheable write, or if the write buffer is full, the P0 and P1 stages
2049	// are frozen until the write request registration is possible,
2050	// while the P2 stage is not frozen.
2051	// The r_dcache_p1_valid bit must be computed at all cycles, and
2052	// the P2 stage must be activated if there is a local copy in dcache.
2053
2054	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2055	{
2056	// frozen if write not cacheable, and previous non cacheable write registered
2057	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2058	{
2059	r_dcache_p1_valid = false;
2060	write_pipe_frozen = true;
2061	}
2062	else // try a registration into write buffer
2063	{
2064
2065	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2066	r_dcache_p0_be.read(),
2067	r_dcache_p0_wdata.read(),
2068	r_dcache_p0_cacheable.read() );
2069	#ifdef INSTRUMENTATION
2070	m_cpt_wbuf_write++;
2071	#endif
2072	if ( not wok ) // frozen if write buffer full
2073	{
2074	r_dcache_p1_valid = false;
2075	write_pipe_frozen = true;
2076	}
2077	else // update the write_buffer state extension
2078	{
2079	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2080
2081	// read directory to check local copy
2082	size_t cache_way;
2083	size_t cache_set;
2084	size_t cache_word;
2085	bool local_copy;
2086	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2087	{
2088	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2089	&cache_way,
2090	&cache_set,
2091	&cache_word );
2092	#ifdef INSTRUMENTATION
2093	m_cpt_dcache_dir_read++;
2094	#endif
2095	}
2096	else
2097	{
2098	local_copy = false;
2099	}
2100
2101	// store values for P2 pipe stage
2102	if ( local_copy )
2103	{
2104	r_dcache_p1_valid = true;
2105	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2106	r_dcache_p1_be = r_dcache_p0_be.read();
2107	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2108	r_dcache_p1_cache_way = cache_way;
2109	r_dcache_p1_cache_set = cache_set;
2110	r_dcache_p1_cache_word = cache_word;
2111	}
2112	else
2113	{
2114	r_dcache_p1_valid = false;
2115	}
2116	}
2117	}
2118	}
2119	else // P1 stage not activated
2120	{
2121	r_dcache_p1_valid = false;
2122	} // end P1 stage
2123
2124	/////////////////////////////////////////////////////////////////////////////////
2125	// handling P0 pipe-line stage
2126	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2127	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2128	// - the TLB invalidate requests have the highest priority,
2129	// - then the external coherence requests,
2130	// - then the itlb miss requests,
2131	// - and finally the processor requests.
2132	// If dtlb is activated, there is an unconditionnal access to dtlb,
2133	// for address translation.
2134	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2135	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2136	// handled by the IDLE state), and the processor request is acknowledged.
2137	// 2) A processor READ or LL request generate a simultaneouss access to
2138	// both dcache data and dcache directoty, using speculative PPN, but
2139	// is delayed if the write pipe-line is not empty.
2140	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2141	// DCACHE_MISS_WAIT states.
2142	// 3) A processor SC request is delayed until the write pipe-line is empty.
2143	// A VCI SC transaction is launched, and we wait the VCI response in
2144	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2145	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2146	// The data is not modified in dcache, as it will be done by the
2147	// coherence transaction.
2148
2149	// TLB inval required after a write hit
2150	if ( tlb_inval_required )
2151	{
2152	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2153	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2154	r_dcache_p0_valid = false;
2155	}
2156	// external coherence request
2157	else if ( r_tgt_dcache_req.read() )
2158	{
2159	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2160	r_dcache_fsm = DCACHE_CC_CHECK;
2161	r_dcache_p0_valid = false;
2162	}
2163
2164	// itlb miss request
2165	else if ( r_icache_tlb_miss_req.read() )
2166	{
2167	r_dcache_tlb_ins = true;
2168	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2169	r_dcache_fsm = DCACHE_TLB_MISS;
2170	r_dcache_p0_valid = false;
2171	}
2172
2173	// processor request
2174	else if ( m_dreq.valid and not write_pipe_frozen )
2175	{
2176	// dcache access using speculative PPN only if pipe-line empty
2177	paddr_t cache_paddr;
2178	size_t cache_way;
2179	size_t cache_set;
2180	size_t cache_word;
2181	uint32_t cache_rdata;
2182	bool cache_hit;
2183
2184	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2185	not r_dcache_p0_valid.read() and
2186	not r_dcache_p1_valid.read() ) // pipe-line empty
2187	{
2188	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2189	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2190
2191	cache_hit = r_dcache.read( cache_paddr,
2192	&cache_rdata,
2193	&cache_way,
2194	&cache_set,
2195	&cache_word );
2196	#ifdef INSTRUMENTATION
2197	m_cpt_dcache_dir_read++;
2198	m_cpt_dcache_data_read++;
2199	#endif
2200	}
2201	else
2202	{
2203	cache_hit = false;
2204	} // end dcache access
2205
2206	// systematic dtlb access using virtual address
2207	paddr_t tlb_paddr;
2208	pte_info_t tlb_flags;
2209	size_t tlb_way;
2210	size_t tlb_set;
2211	paddr_t tlb_nline;
2212	bool tlb_hit;
2213
2214	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2215	{
2216	tlb_hit = r_dtlb.translate( m_dreq.addr,
2217	&tlb_paddr,
2218	&tlb_flags,
2219	&tlb_nline,
2220	&tlb_way,
2221	&tlb_set );
2222	#ifdef INSTRUMENTATION
2223	m_cpt_dtlb_read++;
2224	#endif
2225	}
2226	else
2227	{
2228	tlb_hit = false;
2229	} // end dtlb access
2230
2231	// register the processor request
2232	r_dcache_p0_vaddr = m_dreq.addr;
2233	r_dcache_p0_be = m_dreq.be;
2234	r_dcache_p0_wdata = m_dreq.wdata;
2235
2236	// Handling READ XTN requests from processor
2237	// They are executed in this DCACHE_IDLE state.
2238	// The processor must not be in user mode
2239	if (m_dreq.type == iss_t::XTN_READ)
2240	{
2241	int xtn_opcode = (int)m_dreq.addr/4;
2242
2243	// checking processor mode:
2244	if (m_dreq.mode == iss_t::MODE_USER)
2245	{
2246	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2247	r_mmu_dbvar = m_dreq.addr;
2248	m_drsp.valid = true;
2249	m_drsp.error = true;
2250	r_dcache_fsm = DCACHE_IDLE;
2251	}
2252	else
2253	{
2254	switch( xtn_opcode )
2255	{
2256	case iss_t::XTN_INS_ERROR_TYPE:
2257	m_drsp.rdata = r_mmu_ietr.read();
2258	m_drsp.valid = true;
2259	break;
2260
2261	case iss_t::XTN_DATA_ERROR_TYPE:
2262	m_drsp.rdata = r_mmu_detr.read();
2263	m_drsp.valid = true;
2264	break;
2265
2266	case iss_t::XTN_INS_BAD_VADDR:
2267	m_drsp.rdata = r_mmu_ibvar.read();
2268	m_drsp.valid = true;
2269	break;
2270
2271	case iss_t::XTN_DATA_BAD_VADDR:
2272	m_drsp.rdata = r_mmu_dbvar.read();
2273	m_drsp.valid = true;
2274	break;
2275
2276	case iss_t::XTN_PTPR:
2277	m_drsp.rdata = r_mmu_ptpr.read();
2278	m_drsp.valid = true;
2279	break;
2280
2281	case iss_t::XTN_TLB_MODE:
2282	m_drsp.rdata = r_mmu_mode.read();
2283	m_drsp.valid = true;
2284	break;
2285
2286	case iss_t::XTN_MMU_PARAMS:
2287	m_drsp.rdata = r_mmu_params;
2288	m_drsp.valid = true;
2289	break;
2290
2291	case iss_t::XTN_MMU_RELEASE:
2292	m_drsp.rdata = r_mmu_release;
2293	m_drsp.valid = true;
2294	break;
2295
2296	case iss_t::XTN_MMU_WORD_LO:
2297	m_drsp.rdata = r_mmu_word_lo.read();
2298	m_drsp.valid = true;
2299	break;
2300
2301	case iss_t::XTN_MMU_WORD_HI:
2302	m_drsp.rdata = r_mmu_word_hi.read();
2303	m_drsp.valid = true;
2304	break;
2305
2306	default:
2307	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2308	r_mmu_dbvar = m_dreq.addr;
2309	m_drsp.valid = true;
2310	m_drsp.error = true;
2311	break;
2312	} // end switch xtn_opcode
2313	} // end else
2314	r_dcache_p0_valid = false;
2315	} // end if XTN_READ
2316
2317	// Handling WRITE XTN requests from processor.
2318	// They are not executed in this DCACHE_IDLE state,
2319	// if they require access to the caches or the TLBs
2320	// that are already accessed for speculative read.
2321	// Caches can be invalidated or flushed in user mode,
2322	// and the sync instruction can be executed in user mode
2323	else if (m_dreq.type == iss_t::XTN_WRITE)
2324	{
2325	int xtn_opcode = (int)m_dreq.addr/4;
2326	r_dcache_xtn_opcode = xtn_opcode;
2327
2328	// checking processor mode:
2329	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2330	(xtn_opcode != iss_t:: XTN_SYNC) &&
2331	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2332	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2333	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2334	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2335	{
2336	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2337	r_mmu_dbvar = m_dreq.addr;
2338	m_drsp.valid = true;
2339	m_drsp.error = true;
2340	r_dcache_fsm = DCACHE_IDLE;
2341	}
2342	else
2343	{
2344	switch( xtn_opcode )
2345	{
2346	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2347	r_mmu_ptpr = m_dreq.wdata;
2348	r_dcache_xtn_req = true;
2349	r_dcache_fsm = DCACHE_XTN_SWITCH;
2350	break;
2351
2352	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2353	r_mmu_mode = m_dreq.wdata;
2354	m_drsp.valid = true;
2355	r_dcache_fsm = DCACHE_IDLE;
2356	break;
2357
2358	case iss_t::XTN_DTLB_INVAL: // dtlb access
2359	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2360	break;
2361
2362	case iss_t::XTN_ITLB_INVAL: // itlb access
2363	r_dcache_xtn_req = true;
2364	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2365	break;
2366
2367	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2368	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2369	break;
2370
2371	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2372	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2373	if (sizeof(paddr_t) <= 32) {
2374	assert(r_mmu_word_hi.read() == 0 &&
2375	"high bits should be 0 for 32bit paddr");
2376	r_dcache_p0_paddr =
2377	(paddr_t)r_mmu_word_lo.read();
2378	} else {
2379	r_dcache_p0_paddr =
2380	(paddr_t)r_mmu_word_hi.read() << 32 \|
2381	(paddr_t)r_mmu_word_lo.read();
2382	}
2383	break;
2384
2385	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2386	r_dcache_flush_count = 0;
2387	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2388	break;
2389
2390	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2391	r_dcache_xtn_req = true;
2392	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2393	break;
2394
2395	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2396	r_dcache_xtn_req = true;
2397	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2398	break;
2399
2400	case iss_t::XTN_ICACHE_FLUSH: // icache access
2401	r_dcache_xtn_req = true;
2402	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2403	break;
2404
2405	case iss_t::XTN_SYNC: // wait until write buffer empty
2406	r_dcache_fsm = DCACHE_XTN_SYNC;
2407	break;
2408
2409	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2410	r_mmu_word_lo = m_dreq.wdata;
2411	m_drsp.valid = true;
2412	r_dcache_fsm = DCACHE_IDLE;
2413	break;
2414
2415	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2416	r_mmu_word_hi = m_dreq.wdata;
2417	m_drsp.valid = true;
2418	r_dcache_fsm = DCACHE_IDLE;
2419	break;
2420
2421	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2422	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2423	m_drsp.valid = true;
2424	r_dcache_fsm = DCACHE_IDLE;
2425	break;
2426
2427	default:
2428	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2429	r_mmu_dbvar = m_dreq.addr;
2430	m_drsp.valid = true;
2431	m_drsp.error = true;
2432	r_dcache_fsm = DCACHE_IDLE;
2433	break;
2434	} // end switch xtn_opcode
2435	} // end else
2436	r_dcache_p0_valid = false;
2437	} // end if XTN_WRITE
2438
2439	// Handling read/write/ll/sc processor requests.
2440	// The dtlb and dcache can be activated or not.
2441	// We compute the physical address, the cacheability, and check processor request.
2442	// - If DTLB not activated : cacheability is defined by the segment table,
2443	// the physical address is equal to the virtual address (identity mapping)
2444	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2445	// the physical address is obtained from the TLB, and the U & W bits
2446	// of the PTE are checked.
2447	// The processor request is decoded only if the TLB is not activated or if
2448	// the virtual address hits in tLB and access rights are OK.
2449	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2450	else
2451	{
2452	bool valid_req = false;
2453	bool cacheable = false;
2454	paddr_t paddr = 0;
2455
2456	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2457	{
2458	valid_req = true;
2459
2460	// cacheability
2461	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2462	else cacheable = m_cacheability_table[m_dreq.addr];
2463
2464	// physical address
2465	paddr = (paddr_t)m_dreq.addr;
2466	}
2467	else // dtlb activated
2468	{
2469	if ( tlb_hit ) // tlb hit
2470	{
2471	// cacheability
2472	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2473	else cacheable = tlb_flags.c;
2474
2475	// access rights checking
2476	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2477	{
2478	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2479	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2480	else
2481	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2482
2483	r_mmu_dbvar = m_dreq.addr;
2484	m_drsp.valid = true;
2485	m_drsp.error = true;
2486	m_drsp.rdata = 0;
2487	#if DEBUG_DCACHE
2488	if ( m_debug_dcache_fsm )
2489	{
2490	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2491	}
2492	#endif
2493	}
2494	else if ( not tlb_flags.w and
2495	((m_dreq.type == iss_t::DATA_WRITE) or
2496	(m_dreq.type == iss_t::DATA_SC)) )
2497	{
2498	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2499	r_mmu_dbvar = m_dreq.addr;
2500	m_drsp.valid = true;
2501	m_drsp.error = true;
2502	m_drsp.rdata = 0;
2503	#if DEBUG_DCACHE
2504	if ( m_debug_dcache_fsm )
2505	{
2506	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2507	}
2508	#endif
2509	}
2510	else
2511	{
2512	valid_req = true;
2513	}
2514
2515	// physical address
2516	paddr = tlb_paddr;
2517	}
2518	else // tlb miss
2519	{
2520	r_dcache_tlb_vaddr = m_dreq.addr;
2521	r_dcache_tlb_ins = false;
2522	r_dcache_fsm = DCACHE_TLB_MISS;
2523	}
2524	} // end DTLB activated
2525
2526	if ( valid_req ) // processor request is valid after TLB check
2527	{
2528	// physical address and cacheability registration
2529	r_dcache_p0_paddr = paddr;
2530	r_dcache_p0_cacheable = cacheable;
2531
2532	// READ or LL request
2533	// The read requests are taken only if the write pipe-line is empty.
2534	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2535	// If speculative access is KO we just pay one extra cycle.
2536	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2537	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2538	// In case of LL, the LL registration is done when the data is returned:
2539	// in DCACHE_IDLE if cacheable / in DCACHE_UNC_WAIT if uncacheable
2540	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2541	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2542	{
2543	if ( cacheable ) // cacheable read
2544	{
2545	// if the speculative access is illegal, we pay an extra cycle
2546	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2547	!= (paddr & ~PAGE_K_MASK))
2548	{
2549	#ifdef INSTRUMENTATION
2550	m_cpt_dcache_spec_miss++;
2551	#endif
2552	#if DEBUG_DCACHE
2553	if ( m_debug_dcache_fsm )
2554	{
2555	std::cout << " <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
2556	}
2557	#endif
2558	}
2559	// if cache miss, try to get the missing line
2560	else if ( not cache_hit )
2561	{
2562	#ifdef INSTRUMENTATION
2563	m_cpt_dcache_miss++;
2564	#endif
2565	r_dcache_vci_paddr = paddr;
2566	r_dcache_vci_miss_req = true;
2567	r_dcache_miss_type = PROC_MISS;
2568	r_dcache_fsm = DCACHE_MISS_VICTIM;
2569	}
2570	// if cache hit return the data
2571	else
2572	{
2573	#ifdef INSTRUMENTATION
2574	m_cpt_data_read++;
2575	#endif
2576	m_drsp.valid = true;
2577	m_drsp.rdata = cache_rdata;
2578
2579	// makes reservation in case of LL
2580	if ( m_dreq.type == iss_t::DATA_LL )
2581	{
2582	r_dcache_ll_valid = true;
2583	r_dcache_ll_vaddr = m_dreq.addr;
2584	r_dcache_ll_data = cache_rdata;
2585	}
2586	#if DEBUG_DCACHE
2587	if ( m_debug_dcache_fsm )
2588	{
2589	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2590	}
2591	#endif
2592	}
2593	}
2594	else // uncacheable read
2595	{
2596	r_dcache_vci_paddr = paddr;
2597	r_dcache_vci_unc_be = m_dreq.be;
2598	r_dcache_vci_unc_req = true;
2599	r_dcache_fsm = DCACHE_UNC_WAIT;
2600	}
2601
2602	r_dcache_p0_valid = false;
2603	} // end READ or LL
2604
2605	// WRITE request:
2606	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2607	// the processor and set the Dirty bit before handling the write request.
2608	// If we don't need to set the Dirty bit, we can acknowledge
2609	// the processor request, as the write arguments (including the
2610	// physical address) are registered in r_dcache_p0 registers:
2611	// We simply activate the P1 pipeline stage.
2612	else if ( m_dreq.type == iss_t::DATA_WRITE )
2613	{
2614	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2615	and not tlb_flags.d ) // Dirty bit must be set
2616	{
2617	// The PTE physical address is obtained from the nline value (dtlb),
2618	// and the word index (proper bits of the virtual address)
2619	if ( tlb_flags.b ) // PTE1
2620	{
2621	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2622	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2623	}
2624	else // PTE2
2625	{
2626	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2627	(paddr_t)((m_dreq.addr>>9) & 0x38);
2628	}
2629	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2630	r_dcache_p0_valid = false;
2631	}
2632	else // Write request accepted
2633	{
2634	#ifdef INSTRUMENTATION
2635	m_cpt_data_write++;
2636	#endif
2637	m_drsp.valid = true;
2638	m_drsp.rdata = 0;
2639	r_dcache_p0_valid = true;
2640	}
2641	} // end WRITE
2642
2643	// SC request:
2644	// The SC requests are taken only if the write pipe-line is empty.
2645	// - if there is no valid registered LL, we just return rdata = 1
2646	// (atomic access failed) and the SC transaction is completed.
2647	// - if a valid LL reservation (with the same address) is registered,
2648	// we test if a DIRTY bit update is required.
2649	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2650	// the processor and set the Dirty bit before handling the write request.
2651	// If we don't need to set the Dirty bit, we request a SC transaction
2652	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2653	// the response to the processor.
2654	// We don't check a possible write hit in dcache, as the cache update
2655	// is done by the coherence transaction induced by the SC...
2656	else if ( ( m_dreq.type == iss_t::DATA_SC )
2657	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2658	{
2659	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2660	or not r_dcache_ll_valid.read() ) // no valid registered LL
2661	{
2662	#ifdef INSTRUMENTATION
2663	m_cpt_data_sc++;
2664	#endif
2665	m_drsp.valid = true;
2666	m_drsp.rdata = 1;
2667	r_dcache_ll_valid = false;
2668	}
2669	else // valid registered LL
2670	{
2671	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2672	and not tlb_flags.d ) // Dirty bit must be set
2673	{
2674	// The PTE physical address is obtained from the nline value (dtlb),
2675	// and the word index (virtual address)
2676	if ( tlb_flags.b ) // PTE1
2677	{
2678	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2679	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2680	}
2681	else // PTE2
2682	{
2683	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2684	(paddr_t)((m_dreq.addr>>9) & 0x38);
2685	}
2686	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2687	}
2688	else // SC request accepted
2689	{
2690	#ifdef INSTRUMENTATION
2691	m_cpt_data_sc++;
2692	#endif
2693
2694	r_dcache_vci_paddr = paddr;
2695	r_dcache_vci_sc_req = true;
2696	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2697	r_dcache_vci_sc_new = m_dreq.wdata;
2698	r_dcache_ll_valid = false;
2699	r_dcache_fsm = DCACHE_SC_WAIT;
2700	}
2701	}
2702	r_dcache_p0_valid = false;
2703	} // end SC
2704	else
2705	{
2706	r_dcache_p0_valid = false;
2707	}
2708	} // end valid_req
2709	else
2710	{
2711	r_dcache_p0_valid = false;
2712	}
2713	} // end if read/write/ll/sc request
2714	} // end dreq.valid
2715	else
2716	{
2717	r_dcache_p0_valid = false;
2718	} // end P0 pipe stage
2719	break;
2720	}
2721	/////////////////////
2722	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2723	// Input arguments are:
2724	// - r_dcache_tlb_vaddr
2725	// - r_dcache_tlb_ins (true when itlb miss)
2726	// The sub-fsm access the dcache to find the missing TLB entry,
2727	// and activates the cache miss procedure in case of miss.
2728	// It bypass the first level page table access if possible.
2729	// It uses atomic access to update the R/L access bits
2730	// in the page table if required.
2731	// It directly updates the itlb or dtlb, and writes into the
2732	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2733	{
2734	uint32_t ptba = 0;
2735	bool bypass;
2736	paddr_t pte_paddr;
2737
2738	// evaluate bypass in order to skip first level page table access
2739	if ( r_dcache_tlb_ins.read() ) // itlb miss
2740	{
2741	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2742	}
2743	else // dtlb miss
2744	{
2745	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2746	}
2747
2748	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2749	{
2750	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2751	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2752	r_dcache_tlb_paddr = pte_paddr;
2753	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2754	}
2755	else // Try to read PTE2 in dcache
2756	{
2757	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2758	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2759	r_dcache_tlb_paddr = pte_paddr;
2760	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2761	}
2762
2763	#if DEBUG_DCACHE
2764	if ( m_debug_dcache_fsm )
2765	{
2766	if ( r_dcache_tlb_ins.read() )
2767	{
2768	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2769	}
2770	else
2771	{
2772	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2773	}
2774	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2775	<< " / BYPASS = " << bypass
2776	<< " / PTE_ADR = " << pte_paddr << std::endl;
2777	}
2778	#endif
2779
2780	break;
2781	}
2782	/////////////////////////
2783	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2784	{
2785	uint32_t entry;
2786	size_t way;
2787	size_t set;
2788	size_t word;
2789
2790	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2791	&entry,
2792	&way,
2793	&set,
2794	&word );
2795	#ifdef INSTRUMENTATION
2796	m_cpt_dcache_data_read++;
2797	m_cpt_dcache_dir_read++;
2798	#endif
2799	if ( hit ) // hit in dcache
2800	{
2801	if ( not (entry & PTE_V_MASK) ) // unmapped
2802	{
2803	if ( r_dcache_tlb_ins.read() )
2804	{
2805	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2806	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2807	r_icache_tlb_miss_req = false;
2808	r_icache_tlb_rsp_error = true;
2809	}
2810	else
2811	{
2812	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2813	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2814	m_drsp.valid = true;
2815	m_drsp.error = true;
2816	}
2817	r_dcache_fsm = DCACHE_IDLE;
2818
2819	#if DEBUG_DCACHE
2820	if ( m_debug_dcache_fsm )
2821	{
2822	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2823	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2824	<< std::dec << " / way = " << way
2825	<< std::dec << " / set = " << set
2826	<< std::dec << " / word = " << word
2827	<< std::hex << " / PTE1 = " << entry << std::endl;
2828	}
2829	#endif
2830
2831	}
2832	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2833	{
2834	// mark the cache line ac containing a PTD
2835	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2836
2837	// register bypass
2838	if ( r_dcache_tlb_ins.read() ) // itlb
2839	{
2840	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2841	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2842	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2843	}
2844	else // dtlb
2845	{
2846	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2847	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2848	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2849	}
2850	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2851	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2852	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2853
2854	#if DEBUG_DCACHE
2855	if ( m_debug_dcache_fsm )
2856	{
2857	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2858	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2859	<< std::dec << " / way = " << way
2860	<< std::dec << " / set = " << set
2861	<< std::dec << " / word = " << word
2862	<< std::hex << " / PTD = " << entry << std::endl;
2863	}
2864	#endif
2865	}
2866	else // PTE1 : we must update the TLB
2867	{
2868	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2869	r_dcache_tlb_pte_flags = entry;
2870	r_dcache_tlb_cache_way = way;
2871	r_dcache_tlb_cache_set = set;
2872	r_dcache_tlb_cache_word = word;
2873	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2874
2875	#if DEBUG_DCACHE
2876	if ( m_debug_dcache_fsm )
2877	{
2878	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2879	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2880	<< std::dec << " / way = " << way
2881	<< std::dec << " / set = " << set
2882	<< std::dec << " / word = " << word
2883	<< std::hex << " / PTE1 = " << entry << std::endl;
2884	}
2885	#endif
2886	}
2887	}
2888	else // we must load the missing cache line in dcache
2889	{
2890	r_dcache_vci_miss_req = true;
2891	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2892	r_dcache_miss_type = PTE1_MISS;
2893	r_dcache_fsm = DCACHE_MISS_VICTIM;
2894
2895	#if DEBUG_DCACHE
2896	if ( m_debug_dcache_fsm )
2897	{
2898	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2899	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2900	}
2901	#endif
2902	}
2903	break;
2904	}
2905	////////////////////////////
2906	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2907	{
2908	size_t way;
2909	size_t set;
2910
2911	if ( r_dcache_tlb_ins.read() )
2912	{
2913	r_itlb.select( r_dcache_tlb_vaddr.read(),
2914	true, // PTE1
2915	&way,
2916	&set );
2917	#ifdef INSTRUMENTATION
2918	m_cpt_itlb_read++;
2919	#endif
2920	}
2921	else
2922	{
2923	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2924	true, // PTE1
2925	&way,
2926	&set );
2927	#ifdef INSTRUMENTATION
2928	m_cpt_dtlb_read++;
2929	#endif
2930	}
2931	r_dcache_tlb_way = way;
2932	r_dcache_tlb_set = set;
2933	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2934
2935	#if DEBUG_DCACHE
2936	if ( m_debug_dcache_fsm )
2937	{
2938	if ( r_dcache_tlb_ins.read() )
2939	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2940	else
2941	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2942	std::cout << " way = " << std::dec << way
2943	<< " / set = " << set << std::endl;
2944	}
2945	#endif
2946	break;
2947	}
2948	//////////////////////////
2949	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2950	// if L/R bit already set, exit the sub-fsm
2951	// if not, the page table must be updated
2952	{
2953	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2954	uint32_t pte = r_dcache_tlb_pte_flags.read();
2955	bool updt = false;
2956	bool local = true;
2957
2958	// We should compute the access locality:
2959	// The PPN MSB bits define the destination cluster index.
2960	// The m_srcid_d MSB bits define the source cluster index.
2961	// The number of bits to compare depends on the number of clusters,
2962	// and can be obtained in the mapping table.
2963	// As long as this computation is not done, all access are local.
2964
2965	if ( local ) // local access
2966	{
2967	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2968	{
2969	updt = true;
2970	r_dcache_vci_sc_old = pte;
2971	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2972	pte = pte \| PTE_L_MASK;
2973	}
2974	}
2975	else // remote access
2976	{
2977	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2978	{
2979	updt = true;
2980	r_dcache_vci_sc_old = pte;
2981	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2982	pte = pte \| PTE_R_MASK;
2983	}
2984	}
2985
2986	// update TLB
2987	if ( r_dcache_tlb_ins.read() )
2988	{
2989	r_itlb.write( true, // 2M page
2990	pte,
2991	0, // argument unused for a PTE1
2992	r_dcache_tlb_vaddr.read(),
2993	r_dcache_tlb_way.read(),
2994	r_dcache_tlb_set.read(),
2995	nline );
2996	#ifdef INSTRUMENTATION
2997	m_cpt_itlb_write++;
2998	#endif
2999	}
3000	else
3001	{
3002	r_dtlb.write( true, // 2M page
3003	pte,
3004	0, // argument unused for a PTE1
3005	r_dcache_tlb_vaddr.read(),
3006	r_dcache_tlb_way.read(),
3007	r_dcache_tlb_set.read(),
3008	nline );
3009	#ifdef INSTRUMENTATION
3010	m_cpt_dtlb_write++;
3011	#endif
3012	}
3013	// next state
3014	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3015	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3016
3017	#if DEBUG_DCACHE
3018	if ( m_debug_dcache_fsm )
3019	{
3020	if ( r_dcache_tlb_ins.read() )
3021	{
3022	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3023	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3024	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3025	r_itlb.printTrace();
3026	}
3027	else
3028	{
3029	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3030	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3031	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3032	r_dtlb.printTrace();
3033	}
3034
3035	}
3036	#endif
3037	break;
3038	}
3039	/////////////////////////
3040	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3041	{
3042	uint32_t pte_flags;
3043	uint32_t pte_ppn;
3044	size_t way;
3045	size_t set;
3046	size_t word;
3047
3048	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3049	&pte_flags,
3050	&pte_ppn,
3051	&way,
3052	&set,
3053	&word );
3054	#ifdef INSTRUMENTATION
3055	m_cpt_dcache_data_read++;
3056	m_cpt_dcache_dir_read++;
3057	#endif
3058	if ( hit ) // request hits in dcache
3059	{
3060	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3061	{
3062	if ( r_dcache_tlb_ins.read() )
3063	{
3064	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3065	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3066	r_icache_tlb_miss_req = false;
3067	r_icache_tlb_rsp_error = true;
3068	}
3069	else
3070	{
3071	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3072	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3073	m_drsp.valid = true;
3074	m_drsp.error = true;
3075	}
3076	r_dcache_fsm = DCACHE_IDLE;
3077
3078	#if DEBUG_DCACHE
3079	if ( m_debug_dcache_fsm )
3080	{
3081	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3082	<< " PTE_FLAGS = " << std::hex << pte_flags
3083	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3084	}
3085	#endif
3086	}
3087	else // mapped : we must update the TLB
3088	{
3089	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3090	r_dcache_tlb_pte_flags = pte_flags;
3091	r_dcache_tlb_pte_ppn = pte_ppn;
3092	r_dcache_tlb_cache_way = way;
3093	r_dcache_tlb_cache_set = set;
3094	r_dcache_tlb_cache_word = word;
3095	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3096
3097	#if DEBUG_DCACHE
3098	if ( m_debug_dcache_fsm )
3099	{
3100	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3101	<< " PTE_FLAGS = " << std::hex << pte_flags
3102	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3103	}
3104	#endif
3105	}
3106	}
3107	else // we must load the missing cache line in dcache
3108	{
3109	r_dcache_fsm = DCACHE_MISS_VICTIM;
3110	r_dcache_vci_miss_req = true;
3111	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3112	r_dcache_miss_type = PTE2_MISS;
3113
3114	#if DEBUG_DCACHE
3115	if ( m_debug_dcache_fsm )
3116	{
3117	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3118	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3119	}
3120	#endif
3121	}
3122	break;
3123	}
3124	////////////////////////////
3125	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3126	{
3127	size_t way;
3128	size_t set;
3129
3130	if ( r_dcache_tlb_ins.read() )
3131	{
3132	r_itlb.select( r_dcache_tlb_vaddr.read(),
3133	false, // PTE2
3134	&way,
3135	&set );
3136	#ifdef INSTRUMENTATION
3137	m_cpt_itlb_read++;
3138	#endif
3139	}
3140	else
3141	{
3142	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3143	false, // PTE2
3144	&way,
3145	&set );
3146	#ifdef INSTRUMENTATION
3147	m_cpt_dtlb_read++;
3148	#endif
3149	}
3150
3151	#if DEBUG_DCACHE
3152	if ( m_debug_dcache_fsm )
3153	{
3154	if ( r_dcache_tlb_ins.read() )
3155	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3156	else
3157	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3158	std::cout << " way = " << std::dec << way
3159	<< " / set = " << set << std::endl;
3160	}
3161	#endif
3162	r_dcache_tlb_way = way;
3163	r_dcache_tlb_set = set;
3164	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3165	break;
3166	}
3167	//////////////////////////
3168	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3169	// if L/R bit already set, exit the sub-fsm
3170	// if not, the page table must be updated by an atomic access
3171	{
3172	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3173	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3174	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3175	bool updt = false;
3176	bool local = true;
3177
3178	// We should compute the access locality:
3179	// The PPN MSB bits define the destination cluster index.
3180	// The m_srcid_d MSB bits define the source cluster index.
3181	// The number of bits to compare depends on the number of clusters,
3182	// and can be obtained in the mapping table.
3183	// As long as this computation is not done, all access are local.
3184
3185	if ( local ) // local access
3186	{
3187	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3188	{
3189	updt = true;
3190	r_dcache_vci_sc_old = pte_flags;
3191	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3192	pte_flags = pte_flags \| PTE_L_MASK;
3193	}
3194	}
3195	else // remote access
3196	{
3197	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3198	{
3199	updt = true;
3200	r_dcache_vci_sc_old = pte_flags;
3201	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3202	pte_flags = pte_flags \| PTE_R_MASK;
3203	}
3204	}
3205
3206	// update TLB for a PTE2
3207	if ( r_dcache_tlb_ins.read() )
3208	{
3209	r_itlb.write( false, // 4K page
3210	pte_flags,
3211	pte_ppn,
3212	r_dcache_tlb_vaddr.read(),
3213	r_dcache_tlb_way.read(),
3214	r_dcache_tlb_set.read(),
3215	nline );
3216	#ifdef INSTRUMENTATION
3217	m_cpt_itlb_write++;
3218	#endif
3219	}
3220	else
3221	{
3222	r_dtlb.write( false, // 4K page
3223	pte_flags,
3224	pte_ppn,
3225	r_dcache_tlb_vaddr.read(),
3226	r_dcache_tlb_way.read(),
3227	r_dcache_tlb_set.read(),
3228	nline );
3229	#ifdef INSTRUMENTATION
3230	m_cpt_dtlb_write++;
3231	#endif
3232	}
3233
3234	#if DEBUG_DCACHE
3235	if ( m_debug_dcache_fsm )
3236	{
3237	if ( r_dcache_tlb_ins.read() )
3238	{
3239	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3240	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3241	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3242	r_itlb.printTrace();
3243	}
3244	else
3245	{
3246	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3247	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3248	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3249	r_dtlb.printTrace();
3250	}
3251	}
3252	#endif
3253	// next state
3254	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3255	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3256	break;
3257	}
3258	////////////////////////
3259	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3260	// request a SC transaction to CMD FSM
3261	{
3262	#if DEBUG_DCACHE
3263	if ( m_debug_dcache_fsm )
3264	{
3265	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3266	}
3267	#endif
3268	r_dcache.write(r_dcache_tlb_cache_way.read(),
3269	r_dcache_tlb_cache_set.read(),
3270	r_dcache_tlb_cache_word.read(),
3271	r_dcache_tlb_pte_flags.read());
3272	#ifdef INSTRUMENTATION
3273	m_cpt_dcache_data_write++;
3274	#endif
3275	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3276	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3277	r_dcache_vci_sc_req = true;
3278	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3279	break;
3280	}
3281	////////////////////////
3282	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3283	// We consume the response in rsp FIFO,
3284	// and exit the sub-fsm, but we don't
3285	// analyse the response, because we don't
3286	// care if the L/R bit update is not done.
3287	// We must take the coherence requests because
3288	// there is a risk of dead-lock
3289
3290	{
3291	// external coherence request
3292	if ( r_tgt_dcache_req )
3293	{
3294	r_dcache_fsm = DCACHE_CC_CHECK;
3295	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3296	break;
3297	}
3298
3299	if ( r_vci_rsp_data_error.read() ) // bus error
3300	{
3301	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3302	std::cout << "This should not happen in this state" << std::endl;
3303	exit(0);
3304	}
3305	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3306	{
3307	#if DEBUG_DCACHE
3308	if ( m_debug_dcache_fsm )
3309	{
3310	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3311	}
3312	#endif
3313	vci_rsp_fifo_dcache_get = true;
3314	r_dcache_fsm = DCACHE_TLB_RETURN;
3315	}
3316	break;
3317	}
3318	///////////////////////
3319	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3320	{
3321	#if DEBUG_DCACHE
3322	if ( m_debug_dcache_fsm )
3323	{
3324	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3325	}
3326	#endif
3327	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3328	r_dcache_fsm = DCACHE_IDLE;
3329	break;
3330	}
3331	///////////////////////
3332	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3333	{
3334	if ( not r_dcache_xtn_req.read() )
3335	{
3336	r_dtlb.flush();
3337	r_dcache_fsm = DCACHE_IDLE;
3338	m_drsp.valid = true;
3339	}
3340	break;
3341	}
3342	/////////////////////
3343	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3344	// The coherence request must be taken
3345	// as there is a risk of dead-lock
3346	{
3347	// external coherence request
3348	if ( r_tgt_dcache_req.read() )
3349	{
3350	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3351	r_dcache_fsm = DCACHE_CC_CHECK;
3352	}
3353
3354	if ( r_wbuf.empty() )
3355	{
3356	m_drsp.valid = true;
3357	r_dcache_fsm = DCACHE_IDLE;
3358	}
3359	break;
3360	}
3361	////////////////////////
3362	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3363	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3364	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3365	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3366	{
3367	// external coherence request
3368	if ( r_tgt_dcache_req )
3369	{
3370	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3371	r_dcache_fsm = DCACHE_CC_CHECK;
3372	break;
3373	}
3374
3375	// itlb miss request
3376	if ( r_icache_tlb_miss_req.read() )
3377	{
3378	r_dcache_tlb_ins = true;
3379	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3380	r_dcache_fsm = DCACHE_TLB_MISS;
3381	break;
3382	}
3383
3384	// test if XTN request to icache completed
3385	if ( not r_dcache_xtn_req.read() )
3386	{
3387	r_dcache_fsm = DCACHE_IDLE;
3388	m_drsp.valid = true;
3389	}
3390	break;
3391	}
3392	/////////////////////////
3393	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3394	// the r_dcache_flush counter as a slot counter.
3395	// We loop in this state until all slots have been visited.
3396	// A cleanup request is generated for each valid line
3397	// and we are blocked until the previous cleanup is completed
3398	// Finally, both the itlb and dtlb are flushed
3399	// (including global entries)
3400	{
3401	if ( not r_dcache_cleanup_req )
3402	{
3403	paddr_t nline;
3404	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3405	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3406
3407	bool cleanup_req = r_dcache.inval( way,
3408	set,
3409	&nline );
3410	if ( cleanup_req )
3411	{
3412	r_dcache_cleanup_req = true;
3413	r_dcache_cleanup_line = nline;
3414	}
3415
3416	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3417	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3418
3419	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3420
3421	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3422	{
3423	r_dtlb.reset();
3424	r_itlb.reset();
3425	r_dcache_fsm = DCACHE_IDLE;
3426	m_drsp.valid = true;
3427	}
3428	}
3429	break;
3430	}
3431	/////////////////////////
3432	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3433	{
3434	r_dtlb.inval(r_dcache_p0_wdata.read());
3435	r_dcache_fsm = DCACHE_IDLE;
3436	m_drsp.valid = true;
3437	break;
3438	}
3439	////////////////////////////
3440	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3441	// requires 3 cycles: access tlb, read cache, inval cache
3442	// we compute the physical address in this state
3443	{
3444	paddr_t paddr;
3445	bool hit;
3446
3447	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3448	{
3449	#ifdef INSTRUMENTATION
3450	m_cpt_dtlb_read++;
3451	#endif
3452	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3453	&paddr );
3454	}
3455	else // dtlb not activated
3456	{
3457	paddr = (paddr_t)r_dcache_p0_wdata.read();
3458	hit = true;
3459	}
3460
3461	if ( hit ) // tlb hit
3462	{
3463	r_dcache_p0_paddr = paddr;
3464	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3465	}
3466	else // tlb miss
3467	{
3468	#ifdef INSTRUMENTATION
3469	m_cpt_dtlb_miss++;
3470	#endif
3471	r_dcache_tlb_ins = false; // dtlb
3472	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3473	r_dcache_fsm = DCACHE_TLB_MISS;
3474	}
3475
3476	#if DEBUG_DCACHE
3477	if ( m_debug_dcache_fsm )
3478	{
3479	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3480	<< " / VADDR = " << r_dcache_p0_wdata.read()
3481	<< " / PADDR = " << paddr << std::endl;
3482	}
3483	#endif
3484
3485	break;
3486	}
3487	////////////////////////////
3488	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3489	// requires 2 cycles: read cache / inval cache
3490	// In this state we read dcache.
3491	{
3492	uint32_t data;
3493	size_t way;
3494	size_t set;
3495	size_t word;
3496	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3497	&data,
3498	&way,
3499	&set,
3500	&word );
3501	#ifdef INSTRUMENTATION
3502	m_cpt_dcache_data_read++;
3503	m_cpt_dcache_dir_read++;
3504	#endif
3505	if ( hit ) // inval to be done
3506	{
3507	r_dcache_xtn_way = way;
3508	r_dcache_xtn_set = set;
3509	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3510	}
3511	else // miss : nothing to do
3512	{
3513	r_dcache_fsm = DCACHE_IDLE;
3514	m_drsp.valid = true;
3515	}
3516
3517	#if DEBUG_DCACHE
3518	if ( m_debug_dcache_fsm )
3519	{
3520	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3521	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3522	<< " / HIT = " << hit
3523	<< " / SET = " << set
3524	<< " / WAY = " << way << std::endl;
3525	}
3526	#endif
3527	break;
3528	}
3529	////////////////////////////
3530	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3531	// Blocked if previous cleanup not completed
3532	// Test if itlb or dtlb inval is required
3533	{
3534	if ( not r_dcache_cleanup_req.read() )
3535	{
3536	paddr_t nline;
3537	size_t way = r_dcache_xtn_way.read();
3538	size_t set = r_dcache_xtn_set.read();
3539	bool hit;
3540
3541	hit = r_dcache.inval( way,
3542	set,
3543	&nline );
3544	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3545
3546	// request cleanup
3547	r_dcache_cleanup_req = true;
3548	r_dcache_cleanup_line = nline;
3549
3550	// possible itlb & dtlb invalidate
3551	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3552	{
3553	r_dcache_tlb_inval_line = nline;
3554	r_dcache_tlb_inval_count = 0;
3555	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3556	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3557	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3558	}
3559	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3560	{
3561	r_itlb.reset();
3562	r_dtlb.reset();
3563	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3564	r_dcache_fsm = DCACHE_IDLE;
3565	m_drsp.valid = true;
3566	}
3567	else
3568	{
3569	r_dcache_fsm = DCACHE_IDLE;
3570	m_drsp.valid = true;
3571	}
3572
3573	#if DEBUG_DCACHE
3574	if ( m_debug_dcache_fsm )
3575	{
3576	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3577	<< " / NLINE = " << nline << std::endl;
3578	}
3579	#endif
3580	}
3581	break;
3582	}
3583	//////////////////////////////
3584	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3585	{
3586	r_dcache_fsm = DCACHE_IDLE;
3587	m_drsp.valid = true;
3588	break;
3589	}
3590	////////////////////////
3591	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3592	// on the missing line, and if a new cleanup can be posted.
3593	// Set the r_dcache_cleanup_req flip-flop if required
3594	{
3595	size_t index; // unused
3596	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3597	if ( not hit and not r_dcache_cleanup_req.read() )
3598	{
3599	bool valid;
3600	size_t way;
3601	size_t set;
3602	paddr_t victim;
3603
3604	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3605	&victim,
3606	&way,
3607	&set );
3608	r_dcache_miss_way = way;
3609	r_dcache_miss_set = set;
3610
3611	if ( valid )
3612	{
3613	r_dcache_cleanup_req = true;
3614	r_dcache_cleanup_line = victim;
3615	r_dcache_fsm = DCACHE_MISS_INVAL;
3616	}
3617	else
3618	{
3619	r_dcache_fsm = DCACHE_MISS_WAIT;
3620	}
3621
3622	#if DEBUG_DCACHE
3623	if ( m_debug_dcache_fsm )
3624	{
3625	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3626	<< " / WAY = " << way
3627	<< " / SET = " << set
3628	<< " / VALID = " << valid
3629	<< " / LINE = " << std::hex << victim << std::endl;
3630	}
3631	#endif
3632	}
3633	break;
3634	}
3635	///////////////////////
3636	case DCACHE_MISS_INVAL: // invalidate the victim line
3637	// and possibly request itlb or dtlb invalidate
3638	{
3639	paddr_t nline;
3640	size_t way = r_dcache_miss_way.read();
3641	size_t set = r_dcache_miss_set.read();
3642	bool hit;
3643
3644	hit = r_dcache.inval( way,
3645	set,
3646	&nline );
3647
3648	assert(hit && "selected way/set line should be in dcache");
3649
3650	#if DEBUG_DCACHE
3651	if ( m_debug_dcache_fsm )
3652	{
3653	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
3654	<< " / way = " << way
3655	<< " / set = " << set
3656	<< " / nline = " << std::hex << nline << std::endl;
3657	}
3658	#endif
3659	// if selective itlb & dtlb invalidate are required
3660	// the miss response is not handled before invalidate completed
3661	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3662	{
3663	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3664	r_dcache_tlb_inval_line = nline;
3665	r_dcache_tlb_inval_count = 0;
3666	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3667	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3668	}
3669	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3670	{
3671	r_itlb.reset();
3672	r_dtlb.reset();
3673	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3674	r_dcache_fsm = DCACHE_MISS_WAIT;
3675	}
3676	else
3677	{
3678	r_dcache_fsm = DCACHE_MISS_WAIT;
3679	}
3680	break;
3681	}
3682	//////////////////////
3683	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3684	// This state is in charge of error signaling
3685	// There is 5 types of error depending on the requester
3686	{
3687	// external coherence request
3688	if ( r_tgt_dcache_req )
3689	{
3690	r_dcache_fsm_cc_save = r_dcache_fsm;
3691	r_dcache_fsm = DCACHE_CC_CHECK;
3692	break;
3693	}
3694
3695	if ( r_vci_rsp_data_error.read() ) // bus error
3696	{
3697	switch ( r_dcache_miss_type.read() )
3698	{
3699	case PROC_MISS:
3700	{
3701	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3702	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3703	m_drsp.valid = true;
3704	m_drsp.error = true;
3705	r_dcache_fsm = DCACHE_IDLE;
3706	break;
3707	}
3708	case PTE1_MISS:
3709	{
3710	if ( r_dcache_tlb_ins.read() )
3711	{
3712	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3713	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3714	r_icache_tlb_miss_req = false;
3715	r_icache_tlb_rsp_error = true;
3716	}
3717	else
3718	{
3719	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3720	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3721	m_drsp.valid = true;
3722	m_drsp.error = true;
3723	}
3724	r_dcache_fsm = DCACHE_IDLE;
3725	break;
3726	}
3727	case PTE2_MISS:
3728	{
3729	if ( r_dcache_tlb_ins.read() )
3730	{
3731	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3732	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3733	r_icache_tlb_miss_req = false;
3734	r_icache_tlb_rsp_error = true;
3735	}
3736	else
3737	{
3738	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3739	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3740	m_drsp.valid = true;
3741	m_drsp.error = true;
3742	}
3743	r_dcache_fsm = DCACHE_IDLE;
3744	break;
3745	}
3746	} // end switch type
3747	r_vci_rsp_data_error = false;
3748	}
3749	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3750	{
3751	r_dcache_miss_word = 0;
3752	r_dcache_fsm = DCACHE_MISS_UPDT;
3753	}
3754	break;
3755	}
3756	//////////////////////
3757	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3758	// returns the response depending on the miss type
3759	{
3760	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3761	{
3762	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3763	// pop the FIFO, without cache update
3764	// send a cleanup for the missing line
3765	// if the previous cleanup is completed
3766	{
3767	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3768	{
3769	vci_rsp_fifo_dcache_get = true;
3770	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3771	}
3772	else // last word
3773	{
3774	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3775	{
3776	vci_rsp_fifo_dcache_get = true;
3777	r_dcache_cleanup_req = true;
3778	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3779	(uint32_log2(m_dcache_words)+2);
3780	r_dcache_miss_inval = false;
3781	r_dcache_fsm = DCACHE_IDLE;
3782	}
3783	}
3784	}
3785	else // No matching coherence request
3786	// pop the FIFO and update the cache
3787	// update the directory at the last word
3788	{
3789	size_t way = r_dcache_miss_way.read();
3790	size_t set = r_dcache_miss_set.read();
3791	size_t word = r_dcache_miss_word.read();
3792
3793	#ifdef INSTRUMENTATION
3794	m_cpt_dcache_data_write++;
3795	#endif
3796	r_dcache.write( way,
3797	set,
3798	word,
3799	r_vci_rsp_fifo_dcache.read());
3800
3801	vci_rsp_fifo_dcache_get = true;
3802	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3803
3804	// if last word, update directory, set in_tlb & contains_ptd bits
3805	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3806	{
3807
3808	#ifdef INSTRUMENTATION
3809	m_cpt_dcache_dir_write++;
3810	#endif
3811	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3812	r_dcache_miss_way.read(),
3813	r_dcache_miss_set.read() );
3814
3815	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3816	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3817
3818	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3819	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3820	else r_dcache_fsm = DCACHE_IDLE;
3821	}
3822	}
3823
3824	#if DEBUG_DCACHE
3825	if ( m_debug_dcache_fsm )
3826	{
3827	if ( r_dcache_miss_inval.read() )
3828	{
3829	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3830	{
3831	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3832	<< " pop the FIFO, don't update the cache" << std::endl;
3833	}
3834	else
3835	{
3836	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3837	<< " last word : send a cleanup request " << std::endl;
3838	}
3839	}
3840	else
3841	{
3842	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3843	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3844	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3845	<< " / way = " << std::dec << r_dcache_miss_way.read()
3846	<< " / set = " << r_dcache_miss_set.read()
3847	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3848	}
3849	}
3850	#endif
3851
3852	} // end if rok
3853	break;
3854	}
3855	/////////////////////
3856	case DCACHE_UNC_WAIT:
3857	{
3858	// external coherence request
3859	if ( r_tgt_dcache_req.read() )
3860	{
3861	r_dcache_fsm_cc_save = r_dcache_fsm;
3862	r_dcache_fsm = DCACHE_CC_CHECK;
3863	break;
3864	}
3865
3866	if ( r_vci_rsp_data_error.read() ) // bus error
3867	{
3868	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3869	r_mmu_dbvar = m_dreq.addr;
3870	r_vci_rsp_data_error = false;
3871	m_drsp.error = true;
3872	m_drsp.valid = true;
3873	r_dcache_fsm = DCACHE_IDLE;
3874	break;
3875	}
3876	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3877	{
3878	// consume data
3879	vci_rsp_fifo_dcache_get = true;
3880	r_dcache_fsm = DCACHE_IDLE;
3881
3882	// acknowledge the processor request if it has not been modified
3883	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3884	{
3885	m_drsp.valid = true;
3886	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3887
3888	// makes reservation in case of LL
3889	if ( m_dreq.type == iss_t::DATA_LL )
3890	{
3891	r_dcache_ll_valid = true;
3892	r_dcache_ll_data = r_vci_rsp_fifo_dcache.read();
3893	r_dcache_ll_vaddr = m_dreq.addr;
3894	}
3895	}
3896	}
3897	break;
3898	}
3899	////////////////////
3900	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3901	{
3902	// external coherence request
3903	if ( r_tgt_dcache_req.read() )
3904	{
3905	r_dcache_fsm_cc_save = r_dcache_fsm;
3906	r_dcache_fsm = DCACHE_CC_CHECK;
3907	break;
3908	}
3909
3910	if ( r_vci_rsp_data_error.read() ) // bus error
3911	{
3912	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3913	r_mmu_dbvar = m_dreq.addr;
3914	r_vci_rsp_data_error = false;
3915	m_drsp.error = true;
3916	m_drsp.valid = true;
3917	r_dcache_fsm = DCACHE_IDLE;
3918	break;
3919	}
3920	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3921	{
3922	vci_rsp_fifo_dcache_get = true;
3923	m_drsp.valid = true;
3924	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3925	r_dcache_fsm = DCACHE_IDLE;
3926	}
3927	break;
3928	}
3929	//////////////////////////
3930	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3931	// before handling a processor WRITE or SC request
3932	// Input argument is r_dcache_dirty_paddr
3933	// In this first state, we get PTE value in dcache
3934	// and post a SC request to CMD FSM
3935	{
3936	// get PTE in dcache
3937	uint32_t pte;
3938	size_t way;
3939	size_t set;
3940	size_t word; // unused
3941	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3942	&pte,
3943	&way,
3944	&set,
3945	&word );
3946	#ifdef INSTRUMENTATION
3947	m_cpt_dcache_data_read++;
3948	m_cpt_dcache_dir_read++;
3949	#endif
3950	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3951
3952	// request sc transaction to CMD_FSM
3953	r_dcache_dirty_way = way;
3954	r_dcache_dirty_set = set;
3955	r_dcache_vci_sc_req = true;
3956	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3957	r_dcache_vci_sc_old = pte;
3958	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3959	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3960
3961	#if DEBUG_DCACHE
3962	if ( m_debug_dcache_fsm )
3963	{
3964	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3965	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3966	<< " / PTE_VALUE = " << pte << std::dec
3967	<< " / CACHE_SET = " << set
3968	<< " / CACHE_WAY = " << way << std::endl;
3969	}
3970	#endif
3971	break;
3972	}
3973	//////////////////////////
3974	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3975	// If PTE update is a success, return to IDLE state.
3976	// If PTE update is a failure, invalidate cache line
3977	// in DCACHE and invalidate the matching TLB entries.
3978	{
3979	// external coherence request
3980	if ( r_tgt_dcache_req )
3981	{
3982	r_dcache_fsm_cc_save = r_dcache_fsm;
3983	r_dcache_fsm = DCACHE_CC_CHECK;
3984	break;
3985	}
3986
3987	if ( r_vci_rsp_data_error.read() ) // bus error
3988	{
3989	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3990	std::cout << "This should not happen in this state" << std::endl;
3991	exit(0);
3992	}
3993	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3994	{
3995	vci_rsp_fifo_dcache_get = true;
3996	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
3997	{
3998	r_dcache_fsm = DCACHE_IDLE;
3999
4000	#if DEBUG_DCACHE
4001	if ( m_debug_dcache_fsm )
4002	{
4003	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
4004	<< std::endl;
4005	}
4006	#endif
4007	}
4008	else // invalidate the cache line TLBs
4009	{
4010
4011	#if DEBUG_DCACHE
4012	if ( m_debug_dcache_fsm )
4013	{
4014	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
4015	<< std::endl;
4016	}
4017	#endif
4018	paddr_t nline;
4019	size_t way = r_dcache_dirty_way.read();
4020	size_t set = r_dcache_dirty_set.read();
4021	bool hit;
4022
4023	hit = r_dcache.inval( way,
4024	set,
4025	&nline );
4026
4027	assert(hit && "PTE should still be in dcache");
4028
4029	// request cleanup
4030	r_dcache_cleanup_req = true;
4031	r_dcache_cleanup_line = nline;
4032
4033	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
4034	{
4035	r_dcache_tlb_inval_line = nline;
4036	r_dcache_tlb_inval_count = 0;
4037	r_dcache_fsm_scan_save = DCACHE_IDLE;
4038	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4039	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4040	}
4041	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
4042	{
4043	r_itlb.reset();
4044	r_dtlb.reset();
4045	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4046	r_dcache_fsm = DCACHE_IDLE;
4047	}
4048	else
4049	{
4050	r_dcache_fsm = DCACHE_IDLE;
4051	}
4052	}
4053	}
4054	break;
4055	}
4056	/////////////////////
4057	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4058	// handling coherence requests.
4059	// If there is a matching pending miss on the modified cache
4060	// line this is signaled in the r_dcache_miss inval flip-flop.
4061	// If the updated (or invalidated) cache line has copies in TLBs
4062	// these TLB copies are invalidated.
4063	// The return state is defined in r_dcache_fsm_cc_save
4064	{
4065	paddr_t paddr = r_tgt_paddr.read();
4066	paddr_t mask = ~((m_dcache_words<<2)-1);
4067
4068
4069	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4070	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4071	{
4072	r_dcache_miss_inval = true; // signaling the match
4073	r_tgt_dcache_req = false; // coherence request completed
4074	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4075	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4076
4077	#if DEBUG_DCACHE
4078	if ( m_debug_dcache_fsm )
4079	{
4080	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4081	<< " address = " << std::hex << paddr << std::endl;
4082	}
4083	#endif
4084
4085	}
4086	else // no match
4087	{
4088	uint32_t rdata;
4089	size_t way;
4090	size_t set;
4091	size_t word;
4092
4093	bool hit = r_dcache.read(paddr,
4094	&rdata, // unused
4095	&way,
4096	&set,
4097	&word); // unused
4098	#ifdef INSTRUMENTATION
4099	m_cpt_dcache_data_read++;
4100	m_cpt_dcache_dir_read++;
4101	#endif
4102	r_dcache_cc_way = way;
4103	r_dcache_cc_set = set;
4104
4105	if ( hit and r_tgt_update.read() ) // hit update
4106	{
4107	r_dcache_fsm = DCACHE_CC_UPDT;
4108	r_dcache_cc_word = r_tgt_word_min.read();
4109	}
4110	else if ( hit and not r_tgt_update.read() ) // hit inval
4111	{
4112	r_dcache_fsm = DCACHE_CC_INVAL;
4113	}
4114	else // miss can happen
4115	{
4116	r_tgt_dcache_req = false;
4117	r_tgt_dcache_rsp = r_tgt_update.read();
4118	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4119	}
4120
4121	#if DEBUG_DCACHE
4122	if ( m_debug_dcache_fsm )
4123	{
4124
4125	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4126	<< " address = " << std::hex << paddr << std::dec;
4127	if ( hit )
4128	{
4129	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4130	}
4131	else
4132	{
4133	std::cout << " / MISS" << std::endl;
4134	}
4135	}
4136	#endif
4137
4138	}
4139	break;
4140	}
4141	/////////////////////
4142	case DCACHE_CC_INVAL: // invalidate one cache line
4143	// and test possible copies in TLBs
4144	{
4145	paddr_t nline;
4146	size_t way = r_dcache_cc_way.read();
4147	size_t set = r_dcache_cc_set.read();
4148	bool hit;
4149
4150	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4151	{
4152	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4153	r_dcache_tlb_inval_line = nline;
4154	r_dcache_tlb_inval_count = 0;
4155	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4156	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4157	}
4158	else // actual cache line inval
4159	{
4160	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4161	{
4162	r_itlb.reset();
4163	r_dtlb.reset();
4164	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4165	}
4166	r_tgt_dcache_rsp = true;
4167	r_tgt_dcache_req = false;
4168	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4169
4170	hit = r_dcache.inval( way,
4171	set,
4172	&nline );
4173	#if DEBUG_DCACHE
4174	if ( m_debug_dcache_fsm )
4175	{
4176	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4177	<< " / WAY = " << way
4178	<< " / SET = " << set << std::endl;
4179	}
4180	#endif
4181
4182	assert(hit && "CC_INVAL way/set should still be in dcache");
4183	}
4184	break;
4185	}
4186	///////////////////
4187	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4188	// and test possible copies in TLBs
4189	{
4190	size_t word = r_dcache_cc_word.read();
4191	size_t way = r_dcache_cc_way.read();
4192	size_t set = r_dcache_cc_set.read();
4193	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4194
4195	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4196	{
4197	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4198	r_dcache_tlb_inval_line = nline;
4199	r_dcache_tlb_inval_count = 0;
4200	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4201	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4202	}
4203	else // cache update
4204	{
4205	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4206	{
4207	r_itlb.reset();
4208	r_dtlb.reset();
4209	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4210	}
4211
4212	r_dcache.write( way,
4213	set,
4214	word,
4215	r_tgt_buf[word],
4216	r_tgt_be[word] );
4217	#ifdef INSTRUMENTATION
4218	m_cpt_dcache_data_write++;
4219	#endif
4220	r_dcache_cc_word = word + 1;
4221
4222	#if DEBUG_DCACHE
4223	if ( m_debug_dcache_fsm )
4224	{
4225	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4226	<< " / WAY = " << way
4227	<< " / SET = " << set
4228	<< " / WORD = " << word
4229	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4230	}
4231	#endif
4232	if ( word == r_tgt_word_max.read() ) // last word
4233	{
4234	r_tgt_dcache_rsp = true;
4235	r_tgt_dcache_req = false;
4236	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4237	}
4238	}
4239
4240	break;
4241	}
4242	///////////////////////////
4243	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4244	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4245	// and (m_itlb_ways == m_dtlb_ways)
4246	// We enter this state when a DCACHE line is modified,
4247	// and there is a copy in itlb or dtlb.
4248	// It can be caused by:
4249	// - a coherence inval or updt transaction,
4250	// - a line inval caused by a cache miss
4251	// - a processor XTN inval request,
4252	// - a WRITE hit,
4253	// - a Dirty bit update failure
4254	// Input arguments are:
4255	// - r_dcache_tlb_inval_line
4256	// - r_dcache_tlb_inval_count
4257	// - r_dcache_fsm_cc_save
4258	{
4259	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4260	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4261	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4262	bool ok;
4263
4264	ok = r_itlb.inval( line,
4265	way,
4266	set );
4267	#if DEBUG_DCACHE
4268	if ( m_debug_dcache_fsm and ok )
4269	{
4270	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4271	<< " line = " << line << std::dec
4272	<< " / set = " << set
4273	<< " / way = " << way << std::endl;
4274	r_itlb.printTrace();
4275	}
4276	#endif
4277	ok = r_dtlb.inval( line,
4278	way,
4279	set );
4280	#if DEBUG_DCACHE
4281	if ( m_debug_dcache_fsm and ok )
4282	{
4283	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4284	<< " line = " << line << std::dec
4285	<< " / set = " << set
4286	<< " / way = " << way << std::endl;
4287	r_dtlb.printTrace();
4288	}
4289	#endif
4290
4291	// return to the calling state when TLB inval completed
4292	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4293	{
4294	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4295	}
4296	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4297	break;
4298	}
4299	} // end switch r_dcache_fsm
4300
4301	///////////////// wbuf update //////////////////////////////////////////////////////
4302	r_wbuf.update();
4303
4304	//////////////// test processor frozen /////////////////////////////////////////////
4305	// The simulation exit if the number of consecutive frozen cycles
4306	// is larger than the m_max_frozen_cycles (constructor parameter)
4307	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4308	{
4309	m_cpt_frz_cycles++; // used for instrumentation
4310	m_cpt_stop_simulation++; // used for debug
4311	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4312	{
4313	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4314	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4315	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4316	<< std::endl;
4317	exit(1);
4318	}
4319	}
4320	else
4321	{
4322	m_cpt_stop_simulation = 0;
4323	}
4324
4325	/////////// execute one iss cycle /////////////////////////////////
4326	{
4327	uint32_t it = 0;
4328	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4329	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4330	}
4331
4332	////////////////////////////////////////////////////////////////////////////
4333	// The VCI_CMD FSM controls the following ressources:
4334	// - r_vci_cmd_fsm
4335	// - r_vci_cmd_min
4336	// - r_vci_cmd_max
4337	// - r_vci_cmd_cpt
4338	// - r_vci_cmd_imiss_prio
4339	// - wbuf (reset)
4340	// - r_icache_miss_req (reset)
4341	// - r_icache_unc_req (reset)
4342	// - r_dcache_vci_miss_req (reset)
4343	// - r_dcache_vci_unc_req (reset)
4344	// - r_dcache_vci_sc_req (reset)
4345	//
4346	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4347	// There is 6 request types, with the following priorities :
4348	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4349	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4350	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4351	// 4 - Instruction Uncachable : r_icache_unc_req
4352	// 5 - Data Write : r_wbuf.rok()
4353	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4354	//
4355	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4356	// and the VCI_RSP_FSM are fully desynchronized.
4357	//
4358	// VCI formats:
4359	// According to the VCI advanced specification, all read requests packets
4360	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4361	// are one word packets.
4362	// For write burst packets, all words are in the same cache line,
4363	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4364	// The sc command packet implements actually a compare-and-swap mechanism
4365	// and the packet contains two flits.
4366	////////////////////////////////////////////////////////////////////////////////////
4367
4368	switch ( r_vci_cmd_fsm.read() )
4369	{
4370	//////////////
4371	case CMD_IDLE:
4372	{
4373	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4374	// to check a possible pending write on the same cache line.
4375	// As there is only one possible access per cycle to write buffer, we implement
4376	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4377
4378	size_t wbuf_min;
4379	size_t wbuf_max;
4380
4381	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4382	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4383
4384	bool icache_miss_req = r_icache_miss_req.read()
4385	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4386
4387	// 1 - Data Read Miss
4388	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4389	{
4390	r_vci_cmd_fsm = CMD_DATA_MISS;
4391	r_dcache_vci_miss_req = false;
4392	r_vci_cmd_imiss_prio = true;
4393	// m_cpt_dmiss_transaction++;
4394	}
4395	// 2 - Data Read Uncachable
4396	else if ( r_dcache_vci_unc_req.read() )
4397	{
4398	r_vci_cmd_fsm = CMD_DATA_UNC;
4399	r_dcache_vci_unc_req = false;
4400	// m_cpt_dunc_transaction++;
4401	}
4402	// 3 - Instruction Miss
4403	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4404	{
4405	r_vci_cmd_fsm = CMD_INS_MISS;
4406	r_icache_miss_req = false;
4407	r_vci_cmd_imiss_prio = false;
4408	// m_cpt_imiss_transaction++;
4409	}
4410	// 4 - Instruction Uncachable
4411	else if ( r_icache_unc_req.read() )
4412	{
4413	r_vci_cmd_fsm = CMD_INS_UNC;
4414	r_icache_unc_req = false;
4415	// m_cpt_iunc_transaction++;
4416	}
4417	// 5 - Data Write
4418	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4419	{
4420	r_vci_cmd_fsm = CMD_DATA_WRITE;
4421	r_vci_cmd_cpt = wbuf_min;
4422	r_vci_cmd_min = wbuf_min;
4423	r_vci_cmd_max = wbuf_max;
4424	// m_cpt_write_transaction++;
4425	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4426	}
4427	// 6 - Data Store Conditionnal
4428	else if ( r_dcache_vci_sc_req.read() )
4429	{
4430	r_vci_cmd_fsm = CMD_DATA_SC;
4431	r_dcache_vci_sc_req = false;
4432	r_vci_cmd_cpt = 0;
4433	// m_cpt_sc_transaction++;
4434	}
4435	break;
4436	}
4437	////////////////////
4438	case CMD_DATA_WRITE:
4439	{
4440	if ( p_vci_ini_d.cmdack.read() )
4441	{
4442	// m_conso_wbuf_read++;
4443	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4444	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4445	{
4446	r_vci_cmd_fsm = CMD_IDLE ;
4447	r_wbuf.sent() ;
4448	}
4449	}
4450	break;
4451	}
4452	/////////////////
4453	case CMD_DATA_SC:
4454	{
4455	// The SC VCI command contains two flits
4456	if ( p_vci_ini_d.cmdack.read() )
4457	{
4458	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4459	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4460	}
4461	break;
4462	}
4463	//////////////////
4464	case CMD_INS_MISS:
4465	case CMD_INS_UNC:
4466	case CMD_DATA_MISS:
4467	case CMD_DATA_UNC:
4468	{
4469	// all read VCI commands contain one single flit
4470	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4471	break;
4472	}
4473
4474	} // end switch r_vci_cmd_fsm
4475
4476	//////////////////////////////////////////////////////////////////////////
4477	// The VCI_RSP FSM controls the following ressources:
4478	// - r_vci_rsp_fsm:
4479	// - r_vci_rsp_fifo_icache (push)
4480	// - r_vci_rsp_fifo_dcache (push)
4481	// - r_vci_rsp_data_error (set)
4482	// - r_vci_rsp_ins_error (set)
4483	// - r_vci_rsp_cpt
4484	//
4485	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4486	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4487	// to identify the transactions.
4488	//
4489	// VCI vormat:
4490	// This component checks the response packet length and accepts only
4491	// single word packets for write response packets.
4492	//
4493	// Error handling:
4494	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4495	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4496	// flip_flop and the error is signaled by the DCACHE FSM.
4497	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4498	// flip_flop and the error is signaled by the ICACHE FSM.
4499	// In case of Cleanup Error, the simulation stops with an error message...
4500	//////////////////////////////////////////////////////////////////////////
4501
4502	switch ( r_vci_rsp_fsm.read() )
4503	{
4504	//////////////
4505	case RSP_IDLE:
4506	{
4507	if ( p_vci_ini_d.rspval.read() )
4508	{
4509	r_vci_rsp_cpt = 0;
4510
4511	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4512	{
4513	r_vci_rsp_fsm = RSP_DATA_WRITE;
4514	}
4515	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4516	{
4517	r_vci_rsp_fsm = RSP_INS_MISS;
4518	}
4519	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4520	{
4521	r_vci_rsp_fsm = RSP_INS_UNC;
4522	}
4523	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4524	{
4525	r_vci_rsp_fsm = RSP_DATA_MISS;
4526	}
4527	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4528	{
4529	r_vci_rsp_fsm = RSP_DATA_UNC;
4530	}
4531	else
4532	{
4533	assert(false and "Unexpected VCI response");
4534	}
4535	}
4536	break;
4537	}
4538	//////////////////
4539	case RSP_INS_MISS:
4540	{
4541	if ( p_vci_ini_d.rspval.read() )
4542	{
4543	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4544	{
4545	r_vci_rsp_ins_error = true;
4546	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4547	}
4548	else // no error reported
4549	{
4550	if ( r_vci_rsp_fifo_icache.wok() )
4551	{
4552	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4553	"The VCI response packet for instruction miss is too long" );
4554
4555	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4556	vci_rsp_fifo_icache_put = true,
4557	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4558	if ( p_vci_ini_d.reop.read() )
4559	{
4560	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4561	"The VCI response packet for instruction miss is too short");
4562
4563	r_vci_rsp_fsm = RSP_IDLE;
4564	}
4565	}
4566	}
4567	}
4568	break;
4569	}
4570	/////////////////
4571	case RSP_INS_UNC:
4572	{
4573	if (p_vci_ini_d.rspval.read() )
4574	{
4575	assert( p_vci_ini_d.reop.read() and
4576	"illegal VCI response packet for uncachable instruction");
4577
4578	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4579	{
4580	r_vci_rsp_ins_error = true;
4581	r_vci_rsp_fsm = RSP_IDLE;
4582	}
4583	else // no error reported
4584	{
4585	if ( r_vci_rsp_fifo_icache.wok())
4586	{
4587	vci_rsp_fifo_icache_put = true;
4588	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4589	r_vci_rsp_fsm = RSP_IDLE;
4590	}
4591	}
4592	}
4593	break;
4594	}
4595	///////////////////
4596	case RSP_DATA_MISS:
4597	{
4598	if ( p_vci_ini_d.rspval.read() )
4599	{
4600	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4601	{
4602	r_vci_rsp_data_error = true;
4603	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4604	}
4605	else // no error reported
4606	{
4607	if ( r_vci_rsp_fifo_dcache.wok() )
4608	{
4609	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4610	"The VCI response packet for data miss is too long");
4611
4612	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4613	vci_rsp_fifo_dcache_put = true,
4614	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4615	if ( p_vci_ini_d.reop.read() )
4616	{
4617	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4618	"The VCI response packet for data miss is too short");
4619
4620	r_vci_rsp_fsm = RSP_IDLE;
4621	}
4622	}
4623	}
4624	}
4625	break;
4626	}
4627	//////////////////
4628	case RSP_DATA_UNC:
4629	{
4630	if (p_vci_ini_d.rspval.read() )
4631	{
4632	assert( p_vci_ini_d.reop.read() and
4633	"illegal VCI response packet for uncachable read data");
4634
4635	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4636	{
4637	r_vci_rsp_data_error = true;
4638	r_vci_rsp_fsm = RSP_IDLE;
4639	}
4640	else // no error reported
4641	{
4642	if ( r_vci_rsp_fifo_dcache.wok())
4643	{
4644	vci_rsp_fifo_dcache_put = true;
4645	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4646	r_vci_rsp_fsm = RSP_IDLE;
4647	}
4648	}
4649	}
4650	break;
4651	}
4652	////////////////////
4653	case RSP_DATA_WRITE:
4654	{
4655	if (p_vci_ini_d.rspval.read())
4656	{
4657	assert( p_vci_ini_d.reop.read() and
4658	"a VCI response packet must contain one flit for a write transaction");
4659
4660	r_vci_rsp_fsm = RSP_IDLE;
4661	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4662	bool cacheable = r_wbuf.completed(wbuf_index);
4663	if ( not cacheable ) r_dcache_pending_unc_write = false;
4664	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4665	}
4666	break;
4667	}
4668	} // end switch r_vci_rsp_fsm
4669
4670	/////////////////////////////////////////////////////////////////////////////////////
4671	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4672	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4673	// with a round-robin priority. All cleanup commands are registered in the
4674	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4675	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4676	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4677	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4678	// the request has been sent and registered in the buffer.
4679	// The buffer itself is cleared when the cleanup response is received.
4680	// We use an assocative registration buffer (CAM) in order to support several
4681	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4682	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4683	// - if data cleanup : TRDID = 2*index + 0
4684	// - if instruction cleanup : TRDID = 2*index + 1
4685	/////////////////////////////////////////////////////////////////////////////////////
4686
4687	switch ( r_cleanup_fsm.read() )
4688	{
4689	///////////////////////
4690	case CLEANUP_DATA_IDLE: // dcache has highest priority
4691	{
4692	size_t index = 0;
4693	bool ok;
4694	if ( r_dcache_cleanup_req.read() ) // dcache request
4695	{
4696	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4697	&index );
4698	if ( ok ) // successful registration
4699	{
4700	r_cleanup_fsm = CLEANUP_DATA_GO;
4701	r_cleanup_trdid = index<<1;
4702	}
4703	}
4704	else if ( r_icache_cleanup_req.read() ) // icache request
4705	{
4706	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4707	&index );
4708	if ( ok ) // successful registration
4709	{
4710	r_cleanup_fsm = CLEANUP_INS_GO;
4711	r_cleanup_trdid = (index<<1) + 1;
4712	}
4713	}
4714	break;
4715	}
4716	//////////////////////
4717	case CLEANUP_INS_IDLE: // icache has highest priority
4718	{
4719	size_t index = 0;
4720	bool ok;
4721	if ( r_icache_cleanup_req.read() ) // icache request
4722	{
4723	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4724	&index );
4725	if ( ok ) // successful registration
4726	{
4727	r_cleanup_fsm = CLEANUP_INS_GO;
4728	r_cleanup_trdid = (index<<1) + 1;
4729	}
4730	}
4731	else if ( r_dcache_cleanup_req.read() ) // dcache request
4732	{
4733	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4734	&index );
4735	if ( ok ) // successful registration
4736	{
4737	r_cleanup_fsm = CLEANUP_DATA_GO;
4738	r_cleanup_trdid = index<<1;
4739	}
4740	}
4741	break;
4742	}
4743	/////////////////////
4744	case CLEANUP_DATA_GO:
4745	{
4746	if ( p_vci_ini_c.cmdack.read() )
4747	{
4748	r_cleanup_fsm = CLEANUP_INS_IDLE;
4749	r_dcache_cleanup_req = false;
4750
4751	#if DEBUG_CLEANUP
4752	if ( m_debug_cleanup_fsm )
4753	{
4754	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4755	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4756	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4757	}
4758	#endif
4759	}
4760	break;
4761	}
4762	////////////////////
4763	case CLEANUP_INS_GO:
4764	{
4765	if ( p_vci_ini_c.cmdack.read() )
4766	{
4767	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4768	r_icache_cleanup_req = false;
4769
4770	#if DEBUG_CLEANUP
4771	if ( m_debug_cleanup_fsm )
4772	{
4773	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4774	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4775	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4776	}
4777	#endif
4778	}
4779	break;
4780	}
4781	} // end switch CLEANUP FSM
4782
4783	//////////////// Handling cleanup responses //////////////////
4784	if ( p_vci_ini_c.rspval.read() )
4785	{
4786	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
4787	}
4788
4789	///////////////// Response FIFOs update //////////////////////
4790	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4791	vci_rsp_fifo_icache_put,
4792	vci_rsp_fifo_icache_data);
4793
4794	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4795	vci_rsp_fifo_dcache_put,
4796	vci_rsp_fifo_dcache_data);
4797	} // end transition()
4798
4799	///////////////////////
4800	tmpl(void)::genMoore()
4801	///////////////////////
4802	{
4803	////////////////////////////////////////////////////////////////
4804	// VCI initiator command on the coherence network (cleanup)
4805	// it depends on the CLEANUP FSM state
4806
4807	paddr_t address;
4808
4809	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4810	address = r_dcache_cleanup_line.read()m_dcache_words4;
4811	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4812	address = r_icache_cleanup_line.read()m_icache_words4;
4813	else
4814	address = 0;
4815
4816	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4817	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4818	p_vci_ini_c.address = address;
4819	p_vci_ini_c.wdata = 0;
4820	p_vci_ini_c.be = 0xF;
4821	p_vci_ini_c.plen = 4;
4822	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4823	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4824	p_vci_ini_c.pktid = 0;
4825	p_vci_ini_c.srcid = m_srcid_c;
4826	p_vci_ini_c.cons = false;
4827	p_vci_ini_c.wrap = false;
4828	p_vci_ini_c.contig = false;
4829	p_vci_ini_c.clen = 0;
4830	p_vci_ini_c.cfixed = false;
4831	p_vci_ini_c.eop = true;
4832
4833	/////////////////////////////////////////////////////////////////
4834	// VCI initiator response on the coherence network (cleanup)
4835	// We always consume the response, and we don't use it.
4836
4837	p_vci_ini_c.rspack = true;
4838
4839	/////////////////////////////////////////////////////////////////
4840	// VCI initiator command on the direct network
4841	// it depends on the CMD FSM state
4842
4843	p_vci_ini_d.pktid = 0;
4844	p_vci_ini_d.srcid = m_srcid_d;
4845	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4846	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4847	p_vci_ini_d.wrap = false;
4848	p_vci_ini_d.clen = 0;
4849	p_vci_ini_d.cfixed = false;
4850
4851	switch ( r_vci_cmd_fsm.read() ) {
4852
4853	case CMD_IDLE:
4854	p_vci_ini_d.cmdval = false;
4855	p_vci_ini_d.address = 0;
4856	p_vci_ini_d.wdata = 0;
4857	p_vci_ini_d.be = 0;
4858	p_vci_ini_d.trdid = 0;
4859	p_vci_ini_d.plen = 0;
4860	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4861	p_vci_ini_d.eop = false;
4862	break;
4863
4864	case CMD_INS_MISS:
4865	p_vci_ini_d.cmdval = true;
4866	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4867	p_vci_ini_d.wdata = 0;
4868	p_vci_ini_d.be = 0xF;
4869	p_vci_ini_d.trdid = TYPE_INS_MISS;
4870	p_vci_ini_d.plen = m_icache_words<<2;
4871	p_vci_ini_d.cmd = vci_param::CMD_READ;
4872	p_vci_ini_d.eop = true;
4873	break;
4874
4875	case CMD_INS_UNC:
4876	p_vci_ini_d.cmdval = true;
4877	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4878	p_vci_ini_d.wdata = 0;
4879	p_vci_ini_d.be = 0xF;
4880	p_vci_ini_d.trdid = TYPE_INS_UNC;
4881	p_vci_ini_d.plen = 4;
4882	p_vci_ini_d.cmd = vci_param::CMD_READ;
4883	p_vci_ini_d.eop = true;
4884	break;
4885
4886	case CMD_DATA_MISS:
4887	p_vci_ini_d.cmdval = true;
4888	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4889	p_vci_ini_d.wdata = 0;
4890	p_vci_ini_d.be = 0xF;
4891	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4892	p_vci_ini_d.plen = m_dcache_words << 2;
4893	p_vci_ini_d.cmd = vci_param::CMD_READ;
4894	p_vci_ini_d.eop = true;
4895	break;
4896
4897	case CMD_DATA_UNC:
4898	p_vci_ini_d.cmdval = true;
4899	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4900	p_vci_ini_d.wdata = 0;
4901	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4902	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4903	p_vci_ini_d.plen = 4;
4904	p_vci_ini_d.cmd = vci_param::CMD_READ;
4905	p_vci_ini_d.eop = true;
4906	break;
4907
4908	case CMD_DATA_WRITE:
4909	p_vci_ini_d.cmdval = true;
4910	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4911	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4912	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4913	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4914	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4915	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4916	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4917	break;
4918
4919	case CMD_DATA_SC:
4920	p_vci_ini_d.cmdval = true;
4921	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4922	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4923	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4924	p_vci_ini_d.be = 0xF;
4925	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4926	p_vci_ini_d.plen = 8;
4927	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4928	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4929	break;
4930	} // end switch r_vci_cmd_fsm
4931
4932	//////////////////////////////////////////////////////////
4933	// VCI initiator response on the direct network
4934	// it depends on the VCI RSP state
4935
4936	switch (r_vci_rsp_fsm.read() )
4937	{
4938	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4939	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4940	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4941	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4942	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4943	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4944	} // end switch r_vci_rsp_fsm
4945
4946	////////////////////////////////////////////////////////////////
4947	// VCI target command and response on the coherence network
4948	switch ( r_tgt_fsm.read() )
4949	{
4950	case TGT_IDLE:
4951	case TGT_UPDT_WORD:
4952	case TGT_UPDT_DATA:
4953	p_vci_tgt_c.cmdack = true;
4954	p_vci_tgt_c.rspval = false;
4955	break;
4956
4957	case TGT_RSP_BROADCAST:
4958	p_vci_tgt_c.cmdack = false;
4959	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4960	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4961	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4962	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4963	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4964	p_vci_tgt_c.rdata = 0;
4965	p_vci_tgt_c.rerror = 0;
4966	p_vci_tgt_c.reop = true;
4967	break;
4968
4969	case TGT_RSP_ICACHE:
4970	p_vci_tgt_c.cmdack = false;
4971	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4972	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4973	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4974	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4975	p_vci_tgt_c.rdata = 0;
4976	p_vci_tgt_c.rerror = 0;
4977	p_vci_tgt_c.reop = true;
4978	break;
4979
4980	case TGT_RSP_DCACHE:
4981	p_vci_tgt_c.cmdack = false;
4982	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4983	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4984	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4985	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4986	p_vci_tgt_c.rdata = 0;
4987	p_vci_tgt_c.rerror = 0;
4988	p_vci_tgt_c.reop = true;
4989	break;
4990
4991	case TGT_REQ_BROADCAST:
4992	case TGT_REQ_ICACHE:
4993	case TGT_REQ_DCACHE:
4994	p_vci_tgt_c.cmdack = false;
4995	p_vci_tgt_c.rspval = false;
4996	break;
4997
4998	} // end switch TGT_FSM
4999	} // end genMoore
5000
5001	}}
5002
5003	// Local Variables:
5004	// tab-width: 4
5005	// c-basic-offset: 4
5006	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5007	// indent-tabs-mode: nil
5008	// End:
5009
5010	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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