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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 235

Last change on this file since 235 was 235, checked in by haoliu, 12 years ago
BUG FIX: In the ICACHE FSM, state ICACHE_XTN_CACHE_FLUSH
File size: 188.5 KB

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1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtd,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_c,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	uint32_t max_frozen_cycles,
169	uint32_t debug_start_cycle,
170	bool debug_ok)
171	: soclib::caba::BaseModule(name),
172
173	p_clk("clk"),
174	p_resetn("resetn"),
175	p_vci_ini_d("vci_ini_d"),
176	p_vci_ini_c("vci_ini_c"),
177	p_vci_tgt_c("vci_tgt_d"),
178
179	m_cacheability_table(mtd.getCacheabilityTable()),
180	m_segment(mtc.getSegment(target_index_c)),
181	m_srcid_d(mtd.indexForId(initiator_index_d)),
182	m_srcid_c(mtc.indexForId(initiator_index_c)),
183
184	m_itlb_ways(itlb_ways),
185	m_itlb_sets(itlb_sets),
186
187	m_dtlb_ways(dtlb_ways),
188	m_dtlb_sets(dtlb_sets),
189
190	m_icache_ways(icache_ways),
191	m_icache_sets(icache_sets),
192	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
193	m_icache_words(icache_words),
194
195	m_dcache_ways(dcache_ways),
196	m_dcache_sets(dcache_sets),
197	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
198	m_dcache_words(dcache_words),
199
200	m_proc_id(proc_id),
201
202	m_max_frozen_cycles(max_frozen_cycles),
203
204	m_paddr_nbits(vci_param::N),
205
206	m_debug_start_cycle(debug_start_cycle),
207	m_debug_ok(debug_ok),
208
209	r_mmu_ptpr("r_mmu_ptpr"),
210	r_mmu_mode("r_mmu_mode"),
211	r_mmu_word_lo("r_mmu_word_lo"),
212	r_mmu_word_hi("r_mmu_word_hi"),
213	r_mmu_ibvar("r_mmu_ibvar"),
214	r_mmu_dbvar("r_mmu_dbvar"),
215	r_mmu_ietr("r_mmu_ietr"),
216	r_mmu_detr("r_mmu_detr"),
217
218	r_icache_fsm("r_icache_fsm"),
219	r_icache_fsm_save("r_icache_fsm_save"),
220
221	r_icache_vci_paddr("r_icache_vci_paddr"),
222	r_icache_vaddr_save("r_icache_vaddr_save"),
223
224	r_icache_miss_way("r_icache_miss_way"),
225	r_icache_miss_set("r_icache_miss_set"),
226	r_icache_miss_word("r_icache_miss_word"),
227	r_icache_miss_inval("r_icache_miss_inval"),
228
229	r_icache_cc_way("r_icache_cc_way"),
230	r_icache_cc_set("r_icache_cc_set"),
231	r_icache_cc_word("r_icache_cc_word"),
232
233	r_icache_flush_count("r_icache_flush_count"),
234
235	r_icache_miss_req("r_icache_miss_req"),
236	r_icache_unc_req("r_icache_unc_req"),
237
238	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
239	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
240
241	r_icache_cleanup_req("r_icache_cleanup_req"),
242	r_icache_cleanup_line("r_icache_cleanup_line"),
243
244	r_dcache_fsm("r_dcache_fsm"),
245	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
246	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
247
248	r_dcache_p0_valid("r_dcache_p0_valid"),
249	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
250	r_dcache_p0_wdata("r_dcache_p0_wdata"),
251	r_dcache_p0_be("r_dcache_p0_be"),
252	r_dcache_p0_paddr("r_dcache_p0_paddr"),
253	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
254
255	r_dcache_p1_valid("r_dcache_p1_valid"),
256	r_dcache_p1_wdata("r_dcache_p1_wdata"),
257	r_dcache_p1_be("r_dcache_p1_be"),
258	r_dcache_p1_paddr("r_dcache_p1_paddr"),
259	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
260	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
261	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
262
263	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
264	r_dcache_dirty_way("r_dcache_dirty_way"),
265	r_dcache_dirty_set("r_dcache_dirty_set"),
266
267	r_dcache_vci_paddr("r_dcache_vci_paddr"),
268	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
269	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
270	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
271	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
272	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
273	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
274
275	r_dcache_xtn_way("r_dcache_xtn_way"),
276	r_dcache_xtn_set("r_dcache_xtn_set"),
277
278	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
279
280	r_dcache_miss_type("r_dcache_miss_type"),
281	r_dcache_miss_word("r_dcache_miss_word"),
282	r_dcache_miss_way("r_dcache_miss_way"),
283	r_dcache_miss_set("r_dcache_miss_set"),
284	r_dcache_miss_inval("r_dcache_miss_inval"),
285
286	r_dcache_cc_way("r_dcache_cc_way"),
287	r_dcache_cc_set("r_dcache_cc_set"),
288	r_dcache_cc_word("r_dcache_cc_word"),
289
290	r_dcache_flush_count("r_dcache_flush_count"),
291
292	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
293	r_dcache_tlb_ins("r_dcache_tlb_ins"),
294	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
295	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
296	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
297	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
298	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
299	r_dcache_tlb_way("r_dcache_tlb_way"),
300	r_dcache_tlb_set("r_dcache_tlb_set"),
301
302	r_dcache_ll_valid("r_dcache_ll_valid"),
303	r_dcache_ll_data("r_dcache_ll_data"),
304	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
305
306	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
307	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
308
309	r_dcache_xtn_req("r_dcache_xtn_req"),
310	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
311
312	r_dcache_cleanup_req("r_dcache_cleanup_req"),
313	r_dcache_cleanup_line("r_dcache_cleanup_line"),
314
315	r_vci_cmd_fsm("r_vci_cmd_fsm"),
316	r_vci_cmd_min("r_vci_cmd_min"),
317	r_vci_cmd_max("r_vci_cmd_max"),
318	r_vci_cmd_cpt("r_vci_cmd_cpt"),
319	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
320
321	r_vci_rsp_fsm("r_vci_rsp_fsm"),
322	r_vci_rsp_cpt("r_vci_rsp_cpt"),
323	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
324	r_vci_rsp_data_error("r_vci_rsp_data_error"),
325	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
326	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
327
328	r_cleanup_fsm("r_cleanup_fsm"),
329	r_cleanup_trdid("r_cleanup_trdid"),
330	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
331
332	r_tgt_fsm("r_tgt_fsm"),
333	r_tgt_paddr("r_tgt_paddr"),
334	r_tgt_word_count("r_tgt_word_count"),
335	r_tgt_word_min("r_tgt_word_min"),
336	r_tgt_word_max("r_tgt_word_max"),
337	r_tgt_update("r_tgt_update"),
338	r_tgt_update_data("r_tgt_update_data"),
339	r_tgt_srcid("r_tgt_srcid"),
340	r_tgt_pktid("r_tgt_pktid"),
341	r_tgt_trdid("r_tgt_trdid"),
342
343	r_tgt_icache_req("r_tgt_icache_req"),
344	r_tgt_dcache_req("r_tgt_dcache_req"),
345	r_tgt_icache_rsp("r_tgt_icache_rsp"),
346	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
347
348	r_iss(this->name(), proc_id),
349	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
350	r_icache("icache", icache_ways, icache_sets, icache_words),
351	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
352	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
353	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
354	{
355	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
356	"Need more PLEN bits.");
357
358	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
359	"Need more TRDID bits.");
360
361	assert( (icache_words == dcache_words) and
362	"icache_words and dcache_words parameters must be equal");
363
364	assert( (itlb_sets == dtlb_sets) and
365	"itlb_sets and dtlb_sets parameters must be etqual");
366
367	assert( (itlb_ways == dtlb_ways) and
368	"itlb_ways and dtlb_ways parameters must be etqual");
369
370	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
371	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
372	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
373	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
374	(uint32_log2(m_icache_words<<2));
375
376	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
377
378	r_tgt_buf = new uint32_t[dcache_words];
379	r_tgt_be = new vci_be_t[dcache_words];
380	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
381	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
382
383	SC_METHOD(transition);
384	dont_initialize();
385	sensitive << p_clk.pos();
386
387	SC_METHOD(genMoore);
388	dont_initialize();
389	sensitive << p_clk.neg();
390
391	typename iss_t::CacheInfo cache_info;
392	cache_info.has_mmu = true;
393	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
394	cache_info.icache_assoc = icache_ways;
395	cache_info.icache_n_lines = icache_sets;
396	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
397	cache_info.dcache_assoc = dcache_ways;
398	cache_info.dcache_n_lines = dcache_sets;
399	r_iss.setCacheInfo(cache_info);
400	}
401
402	/////////////////////////////////////
403	tmpl(/**/)::~VciCcVCacheWrapperV4()
404	/////////////////////////////////////
405	{
406	delete [] r_tgt_be;
407	delete [] r_tgt_buf;
408	delete [] r_dcache_in_tlb;
409	delete [] r_dcache_contains_ptd;
410	}
411
412	////////////////////////
413	tmpl(void)::print_cpi()
414	////////////////////////
415	{
416	std::cout << name() << " CPI = "
417	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
418	}
419
420	////////////////////////////////////
421	tmpl(void)::print_trace(size_t mode)
422	////////////////////////////////////
423	{
424	// b0 : write buffer trace
425	// b1 : write buffer verbose
426	// b2 : dcache trace
427	// b3 : icache trace
428	// b4 : dtlb trace
429	// b5 : itlb trace
430
431	std::cout << std::dec << "PROC " << name() << std::endl;
432
433	std::cout << " " << m_ireq << std::endl;
434	std::cout << " " << m_irsp << std::endl;
435	std::cout << " " << m_dreq << std::endl;
436	std::cout << " " << m_drsp << std::endl;
437
438	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
439	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
440	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
441	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
442	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
443	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
444	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
445	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
446	std::cout << std::endl;
447
448	if(mode & 0x01)
449	{
450	r_wbuf.printTrace((mode>>1)&1);
451	}
452	if(mode & 0x04)
453	{
454	std::cout << " Data Cache" << std::endl;
455	r_dcache.printTrace();
456	}
457	if(mode & 0x08)
458	{
459	std::cout << " Instruction Cache" << std::endl;
460	r_icache.printTrace();
461	}
462	if(mode & 0x10)
463	{
464	std::cout << " Data TLB" << std::endl;
465	r_dtlb.printTrace();
466	}
467	if(mode & 0x20)
468	{
469	std::cout << " Instruction TLB" << std::endl;
470	r_itlb.printTrace();
471	}
472	}
473
474	//////////////////////////////////////////
475	tmpl(void)::cache_monitor( paddr_t addr )
476	//////////////////////////////////////////
477	{
478	size_t cache_way;
479	size_t cache_set;
480	size_t cache_word;
481	uint32_t cache_rdata;
482	bool cache_hit = r_dcache.read_neutral( addr,
483	&cache_rdata,
484	&cache_way,
485	&cache_set,
486	&cache_word );
487	bool icache_hit = r_icache.read_neutral( addr,
488	&cache_rdata,
489	&cache_way,
490	&cache_set,
491	&cache_word );
492	if ( cache_hit != m_debug_previous_hit )
493	{
494	std::cout << "PROC " << name()
495	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
496	<< " for adresse " << std::hex << addr
497	<< " / HIT = " << std::dec << cache_hit << std::endl;
498	m_debug_previous_hit = cache_hit;
499	}
500	if ( icache_hit != m_idebug_previous_hit )
501	{
502	std::cout << "PROC " << name()
503	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
504	<< " for adresse " << std::hex << addr
505	<< " / HIT = " << icache_hit << std::endl;
506	m_idebug_previous_hit = icache_hit;
507	}
508	}
509
510	/*
511	////////////////////////
512	tmpl(void)::print_stats()
513	////////////////////////
514	{
515	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
516	std::cout << name() << std::endl
517	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
518	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
519	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
520	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
521	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
522	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
523	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
524	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
525	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
526	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
527	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
528	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
529	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
530	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
531	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
532	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
533	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
534	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
535	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
536	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
537	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
538	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
539	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
540	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
541	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
542	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
543	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
544	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
545	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
546	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
547	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
548	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
549	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
550	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
551	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
552	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
553	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
554	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
555	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
556	}
557
558	////////////////////////
559	tmpl(void)::clear_stats()
560	////////////////////////
561	{
562	m_cpt_dcache_data_read = 0;
563	m_cpt_dcache_data_write = 0;
564	m_cpt_dcache_dir_read = 0;
565	m_cpt_dcache_dir_write = 0;
566	m_cpt_icache_data_read = 0;
567	m_cpt_icache_data_write = 0;
568	m_cpt_icache_dir_read = 0;
569	m_cpt_icache_dir_write = 0;
570
571	m_cpt_frz_cycles = 0;
572	m_cpt_dcache_frz_cycles = 0;
573	m_cpt_total_cycles = 0;
574
575	m_cpt_read = 0;
576	m_cpt_write = 0;
577	m_cpt_data_miss = 0;
578	m_cpt_ins_miss = 0;
579	m_cpt_unc_read = 0;
580	m_cpt_write_cached = 0;
581	m_cpt_ins_read = 0;
582
583	m_cost_write_frz = 0;
584	m_cost_data_miss_frz = 0;
585	m_cost_unc_read_frz = 0;
586	m_cost_ins_miss_frz = 0;
587
588	m_cpt_imiss_transaction = 0;
589	m_cpt_dmiss_transaction = 0;
590	m_cpt_unc_transaction = 0;
591	m_cpt_write_transaction = 0;
592	m_cpt_icache_unc_transaction = 0;
593
594	m_cost_imiss_transaction = 0;
595	m_cost_dmiss_transaction = 0;
596	m_cost_unc_transaction = 0;
597	m_cost_write_transaction = 0;
598	m_cost_icache_unc_transaction = 0;
599	m_length_write_transaction = 0;
600
601	m_cpt_ins_tlb_read = 0;
602	m_cpt_ins_tlb_miss = 0;
603	m_cpt_ins_tlb_update_acc = 0;
604
605	m_cpt_data_tlb_read = 0;
606	m_cpt_data_tlb_miss = 0;
607	m_cpt_data_tlb_update_acc = 0;
608	m_cpt_data_tlb_update_dirty = 0;
609	m_cpt_ins_tlb_hit_dcache = 0;
610	m_cpt_data_tlb_hit_dcache = 0;
611	m_cpt_ins_tlb_occup_cache = 0;
612	m_cpt_data_tlb_occup_cache = 0;
613
614	m_cost_ins_tlb_miss_frz = 0;
615	m_cost_data_tlb_miss_frz = 0;
616	m_cost_ins_tlb_update_acc_frz = 0;
617	m_cost_data_tlb_update_acc_frz = 0;
618	m_cost_data_tlb_update_dirty_frz = 0;
619	m_cost_ins_tlb_occup_cache_frz = 0;
620	m_cost_data_tlb_occup_cache_frz = 0;
621
622	m_cpt_itlbmiss_transaction = 0;
623	m_cpt_itlb_ll_transaction = 0;
624	m_cpt_itlb_sc_transaction = 0;
625	m_cpt_dtlbmiss_transaction = 0;
626	m_cpt_dtlb_ll_transaction = 0;
627	m_cpt_dtlb_sc_transaction = 0;
628	m_cpt_dtlb_ll_dirty_transaction = 0;
629	m_cpt_dtlb_sc_dirty_transaction = 0;
630
631	m_cost_itlbmiss_transaction = 0;
632	m_cost_itlb_ll_transaction = 0;
633	m_cost_itlb_sc_transaction = 0;
634	m_cost_dtlbmiss_transaction = 0;
635	m_cost_dtlb_ll_transaction = 0;
636	m_cost_dtlb_sc_transaction = 0;
637	m_cost_dtlb_ll_dirty_transaction = 0;
638	m_cost_dtlb_sc_dirty_transaction = 0;
639
640	m_cpt_cc_update_data = 0;
641	m_cpt_cc_inval_ins = 0;
642	m_cpt_cc_inval_data = 0;
643	m_cpt_cc_broadcast = 0;
644
645	m_cost_updt_data_frz = 0;
646	m_cost_inval_ins_frz = 0;
647	m_cost_inval_data_frz = 0;
648	m_cost_broadcast_frz = 0;
649
650	m_cpt_cc_cleanup_data = 0;
651	m_cpt_cc_cleanup_ins = 0;
652	}
653
654	*/
655
656	/////////////////////////
657	tmpl(void)::transition()
658	/////////////////////////
659	{
660	if ( not p_resetn.read() )
661	{
662	r_iss.reset();
663	r_wbuf.reset();
664	r_icache.reset();
665	r_dcache.reset();
666	r_itlb.reset();
667	r_dtlb.reset();
668
669	r_dcache_fsm = DCACHE_IDLE;
670	r_icache_fsm = ICACHE_IDLE;
671	r_vci_cmd_fsm = CMD_IDLE;
672	r_vci_rsp_fsm = RSP_IDLE;
673	r_tgt_fsm = TGT_IDLE;
674	r_cleanup_fsm = CLEANUP_DATA_IDLE;
675
676	// reset dcache directory extension
677	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
678	{
679	r_dcache_in_tlb[i] = false;
680	r_dcache_contains_ptd[i] = false;
681	}
682
683	// Response FIFOs and cleanup buffer
684	r_vci_rsp_fifo_icache.init();
685	r_vci_rsp_fifo_dcache.init();
686	r_cleanup_buffer.reset();
687
688	// ICACHE & DCACHE activated
689	r_mmu_mode = 0x3;
690
691	// No request from ICACHE FSM to CMD FSM
692	r_icache_miss_req = false;
693	r_icache_unc_req = false;
694
695	// No request from ICACHE_FSM to DCACHE FSM
696	r_icache_tlb_miss_req = false;
697
698	// No request from ICACHE_FSM to CLEANUP FSMs
699	r_icache_cleanup_req = false;
700
701	// No pending write in pipeline
702	r_dcache_p0_valid = false;
703	r_dcache_p1_valid = false;
704
705	// No request from DCACHE_FSM to CMD_FSM
706	r_dcache_vci_miss_req = false;
707	r_dcache_vci_unc_req = false;
708	r_dcache_vci_sc_req = false;
709
710	// No uncacheable write pending
711	r_dcache_pending_unc_write = false;
712
713	// No LL reservation
714	r_dcache_ll_valid = false;
715
716	// No processor XTN request pending
717	r_dcache_xtn_req = false;
718
719	// No request from DCACHE FSM to CLEANUP FSMs
720	r_dcache_cleanup_req = false;
721
722	// No request from TGT FSM to ICACHE/DCACHE FSMs
723	r_tgt_icache_req = false;
724	r_tgt_dcache_req = false;
725
726	// No signalisation of a coherence request matching a pending miss
727	r_icache_miss_inval = false;
728	r_dcache_miss_inval = false;
729
730	// No signalisation of errors
731	r_vci_rsp_ins_error = false;
732	r_vci_rsp_data_error = false;
733
734	// Debug variables
735	m_debug_previous_hit = false;
736	m_idebug_previous_hit = false;
737	m_debug_dcache_fsm = false;
738	m_debug_icache_fsm = false;
739	m_debug_cleanup_fsm = false;
740
741	// activity counters
742	m_cpt_dcache_data_read = 0;
743	m_cpt_dcache_data_write = 0;
744	m_cpt_dcache_dir_read = 0;
745	m_cpt_dcache_dir_write = 0;
746	m_cpt_icache_data_read = 0;
747	m_cpt_icache_data_write = 0;
748	m_cpt_icache_dir_read = 0;
749	m_cpt_icache_dir_write = 0;
750
751	m_cpt_frz_cycles = 0;
752	m_cpt_total_cycles = 0;
753	m_cpt_stop_simulation = 0;
754
755	m_cpt_data_miss = 0;
756	m_cpt_ins_miss = 0;
757	m_cpt_unc_read = 0;
758	m_cpt_write_cached = 0;
759	m_cpt_ins_read = 0;
760
761	m_cost_write_frz = 0;
762	m_cost_data_miss_frz = 0;
763	m_cost_unc_read_frz = 0;
764	m_cost_ins_miss_frz = 0;
765
766	m_cpt_imiss_transaction = 0;
767	m_cpt_dmiss_transaction = 0;
768	m_cpt_unc_transaction = 0;
769	m_cpt_write_transaction = 0;
770	m_cpt_icache_unc_transaction = 0;
771
772	m_cost_imiss_transaction = 0;
773	m_cost_dmiss_transaction = 0;
774	m_cost_unc_transaction = 0;
775	m_cost_write_transaction = 0;
776	m_cost_icache_unc_transaction = 0;
777	m_length_write_transaction = 0;
778
779	m_cpt_ins_tlb_read = 0;
780	m_cpt_ins_tlb_miss = 0;
781	m_cpt_ins_tlb_update_acc = 0;
782
783	m_cpt_data_tlb_read = 0;
784	m_cpt_data_tlb_miss = 0;
785	m_cpt_data_tlb_update_acc = 0;
786	m_cpt_data_tlb_update_dirty = 0;
787	m_cpt_ins_tlb_hit_dcache = 0;
788	m_cpt_data_tlb_hit_dcache = 0;
789	m_cpt_ins_tlb_occup_cache = 0;
790	m_cpt_data_tlb_occup_cache = 0;
791
792	m_cost_ins_tlb_miss_frz = 0;
793	m_cost_data_tlb_miss_frz = 0;
794	m_cost_ins_tlb_update_acc_frz = 0;
795	m_cost_data_tlb_update_acc_frz = 0;
796	m_cost_data_tlb_update_dirty_frz = 0;
797	m_cost_ins_tlb_occup_cache_frz = 0;
798	m_cost_data_tlb_occup_cache_frz = 0;
799
800	m_cpt_ins_tlb_inval = 0;
801	m_cpt_data_tlb_inval = 0;
802	m_cost_ins_tlb_inval_frz = 0;
803	m_cost_data_tlb_inval_frz = 0;
804
805	m_cpt_cc_broadcast = 0;
806
807	m_cost_updt_data_frz = 0;
808	m_cost_inval_ins_frz = 0;
809	m_cost_inval_data_frz = 0;
810	m_cost_broadcast_frz = 0;
811
812	m_cpt_cc_cleanup_data = 0;
813	m_cpt_cc_cleanup_ins = 0;
814
815	m_cpt_itlbmiss_transaction = 0;
816	m_cpt_itlb_ll_transaction = 0;
817	m_cpt_itlb_sc_transaction = 0;
818	m_cpt_dtlbmiss_transaction = 0;
819	m_cpt_dtlb_ll_transaction = 0;
820	m_cpt_dtlb_sc_transaction = 0;
821	m_cpt_dtlb_ll_dirty_transaction = 0;
822	m_cpt_dtlb_sc_dirty_transaction = 0;
823
824	m_cost_itlbmiss_transaction = 0;
825	m_cost_itlb_ll_transaction = 0;
826	m_cost_itlb_sc_transaction = 0;
827	m_cost_dtlbmiss_transaction = 0;
828	m_cost_dtlb_ll_transaction = 0;
829	m_cost_dtlb_sc_transaction = 0;
830	m_cost_dtlb_ll_dirty_transaction = 0;
831	m_cost_dtlb_sc_dirty_transaction = 0;
832	/*
833	m_cpt_dcache_frz_cycles = 0;
834	m_cpt_read = 0;
835	m_cpt_write = 0;
836	m_cpt_cc_update_data = 0;
837	m_cpt_cc_inval_ins = 0;
838	m_cpt_cc_inval_data = 0;
839	*/
840
841	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
842	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
843	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
844	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
845	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
846	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
847	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
848
849	return;
850	}
851
852	// Response FIFOs default values
853	bool vci_rsp_fifo_icache_get = false;
854	bool vci_rsp_fifo_icache_put = false;
855	uint32_t vci_rsp_fifo_icache_data = 0;
856
857	bool vci_rsp_fifo_dcache_get = false;
858	bool vci_rsp_fifo_dcache_put = false;
859	uint32_t vci_rsp_fifo_dcache_data = 0;
860
861	#ifdef INSTRUMENTATION
862	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
863	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
864	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
865	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
866	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
867	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
868	#endif
869
870	m_cpt_total_cycles++;
871
872	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
873	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
874	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
875
876	/////////////////////////////////////////////////////////////////////
877	// The TGT_FSM controls the following ressources:
878	// - r_tgt_fsm
879	// - r_tgt_buf[nwords]
880	// - r_tgt_be[nwords]
881	// - r_tgt_update
882	// - r_tgt_word_min
883	// - r_tgt_word_max
884	// - r_tgt_word_count
885	// - r_tgt_paddr
886	// - r_tgt_srcid
887	// - r_tgt_trdid
888	// - r_tgt_pktid
889	// - r_tgt_icache_req (set)
890	// - r_tgt_dcache_req (set)
891	//
892	// All VCI commands must be CMD_WRITE.
893	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
894	// It is a multicast request otherwise.
895	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
896	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
897	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
898	//
899	// For all types of coherence request, the line index (i.e. the Z & Y fields)
900	// is coded on 34 bits, and is contained in the WDATA and BE fields
901	// of the first VCI flit.
902	// - for a multicast invalidate or for a broadcast invalidate request
903	// the VCI packet length is 1 word.
904	// - for an update request the VCI packet length is (n+2) words.
905	// The WDATA field of the second VCI word contains the word index.
906	// The WDATA field of the n following words contains the values.
907	// - for all transaction types, the VCI response is one single word.
908	// In case of errors in the VCI command packet, the simulation
909	// is stopped with an error message.
910	//
911	// This FSM is NOT pipelined : It consumes a new coherence request
912	// on the VCI port only when the previous request is completed.
913	//
914	// The VCI_TGT FSM stores the external request arguments in the
915	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
916	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
917	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
918	// states. It waits the completion of the coherence request by polling the
919	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
920	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
921	// These two FSMs signal if a VCI answer must be send by setting
922	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
923	///////////////////////////////////////////////////////////////////////////////
924
925	switch( r_tgt_fsm.read() )
926	{
927	//////////////
928	case TGT_IDLE:
929	{
930	if ( p_vci_tgt_c.cmdval.read() )
931	{
932	paddr_t address = p_vci_tgt_c.address.read();
933
934	// command checking
935	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
936	{
937	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
938	std::cout << "the received VCI coherence command is not a write" << std::endl;
939	exit(0);
940	}
941
942	// address checking
943	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
944	{
945	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
946	std::cout << "out of segment VCI coherence command received" << std::endl;
947	exit(0);
948	}
949
950	r_tgt_srcid = p_vci_tgt_c.srcid.read();
951	r_tgt_trdid = p_vci_tgt_c.trdid.read();
952	r_tgt_pktid = p_vci_tgt_c.pktid.read();
953
954	if (sizeof(paddr_t) <= 32) {
955	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
956	r_tgt_paddr =
957	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
958	} else {
959	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
960	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
961	}
962
963	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
964	{
965	if ( not p_vci_tgt_c.eop.read() )
966	{
967	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
968	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
969	exit(0);
970	}
971	r_tgt_update = false;
972	r_tgt_fsm = TGT_REQ_BROADCAST;
973
974	#ifdef INSTRUMENTATION
975	m_cpt_cc_broadcast++;
976	#endif
977	}
978	else // multi-update or multi-invalidate for data type
979	{
980	paddr_t cell = address - m_segment.baseAddress();
981
982	if (cell == 0) // invalidate data
983	{
984	if ( not p_vci_tgt_c.eop.read() )
985	{
986	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
987	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
988	exit(0);
989	}
990	r_tgt_update = false;
991	r_tgt_fsm = TGT_REQ_DCACHE;
992
993	#ifdef INSTRUMENTATION
994	m_cpt_cc_inval_dcache++;
995	#endif
996	}
997	else if (cell == 4) // invalidate instruction
998	{
999	if ( not p_vci_tgt_c.eop.read() )
1000	{
1001	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1002	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1003	exit(0);
1004	}
1005	r_tgt_update = false;
1006	r_tgt_fsm = TGT_REQ_ICACHE;
1007
1008	#ifdef INSTRUMENTATION
1009	m_cpt_cc_inval_icache++;
1010	#endif
1011	}
1012	else if (cell == 8) // update data
1013	{
1014	if ( p_vci_tgt_c.eop.read() )
1015	{
1016	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1017	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1018	exit(0);
1019	}
1020	r_tgt_update = true;
1021	r_tgt_update_data = true;
1022	r_tgt_fsm = TGT_UPDT_WORD;
1023
1024	#ifdef INSTRUMENTATION
1025	m_cpt_cc_update_dcache++;
1026	#endif
1027	}
1028	else // update instruction
1029	{
1030	if ( p_vci_tgt_c.eop.read() )
1031	{
1032	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1033	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1034	exit(0);
1035	}
1036	r_tgt_update = true;
1037	r_tgt_update_data = false;
1038	r_tgt_fsm = TGT_UPDT_WORD;
1039
1040	#ifdef INSTRUMENTATION
1041	m_cpt_cc_update_icache++;
1042	#endif
1043	}
1044	} // end if multi
1045	} // end if cmdval
1046	break;
1047	}
1048	///////////////////
1049	case TGT_UPDT_WORD: // first word index acquisition
1050	{
1051	if (p_vci_tgt_c.cmdval.read())
1052	{
1053	if ( p_vci_tgt_c.eop.read() )
1054	{
1055	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1056	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1057	exit(0);
1058	}
1059	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1060
1061	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1062	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1063	r_tgt_fsm = TGT_UPDT_DATA;
1064	}
1065	break;
1066	}
1067	///////////////////
1068	case TGT_UPDT_DATA:
1069	{
1070	if (p_vci_tgt_c.cmdval.read())
1071	{
1072	size_t word = r_tgt_word_count.read();
1073	if (word >= m_dcache_words)
1074	{
1075	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1076	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1077	exit(0);
1078	}
1079	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1080	r_tgt_be[word] = p_vci_tgt_c.be.read();
1081	r_tgt_word_count = word + 1;
1082
1083	if (p_vci_tgt_c.eop.read()) // last word
1084	{
1085	r_tgt_word_max = word;
1086	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1087	else r_tgt_fsm = TGT_REQ_ICACHE;
1088	}
1089	}
1090	break;
1091	}
1092	///////////////////////
1093	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1094	{
1095	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1096	{
1097	r_tgt_fsm = TGT_RSP_BROADCAST;
1098	r_tgt_icache_req = true;
1099	r_tgt_dcache_req = true;
1100	}
1101	break;
1102	}
1103	/////////////////////
1104	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1105	{
1106	if ( not r_tgt_icache_req.read() )
1107	{
1108	r_tgt_fsm = TGT_RSP_ICACHE;
1109	r_tgt_icache_req = true;
1110	}
1111	break;
1112	}
1113	////////////////////
1114	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1115	{
1116	if ( not r_tgt_dcache_req.read() )
1117	{
1118	r_tgt_fsm = TGT_RSP_DCACHE;
1119	r_tgt_dcache_req = true;
1120	}
1121	break;
1122	}
1123	///////////////////////
1124	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1125	// no response when r_tgt_*cache_rsp is false
1126	{
1127	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1128	{
1129	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1130	{
1131	if ( p_vci_tgt_c.rspack.read() )
1132	{
1133	// reset dcache first if activated
1134	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1135	else r_tgt_icache_rsp = false;
1136	}
1137	}
1138	else
1139	{
1140	r_tgt_fsm = TGT_IDLE;
1141	}
1142	}
1143	break;
1144	}
1145	////////////////////
1146	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1147	{
1148	// no response when r_tgt_icache_rsp is false
1149	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1150	{
1151	r_tgt_fsm = TGT_IDLE;
1152	r_tgt_icache_rsp = false;
1153	}
1154	break;
1155	}
1156	////////////////////
1157	case TGT_RSP_DCACHE:
1158	{
1159	// no response when r_tgt_dcache_rsp is false
1160	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1161	{
1162	r_tgt_fsm = TGT_IDLE;
1163	r_tgt_dcache_rsp = false;
1164	}
1165	break;
1166	}
1167	} // end switch TGT_FSM
1168
1169	/////////////////////////////////////////////////////////////////////
1170	// Get data and instruction requests from processor
1171	///////////////////////////////////////////////////////////////////////
1172
1173	r_iss.getRequests(m_ireq, m_dreq);
1174
1175	////////////////////////////////////////////////////////////////////////////////////
1176	// ICACHE_FSM
1177	//
1178	// There is 9 conditions to exit the IDLE state:
1179	// One condition is a coherence request from TGT FSM :
1180	// - Coherence operation => ICACHE_CC_CHEK
1181	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1182	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1183	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1184	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1185	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1186	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1187	// three configurations corresponding to instruction processor requests :
1188	// - tlb miss => ICACHE_TLB_WAIT
1189	// - cacheable read miss => ICACHE_MISS_VICTIM
1190	// - uncacheable read miss => ICACHE_UNC_REQ
1191	//
1192	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1193	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1194	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1195	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1196	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1197	// The availability of the missing cache line is signaled by the response fifo,
1198	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1199	//
1200	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1201	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1202	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1203	// the response from the RSP FSM, through the response fifo. The missing instruction
1204	// is directly returned to processor in this state.
1205	//
1206	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1207	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1208	// and goes to the ICACHE_TLB_WAIT state.
1209	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1210	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1211	//
1212	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1213	// using the r_dcache_xtn_req flip-flop.
1214	// The request opcode and the address to be invalidated are transmitted
1215	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1216	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1217	// is completed.
1218	//
1219	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1220	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1221	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1222	////////////////////////////////////////////////////////////////////////////////////////
1223
1224	// default value for m_irsp
1225	m_irsp.valid = false;
1226	m_irsp.error = false;
1227	m_irsp.instruction = 0;
1228
1229	switch( r_icache_fsm.read() )
1230	{
1231	/////////////////
1232	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1233	// by DCACHE FSM, and coherence requests with a fixed priority:
1234	// coherence > XTN > instruction
1235	// We access the itlb and dcache in parallel with the virtual address
1236	// for itlb, and with a speculative physical address for icache,
1237	// computed during the previous cycle.
1238	{
1239	// coherence request from the target FSM
1240	if ( r_tgt_icache_req.read() )
1241	{
1242	r_icache_fsm = ICACHE_CC_CHECK;
1243	r_icache_fsm_save = r_icache_fsm.read();
1244	break;
1245	}
1246
1247	// Decoding processor XTN requests sent by DCACHE FSM
1248	// These request are not executed in this IDLE state, because
1249	// they require access to icache or itlb, that are already accessed
1250	if ( r_dcache_xtn_req.read() )
1251	{
1252	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1253	{
1254	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1255	break;
1256	}
1257	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1258	{
1259	r_icache_flush_count = 0;
1260	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1261	break;
1262	}
1263	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1264	{
1265	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1266	break;
1267	}
1268	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1269	{
1270	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1271	break;
1272	}
1273	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1274	{
1275	if (sizeof(paddr_t) <= 32) {
1276	assert(r_mmu_word_hi.read() == 0 &&
1277	"high bits should be 0 for 32bit paddr");
1278	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1279	} else {
1280	r_icache_vci_paddr =
1281	(paddr_t)r_mmu_word_hi.read() << 32 \|
1282	(paddr_t)r_mmu_word_lo.read();
1283	}
1284	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1285	break;
1286	}
1287	} // end if xtn_req
1288
1289	// processor request
1290	if ( m_ireq.valid )
1291	{
1292	bool cacheable;
1293	paddr_t paddr;
1294
1295	// We register processor request
1296	r_icache_vaddr_save = m_ireq.addr;
1297
1298	// speculative icache access (if cache activated)
1299	// we use the speculative PPN computed during the previous cycle
1300
1301	uint32_t cache_inst = 0;
1302	bool cache_hit = false;
1303
1304	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1305	{
1306	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1307	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1308
1309	#ifdef INSTRUMENTATION
1310	m_cpt_icache_data_read++;
1311	m_cpt_icache_dir_read++;
1312	#endif
1313	cache_hit = r_icache.read( spc_paddr,
1314	&cache_inst );
1315	}
1316
1317	// systematic itlb access (if tlb activated)
1318	// we use the virtual address
1319
1320	paddr_t tlb_paddr;
1321	pte_info_t tlb_flags;
1322	size_t tlb_way;
1323	size_t tlb_set;
1324	paddr_t tlb_nline;
1325	bool tlb_hit = false;;
1326
1327	if ( r_mmu_mode.read() & INS_TLB_MASK )
1328	{
1329
1330	#ifdef INSTRUMENTATION
1331	m_cpt_itlb_read++;
1332	#endif
1333	tlb_hit = r_itlb.translate( m_ireq.addr,
1334	&tlb_paddr,
1335	&tlb_flags,
1336	&tlb_nline, // unused
1337	&tlb_way, // unused
1338	&tlb_set ); // unused
1339	}
1340
1341	// We compute cacheability, physical address and check access rights:
1342	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1343	// the physical address is obtained from the TLB, and the access rights are
1344	// defined by the U and X bits in the PTE.
1345	// - If MMU not activated : cacheability is defined by the segment table,
1346	// the physical address is equal to the virtual address (identity mapping)
1347	// and there is no access rights checking
1348
1349	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1350	{
1351	// cacheability
1352	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1353	else cacheable = m_cacheability_table[m_ireq.addr];
1354
1355	// physical address
1356	paddr = (paddr_t)m_ireq.addr;
1357	}
1358	else // itlb activated
1359	{
1360	if ( tlb_hit ) // tlb hit
1361	{
1362	// cacheability
1363	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1364	else cacheable = tlb_flags.c;
1365
1366	// physical address
1367	paddr = tlb_paddr;
1368
1369	// access rights checking
1370	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1371	{
1372	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1373	r_mmu_ibvar = m_ireq.addr;
1374	m_irsp.valid = true;
1375	m_irsp.error = true;
1376	m_irsp.instruction = 0;
1377	break;
1378	}
1379	else if ( not tlb_flags.x )
1380	{
1381	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1382	r_mmu_ibvar = m_ireq.addr;
1383	m_irsp.valid = true;
1384	m_irsp.error = true;
1385	m_irsp.instruction = 0;
1386	break;
1387	}
1388	}
1389	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1390	else
1391	{
1392
1393	#ifdef INSTRUMENTATION
1394	m_cpt_itlb_miss++;
1395	#endif
1396	r_icache_fsm = ICACHE_TLB_WAIT;
1397	r_icache_tlb_miss_req = true;
1398	break;
1399	}
1400	} // end if itlb activated
1401
1402	// physical address registration (for next cycle)
1403	r_icache_vci_paddr = paddr;
1404
1405	// We enter this section only in case of TLB hit:
1406	// Finally, we get the instruction depending on cacheability,
1407	// we send the response to processor, and compute next state
1408	if ( cacheable ) // cacheable read
1409	{
1410	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1411	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1412	{
1413
1414	#ifdef INSTRUMENTATION
1415	m_cpt_icache_spc_miss++;
1416	#endif
1417	// we return an invalid response and stay in IDLE state
1418	// the cache access will cost one extra cycle.
1419	break;
1420	}
1421
1422	if ( not cache_hit ) // cache miss
1423	{
1424
1425	#ifdef INSTRUMENTATION
1426	m_cpt_icache_miss++;
1427	#endif
1428	r_icache_fsm = ICACHE_MISS_VICTIM;
1429	r_icache_miss_req = true;
1430	}
1431	else // cache hit
1432	{
1433
1434	#ifdef INSTRUMENTATION
1435	m_cpt_ins_read++;
1436	#endif
1437	m_irsp.valid = true;
1438	m_irsp.instruction = cache_inst;
1439	}
1440	}
1441	else // non cacheable read
1442	{
1443	r_icache_unc_req = true;
1444	r_icache_fsm = ICACHE_UNC_WAIT;
1445	}
1446	} // end if m_ireq.valid
1447	break;
1448	}
1449	/////////////////////
1450	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1451	// the itlb is udated by the DCACHE FSM, as well as the
1452	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1453	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1454	// reset the r_icache_tlb_miss_req flip-flop
1455	// external coherence request are accepted in this state.
1456	{
1457	// external coherence request
1458	if ( r_tgt_icache_req.read() )
1459	{
1460	r_icache_fsm = ICACHE_CC_CHECK;
1461	r_icache_fsm_save = r_icache_fsm.read();
1462	break;
1463	}
1464
1465	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1466
1467	// DCACHE FSM signals response by reseting the request flip-flop
1468	if ( not r_icache_tlb_miss_req.read() )
1469	{
1470	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1471	{
1472	r_icache_tlb_rsp_error = false;
1473	m_irsp.error = true;
1474	m_irsp.valid = true;
1475	r_icache_fsm = ICACHE_IDLE;
1476	}
1477	else // tlb updated : return to IDLE state
1478	{
1479	r_icache_fsm = ICACHE_IDLE;
1480	}
1481	}
1482	break;
1483	}
1484	//////////////////////////
1485	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1486	{
1487	r_itlb.flush();
1488	r_dcache_xtn_req = false;
1489	r_icache_fsm = ICACHE_IDLE;
1490	break;
1491	}
1492	////////////////////////////
1493	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1494	// the r_icache_flush_count register as a slot counter.
1495	// We loop in this state until all slots have been visited.
1496	// A cleanup request is generated for each valid line
1497	// and we are blocked until the previous cleanup is completed
1498	{
1499	if ( not r_icache_cleanup_req.read() )
1500	{
1501	size_t way = r_icache_flush_count.read()/m_icache_sets;
1502	size_t set = r_icache_flush_count.read()%m_icache_sets;
1503	paddr_t nline;
1504	bool cleanup_req = r_icache.inval( way,
1505	set,
1506	&nline );
1507	if ( cleanup_req )
1508	{
1509	r_icache_cleanup_req = true;
1510	r_icache_cleanup_line = nline;
1511	}
1512	r_icache_flush_count = r_icache_flush_count.read() + 1;
1513
1514
1515	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1516	{
1517	r_dcache_xtn_req = false;
1518	r_icache_fsm = ICACHE_IDLE;
1519	}
1520	}
1521
1522	break;
1523	}
1524	//////////////////////////
1525	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1526	// stored in the r_dcache_p0_wdata register
1527	{
1528	r_itlb.inval(r_dcache_p0_wdata.read());
1529	r_dcache_xtn_req = false;
1530	r_icache_fsm = ICACHE_IDLE;
1531	break;
1532	}
1533	///////////////////////////////
1534	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1535	// requires 3 cycles (in case of hit on itlb and icache).
1536	// In this state, we access TLB to translate virtual address
1537	// stored in the r_dcache_p0_wdata register.
1538	{
1539	paddr_t paddr;
1540	bool hit;
1541
1542	// read physical address in TLB when MMU activated
1543	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1544	{
1545
1546	#ifdef INSTRUMENTATION
1547	m_cpt_itlb_read++;
1548	#endif
1549	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1550	&paddr);
1551	}
1552	else // itlb not activated
1553	{
1554	paddr = (paddr_t)r_dcache_p0_wdata.read();
1555	hit = true;
1556	}
1557
1558	if ( hit ) // continue the selective inval process
1559	{
1560	r_icache_vci_paddr = paddr;
1561	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1562	}
1563	else // miss : send a request to DCACHE FSM
1564	{
1565
1566	#ifdef INSTRUMENTATION
1567	m_cpt_itlb_miss++;
1568	#endif
1569	r_icache_tlb_miss_req = true;
1570	r_icache_fsm = ICACHE_TLB_WAIT;
1571	}
1572	break;
1573	}
1574	///////////////////////////////
1575	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1576	// require 2 cycles. In this state, we read dcache,
1577	// with address stored in r_icache_vci_paddr register.
1578	{
1579	uint32_t data;
1580	size_t way;
1581	size_t set;
1582	size_t word;
1583	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1584	&data,
1585	&way,
1586	&set,
1587	&word);
1588	if ( hit ) // inval to be done
1589	{
1590	r_icache_miss_way = way;
1591	r_icache_miss_set = set;
1592	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1593	}
1594	else // miss : acknowlege the XTN request and return
1595	{
1596	r_dcache_xtn_req = false;
1597	r_icache_fsm = ICACHE_IDLE;
1598	}
1599	break;
1600	}
1601	///////////////////////////////
1602	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1603	// We are blocked if the previous cleanup is not completed
1604	{
1605	paddr_t nline;
1606
1607	if ( not r_icache_cleanup_req.read() )
1608	{
1609	bool hit;
1610	hit = r_icache.inval( r_icache_miss_way.read(),
1611	r_icache_miss_set.read(),
1612	&nline );
1613	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1614
1615	// request cleanup
1616	r_icache_cleanup_req = true;
1617	r_icache_cleanup_line = nline;
1618	// acknowledge the XTN request and return
1619	r_dcache_xtn_req = false;
1620	r_icache_fsm = ICACHE_IDLE;
1621	}
1622	break;
1623	}
1624
1625	////////////////////////
1626	case ICACHE_MISS_VICTIM: // Selects a victim line
1627	// Set the r_icache_cleanup_req flip-flop
1628	// when the selected slot is not empty
1629	{
1630	m_cost_ins_miss_frz++;
1631
1632	size_t index; // unused
1633	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1634	if ( not hit and not r_icache_cleanup_req.read() )
1635	{
1636	bool valid;
1637	size_t way;
1638	size_t set;
1639	paddr_t victim;
1640
1641	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1642	&victim,
1643	&way,
1644	&set);
1645	r_icache_miss_way = way;
1646	r_icache_miss_set = set;
1647
1648	if ( valid )
1649	{
1650	r_icache_cleanup_req = true;
1651	r_icache_cleanup_line = victim;
1652	r_icache_fsm = ICACHE_MISS_INVAL;
1653	}
1654	else
1655	{
1656	r_icache_fsm = ICACHE_MISS_WAIT;
1657	}
1658	}
1659	break;
1660	}
1661	///////////////////////
1662	case ICACHE_MISS_INVAL: // invalidate the victim line
1663	{
1664	paddr_t nline;
1665	bool hit;
1666
1667	hit = r_icache.inval( r_icache_miss_way.read(),
1668	r_icache_miss_set.read(),
1669	&nline ); // unused
1670	assert(hit && "selected way/set line should be in icache");
1671
1672	r_icache_fsm = ICACHE_MISS_WAIT;
1673	break;
1674	}
1675	//////////////////////
1676	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1677	{
1678	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1679
1680	// external coherence request
1681	if ( r_tgt_icache_req.read() )
1682	{
1683	r_icache_fsm = ICACHE_CC_CHECK;
1684	r_icache_fsm_save = r_icache_fsm.read();
1685	break;
1686	}
1687
1688	if ( r_vci_rsp_ins_error.read() ) // bus error
1689	{
1690	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1691	r_mmu_ibvar = r_icache_vaddr_save.read();
1692	m_irsp.valid = true;
1693	m_irsp.error = true;
1694	r_vci_rsp_ins_error = false;
1695	r_icache_fsm = ICACHE_IDLE;
1696	}
1697	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1698	{
1699	r_icache_miss_word = 0;
1700	r_icache_fsm = ICACHE_MISS_UPDT;
1701	}
1702	break;
1703	}
1704	//////////////////////
1705	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1706	{
1707	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1708
1709	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1710	{
1711	if ( r_icache_miss_inval ) // Matching coherence request
1712	// We pop the response FIFO, without updating the cache
1713	// We send a cleanup for the missing line at the last word
1714	// Blocked if the previous cleanup is not completed
1715	{
1716	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1717	{
1718	vci_rsp_fifo_icache_get = true;
1719	r_icache_miss_word = r_icache_miss_word.read() + 1;
1720	}
1721	else // last word
1722	{
1723	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1724	{
1725	vci_rsp_fifo_icache_get = true;
1726	r_icache_cleanup_req = true;
1727	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1728	r_icache_miss_inval = false;
1729	r_icache_fsm = ICACHE_IDLE;
1730	}
1731	}
1732	}
1733	else // No matching coherence request
1734	// We pop the FIFO and update the cache
1735	// We update the directory at the last word
1736	{
1737
1738	#ifdef INSTRUMENTATION
1739	m_cpt_icache_data_write++;
1740	#endif
1741	r_icache.write( r_icache_miss_way.read(),
1742	r_icache_miss_set.read(),
1743	r_icache_miss_word.read(),
1744	r_vci_rsp_fifo_icache.read() );
1745	vci_rsp_fifo_icache_get = true;
1746	r_icache_miss_word = r_icache_miss_word.read() + 1;
1747	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1748	{
1749
1750	#ifdef INSTRUMENTATION
1751	m_cpt_icache_dir_write++;
1752	#endif
1753	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1754	r_icache_miss_way.read(),
1755	r_icache_miss_set.read() );
1756	r_icache_fsm = ICACHE_IDLE;
1757	}
1758	}
1759	}
1760	break;
1761	}
1762	////////////////////
1763	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1764	//
1765	{
1766	// external coherence request
1767	if ( r_tgt_icache_req.read() )
1768	{
1769	r_icache_fsm = ICACHE_CC_CHECK;
1770	r_icache_fsm_save = r_icache_fsm.read();
1771	break;
1772	}
1773
1774	if ( r_vci_rsp_ins_error.read() ) // bus error
1775	{
1776	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1777	r_mmu_ibvar = m_ireq.addr;
1778	r_vci_rsp_ins_error = false;
1779	m_irsp.valid = true;
1780	m_irsp.error = true;
1781	r_icache_fsm = ICACHE_IDLE;
1782	}
1783	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1784	{
1785	vci_rsp_fifo_icache_get = true;
1786	r_icache_fsm = ICACHE_IDLE;
1787	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1788	{
1789	m_irsp.valid = true;
1790	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1791	}
1792	}
1793	break;
1794	}
1795	/////////////////////
1796	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1797	// handling coherence requests.
1798	// the return state is defined in r_icache_fsm_save.
1799	{
1800	paddr_t paddr = r_tgt_paddr.read();
1801	paddr_t mask = ~((m_icache_words<<2)-1);
1802
1803	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1804	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1805	{
1806	r_icache_miss_inval = true; // signaling the matching
1807	r_tgt_icache_req = false; // coherence request completed
1808	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1809	r_icache_fsm = r_icache_fsm_save.read();
1810	}
1811	else // no match
1812	{
1813
1814	#ifdef INSTRUMENTATION
1815	m_cpt_icache_dir_read++;
1816	#endif
1817	uint32_t inst;
1818	size_t way;
1819	size_t set;
1820	size_t word;
1821	bool hit = r_icache.read(paddr,
1822	&inst,
1823	&way,
1824	&set,
1825	&word);
1826	r_icache_cc_way = way;
1827	r_icache_cc_set = set;
1828
1829	if ( hit and r_tgt_update.read() ) // hit update
1830	{
1831	r_icache_fsm = ICACHE_CC_UPDT;
1832	r_icache_cc_word = r_tgt_word_min.read();
1833	}
1834	else if ( hit and not r_tgt_update.read() ) // hit inval
1835	{
1836	r_icache_fsm = ICACHE_CC_INVAL;
1837	}
1838	else // miss can happen
1839	{
1840	r_tgt_icache_req = false;
1841	r_tgt_icache_rsp = r_tgt_update.read();
1842	r_icache_fsm = r_icache_fsm_save.read();
1843	}
1844	}
1845	break;
1846	}
1847
1848	/////////////////////
1849	case ICACHE_CC_INVAL: // invalidate a cache line
1850	{
1851	paddr_t nline;
1852	bool hit;
1853	hit = r_icache.inval( r_icache_cc_way.read(),
1854	r_icache_cc_set.read(),
1855	&nline );
1856	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1857	r_tgt_icache_req = false;
1858	r_tgt_icache_rsp = true;
1859	r_icache_fsm = r_icache_fsm_save.read();
1860	break;
1861	}
1862	////////////////////
1863	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1864	{
1865	size_t word = r_icache_cc_word.read();
1866	size_t way = r_icache_cc_way.read();
1867	size_t set = r_icache_cc_set.read();
1868
1869	r_icache.write( way,
1870	set,
1871	word,
1872	r_tgt_buf[word],
1873	r_tgt_be[word] );
1874
1875	r_icache_cc_word = word+1;
1876
1877	if ( word == r_tgt_word_max.read() ) // last word
1878	{
1879	r_tgt_icache_req = false;
1880	r_tgt_icache_rsp = true;
1881	r_icache_fsm = r_icache_fsm_save.read();
1882	}
1883	break;
1884	}
1885
1886	} // end switch r_icache_fsm
1887
1888	////////////////////////////////////////////////////////////////////////////////////
1889	// DCACHE FSM
1890	//
1891	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1892	// the cacheability, depending on the MMU mode.
1893	//
1894	// 1/ Coherence requests :
1895	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1896	// requesting a line invalidation or a line update.
1897	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1898	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1899	// goes to the CC_CHECK state to execute the requested action, and returns to the
1900	// pre-empted state.
1901	//
1902	// 2/ TLB miss
1903	// The page tables can be cacheable.
1904	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1905	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1906	// this sub-fsm implement the table-walk...
1907	//
1908	// 3/ processor requests :
1909	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1910	// The IDLE state implements a three stages pipe-line to handle write bursts:
1911	// - The physical address is computed by dtlb in stage P0.
1912	// - The registration in wbuf and the dcache hit are computed in stage P1.
1913	// - The dcache update is done in stage P2.
1914	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1915	// that is done (before handling the processor request) by a dedicated sub-fsm
1916	// (DCACHE_DIRTY_TLB_SET state).
1917	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1918	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1919	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1920	// (virtual address for itlb, and speculative physical address computed during
1921	// previous cycle for dcache) in order to return the data in one cycle for a READ
1922	// request. We just pay an extra cycle when the speculative access is failing.
1923	//
1924	// 4/ Atomic instructions LL/SC
1925	// The LL/SC address can be cacheable or non cacheable.
1926	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1927	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1928	// memory controller.
1929	// - LL requests from the processor are transmitted as standard VCI
1930	// READ transactions (one word / one line, depending on the cacheability).
1931	// - SC requests from the processor are systematically transmitted to the
1932	// memory cache as Compare&swap requests (both the data value stored in the
1933	// r_dcache_ll_data register and the new value).
1934	// The cache is not updated, as this is done in case of success by the
1935	// coherence transaction.
1936	//
1937	// 5/ Non cacheable access:
1938	// This component implement a strong order between non cacheable access
1939	// (read or write) : A new non cacheable VCI transaction starts only when
1940	// the previous non cacheable transaction is completed. Both cacheable and
1941	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1942	// a non cacheable write transaction posted in the write buffer by setting the
1943	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1944	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1945	// pending non cacheable write transaction completes).
1946	//
1947	// 6/ Error handling:
1948	// When the MMU is not activated, Read Bus Errors are synchronous events,
1949	// but Write Bus Errors are asynchronous events (processor is not frozen).
1950	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1951	// r_vci_rsp_data_error flip-flop, without writing any data in the
1952	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1953	// by the DCACHE FSM.
1954	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1955	// the asynchronous error using the setWriteBerr() method.
1956	// When the MMU is activated bus error are rare events, as the MMU
1957	// checks the physical address before the VCI transaction starts.
1958	////////////////////////////////////////////////////////////////////////////////////////
1959
1960	// default value for m_drsp
1961	m_drsp.valid = false;
1962	m_drsp.error = false;
1963	m_drsp.rdata = 0;
1964
1965	switch ( r_dcache_fsm.read() )
1966	{
1967	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1968	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1969	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1970	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1971	// 4) XTN request (processor) => DCACHE_XTN_*
1972	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1973	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1974	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1975	// 8) SC access (processor) => DCACHE_SC_WAIT
1976	//
1977	// The dtlb is unconditionally accessed to translate the
1978	// virtual adress from processor.
1979	//
1980	// There is 4 configurations to access the cache,
1981	// depending on the pipe-line state, defined
1982	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1983	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1984	// V0 / V1 / Data / Directory / comment
1985	// 0 / 0 / read(A0) / read(A0) / read speculative access
1986	// 0 / 1 / write(A2) / nop / read request delayed
1987	// 1 / 0 / nop / read(A1) / read request delayed
1988	// 1 / 1 / write(A2) / read(A1) / read request delayed
1989	{
1990	bool tlb_inval_required = false;
1991	bool write_pipe_frozen = false;
1992
1993	////////////////////////////////////////////////////////////////////////////////
1994	// Handling P2 pipe-line stage
1995	// Inputs are r_dcache_p1_* registers.
1996	// If r_dcache_p1_valid is true, we update the local copy in dcache.
1997	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
1998	// operation, going to DCACHE_INVAL_TLB_SCAN state.
1999
2000	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2001	{
2002	size_t way = r_dcache_p1_cache_way.read();
2003	size_t set = r_dcache_p1_cache_set.read();
2004	size_t word = r_dcache_p1_cache_word.read();
2005	uint32_t wdata = r_dcache_p1_wdata.read();
2006	vci_be_t be = r_dcache_p1_be.read();
2007
2008	r_dcache.write( way,
2009	set,
2010	word,
2011	wdata,
2012	be );
2013	#ifdef INSTRUMENTATION
2014	m_cpt_dcache_data_write++;
2015	#endif
2016	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2017	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2018	{
2019	tlb_inval_required = true;
2020	r_dcache_tlb_inval_count = 0;
2021	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2022	(uint32_log2(m_dcache_words<<2));
2023	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2024	}
2025	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2026	{
2027	r_itlb.reset();
2028	r_dtlb.reset();
2029	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2030	}
2031
2032	#if DEBUG_DCACHE
2033	if ( m_debug_dcache_fsm )
2034	{
2035	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2036	<< " / WAY = " << way
2037	<< " / SET = " << set
2038	<< " / WORD = " << word << std::hex
2039	<< " / DATA = " << wdata
2040	<< " / BE = " << be << std::endl;
2041	}
2042	#endif
2043	} // end P2 stage
2044
2045	///////////////////////////////////////////////////////////////////////////
2046	// Handling P1 pipe-line stage
2047	// Inputs are r_dcache_p0_* registers.
2048	// We must write into wbuf and test the hit in dcache.
2049	// If the write request is non cacheable, and there is a pending
2050	// non cacheable write, or if the write buffer is full, the P0 and P1 stages
2051	// are frozen until the write request registration is possible,
2052	// while the P2 stage is not frozen.
2053	// The r_dcache_p1_valid bit must be computed at all cycles, and
2054	// the P2 stage must be activated if there is a local copy in dcache.
2055
2056	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2057	{
2058	// frozen if write not cacheable, and previous non cacheable write registered
2059	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2060	{
2061	r_dcache_p1_valid = false;
2062	write_pipe_frozen = true;
2063	}
2064	else // try a registration into write buffer
2065	{
2066
2067	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2068	r_dcache_p0_be.read(),
2069	r_dcache_p0_wdata.read(),
2070	r_dcache_p0_cacheable.read() );
2071	#ifdef INSTRUMENTATION
2072	m_cpt_wbuf_write++;
2073	#endif
2074	if ( not wok ) // frozen if write buffer full
2075	{
2076	r_dcache_p1_valid = false;
2077	write_pipe_frozen = true;
2078	}
2079	else // update the write_buffer state extension
2080	{
2081	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2082
2083	// read directory to check local copy
2084	size_t cache_way;
2085	size_t cache_set;
2086	size_t cache_word;
2087	bool local_copy;
2088	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2089	{
2090	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2091	&cache_way,
2092	&cache_set,
2093	&cache_word );
2094	#ifdef INSTRUMENTATION
2095	m_cpt_dcache_dir_read++;
2096	#endif
2097	}
2098	else
2099	{
2100	local_copy = false;
2101	}
2102
2103	// store values for P2 pipe stage
2104	if ( local_copy )
2105	{
2106	r_dcache_p1_valid = true;
2107	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2108	r_dcache_p1_be = r_dcache_p0_be.read();
2109	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2110	r_dcache_p1_cache_way = cache_way;
2111	r_dcache_p1_cache_set = cache_set;
2112	r_dcache_p1_cache_word = cache_word;
2113	}
2114	else
2115	{
2116	r_dcache_p1_valid = false;
2117	}
2118	}
2119	}
2120	}
2121	else // P1 stage not activated
2122	{
2123	r_dcache_p1_valid = false;
2124	} // end P1 stage
2125
2126	/////////////////////////////////////////////////////////////////////////////////
2127	// handling P0 pipe-line stage
2128	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2129	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2130	// - the TLB invalidate requests have the highest priority,
2131	// - then the external coherence requests,
2132	// - then the itlb miss requests,
2133	// - and finally the processor requests.
2134	// If dtlb is activated, there is an unconditionnal access to dtlb,
2135	// for address translation.
2136	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2137	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2138	// handled by the IDLE state), and the processor request is acknowledged.
2139	// 2) A processor READ or LL request generate a simultaneouss access to
2140	// both dcache data and dcache directoty, using speculative PPN, but
2141	// is delayed if the write pipe-line is not empty.
2142	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2143	// DCACHE_MISS_WAIT states.
2144	// 3) A processor SC request is delayed until the write pipe-line is empty.
2145	// A VCI SC transaction is launched, and we wait the VCI response in
2146	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2147	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2148	// The data is not modified in dcache, as it will be done by the
2149	// coherence transaction.
2150
2151	// TLB inval required after a write hit
2152	if ( tlb_inval_required )
2153	{
2154	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2155	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2156	r_dcache_p0_valid = false;
2157	}
2158	// external coherence request
2159	else if ( r_tgt_dcache_req.read() )
2160	{
2161	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2162	r_dcache_fsm = DCACHE_CC_CHECK;
2163	r_dcache_p0_valid = false;
2164	}
2165
2166	// itlb miss request
2167	else if ( r_icache_tlb_miss_req.read() )
2168	{
2169	r_dcache_tlb_ins = true;
2170	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2171	r_dcache_fsm = DCACHE_TLB_MISS;
2172	r_dcache_p0_valid = false;
2173	}
2174
2175	// processor request
2176	else if ( m_dreq.valid and not write_pipe_frozen )
2177	{
2178	// dcache access using speculative PPN only if pipe-line empty
2179	paddr_t cache_paddr;
2180	size_t cache_way;
2181	size_t cache_set;
2182	size_t cache_word;
2183	uint32_t cache_rdata;
2184	bool cache_hit;
2185
2186	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2187	not r_dcache_p0_valid.read() and
2188	not r_dcache_p1_valid.read() ) // pipe-line empty
2189	{
2190	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2191	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2192
2193	cache_hit = r_dcache.read( cache_paddr,
2194	&cache_rdata,
2195	&cache_way,
2196	&cache_set,
2197	&cache_word );
2198	#ifdef INSTRUMENTATION
2199	m_cpt_dcache_dir_read++;
2200	m_cpt_dcache_data_read++;
2201	#endif
2202	}
2203	else
2204	{
2205	cache_hit = false;
2206	} // end dcache access
2207
2208	// systematic dtlb access using virtual address
2209	paddr_t tlb_paddr;
2210	pte_info_t tlb_flags;
2211	size_t tlb_way;
2212	size_t tlb_set;
2213	paddr_t tlb_nline;
2214	bool tlb_hit;
2215
2216	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2217	{
2218	tlb_hit = r_dtlb.translate( m_dreq.addr,
2219	&tlb_paddr,
2220	&tlb_flags,
2221	&tlb_nline,
2222	&tlb_way,
2223	&tlb_set );
2224	#ifdef INSTRUMENTATION
2225	m_cpt_dtlb_read++;
2226	#endif
2227	}
2228	else
2229	{
2230	tlb_hit = false;
2231	} // end dtlb access
2232
2233	// register the processor request
2234	r_dcache_p0_vaddr = m_dreq.addr;
2235	r_dcache_p0_be = m_dreq.be;
2236	r_dcache_p0_wdata = m_dreq.wdata;
2237
2238	// Handling READ XTN requests from processor
2239	// They are executed in this DCACHE_IDLE state.
2240	// The processor must not be in user mode
2241	if (m_dreq.type == iss_t::XTN_READ)
2242	{
2243	int xtn_opcode = (int)m_dreq.addr/4;
2244
2245	// checking processor mode:
2246	if (m_dreq.mode == iss_t::MODE_USER)
2247	{
2248	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2249	r_mmu_dbvar = m_dreq.addr;
2250	m_drsp.valid = true;
2251	m_drsp.error = true;
2252	r_dcache_fsm = DCACHE_IDLE;
2253	}
2254	else
2255	{
2256	switch( xtn_opcode )
2257	{
2258	case iss_t::XTN_INS_ERROR_TYPE:
2259	m_drsp.rdata = r_mmu_ietr.read();
2260	m_drsp.valid = true;
2261	break;
2262
2263	case iss_t::XTN_DATA_ERROR_TYPE:
2264	m_drsp.rdata = r_mmu_detr.read();
2265	m_drsp.valid = true;
2266	break;
2267
2268	case iss_t::XTN_INS_BAD_VADDR:
2269	m_drsp.rdata = r_mmu_ibvar.read();
2270	m_drsp.valid = true;
2271	break;
2272
2273	case iss_t::XTN_DATA_BAD_VADDR:
2274	m_drsp.rdata = r_mmu_dbvar.read();
2275	m_drsp.valid = true;
2276	break;
2277
2278	case iss_t::XTN_PTPR:
2279	m_drsp.rdata = r_mmu_ptpr.read();
2280	m_drsp.valid = true;
2281	break;
2282
2283	case iss_t::XTN_TLB_MODE:
2284	m_drsp.rdata = r_mmu_mode.read();
2285	m_drsp.valid = true;
2286	break;
2287
2288	case iss_t::XTN_MMU_PARAMS:
2289	m_drsp.rdata = r_mmu_params;
2290	m_drsp.valid = true;
2291	break;
2292
2293	case iss_t::XTN_MMU_RELEASE:
2294	m_drsp.rdata = r_mmu_release;
2295	m_drsp.valid = true;
2296	break;
2297
2298	case iss_t::XTN_MMU_WORD_LO:
2299	m_drsp.rdata = r_mmu_word_lo.read();
2300	m_drsp.valid = true;
2301	break;
2302
2303	case iss_t::XTN_MMU_WORD_HI:
2304	m_drsp.rdata = r_mmu_word_hi.read();
2305	m_drsp.valid = true;
2306	break;
2307
2308	default:
2309	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2310	r_mmu_dbvar = m_dreq.addr;
2311	m_drsp.valid = true;
2312	m_drsp.error = true;
2313	break;
2314	} // end switch xtn_opcode
2315	} // end else
2316	r_dcache_p0_valid = false;
2317	} // end if XTN_READ
2318
2319	// Handling WRITE XTN requests from processor.
2320	// They are not executed in this DCACHE_IDLE state,
2321	// if they require access to the caches or the TLBs
2322	// that are already accessed for speculative read.
2323	// Caches can be invalidated or flushed in user mode,
2324	// and the sync instruction can be executed in user mode
2325	else if (m_dreq.type == iss_t::XTN_WRITE)
2326	{
2327	int xtn_opcode = (int)m_dreq.addr/4;
2328	r_dcache_xtn_opcode = xtn_opcode;
2329
2330	// checking processor mode:
2331	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2332	(xtn_opcode != iss_t:: XTN_SYNC) &&
2333	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2334	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2335	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2336	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2337	{
2338	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2339	r_mmu_dbvar = m_dreq.addr;
2340	m_drsp.valid = true;
2341	m_drsp.error = true;
2342	r_dcache_fsm = DCACHE_IDLE;
2343	}
2344	else
2345	{
2346	switch( xtn_opcode )
2347	{
2348	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2349	r_mmu_ptpr = m_dreq.wdata;
2350	r_dcache_xtn_req = true;
2351	r_dcache_fsm = DCACHE_XTN_SWITCH;
2352	break;
2353
2354	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2355	r_mmu_mode = m_dreq.wdata;
2356	m_drsp.valid = true;
2357	r_dcache_fsm = DCACHE_IDLE;
2358	break;
2359
2360	case iss_t::XTN_DTLB_INVAL: // dtlb access
2361	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2362	break;
2363
2364	case iss_t::XTN_ITLB_INVAL: // itlb access
2365	r_dcache_xtn_req = true;
2366	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2367	break;
2368
2369	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2370	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2371	break;
2372
2373	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2374	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2375	if (sizeof(paddr_t) <= 32) {
2376	assert(r_mmu_word_hi.read() == 0 &&
2377	"high bits should be 0 for 32bit paddr");
2378	r_dcache_p0_paddr =
2379	(paddr_t)r_mmu_word_lo.read();
2380	} else {
2381	r_dcache_p0_paddr =
2382	(paddr_t)r_mmu_word_hi.read() << 32 \|
2383	(paddr_t)r_mmu_word_lo.read();
2384	}
2385	break;
2386
2387	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2388	r_dcache_flush_count = 0;
2389	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2390	break;
2391
2392	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2393	r_dcache_xtn_req = true;
2394	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2395	break;
2396
2397	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2398	r_dcache_xtn_req = true;
2399	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2400	break;
2401
2402	case iss_t::XTN_ICACHE_FLUSH: // icache access
2403	r_dcache_xtn_req = true;
2404	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2405	break;
2406
2407	case iss_t::XTN_SYNC: // wait until write buffer empty
2408	r_dcache_fsm = DCACHE_XTN_SYNC;
2409	break;
2410
2411	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2412	r_mmu_word_lo = m_dreq.wdata;
2413	m_drsp.valid = true;
2414	r_dcache_fsm = DCACHE_IDLE;
2415	break;
2416
2417	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2418	r_mmu_word_hi = m_dreq.wdata;
2419	m_drsp.valid = true;
2420	r_dcache_fsm = DCACHE_IDLE;
2421	break;
2422
2423	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2424	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2425	m_drsp.valid = true;
2426	r_dcache_fsm = DCACHE_IDLE;
2427	break;
2428
2429	default:
2430	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2431	r_mmu_dbvar = m_dreq.addr;
2432	m_drsp.valid = true;
2433	m_drsp.error = true;
2434	r_dcache_fsm = DCACHE_IDLE;
2435	break;
2436	} // end switch xtn_opcode
2437	} // end else
2438	r_dcache_p0_valid = false;
2439	} // end if XTN_WRITE
2440
2441	// Handling read/write/ll/sc processor requests.
2442	// The dtlb and dcache can be activated or not.
2443	// We compute the physical address, the cacheability, and check processor request.
2444	// - If DTLB not activated : cacheability is defined by the segment table,
2445	// the physical address is equal to the virtual address (identity mapping)
2446	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2447	// the physical address is obtained from the TLB, and the U & W bits
2448	// of the PTE are checked.
2449	// The processor request is decoded only if the TLB is not activated or if
2450	// the virtual address hits in tLB and access rights are OK.
2451	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2452	else
2453	{
2454	bool valid_req = false;
2455	bool cacheable = false;
2456	paddr_t paddr = 0;
2457
2458	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2459	{
2460	valid_req = true;
2461
2462	// cacheability
2463	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2464	else cacheable = m_cacheability_table[m_dreq.addr];
2465
2466	// physical address
2467	paddr = (paddr_t)m_dreq.addr;
2468	}
2469	else // dtlb activated
2470	{
2471	if ( tlb_hit ) // tlb hit
2472	{
2473	// cacheability
2474	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2475	else cacheable = tlb_flags.c;
2476
2477	// access rights checking
2478	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2479	{
2480	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2481	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2482	else
2483	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2484
2485	r_mmu_dbvar = m_dreq.addr;
2486	m_drsp.valid = true;
2487	m_drsp.error = true;
2488	m_drsp.rdata = 0;
2489	#if DEBUG_DCACHE
2490	if ( m_debug_dcache_fsm )
2491	{
2492	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2493	}
2494	#endif
2495	}
2496	else if ( not tlb_flags.w and
2497	((m_dreq.type == iss_t::DATA_WRITE) or
2498	(m_dreq.type == iss_t::DATA_SC)) )
2499	{
2500	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2501	r_mmu_dbvar = m_dreq.addr;
2502	m_drsp.valid = true;
2503	m_drsp.error = true;
2504	m_drsp.rdata = 0;
2505	#if DEBUG_DCACHE
2506	if ( m_debug_dcache_fsm )
2507	{
2508	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2509	}
2510	#endif
2511	}
2512	else
2513	{
2514	valid_req = true;
2515	}
2516
2517	// physical address
2518	paddr = tlb_paddr;
2519	}
2520	else // tlb miss
2521	{
2522	r_dcache_tlb_vaddr = m_dreq.addr;
2523	r_dcache_tlb_ins = false;
2524	r_dcache_fsm = DCACHE_TLB_MISS;
2525	}
2526	} // end DTLB activated
2527
2528	if ( valid_req ) // processor request is valid after TLB check
2529	{
2530	// physical address and cacheability registration
2531	r_dcache_p0_paddr = paddr;
2532	r_dcache_p0_cacheable = cacheable;
2533
2534	// READ or LL request
2535	// The read requests are taken only if the write pipe-line is empty.
2536	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2537	// If speculative access is KO we just pay one extra cycle.
2538	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2539	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2540	// In case of LL, the LL registration is done when the data is returned:
2541	// in DCACHE_IDLE if cacheable / in DCACHE_UNC_WAIT if uncacheable
2542	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2543	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2544	{
2545	if ( cacheable ) // cacheable read
2546	{
2547	// if the speculative access is illegal, we pay an extra cycle
2548	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2549	!= (paddr & ~PAGE_K_MASK))
2550	{
2551	#ifdef INSTRUMENTATION
2552	m_cpt_dcache_spec_miss++;
2553	#endif
2554	#if DEBUG_DCACHE
2555	if ( m_debug_dcache_fsm )
2556	{
2557	std::cout << " <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
2558	}
2559	#endif
2560	}
2561	// if cache miss, try to get the missing line
2562	else if ( not cache_hit )
2563	{
2564	#ifdef INSTRUMENTATION
2565	m_cpt_dcache_miss++;
2566	#endif
2567	r_dcache_vci_paddr = paddr;
2568	r_dcache_vci_miss_req = true;
2569	r_dcache_miss_type = PROC_MISS;
2570	r_dcache_fsm = DCACHE_MISS_VICTIM;
2571	}
2572	// if cache hit return the data
2573	else
2574	{
2575	#ifdef INSTRUMENTATION
2576	m_cpt_data_read++;
2577	#endif
2578	m_drsp.valid = true;
2579	m_drsp.rdata = cache_rdata;
2580
2581	// makes reservation in case of LL
2582	if ( m_dreq.type == iss_t::DATA_LL )
2583	{
2584	r_dcache_ll_valid = true;
2585	r_dcache_ll_vaddr = m_dreq.addr;
2586	r_dcache_ll_data = cache_rdata;
2587	}
2588	#if DEBUG_DCACHE
2589	if ( m_debug_dcache_fsm )
2590	{
2591	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2592	}
2593	#endif
2594	}
2595	}
2596	else // uncacheable read
2597	{
2598	r_dcache_vci_paddr = paddr;
2599	r_dcache_vci_unc_be = m_dreq.be;
2600	r_dcache_vci_unc_req = true;
2601	r_dcache_fsm = DCACHE_UNC_WAIT;
2602	}
2603
2604	r_dcache_p0_valid = false;
2605	} // end READ or LL
2606
2607	// WRITE request:
2608	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2609	// the processor and set the Dirty bit before handling the write request.
2610	// If we don't need to set the Dirty bit, we can acknowledge
2611	// the processor request, as the write arguments (including the
2612	// physical address) are registered in r_dcache_p0 registers:
2613	// We simply activate the P1 pipeline stage.
2614	else if ( m_dreq.type == iss_t::DATA_WRITE )
2615	{
2616	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2617	and not tlb_flags.d ) // Dirty bit must be set
2618	{
2619	// The PTE physical address is obtained from the nline value (dtlb),
2620	// and the word index (proper bits of the virtual address)
2621	if ( tlb_flags.b ) // PTE1
2622	{
2623	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2624	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2625	}
2626	else // PTE2
2627	{
2628	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2629	(paddr_t)((m_dreq.addr>>9) & 0x38);
2630	}
2631	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2632	r_dcache_p0_valid = false;
2633	}
2634	else // Write request accepted
2635	{
2636	#ifdef INSTRUMENTATION
2637	m_cpt_data_write++;
2638	#endif
2639	m_drsp.valid = true;
2640	m_drsp.rdata = 0;
2641	r_dcache_p0_valid = true;
2642	}
2643	} // end WRITE
2644
2645	// SC request:
2646	// The SC requests are taken only if the write pipe-line is empty.
2647	// - if there is no valid registered LL, we just return rdata = 1
2648	// (atomic access failed) and the SC transaction is completed.
2649	// - if a valid LL reservation (with the same address) is registered,
2650	// we test if a DIRTY bit update is required.
2651	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2652	// the processor and set the Dirty bit before handling the write request.
2653	// If we don't need to set the Dirty bit, we request a SC transaction
2654	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2655	// the response to the processor.
2656	// We don't check a possible write hit in dcache, as the cache update
2657	// is done by the coherence transaction induced by the SC...
2658	else if ( ( m_dreq.type == iss_t::DATA_SC )
2659	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2660	{
2661	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2662	or not r_dcache_ll_valid.read() ) // no valid registered LL
2663	{
2664	#ifdef INSTRUMENTATION
2665	m_cpt_data_sc++;
2666	#endif
2667	m_drsp.valid = true;
2668	m_drsp.rdata = 1;
2669	r_dcache_ll_valid = false;
2670	}
2671	else // valid registered LL
2672	{
2673	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2674	and not tlb_flags.d ) // Dirty bit must be set
2675	{
2676	// The PTE physical address is obtained from the nline value (dtlb),
2677	// and the word index (virtual address)
2678	if ( tlb_flags.b ) // PTE1
2679	{
2680	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2681	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2682	}
2683	else // PTE2
2684	{
2685	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2686	(paddr_t)((m_dreq.addr>>9) & 0x38);
2687	}
2688	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2689	}
2690	else // SC request accepted
2691	{
2692	#ifdef INSTRUMENTATION
2693	m_cpt_data_sc++;
2694	#endif
2695
2696	r_dcache_vci_paddr = paddr;
2697	r_dcache_vci_sc_req = true;
2698	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2699	r_dcache_vci_sc_new = m_dreq.wdata;
2700	r_dcache_ll_valid = false;
2701	r_dcache_fsm = DCACHE_SC_WAIT;
2702	}
2703	}
2704	r_dcache_p0_valid = false;
2705	} // end SC
2706	else
2707	{
2708	r_dcache_p0_valid = false;
2709	}
2710	} // end valid_req
2711	else
2712	{
2713	r_dcache_p0_valid = false;
2714	}
2715	} // end if read/write/ll/sc request
2716	} // end dreq.valid
2717	else
2718	{
2719	r_dcache_p0_valid = false;
2720	} // end P0 pipe stage
2721	break;
2722	}
2723	/////////////////////
2724	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2725	// Input arguments are:
2726	// - r_dcache_tlb_vaddr
2727	// - r_dcache_tlb_ins (true when itlb miss)
2728	// The sub-fsm access the dcache to find the missing TLB entry,
2729	// and activates the cache miss procedure in case of miss.
2730	// It bypass the first level page table access if possible.
2731	// It uses atomic access to update the R/L access bits
2732	// in the page table if required.
2733	// It directly updates the itlb or dtlb, and writes into the
2734	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2735	{
2736	uint32_t ptba = 0;
2737	bool bypass;
2738	paddr_t pte_paddr;
2739
2740	// evaluate bypass in order to skip first level page table access
2741	if ( r_dcache_tlb_ins.read() ) // itlb miss
2742	{
2743	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2744	}
2745	else // dtlb miss
2746	{
2747	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2748	}
2749
2750	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2751	{
2752	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2753	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2754	r_dcache_tlb_paddr = pte_paddr;
2755	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2756	}
2757	else // Try to read PTE2 in dcache
2758	{
2759	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2760	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2761	r_dcache_tlb_paddr = pte_paddr;
2762	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2763	}
2764
2765	#if DEBUG_DCACHE
2766	if ( m_debug_dcache_fsm )
2767	{
2768	if ( r_dcache_tlb_ins.read() )
2769	{
2770	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2771	}
2772	else
2773	{
2774	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2775	}
2776	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2777	<< " / BYPASS = " << bypass
2778	<< " / PTE_ADR = " << pte_paddr << std::endl;
2779	}
2780	#endif
2781
2782	break;
2783	}
2784	/////////////////////////
2785	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2786	{
2787	uint32_t entry;
2788	size_t way;
2789	size_t set;
2790	size_t word;
2791
2792	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2793	&entry,
2794	&way,
2795	&set,
2796	&word );
2797	#ifdef INSTRUMENTATION
2798	m_cpt_dcache_data_read++;
2799	m_cpt_dcache_dir_read++;
2800	#endif
2801	if ( hit ) // hit in dcache
2802	{
2803	if ( not (entry & PTE_V_MASK) ) // unmapped
2804	{
2805	if ( r_dcache_tlb_ins.read() )
2806	{
2807	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2808	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2809	r_icache_tlb_miss_req = false;
2810	r_icache_tlb_rsp_error = true;
2811	}
2812	else
2813	{
2814	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2815	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2816	m_drsp.valid = true;
2817	m_drsp.error = true;
2818	}
2819	r_dcache_fsm = DCACHE_IDLE;
2820
2821	#if DEBUG_DCACHE
2822	if ( m_debug_dcache_fsm )
2823	{
2824	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2825	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2826	<< std::dec << " / way = " << way
2827	<< std::dec << " / set = " << set
2828	<< std::dec << " / word = " << word
2829	<< std::hex << " / PTE1 = " << entry << std::endl;
2830	}
2831	#endif
2832
2833	}
2834	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2835	{
2836	// mark the cache line ac containing a PTD
2837	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2838
2839	// register bypass
2840	if ( r_dcache_tlb_ins.read() ) // itlb
2841	{
2842	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2843	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2844	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2845	}
2846	else // dtlb
2847	{
2848	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2849	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2850	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2851	}
2852	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2853	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2854	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2855
2856	#if DEBUG_DCACHE
2857	if ( m_debug_dcache_fsm )
2858	{
2859	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2860	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2861	<< std::dec << " / way = " << way
2862	<< std::dec << " / set = " << set
2863	<< std::dec << " / word = " << word
2864	<< std::hex << " / PTD = " << entry << std::endl;
2865	}
2866	#endif
2867	}
2868	else // PTE1 : we must update the TLB
2869	{
2870	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2871	r_dcache_tlb_pte_flags = entry;
2872	r_dcache_tlb_cache_way = way;
2873	r_dcache_tlb_cache_set = set;
2874	r_dcache_tlb_cache_word = word;
2875	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2876
2877	#if DEBUG_DCACHE
2878	if ( m_debug_dcache_fsm )
2879	{
2880	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2881	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2882	<< std::dec << " / way = " << way
2883	<< std::dec << " / set = " << set
2884	<< std::dec << " / word = " << word
2885	<< std::hex << " / PTE1 = " << entry << std::endl;
2886	}
2887	#endif
2888	}
2889	}
2890	else // we must load the missing cache line in dcache
2891	{
2892	r_dcache_vci_miss_req = true;
2893	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2894	r_dcache_miss_type = PTE1_MISS;
2895	r_dcache_fsm = DCACHE_MISS_VICTIM;
2896
2897	#if DEBUG_DCACHE
2898	if ( m_debug_dcache_fsm )
2899	{
2900	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2901	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2902	}
2903	#endif
2904	}
2905	break;
2906	}
2907	////////////////////////////
2908	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2909	{
2910	size_t way;
2911	size_t set;
2912
2913	if ( r_dcache_tlb_ins.read() )
2914	{
2915	r_itlb.select( r_dcache_tlb_vaddr.read(),
2916	true, // PTE1
2917	&way,
2918	&set );
2919	#ifdef INSTRUMENTATION
2920	m_cpt_itlb_read++;
2921	#endif
2922	}
2923	else
2924	{
2925	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2926	true, // PTE1
2927	&way,
2928	&set );
2929	#ifdef INSTRUMENTATION
2930	m_cpt_dtlb_read++;
2931	#endif
2932	}
2933	r_dcache_tlb_way = way;
2934	r_dcache_tlb_set = set;
2935	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2936
2937	#if DEBUG_DCACHE
2938	if ( m_debug_dcache_fsm )
2939	{
2940	if ( r_dcache_tlb_ins.read() )
2941	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2942	else
2943	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2944	std::cout << " way = " << std::dec << way
2945	<< " / set = " << set << std::endl;
2946	}
2947	#endif
2948	break;
2949	}
2950	//////////////////////////
2951	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2952	// if L/R bit already set, exit the sub-fsm
2953	// if not, the page table must be updated
2954	{
2955	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2956	uint32_t pte = r_dcache_tlb_pte_flags.read();
2957	bool updt = false;
2958	bool local = true;
2959
2960	// We should compute the access locality:
2961	// The PPN MSB bits define the destination cluster index.
2962	// The m_srcid_d MSB bits define the source cluster index.
2963	// The number of bits to compare depends on the number of clusters,
2964	// and can be obtained in the mapping table.
2965	// As long as this computation is not done, all access are local.
2966
2967	if ( local ) // local access
2968	{
2969	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2970	{
2971	updt = true;
2972	r_dcache_vci_sc_old = pte;
2973	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2974	pte = pte \| PTE_L_MASK;
2975	}
2976	}
2977	else // remote access
2978	{
2979	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2980	{
2981	updt = true;
2982	r_dcache_vci_sc_old = pte;
2983	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2984	pte = pte \| PTE_R_MASK;
2985	}
2986	}
2987
2988	// update TLB
2989	if ( r_dcache_tlb_ins.read() )
2990	{
2991	r_itlb.write( true, // 2M page
2992	pte,
2993	0, // argument unused for a PTE1
2994	r_dcache_tlb_vaddr.read(),
2995	r_dcache_tlb_way.read(),
2996	r_dcache_tlb_set.read(),
2997	nline );
2998	#ifdef INSTRUMENTATION
2999	m_cpt_itlb_write++;
3000	#endif
3001	}
3002	else
3003	{
3004	r_dtlb.write( true, // 2M page
3005	pte,
3006	0, // argument unused for a PTE1
3007	r_dcache_tlb_vaddr.read(),
3008	r_dcache_tlb_way.read(),
3009	r_dcache_tlb_set.read(),
3010	nline );
3011	#ifdef INSTRUMENTATION
3012	m_cpt_dtlb_write++;
3013	#endif
3014	}
3015	// next state
3016	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3017	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3018
3019	#if DEBUG_DCACHE
3020	if ( m_debug_dcache_fsm )
3021	{
3022	if ( r_dcache_tlb_ins.read() )
3023	{
3024	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3025	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3026	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3027	r_itlb.printTrace();
3028	}
3029	else
3030	{
3031	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3032	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3033	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3034	r_dtlb.printTrace();
3035	}
3036
3037	}
3038	#endif
3039	break;
3040	}
3041	/////////////////////////
3042	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3043	{
3044	uint32_t pte_flags;
3045	uint32_t pte_ppn;
3046	size_t way;
3047	size_t set;
3048	size_t word;
3049
3050	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3051	&pte_flags,
3052	&pte_ppn,
3053	&way,
3054	&set,
3055	&word );
3056	#ifdef INSTRUMENTATION
3057	m_cpt_dcache_data_read++;
3058	m_cpt_dcache_dir_read++;
3059	#endif
3060	if ( hit ) // request hits in dcache
3061	{
3062	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3063	{
3064	if ( r_dcache_tlb_ins.read() )
3065	{
3066	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3067	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3068	r_icache_tlb_miss_req = false;
3069	r_icache_tlb_rsp_error = true;
3070	}
3071	else
3072	{
3073	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3074	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3075	m_drsp.valid = true;
3076	m_drsp.error = true;
3077	}
3078	r_dcache_fsm = DCACHE_IDLE;
3079
3080	#if DEBUG_DCACHE
3081	if ( m_debug_dcache_fsm )
3082	{
3083	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3084	<< " PTE_FLAGS = " << std::hex << pte_flags
3085	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3086	}
3087	#endif
3088	}
3089	else // mapped : we must update the TLB
3090	{
3091	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3092	r_dcache_tlb_pte_flags = pte_flags;
3093	r_dcache_tlb_pte_ppn = pte_ppn;
3094	r_dcache_tlb_cache_way = way;
3095	r_dcache_tlb_cache_set = set;
3096	r_dcache_tlb_cache_word = word;
3097	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3098
3099	#if DEBUG_DCACHE
3100	if ( m_debug_dcache_fsm )
3101	{
3102	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3103	<< " PTE_FLAGS = " << std::hex << pte_flags
3104	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3105	}
3106	#endif
3107	}
3108	}
3109	else // we must load the missing cache line in dcache
3110	{
3111	r_dcache_fsm = DCACHE_MISS_VICTIM;
3112	r_dcache_vci_miss_req = true;
3113	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3114	r_dcache_miss_type = PTE2_MISS;
3115
3116	#if DEBUG_DCACHE
3117	if ( m_debug_dcache_fsm )
3118	{
3119	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3120	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3121	}
3122	#endif
3123	}
3124	break;
3125	}
3126	////////////////////////////
3127	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3128	{
3129	size_t way;
3130	size_t set;
3131
3132	if ( r_dcache_tlb_ins.read() )
3133	{
3134	r_itlb.select( r_dcache_tlb_vaddr.read(),
3135	false, // PTE2
3136	&way,
3137	&set );
3138	#ifdef INSTRUMENTATION
3139	m_cpt_itlb_read++;
3140	#endif
3141	}
3142	else
3143	{
3144	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3145	false, // PTE2
3146	&way,
3147	&set );
3148	#ifdef INSTRUMENTATION
3149	m_cpt_dtlb_read++;
3150	#endif
3151	}
3152
3153	#if DEBUG_DCACHE
3154	if ( m_debug_dcache_fsm )
3155	{
3156	if ( r_dcache_tlb_ins.read() )
3157	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3158	else
3159	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3160	std::cout << " way = " << std::dec << way
3161	<< " / set = " << set << std::endl;
3162	}
3163	#endif
3164	r_dcache_tlb_way = way;
3165	r_dcache_tlb_set = set;
3166	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3167	break;
3168	}
3169	//////////////////////////
3170	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3171	// if L/R bit already set, exit the sub-fsm
3172	// if not, the page table must be updated by an atomic access
3173	{
3174	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3175	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3176	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3177	bool updt = false;
3178	bool local = true;
3179
3180	// We should compute the access locality:
3181	// The PPN MSB bits define the destination cluster index.
3182	// The m_srcid_d MSB bits define the source cluster index.
3183	// The number of bits to compare depends on the number of clusters,
3184	// and can be obtained in the mapping table.
3185	// As long as this computation is not done, all access are local.
3186
3187	if ( local ) // local access
3188	{
3189	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3190	{
3191	updt = true;
3192	r_dcache_vci_sc_old = pte_flags;
3193	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3194	pte_flags = pte_flags \| PTE_L_MASK;
3195	}
3196	}
3197	else // remote access
3198	{
3199	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3200	{
3201	updt = true;
3202	r_dcache_vci_sc_old = pte_flags;
3203	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3204	pte_flags = pte_flags \| PTE_R_MASK;
3205	}
3206	}
3207
3208	// update TLB for a PTE2
3209	if ( r_dcache_tlb_ins.read() )
3210	{
3211	r_itlb.write( false, // 4K page
3212	pte_flags,
3213	pte_ppn,
3214	r_dcache_tlb_vaddr.read(),
3215	r_dcache_tlb_way.read(),
3216	r_dcache_tlb_set.read(),
3217	nline );
3218	#ifdef INSTRUMENTATION
3219	m_cpt_itlb_write++;
3220	#endif
3221	}
3222	else
3223	{
3224	r_dtlb.write( false, // 4K page
3225	pte_flags,
3226	pte_ppn,
3227	r_dcache_tlb_vaddr.read(),
3228	r_dcache_tlb_way.read(),
3229	r_dcache_tlb_set.read(),
3230	nline );
3231	#ifdef INSTRUMENTATION
3232	m_cpt_dtlb_write++;
3233	#endif
3234	}
3235
3236	#if DEBUG_DCACHE
3237	if ( m_debug_dcache_fsm )
3238	{
3239	if ( r_dcache_tlb_ins.read() )
3240	{
3241	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3242	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3243	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3244	r_itlb.printTrace();
3245	}
3246	else
3247	{
3248	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3249	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3250	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3251	r_dtlb.printTrace();
3252	}
3253	}
3254	#endif
3255	// next state
3256	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3257	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3258	break;
3259	}
3260	////////////////////////
3261	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3262	// request a SC transaction to CMD FSM
3263	{
3264	#if DEBUG_DCACHE
3265	if ( m_debug_dcache_fsm )
3266	{
3267	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3268	}
3269	#endif
3270	r_dcache.write(r_dcache_tlb_cache_way.read(),
3271	r_dcache_tlb_cache_set.read(),
3272	r_dcache_tlb_cache_word.read(),
3273	r_dcache_tlb_pte_flags.read());
3274	#ifdef INSTRUMENTATION
3275	m_cpt_dcache_data_write++;
3276	#endif
3277	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3278	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3279	r_dcache_vci_sc_req = true;
3280	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3281	break;
3282	}
3283	////////////////////////
3284	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3285	// We consume the response in rsp FIFO,
3286	// and exit the sub-fsm, but we don't
3287	// analyse the response, because we don't
3288	// care if the L/R bit update is not done.
3289	// We must take the coherence requests because
3290	// there is a risk of dead-lock
3291
3292	{
3293	// external coherence request
3294	if ( r_tgt_dcache_req )
3295	{
3296	r_dcache_fsm = DCACHE_CC_CHECK;
3297	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3298	break;
3299	}
3300
3301	if ( r_vci_rsp_data_error.read() ) // bus error
3302	{
3303	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3304	std::cout << "This should not happen in this state" << std::endl;
3305	exit(0);
3306	}
3307	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3308	{
3309	#if DEBUG_DCACHE
3310	if ( m_debug_dcache_fsm )
3311	{
3312	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3313	}
3314	#endif
3315	vci_rsp_fifo_dcache_get = true;
3316	r_dcache_fsm = DCACHE_TLB_RETURN;
3317	}
3318	break;
3319	}
3320	///////////////////////
3321	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3322	{
3323	#if DEBUG_DCACHE
3324	if ( m_debug_dcache_fsm )
3325	{
3326	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3327	}
3328	#endif
3329	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3330	r_dcache_fsm = DCACHE_IDLE;
3331	break;
3332	}
3333	///////////////////////
3334	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3335	{
3336	if ( not r_dcache_xtn_req.read() )
3337	{
3338	r_dtlb.flush();
3339	r_dcache_fsm = DCACHE_IDLE;
3340	m_drsp.valid = true;
3341	}
3342	break;
3343	}
3344	/////////////////////
3345	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3346	// The coherence request must be taken
3347	// as there is a risk of dead-lock
3348	{
3349	// external coherence request
3350	if ( r_tgt_dcache_req.read() )
3351	{
3352	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3353	r_dcache_fsm = DCACHE_CC_CHECK;
3354	}
3355
3356	if ( r_wbuf.empty() )
3357	{
3358	m_drsp.valid = true;
3359	r_dcache_fsm = DCACHE_IDLE;
3360	}
3361	break;
3362	}
3363	////////////////////////
3364	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3365	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3366	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3367	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3368	{
3369	// external coherence request
3370	if ( r_tgt_dcache_req )
3371	{
3372	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3373	r_dcache_fsm = DCACHE_CC_CHECK;
3374	break;
3375	}
3376
3377	// itlb miss request
3378	if ( r_icache_tlb_miss_req.read() )
3379	{
3380	r_dcache_tlb_ins = true;
3381	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3382	r_dcache_fsm = DCACHE_TLB_MISS;
3383	break;
3384	}
3385
3386	// test if XTN request to icache completed
3387	if ( not r_dcache_xtn_req.read() )
3388	{
3389	r_dcache_fsm = DCACHE_IDLE;
3390	m_drsp.valid = true;
3391	}
3392	break;
3393	}
3394	/////////////////////////
3395	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3396	// the r_dcache_flush counter as a slot counter.
3397	// We loop in this state until all slots have been visited.
3398	// A cleanup request is generated for each valid line
3399	// and we are blocked until the previous cleanup is completed
3400	// Finally, both the itlb and dtlb are flushed
3401	// (including global entries)
3402	{
3403	if ( not r_dcache_cleanup_req )
3404	{
3405	paddr_t nline;
3406	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3407	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3408
3409	bool cleanup_req = r_dcache.inval( way,
3410	set,
3411	&nline );
3412	if ( cleanup_req )
3413	{
3414	r_dcache_cleanup_req = true;
3415	r_dcache_cleanup_line = nline;
3416	}
3417
3418	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3419	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3420
3421	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3422
3423	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3424	{
3425	r_dtlb.reset();
3426	r_itlb.reset();
3427	r_dcache_fsm = DCACHE_IDLE;
3428	m_drsp.valid = true;
3429	}
3430	}
3431	break;
3432	}
3433	/////////////////////////
3434	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3435	{
3436	r_dtlb.inval(r_dcache_p0_wdata.read());
3437	r_dcache_fsm = DCACHE_IDLE;
3438	m_drsp.valid = true;
3439	break;
3440	}
3441	////////////////////////////
3442	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3443	// requires 3 cycles: access tlb, read cache, inval cache
3444	// we compute the physical address in this state
3445	{
3446	paddr_t paddr;
3447	bool hit;
3448
3449	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3450	{
3451	#ifdef INSTRUMENTATION
3452	m_cpt_dtlb_read++;
3453	#endif
3454	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3455	&paddr );
3456	}
3457	else // dtlb not activated
3458	{
3459	paddr = (paddr_t)r_dcache_p0_wdata.read();
3460	hit = true;
3461	}
3462
3463	if ( hit ) // tlb hit
3464	{
3465	r_dcache_p0_paddr = paddr;
3466	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3467	}
3468	else // tlb miss
3469	{
3470	#ifdef INSTRUMENTATION
3471	m_cpt_dtlb_miss++;
3472	#endif
3473	r_dcache_tlb_ins = false; // dtlb
3474	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3475	r_dcache_fsm = DCACHE_TLB_MISS;
3476	}
3477
3478	#if DEBUG_DCACHE
3479	if ( m_debug_dcache_fsm )
3480	{
3481	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3482	<< " / VADDR = " << r_dcache_p0_wdata.read()
3483	<< " / PADDR = " << paddr << std::endl;
3484	}
3485	#endif
3486
3487	break;
3488	}
3489	////////////////////////////
3490	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3491	// requires 2 cycles: read cache / inval cache
3492	// In this state we read dcache.
3493	{
3494	uint32_t data;
3495	size_t way;
3496	size_t set;
3497	size_t word;
3498	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3499	&data,
3500	&way,
3501	&set,
3502	&word );
3503	#ifdef INSTRUMENTATION
3504	m_cpt_dcache_data_read++;
3505	m_cpt_dcache_dir_read++;
3506	#endif
3507	if ( hit ) // inval to be done
3508	{
3509	r_dcache_xtn_way = way;
3510	r_dcache_xtn_set = set;
3511	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3512	}
3513	else // miss : nothing to do
3514	{
3515	r_dcache_fsm = DCACHE_IDLE;
3516	m_drsp.valid = true;
3517	}
3518
3519	#if DEBUG_DCACHE
3520	if ( m_debug_dcache_fsm )
3521	{
3522	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3523	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3524	<< " / HIT = " << hit
3525	<< " / SET = " << set
3526	<< " / WAY = " << way << std::endl;
3527	}
3528	#endif
3529	break;
3530	}
3531	////////////////////////////
3532	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3533	// Blocked if previous cleanup not completed
3534	// Test if itlb or dtlb inval is required
3535	{
3536	if ( not r_dcache_cleanup_req.read() )
3537	{
3538	paddr_t nline;
3539	size_t way = r_dcache_xtn_way.read();
3540	size_t set = r_dcache_xtn_set.read();
3541	bool hit;
3542
3543	hit = r_dcache.inval( way,
3544	set,
3545	&nline );
3546	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3547
3548	// request cleanup
3549	r_dcache_cleanup_req = true;
3550	r_dcache_cleanup_line = nline;
3551
3552	// possible itlb & dtlb invalidate
3553	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3554	{
3555	r_dcache_tlb_inval_line = nline;
3556	r_dcache_tlb_inval_count = 0;
3557	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3558	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3559	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3560	}
3561	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3562	{
3563	r_itlb.reset();
3564	r_dtlb.reset();
3565	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3566	r_dcache_fsm = DCACHE_IDLE;
3567	m_drsp.valid = true;
3568	}
3569	else
3570	{
3571	r_dcache_fsm = DCACHE_IDLE;
3572	m_drsp.valid = true;
3573	}
3574
3575	#if DEBUG_DCACHE
3576	if ( m_debug_dcache_fsm )
3577	{
3578	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3579	<< " / NLINE = " << nline << std::endl;
3580	}
3581	#endif
3582	}
3583	break;
3584	}
3585	//////////////////////////////
3586	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3587	{
3588	r_dcache_fsm = DCACHE_IDLE;
3589	m_drsp.valid = true;
3590	break;
3591	}
3592	////////////////////////
3593	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3594	// on the missing line, and if a new cleanup can be posted.
3595	// Set the r_dcache_cleanup_req flip-flop if required
3596	{
3597	size_t index; // unused
3598	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3599	if ( not hit and not r_dcache_cleanup_req.read() )
3600	{
3601	bool valid;
3602	size_t way;
3603	size_t set;
3604	paddr_t victim;
3605
3606	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3607	&victim,
3608	&way,
3609	&set );
3610	r_dcache_miss_way = way;
3611	r_dcache_miss_set = set;
3612
3613	if ( valid )
3614	{
3615	r_dcache_cleanup_req = true;
3616	r_dcache_cleanup_line = victim;
3617	r_dcache_fsm = DCACHE_MISS_INVAL;
3618	}
3619	else
3620	{
3621	r_dcache_fsm = DCACHE_MISS_WAIT;
3622	}
3623
3624	#if DEBUG_DCACHE
3625	if ( m_debug_dcache_fsm )
3626	{
3627	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3628	<< " / WAY = " << way
3629	<< " / SET = " << set
3630	<< " / VALID = " << valid
3631	<< " / LINE = " << std::hex << victim << std::endl;
3632	}
3633	#endif
3634	}
3635	break;
3636	}
3637	///////////////////////
3638	case DCACHE_MISS_INVAL: // invalidate the victim line
3639	// and possibly request itlb or dtlb invalidate
3640	{
3641	paddr_t nline;
3642	size_t way = r_dcache_miss_way.read();
3643	size_t set = r_dcache_miss_set.read();
3644	bool hit;
3645
3646	hit = r_dcache.inval( way,
3647	set,
3648	&nline );
3649
3650	assert(hit && "selected way/set line should be in dcache");
3651
3652	#if DEBUG_DCACHE
3653	if ( m_debug_dcache_fsm )
3654	{
3655	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
3656	<< " / way = " << way
3657	<< " / set = " << set
3658	<< " / nline = " << std::hex << nline << std::endl;
3659	}
3660	#endif
3661	// if selective itlb & dtlb invalidate are required
3662	// the miss response is not handled before invalidate completed
3663	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3664	{
3665	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3666	r_dcache_tlb_inval_line = nline;
3667	r_dcache_tlb_inval_count = 0;
3668	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3669	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3670	}
3671	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3672	{
3673	r_itlb.reset();
3674	r_dtlb.reset();
3675	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3676	r_dcache_fsm = DCACHE_MISS_WAIT;
3677	}
3678	else
3679	{
3680	r_dcache_fsm = DCACHE_MISS_WAIT;
3681	}
3682	break;
3683	}
3684	//////////////////////
3685	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3686	// This state is in charge of error signaling
3687	// There is 5 types of error depending on the requester
3688	{
3689	// external coherence request
3690	if ( r_tgt_dcache_req )
3691	{
3692	r_dcache_fsm_cc_save = r_dcache_fsm;
3693	r_dcache_fsm = DCACHE_CC_CHECK;
3694	break;
3695	}
3696
3697	if ( r_vci_rsp_data_error.read() ) // bus error
3698	{
3699	switch ( r_dcache_miss_type.read() )
3700	{
3701	case PROC_MISS:
3702	{
3703	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3704	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3705	m_drsp.valid = true;
3706	m_drsp.error = true;
3707	r_dcache_fsm = DCACHE_IDLE;
3708	break;
3709	}
3710	case PTE1_MISS:
3711	{
3712	if ( r_dcache_tlb_ins.read() )
3713	{
3714	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3715	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3716	r_icache_tlb_miss_req = false;
3717	r_icache_tlb_rsp_error = true;
3718	}
3719	else
3720	{
3721	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3722	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3723	m_drsp.valid = true;
3724	m_drsp.error = true;
3725	}
3726	r_dcache_fsm = DCACHE_IDLE;
3727	break;
3728	}
3729	case PTE2_MISS:
3730	{
3731	if ( r_dcache_tlb_ins.read() )
3732	{
3733	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3734	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3735	r_icache_tlb_miss_req = false;
3736	r_icache_tlb_rsp_error = true;
3737	}
3738	else
3739	{
3740	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3741	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3742	m_drsp.valid = true;
3743	m_drsp.error = true;
3744	}
3745	r_dcache_fsm = DCACHE_IDLE;
3746	break;
3747	}
3748	} // end switch type
3749	r_vci_rsp_data_error = false;
3750	}
3751	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3752	{
3753	r_dcache_miss_word = 0;
3754	r_dcache_fsm = DCACHE_MISS_UPDT;
3755	}
3756	break;
3757	}
3758	//////////////////////
3759	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3760	// returns the response depending on the miss type
3761	{
3762	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3763	{
3764	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3765	// pop the FIFO, without cache update
3766	// send a cleanup for the missing line
3767	// if the previous cleanup is completed
3768	{
3769	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3770	{
3771	vci_rsp_fifo_dcache_get = true;
3772	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3773	}
3774	else // last word
3775	{
3776	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3777	{
3778	vci_rsp_fifo_dcache_get = true;
3779	r_dcache_cleanup_req = true;
3780	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3781	(uint32_log2(m_dcache_words)+2);
3782	r_dcache_miss_inval = false;
3783	r_dcache_fsm = DCACHE_IDLE;
3784	}
3785	}
3786	}
3787	else // No matching coherence request
3788	// pop the FIFO and update the cache
3789	// update the directory at the last word
3790	{
3791	size_t way = r_dcache_miss_way.read();
3792	size_t set = r_dcache_miss_set.read();
3793	size_t word = r_dcache_miss_word.read();
3794
3795	#ifdef INSTRUMENTATION
3796	m_cpt_dcache_data_write++;
3797	#endif
3798	r_dcache.write( way,
3799	set,
3800	word,
3801	r_vci_rsp_fifo_dcache.read());
3802
3803	vci_rsp_fifo_dcache_get = true;
3804	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3805
3806	// if last word, update directory, set in_tlb & contains_ptd bits
3807	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3808	{
3809
3810	#ifdef INSTRUMENTATION
3811	m_cpt_dcache_dir_write++;
3812	#endif
3813	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3814	r_dcache_miss_way.read(),
3815	r_dcache_miss_set.read() );
3816
3817	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3818	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3819
3820	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3821	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3822	else r_dcache_fsm = DCACHE_IDLE;
3823	}
3824	}
3825
3826	#if DEBUG_DCACHE
3827	if ( m_debug_dcache_fsm )
3828	{
3829	if ( r_dcache_miss_inval.read() )
3830	{
3831	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3832	{
3833	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3834	<< " pop the FIFO, don't update the cache" << std::endl;
3835	}
3836	else
3837	{
3838	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3839	<< " last word : send a cleanup request " << std::endl;
3840	}
3841	}
3842	else
3843	{
3844	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3845	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3846	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3847	<< " / way = " << std::dec << r_dcache_miss_way.read()
3848	<< " / set = " << r_dcache_miss_set.read()
3849	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3850	}
3851	}
3852	#endif
3853
3854	} // end if rok
3855	break;
3856	}
3857	/////////////////////
3858	case DCACHE_UNC_WAIT:
3859	{
3860	// external coherence request
3861	if ( r_tgt_dcache_req.read() )
3862	{
3863	r_dcache_fsm_cc_save = r_dcache_fsm;
3864	r_dcache_fsm = DCACHE_CC_CHECK;
3865	break;
3866	}
3867
3868	if ( r_vci_rsp_data_error.read() ) // bus error
3869	{
3870	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3871	r_mmu_dbvar = m_dreq.addr;
3872	r_vci_rsp_data_error = false;
3873	m_drsp.error = true;
3874	m_drsp.valid = true;
3875	r_dcache_fsm = DCACHE_IDLE;
3876	break;
3877	}
3878	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3879	{
3880	// consume data
3881	vci_rsp_fifo_dcache_get = true;
3882	r_dcache_fsm = DCACHE_IDLE;
3883
3884	// acknowledge the processor request if it has not been modified
3885	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3886	{
3887	m_drsp.valid = true;
3888	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3889
3890	// makes reservation in case of LL
3891	if ( m_dreq.type == iss_t::DATA_LL )
3892	{
3893	r_dcache_ll_valid = true;
3894	r_dcache_ll_data = r_vci_rsp_fifo_dcache.read();
3895	r_dcache_ll_vaddr = m_dreq.addr;
3896	}
3897	}
3898	}
3899	break;
3900	}
3901	////////////////////
3902	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3903	{
3904	// external coherence request
3905	if ( r_tgt_dcache_req.read() )
3906	{
3907	r_dcache_fsm_cc_save = r_dcache_fsm;
3908	r_dcache_fsm = DCACHE_CC_CHECK;
3909	break;
3910	}
3911
3912	if ( r_vci_rsp_data_error.read() ) // bus error
3913	{
3914	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3915	r_mmu_dbvar = m_dreq.addr;
3916	r_vci_rsp_data_error = false;
3917	m_drsp.error = true;
3918	m_drsp.valid = true;
3919	r_dcache_fsm = DCACHE_IDLE;
3920	break;
3921	}
3922	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3923	{
3924	vci_rsp_fifo_dcache_get = true;
3925	m_drsp.valid = true;
3926	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3927	r_dcache_fsm = DCACHE_IDLE;
3928	}
3929	break;
3930	}
3931	//////////////////////////
3932	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3933	// before handling a processor WRITE or SC request
3934	// Input argument is r_dcache_dirty_paddr
3935	// In this first state, we get PTE value in dcache
3936	// and post a SC request to CMD FSM
3937	{
3938	// get PTE in dcache
3939	uint32_t pte;
3940	size_t way;
3941	size_t set;
3942	size_t word; // unused
3943	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3944	&pte,
3945	&way,
3946	&set,
3947	&word );
3948	#ifdef INSTRUMENTATION
3949	m_cpt_dcache_data_read++;
3950	m_cpt_dcache_dir_read++;
3951	#endif
3952	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3953
3954	// request sc transaction to CMD_FSM
3955	r_dcache_dirty_way = way;
3956	r_dcache_dirty_set = set;
3957	r_dcache_vci_sc_req = true;
3958	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3959	r_dcache_vci_sc_old = pte;
3960	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3961	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3962
3963	#if DEBUG_DCACHE
3964	if ( m_debug_dcache_fsm )
3965	{
3966	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3967	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3968	<< " / PTE_VALUE = " << pte << std::dec
3969	<< " / CACHE_SET = " << set
3970	<< " / CACHE_WAY = " << way << std::endl;
3971	}
3972	#endif
3973	break;
3974	}
3975	//////////////////////////
3976	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3977	// If PTE update is a success, return to IDLE state.
3978	// If PTE update is a failure, invalidate cache line
3979	// in DCACHE and invalidate the matching TLB entries.
3980	{
3981	// external coherence request
3982	if ( r_tgt_dcache_req )
3983	{
3984	r_dcache_fsm_cc_save = r_dcache_fsm;
3985	r_dcache_fsm = DCACHE_CC_CHECK;
3986	break;
3987	}
3988
3989	if ( r_vci_rsp_data_error.read() ) // bus error
3990	{
3991	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3992	std::cout << "This should not happen in this state" << std::endl;
3993	exit(0);
3994	}
3995	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3996	{
3997	vci_rsp_fifo_dcache_get = true;
3998	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
3999	{
4000	r_dcache_fsm = DCACHE_IDLE;
4001
4002	#if DEBUG_DCACHE
4003	if ( m_debug_dcache_fsm )
4004	{
4005	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
4006	<< std::endl;
4007	}
4008	#endif
4009	}
4010	else // invalidate the cache line TLBs
4011	{
4012
4013	#if DEBUG_DCACHE
4014	if ( m_debug_dcache_fsm )
4015	{
4016	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
4017	<< std::endl;
4018	}
4019	#endif
4020	paddr_t nline;
4021	size_t way = r_dcache_dirty_way.read();
4022	size_t set = r_dcache_dirty_set.read();
4023	bool hit;
4024
4025	hit = r_dcache.inval( way,
4026	set,
4027	&nline );
4028
4029	assert(hit && "PTE should still be in dcache");
4030
4031	// request cleanup
4032	r_dcache_cleanup_req = true;
4033	r_dcache_cleanup_line = nline;
4034
4035	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
4036	{
4037	r_dcache_tlb_inval_line = nline;
4038	r_dcache_tlb_inval_count = 0;
4039	r_dcache_fsm_scan_save = DCACHE_IDLE;
4040	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4041	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4042	}
4043	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
4044	{
4045	r_itlb.reset();
4046	r_dtlb.reset();
4047	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4048	r_dcache_fsm = DCACHE_IDLE;
4049	}
4050	else
4051	{
4052	r_dcache_fsm = DCACHE_IDLE;
4053	}
4054	}
4055	}
4056	break;
4057	}
4058	/////////////////////
4059	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4060	// handling coherence requests.
4061	// If there is a matching pending miss on the modified cache
4062	// line this is signaled in the r_dcache_miss inval flip-flop.
4063	// If the updated (or invalidated) cache line has copies in TLBs
4064	// these TLB copies are invalidated.
4065	// The return state is defined in r_dcache_fsm_cc_save
4066	{
4067	paddr_t paddr = r_tgt_paddr.read();
4068	paddr_t mask = ~((m_dcache_words<<2)-1);
4069
4070
4071	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4072	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4073	{
4074	r_dcache_miss_inval = true; // signaling the match
4075	r_tgt_dcache_req = false; // coherence request completed
4076	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4077	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4078
4079	#if DEBUG_DCACHE
4080	if ( m_debug_dcache_fsm )
4081	{
4082	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4083	<< " address = " << std::hex << paddr << std::endl;
4084	}
4085	#endif
4086
4087	}
4088	else // no match
4089	{
4090	uint32_t rdata;
4091	size_t way;
4092	size_t set;
4093	size_t word;
4094
4095	bool hit = r_dcache.read(paddr,
4096	&rdata, // unused
4097	&way,
4098	&set,
4099	&word); // unused
4100	#ifdef INSTRUMENTATION
4101	m_cpt_dcache_data_read++;
4102	m_cpt_dcache_dir_read++;
4103	#endif
4104	r_dcache_cc_way = way;
4105	r_dcache_cc_set = set;
4106
4107	if ( hit and r_tgt_update.read() ) // hit update
4108	{
4109	r_dcache_fsm = DCACHE_CC_UPDT;
4110	r_dcache_cc_word = r_tgt_word_min.read();
4111	}
4112	else if ( hit and not r_tgt_update.read() ) // hit inval
4113	{
4114	r_dcache_fsm = DCACHE_CC_INVAL;
4115	}
4116	else // miss can happen
4117	{
4118	r_tgt_dcache_req = false;
4119	r_tgt_dcache_rsp = r_tgt_update.read();
4120	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4121	}
4122
4123	#if DEBUG_DCACHE
4124	if ( m_debug_dcache_fsm )
4125	{
4126
4127	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4128	<< " address = " << std::hex << paddr << std::dec;
4129	if ( hit )
4130	{
4131	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4132	}
4133	else
4134	{
4135	std::cout << " / MISS" << std::endl;
4136	}
4137	}
4138	#endif
4139
4140	}
4141	break;
4142	}
4143	/////////////////////
4144	case DCACHE_CC_INVAL: // invalidate one cache line
4145	// and test possible copies in TLBs
4146	{
4147	paddr_t nline;
4148	size_t way = r_dcache_cc_way.read();
4149	size_t set = r_dcache_cc_set.read();
4150	bool hit;
4151
4152	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4153	{
4154	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4155	r_dcache_tlb_inval_line = nline;
4156	r_dcache_tlb_inval_count = 0;
4157	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4158	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4159	}
4160	else // actual cache line inval
4161	{
4162	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4163	{
4164	r_itlb.reset();
4165	r_dtlb.reset();
4166	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4167	}
4168	r_tgt_dcache_rsp = true;
4169	r_tgt_dcache_req = false;
4170	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4171
4172	hit = r_dcache.inval( way,
4173	set,
4174	&nline );
4175	#if DEBUG_DCACHE
4176	if ( m_debug_dcache_fsm )
4177	{
4178	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4179	<< " / WAY = " << way
4180	<< " / SET = " << set << std::endl;
4181	}
4182	#endif
4183
4184	assert(hit && "CC_INVAL way/set should still be in dcache");
4185	}
4186	break;
4187	}
4188	///////////////////
4189	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4190	// and test possible copies in TLBs
4191	{
4192	size_t word = r_dcache_cc_word.read();
4193	size_t way = r_dcache_cc_way.read();
4194	size_t set = r_dcache_cc_set.read();
4195	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4196
4197	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4198	{
4199	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4200	r_dcache_tlb_inval_line = nline;
4201	r_dcache_tlb_inval_count = 0;
4202	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4203	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4204	}
4205	else // cache update
4206	{
4207	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4208	{
4209	r_itlb.reset();
4210	r_dtlb.reset();
4211	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4212	}
4213
4214	r_dcache.write( way,
4215	set,
4216	word,
4217	r_tgt_buf[word],
4218	r_tgt_be[word] );
4219	#ifdef INSTRUMENTATION
4220	m_cpt_dcache_data_write++;
4221	#endif
4222	r_dcache_cc_word = word + 1;
4223
4224	#if DEBUG_DCACHE
4225	if ( m_debug_dcache_fsm )
4226	{
4227	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4228	<< " / WAY = " << way
4229	<< " / SET = " << set
4230	<< " / WORD = " << word
4231	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4232	}
4233	#endif
4234	if ( word == r_tgt_word_max.read() ) // last word
4235	{
4236	r_tgt_dcache_rsp = true;
4237	r_tgt_dcache_req = false;
4238	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4239	}
4240	}
4241
4242	break;
4243	}
4244	///////////////////////////
4245	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4246	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4247	// and (m_itlb_ways == m_dtlb_ways)
4248	// We enter this state when a DCACHE line is modified,
4249	// and there is a copy in itlb or dtlb.
4250	// It can be caused by:
4251	// - a coherence inval or updt transaction,
4252	// - a line inval caused by a cache miss
4253	// - a processor XTN inval request,
4254	// - a WRITE hit,
4255	// - a Dirty bit update failure
4256	// Input arguments are:
4257	// - r_dcache_tlb_inval_line
4258	// - r_dcache_tlb_inval_count
4259	// - r_dcache_fsm_cc_save
4260	{
4261	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4262	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4263	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4264	bool ok;
4265
4266	ok = r_itlb.inval( line,
4267	way,
4268	set );
4269	#if DEBUG_DCACHE
4270	if ( m_debug_dcache_fsm and ok )
4271	{
4272	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4273	<< " line = " << line << std::dec
4274	<< " / set = " << set
4275	<< " / way = " << way << std::endl;
4276	r_itlb.printTrace();
4277	}
4278	#endif
4279	ok = r_dtlb.inval( line,
4280	way,
4281	set );
4282	#if DEBUG_DCACHE
4283	if ( m_debug_dcache_fsm and ok )
4284	{
4285	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4286	<< " line = " << line << std::dec
4287	<< " / set = " << set
4288	<< " / way = " << way << std::endl;
4289	r_dtlb.printTrace();
4290	}
4291	#endif
4292
4293	// return to the calling state when TLB inval completed
4294	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4295	{
4296	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4297	}
4298	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4299	break;
4300	}
4301	} // end switch r_dcache_fsm
4302
4303	///////////////// wbuf update //////////////////////////////////////////////////////
4304	r_wbuf.update();
4305
4306	//////////////// test processor frozen /////////////////////////////////////////////
4307	// The simulation exit if the number of consecutive frozen cycles
4308	// is larger than the m_max_frozen_cycles (constructor parameter)
4309	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4310	{
4311	m_cpt_frz_cycles++; // used for instrumentation
4312	m_cpt_stop_simulation++; // used for debug
4313	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4314	{
4315	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4316	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4317	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4318	<< std::endl;
4319	exit(1);
4320	}
4321	}
4322	else
4323	{
4324	m_cpt_stop_simulation = 0;
4325	}
4326
4327	/////////// execute one iss cycle /////////////////////////////////
4328	{
4329	uint32_t it = 0;
4330	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4331	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4332	}
4333
4334	////////////////////////////////////////////////////////////////////////////
4335	// The VCI_CMD FSM controls the following ressources:
4336	// - r_vci_cmd_fsm
4337	// - r_vci_cmd_min
4338	// - r_vci_cmd_max
4339	// - r_vci_cmd_cpt
4340	// - r_vci_cmd_imiss_prio
4341	// - wbuf (reset)
4342	// - r_icache_miss_req (reset)
4343	// - r_icache_unc_req (reset)
4344	// - r_dcache_vci_miss_req (reset)
4345	// - r_dcache_vci_unc_req (reset)
4346	// - r_dcache_vci_sc_req (reset)
4347	//
4348	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4349	// There is 6 request types, with the following priorities :
4350	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4351	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4352	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4353	// 4 - Instruction Uncachable : r_icache_unc_req
4354	// 5 - Data Write : r_wbuf.rok()
4355	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4356	//
4357	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4358	// and the VCI_RSP_FSM are fully desynchronized.
4359	//
4360	// VCI formats:
4361	// According to the VCI advanced specification, all read requests packets
4362	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4363	// are one word packets.
4364	// For write burst packets, all words are in the same cache line,
4365	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4366	// The sc command packet implements actually a compare-and-swap mechanism
4367	// and the packet contains two flits.
4368	////////////////////////////////////////////////////////////////////////////////////
4369
4370	switch ( r_vci_cmd_fsm.read() )
4371	{
4372	//////////////
4373	case CMD_IDLE:
4374	{
4375	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4376	// to check a possible pending write on the same cache line.
4377	// As there is only one possible access per cycle to write buffer, we implement
4378	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4379
4380	size_t wbuf_min;
4381	size_t wbuf_max;
4382
4383	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4384	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4385
4386	bool icache_miss_req = r_icache_miss_req.read()
4387	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4388
4389	// 1 - Data Read Miss
4390	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4391	{
4392	r_vci_cmd_fsm = CMD_DATA_MISS;
4393	r_dcache_vci_miss_req = false;
4394	r_vci_cmd_imiss_prio = true;
4395	// m_cpt_dmiss_transaction++;
4396	}
4397	// 2 - Data Read Uncachable
4398	else if ( r_dcache_vci_unc_req.read() )
4399	{
4400	r_vci_cmd_fsm = CMD_DATA_UNC;
4401	r_dcache_vci_unc_req = false;
4402	// m_cpt_dunc_transaction++;
4403	}
4404	// 3 - Instruction Miss
4405	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4406	{
4407	r_vci_cmd_fsm = CMD_INS_MISS;
4408	r_icache_miss_req = false;
4409	r_vci_cmd_imiss_prio = false;
4410	// m_cpt_imiss_transaction++;
4411	}
4412	// 4 - Instruction Uncachable
4413	else if ( r_icache_unc_req.read() )
4414	{
4415	r_vci_cmd_fsm = CMD_INS_UNC;
4416	r_icache_unc_req = false;
4417	// m_cpt_iunc_transaction++;
4418	}
4419	// 5 - Data Write
4420	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4421	{
4422	r_vci_cmd_fsm = CMD_DATA_WRITE;
4423	r_vci_cmd_cpt = wbuf_min;
4424	r_vci_cmd_min = wbuf_min;
4425	r_vci_cmd_max = wbuf_max;
4426	// m_cpt_write_transaction++;
4427	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4428	}
4429	// 6 - Data Store Conditionnal
4430	else if ( r_dcache_vci_sc_req.read() )
4431	{
4432	r_vci_cmd_fsm = CMD_DATA_SC;
4433	r_dcache_vci_sc_req = false;
4434	r_vci_cmd_cpt = 0;
4435	// m_cpt_sc_transaction++;
4436	}
4437	break;
4438	}
4439	////////////////////
4440	case CMD_DATA_WRITE:
4441	{
4442	if ( p_vci_ini_d.cmdack.read() )
4443	{
4444	// m_conso_wbuf_read++;
4445	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4446	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4447	{
4448	r_vci_cmd_fsm = CMD_IDLE ;
4449	r_wbuf.sent() ;
4450	}
4451	}
4452	break;
4453	}
4454	/////////////////
4455	case CMD_DATA_SC:
4456	{
4457	// The SC VCI command contains two flits
4458	if ( p_vci_ini_d.cmdack.read() )
4459	{
4460	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4461	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4462	}
4463	break;
4464	}
4465	//////////////////
4466	case CMD_INS_MISS:
4467	case CMD_INS_UNC:
4468	case CMD_DATA_MISS:
4469	case CMD_DATA_UNC:
4470	{
4471	// all read VCI commands contain one single flit
4472	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4473	break;
4474	}
4475
4476	} // end switch r_vci_cmd_fsm
4477
4478	//////////////////////////////////////////////////////////////////////////
4479	// The VCI_RSP FSM controls the following ressources:
4480	// - r_vci_rsp_fsm:
4481	// - r_vci_rsp_fifo_icache (push)
4482	// - r_vci_rsp_fifo_dcache (push)
4483	// - r_vci_rsp_data_error (set)
4484	// - r_vci_rsp_ins_error (set)
4485	// - r_vci_rsp_cpt
4486	//
4487	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4488	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4489	// to identify the transactions.
4490	//
4491	// VCI vormat:
4492	// This component checks the response packet length and accepts only
4493	// single word packets for write response packets.
4494	//
4495	// Error handling:
4496	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4497	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4498	// flip_flop and the error is signaled by the DCACHE FSM.
4499	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4500	// flip_flop and the error is signaled by the ICACHE FSM.
4501	// In case of Cleanup Error, the simulation stops with an error message...
4502	//////////////////////////////////////////////////////////////////////////
4503
4504	switch ( r_vci_rsp_fsm.read() )
4505	{
4506	//////////////
4507	case RSP_IDLE:
4508	{
4509	if ( p_vci_ini_d.rspval.read() )
4510	{
4511	r_vci_rsp_cpt = 0;
4512
4513	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4514	{
4515	r_vci_rsp_fsm = RSP_DATA_WRITE;
4516	}
4517	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4518	{
4519	r_vci_rsp_fsm = RSP_INS_MISS;
4520	}
4521	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4522	{
4523	r_vci_rsp_fsm = RSP_INS_UNC;
4524	}
4525	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4526	{
4527	r_vci_rsp_fsm = RSP_DATA_MISS;
4528	}
4529	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4530	{
4531	r_vci_rsp_fsm = RSP_DATA_UNC;
4532	}
4533	else
4534	{
4535	assert(false and "Unexpected VCI response");
4536	}
4537	}
4538	break;
4539	}
4540	//////////////////
4541	case RSP_INS_MISS:
4542	{
4543	if ( p_vci_ini_d.rspval.read() )
4544	{
4545	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4546	{
4547	r_vci_rsp_ins_error = true;
4548	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4549	}
4550	else // no error reported
4551	{
4552	if ( r_vci_rsp_fifo_icache.wok() )
4553	{
4554	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4555	"The VCI response packet for instruction miss is too long" );
4556
4557	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4558	vci_rsp_fifo_icache_put = true,
4559	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4560	if ( p_vci_ini_d.reop.read() )
4561	{
4562	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4563	"The VCI response packet for instruction miss is too short");
4564
4565	r_vci_rsp_fsm = RSP_IDLE;
4566	}
4567	}
4568	}
4569	}
4570	break;
4571	}
4572	/////////////////
4573	case RSP_INS_UNC:
4574	{
4575	if (p_vci_ini_d.rspval.read() )
4576	{
4577	assert( p_vci_ini_d.reop.read() and
4578	"illegal VCI response packet for uncachable instruction");
4579
4580	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4581	{
4582	r_vci_rsp_ins_error = true;
4583	r_vci_rsp_fsm = RSP_IDLE;
4584	}
4585	else // no error reported
4586	{
4587	if ( r_vci_rsp_fifo_icache.wok())
4588	{
4589	vci_rsp_fifo_icache_put = true;
4590	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4591	r_vci_rsp_fsm = RSP_IDLE;
4592	}
4593	}
4594	}
4595	break;
4596	}
4597	///////////////////
4598	case RSP_DATA_MISS:
4599	{
4600	if ( p_vci_ini_d.rspval.read() )
4601	{
4602	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4603	{
4604	r_vci_rsp_data_error = true;
4605	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4606	}
4607	else // no error reported
4608	{
4609	if ( r_vci_rsp_fifo_dcache.wok() )
4610	{
4611	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4612	"The VCI response packet for data miss is too long");
4613
4614	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4615	vci_rsp_fifo_dcache_put = true,
4616	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4617	if ( p_vci_ini_d.reop.read() )
4618	{
4619	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4620	"The VCI response packet for data miss is too short");
4621
4622	r_vci_rsp_fsm = RSP_IDLE;
4623	}
4624	}
4625	}
4626	}
4627	break;
4628	}
4629	//////////////////
4630	case RSP_DATA_UNC:
4631	{
4632	if (p_vci_ini_d.rspval.read() )
4633	{
4634	assert( p_vci_ini_d.reop.read() and
4635	"illegal VCI response packet for uncachable read data");
4636
4637	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4638	{
4639	r_vci_rsp_data_error = true;
4640	r_vci_rsp_fsm = RSP_IDLE;
4641	}
4642	else // no error reported
4643	{
4644	if ( r_vci_rsp_fifo_dcache.wok())
4645	{
4646	vci_rsp_fifo_dcache_put = true;
4647	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4648	r_vci_rsp_fsm = RSP_IDLE;
4649	}
4650	}
4651	}
4652	break;
4653	}
4654	////////////////////
4655	case RSP_DATA_WRITE:
4656	{
4657	if (p_vci_ini_d.rspval.read())
4658	{
4659	assert( p_vci_ini_d.reop.read() and
4660	"a VCI response packet must contain one flit for a write transaction");
4661
4662	r_vci_rsp_fsm = RSP_IDLE;
4663	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4664	bool cacheable = r_wbuf.completed(wbuf_index);
4665	if ( not cacheable ) r_dcache_pending_unc_write = false;
4666	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4667	}
4668	break;
4669	}
4670	} // end switch r_vci_rsp_fsm
4671
4672	/////////////////////////////////////////////////////////////////////////////////////
4673	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4674	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4675	// with a round-robin priority. All cleanup commands are registered in the
4676	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4677	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4678	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4679	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4680	// the request has been sent and registered in the buffer.
4681	// The buffer itself is cleared when the cleanup response is received.
4682	// We use an assocative registration buffer (CAM) in order to support several
4683	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4684	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4685	// - if data cleanup : TRDID = 2*index + 0
4686	// - if instruction cleanup : TRDID = 2*index + 1
4687	/////////////////////////////////////////////////////////////////////////////////////
4688
4689	switch ( r_cleanup_fsm.read() )
4690	{
4691	///////////////////////
4692	case CLEANUP_DATA_IDLE: // dcache has highest priority
4693	{
4694	size_t index = 0;
4695	bool ok;
4696	if ( r_dcache_cleanup_req.read() ) // dcache request
4697	{
4698	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4699	&index );
4700	if ( ok ) // successful registration
4701	{
4702	r_cleanup_fsm = CLEANUP_DATA_GO;
4703	r_cleanup_trdid = index<<1;
4704	}
4705	}
4706	else if ( r_icache_cleanup_req.read() ) // icache request
4707	{
4708	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4709	&index );
4710	if ( ok ) // successful registration
4711	{
4712	r_cleanup_fsm = CLEANUP_INS_GO;
4713	r_cleanup_trdid = (index<<1) + 1;
4714	}
4715	}
4716	break;
4717	}
4718	//////////////////////
4719	case CLEANUP_INS_IDLE: // icache has highest priority
4720	{
4721	size_t index = 0;
4722	bool ok;
4723	if ( r_icache_cleanup_req.read() ) // icache request
4724	{
4725	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4726	&index );
4727	if ( ok ) // successful registration
4728	{
4729	r_cleanup_fsm = CLEANUP_INS_GO;
4730	r_cleanup_trdid = (index<<1) + 1;
4731	}
4732	}
4733	else if ( r_dcache_cleanup_req.read() ) // dcache request
4734	{
4735	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4736	&index );
4737	if ( ok ) // successful registration
4738	{
4739	r_cleanup_fsm = CLEANUP_DATA_GO;
4740	r_cleanup_trdid = index<<1;
4741	}
4742	}
4743	break;
4744	}
4745	/////////////////////
4746	case CLEANUP_DATA_GO:
4747	{
4748	if ( p_vci_ini_c.cmdack.read() )
4749	{
4750	r_cleanup_fsm = CLEANUP_INS_IDLE;
4751	r_dcache_cleanup_req = false;
4752
4753	#if DEBUG_CLEANUP
4754	if ( m_debug_cleanup_fsm )
4755	{
4756	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4757	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4758	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4759	}
4760	#endif
4761	}
4762	break;
4763	}
4764	////////////////////
4765	case CLEANUP_INS_GO:
4766	{
4767	if ( p_vci_ini_c.cmdack.read() )
4768	{
4769	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4770	r_icache_cleanup_req = false;
4771
4772	#if DEBUG_CLEANUP
4773	if ( m_debug_cleanup_fsm )
4774	{
4775	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4776	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4777	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4778	}
4779	#endif
4780	}
4781	break;
4782	}
4783	} // end switch CLEANUP FSM
4784
4785	//////////////// Handling cleanup responses //////////////////
4786	if ( p_vci_ini_c.rspval.read() )
4787	{
4788	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
4789	}
4790
4791	///////////////// Response FIFOs update //////////////////////
4792	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4793	vci_rsp_fifo_icache_put,
4794	vci_rsp_fifo_icache_data);
4795
4796	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4797	vci_rsp_fifo_dcache_put,
4798	vci_rsp_fifo_dcache_data);
4799	} // end transition()
4800
4801	///////////////////////
4802	tmpl(void)::genMoore()
4803	///////////////////////
4804	{
4805	////////////////////////////////////////////////////////////////
4806	// VCI initiator command on the coherence network (cleanup)
4807	// it depends on the CLEANUP FSM state
4808
4809	paddr_t address;
4810
4811	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4812	address = r_dcache_cleanup_line.read()m_dcache_words4;
4813	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4814	address = r_icache_cleanup_line.read()m_icache_words4;
4815	else
4816	address = 0;
4817
4818	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4819	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4820	p_vci_ini_c.address = address;
4821	p_vci_ini_c.wdata = 0;
4822	p_vci_ini_c.be = 0xF;
4823	p_vci_ini_c.plen = 4;
4824	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4825	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4826	p_vci_ini_c.pktid = 0;
4827	p_vci_ini_c.srcid = m_srcid_c;
4828	p_vci_ini_c.cons = false;
4829	p_vci_ini_c.wrap = false;
4830	p_vci_ini_c.contig = false;
4831	p_vci_ini_c.clen = 0;
4832	p_vci_ini_c.cfixed = false;
4833	p_vci_ini_c.eop = true;
4834
4835	/////////////////////////////////////////////////////////////////
4836	// VCI initiator response on the coherence network (cleanup)
4837	// We always consume the response, and we don't use it.
4838
4839	p_vci_ini_c.rspack = true;
4840
4841	/////////////////////////////////////////////////////////////////
4842	// VCI initiator command on the direct network
4843	// it depends on the CMD FSM state
4844
4845	p_vci_ini_d.pktid = 0;
4846	p_vci_ini_d.srcid = m_srcid_d;
4847	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4848	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4849	p_vci_ini_d.wrap = false;
4850	p_vci_ini_d.clen = 0;
4851	p_vci_ini_d.cfixed = false;
4852
4853	switch ( r_vci_cmd_fsm.read() ) {
4854
4855	case CMD_IDLE:
4856	p_vci_ini_d.cmdval = false;
4857	p_vci_ini_d.address = 0;
4858	p_vci_ini_d.wdata = 0;
4859	p_vci_ini_d.be = 0;
4860	p_vci_ini_d.trdid = 0;
4861	p_vci_ini_d.plen = 0;
4862	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4863	p_vci_ini_d.eop = false;
4864	break;
4865
4866	case CMD_INS_MISS:
4867	p_vci_ini_d.cmdval = true;
4868	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4869	p_vci_ini_d.wdata = 0;
4870	p_vci_ini_d.be = 0xF;
4871	p_vci_ini_d.trdid = TYPE_INS_MISS;
4872	p_vci_ini_d.plen = m_icache_words<<2;
4873	p_vci_ini_d.cmd = vci_param::CMD_READ;
4874	p_vci_ini_d.eop = true;
4875	break;
4876
4877	case CMD_INS_UNC:
4878	p_vci_ini_d.cmdval = true;
4879	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4880	p_vci_ini_d.wdata = 0;
4881	p_vci_ini_d.be = 0xF;
4882	p_vci_ini_d.trdid = TYPE_INS_UNC;
4883	p_vci_ini_d.plen = 4;
4884	p_vci_ini_d.cmd = vci_param::CMD_READ;
4885	p_vci_ini_d.eop = true;
4886	break;
4887
4888	case CMD_DATA_MISS:
4889	p_vci_ini_d.cmdval = true;
4890	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4891	p_vci_ini_d.wdata = 0;
4892	p_vci_ini_d.be = 0xF;
4893	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4894	p_vci_ini_d.plen = m_dcache_words << 2;
4895	p_vci_ini_d.cmd = vci_param::CMD_READ;
4896	p_vci_ini_d.eop = true;
4897	break;
4898
4899	case CMD_DATA_UNC:
4900	p_vci_ini_d.cmdval = true;
4901	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4902	p_vci_ini_d.wdata = 0;
4903	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4904	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4905	p_vci_ini_d.plen = 4;
4906	p_vci_ini_d.cmd = vci_param::CMD_READ;
4907	p_vci_ini_d.eop = true;
4908	break;
4909
4910	case CMD_DATA_WRITE:
4911	p_vci_ini_d.cmdval = true;
4912	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4913	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4914	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4915	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4916	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4917	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4918	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4919	break;
4920
4921	case CMD_DATA_SC:
4922	p_vci_ini_d.cmdval = true;
4923	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4924	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4925	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4926	p_vci_ini_d.be = 0xF;
4927	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4928	p_vci_ini_d.plen = 8;
4929	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4930	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4931	break;
4932	} // end switch r_vci_cmd_fsm
4933
4934	//////////////////////////////////////////////////////////
4935	// VCI initiator response on the direct network
4936	// it depends on the VCI RSP state
4937
4938	switch (r_vci_rsp_fsm.read() )
4939	{
4940	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4941	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4942	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4943	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4944	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4945	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4946	} // end switch r_vci_rsp_fsm
4947
4948	////////////////////////////////////////////////////////////////
4949	// VCI target command and response on the coherence network
4950	switch ( r_tgt_fsm.read() )
4951	{
4952	case TGT_IDLE:
4953	case TGT_UPDT_WORD:
4954	case TGT_UPDT_DATA:
4955	p_vci_tgt_c.cmdack = true;
4956	p_vci_tgt_c.rspval = false;
4957	break;
4958
4959	case TGT_RSP_BROADCAST:
4960	p_vci_tgt_c.cmdack = false;
4961	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4962	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4963	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4964	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4965	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4966	p_vci_tgt_c.rdata = 0;
4967	p_vci_tgt_c.rerror = 0;
4968	p_vci_tgt_c.reop = true;
4969	break;
4970
4971	case TGT_RSP_ICACHE:
4972	p_vci_tgt_c.cmdack = false;
4973	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4974	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4975	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4976	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4977	p_vci_tgt_c.rdata = 0;
4978	p_vci_tgt_c.rerror = 0;
4979	p_vci_tgt_c.reop = true;
4980	break;
4981
4982	case TGT_RSP_DCACHE:
4983	p_vci_tgt_c.cmdack = false;
4984	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4985	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4986	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4987	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4988	p_vci_tgt_c.rdata = 0;
4989	p_vci_tgt_c.rerror = 0;
4990	p_vci_tgt_c.reop = true;
4991	break;
4992
4993	case TGT_REQ_BROADCAST:
4994	case TGT_REQ_ICACHE:
4995	case TGT_REQ_DCACHE:
4996	p_vci_tgt_c.cmdack = false;
4997	p_vci_tgt_c.rspval = false;
4998	break;
4999
5000	} // end switch TGT_FSM
5001	} // end genMoore
5002
5003	}}
5004
5005	// Local Variables:
5006	// tab-width: 4
5007	// c-basic-offset: 4
5008	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5009	// indent-tabs-mode: nil
5010	// End:
5011
5012	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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