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vci_cc_xcache_wrapper_v4.h @ 143

Last change on this file since 143 was 143, checked in by kane, 13 years ago
fix bug in ccxcachev4, save cpu_info in memcachev4
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[2]	1	/* -- c++ --
	2	*
	3	* SOCLIB_LGPL_HEADER_BEGIN
	4	*
	5	* This file is part of SoCLib, GNU LGPLv2.1.
	6	*
	7	* SoCLib is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU Lesser General Public License as published
	9	* by the Free Software Foundation; version 2.1 of the License.
	10	*
	11	* SoCLib is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with SoCLib; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* SOCLIB_LGPL_HEADER_END
	22	*
	23	* Copyright (c) UPMC, Lip6, SoC
	24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
	25	*
	26	* Maintainers: alain
	27	*/
	28
	29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
	30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
	31
	32	#include <inttypes.h>
[140]	33	#include <fstream>
[2]	34	#include <systemc>
[134]	35	#include <queue>
[2]	36	#include "caba_base_module.h"
[134]	37	#include "multi_write_buffer.h"
[2]	38	#include "generic_cache.h"
	39	#include "vci_initiator.h"
	40	#include "vci_target.h"
	41	#include "mapping_table.h"
	42	#include "static_assert.h"
	43
[134]	44	/*
	45	* CC_XCACHE_WRAPPER_FIFO_RSP
	46	* Two simple fifo (each 2x32 depth) receive the cache line from
	47	* RAM. Instead of two buffers (m_icache_words and m_dcache_words)
[143]	48	* 1 - nb_icache+nb_dcache simple fifo
	49	* 2 - 2 simple fifo
	50	* else - two buffers (m_icache_words and m_dcache_words)
[134]	51	*
	52	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
	53	* Update cache in "2*cache_words" cycles (read+mask, write)
	54	*
	55	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
	56	* Update cache with only modified data (be != 0)
	57	*
	58	* CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
	59	* Write buffer scheme for update step :
	60	* 1 - multi_scan
	61	* 2 - round_robin_scan
	62	* 3 - one_scan
	63	* else - default scheme
	64	*
	65	* CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
	66	* Write buffer access is conditionnal with dcache_miss_req and icache_miss_req
[143]	67	* 1 - one access with static priority (dcache prior)
	68	* 2 - one access with static priority (icache prior)
	69	* 3 - one access with round robin priority
	70	* 4 - two access authorized
[134]	71	*
[140]	72	* CC_XCACHE_WRAPPER_MULTI_CACHE :
	73	* 1 - icache static partitionnement
	74	* 2 - icache dedicated
	75	*
[134]	76	* CC_XCACHE_WRAPPER_STOP_SIMULATION :
	77	* stop simulation if processor is stall after a long time
	78	* (configurable with "stop_simulation" function)
	79	*
	80	* CC_XCACHE_WRAPPER_DEBUG :
	81	* Add log to help the debugging
	82	*
	83	* CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN :
	84	* Number of cycle before to prinf debug message
	85	*
[140]	86	* CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	87	* Print transaction between :
	88	* - the cpu and the cache (icache and dcache)
	89	* - vci
	90	* - cleanup
	91	* - coherency
[134]	92	*/
[2]	93
[134]	94	// implementation
	95	#ifndef CC_XCACHE_WRAPPER_FIFO_RSP
[140]	96	#define CC_XCACHE_WRAPPER_FIFO_RSP 1
[134]	97	#endif
	98	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
[140]	99	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1
[134]	100	#endif
	101	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
[140]	102	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
[134]	103	#endif
	104	#ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
[140]	105	#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2
[134]	106	#endif
	107	#ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
[143]	108	#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3
[134]	109	#endif
[140]	110	#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
	111	#define CC_XCACHE_WRAPPER_MULTI_CACHE 2
[143]	112	// if multi_cache :
	113	// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
	114	// <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1
	115	#endif
	116
[134]	117	// debugging
[143]	118	#ifndef CC_XCACHE_WRAPPER_VERBOSE
	119	#define CC_XCACHE_WRAPPER_VERBOSE 1
	120	#endif
[134]	121	#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
[140]	122	#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1
[134]	123	#endif
	124	#ifndef CC_XCACHE_WRAPPER_DEBUG
[140]	125	#define CC_XCACHE_WRAPPER_DEBUG 0
[134]	126	#endif
	127	#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
[143]	128	#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500
[134]	129	#endif
[140]	130	#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	131	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0
	132	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
[134]	133	#endif
	134
[140]	135	// don't change
	136	#if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
	137	#undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
	138	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0
	139	#endif
	140
[2]	141	namespace soclib {
	142	namespace caba {
	143
	144	using namespace sc_core;
	145
	146	////////////////////////////////////////////
	147	template<typename vci_param, typename iss_t>
	148	class VciCcXCacheWrapperV4
	149	///////////////////////////////////////////
	150	: public soclib::caba::BaseModule
	151	{
[90]	152	typedef sc_dt::sc_uint<40> addr_40;
[110]	153	typedef sc_dt::sc_uint<64> data_64;
[90]	154	typedef uint32_t data_t;
	155	typedef uint32_t tag_t;
	156	typedef uint32_t be_t;
[2]	157	typedef typename vci_param::fast_addr_t vci_addr_t;
[134]	158
[2]	159	enum dcache_fsm_state_e {
	160	DCACHE_IDLE,
	161	DCACHE_WRITE_UPDT,
[134]	162	DCACHE_MISS_VICTIM,
[2]	163	DCACHE_MISS_WAIT,
	164	DCACHE_MISS_UPDT,
	165	DCACHE_UNC_WAIT,
	166	DCACHE_SC_WAIT,
	167	DCACHE_INVAL,
[134]	168	DCACHE_SYNC,
[2]	169	DCACHE_ERROR,
	170	DCACHE_CC_CHECK,
	171	DCACHE_CC_INVAL,
	172	DCACHE_CC_UPDT,
	173	DCACHE_CC_CLEANUP,
	174	};
	175
	176	enum icache_fsm_state_e {
	177	ICACHE_IDLE,
[134]	178	ICACHE_MISS_VICTIM,
[2]	179	ICACHE_MISS_WAIT,
	180	ICACHE_MISS_UPDT,
	181	ICACHE_UNC_WAIT,
	182	ICACHE_ERROR,
	183	ICACHE_CC_CLEANUP,
	184	ICACHE_CC_CHECK,
	185	ICACHE_CC_INVAL,
	186	ICACHE_CC_UPDT,
	187	};
	188
	189	enum cmd_fsm_state_e {
	190	CMD_IDLE,
	191	CMD_INS_MISS,
	192	CMD_INS_UNC,
	193	CMD_DATA_MISS,
	194	CMD_DATA_UNC,
	195	CMD_DATA_WRITE,
	196	CMD_DATA_SC,
	197	};
	198
	199	enum rsp_fsm_state_e {
	200	RSP_IDLE,
	201	RSP_INS_MISS,
	202	RSP_INS_UNC,
	203	RSP_DATA_MISS,
	204	RSP_DATA_UNC,
	205	RSP_DATA_WRITE,
	206	RSP_DATA_SC,
	207	};
	208
	209	enum tgt_fsm_state_e {
	210	TGT_IDLE,
	211	TGT_UPDT_WORD,
	212	TGT_UPDT_DATA,
	213	TGT_REQ_BROADCAST,
	214	TGT_REQ_ICACHE,
	215	TGT_REQ_DCACHE,
	216	TGT_RSP_BROADCAST,
	217	TGT_RSP_ICACHE,
	218	TGT_RSP_DCACHE,
	219	};
	220
[134]	221	enum cleanup_fsm_state_e {
	222	CLEANUP_IDLE,
[140]	223	CLEANUP_REQ,
	224	CLEANUP_RSP_DCACHE,
	225	CLEANUP_RSP_ICACHE,
[134]	226	};
	227
	228	enum transaction_type_c_e {
	229	// convention with memcache
	230	TYPE_DATA_CLEANUP = 0x0,
	231	TYPE_INS_CLEANUP = 0x1
	232	};
	233
	234	enum transaction_type_rw_e {
	235	// convention with memcache
	236	// b0 : 1 if cached
	237	// b1 : 1 if instruction
	238	// b2 : 1 if sc
	239	TYPE_DATA_UNC = 0x0,
	240	TYPE_DATA_MISS = 0x1,
	241	TYPE_INS_UNC = 0x2,
	242	TYPE_INS_MISS = 0x3,
	243	TYPE_DATA_SC = 0x4, // sc is data and no cached
	244	};
	245
[2]	246	public:
	247
	248	// PORTS
	249	sc_in<bool> p_clk;
	250	sc_in<bool> p_resetn;
[140]	251	sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];
[2]	252	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
	253	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
	254	soclib::caba::VciTarget<vci_param> p_vci_tgt;
	255
	256	private:
	257
	258	// STRUCTURAL PARAMETERS
	259	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
	260	const soclib::common::Segment m_segment;
[140]	261	iss_t ** m_iss; //[m_nb_cpu]
[2]	262	const uint32_t m_srcid_rw;
	263	const uint32_t m_srcid_c;
	264
[140]	265	const size_t m_nb_cpu;
	266	const size_t m_nb_icache;
	267	const size_t m_nb_dcache;
	268	const size_t m_nb_cache;
[2]	269	const size_t m_dcache_ways;
	270	const size_t m_dcache_words;
[134]	271	const uint32_t m_dcache_words_shift;
[2]	272	const size_t m_dcache_yzmask;
	273	const size_t m_icache_ways;
	274	const size_t m_icache_words;
[134]	275	const uint32_t m_icache_words_shift;
[2]	276	const size_t m_icache_yzmask;
[134]	277	const size_t m_cache_words; // max between m_dcache_words and m_icache_words
[2]	278
[134]	279	#if CC_XCACHE_WRAPPER_STOP_SIMULATION
	280	bool m_stop_simulation;
	281	uint32_t m_stop_simulation_nb_frz_cycles_max;
[140]	282	uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
[134]	283	#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
	284
[2]	285	// REGISTERS
[140]	286	sc_signal<uint32_t> r_cpu_prior;
	287	sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache]
	288	sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache]
	289	sc_signal<bool> * r_dcache_sync;//[m_nb_dcache]
[2]	290
[140]	291	sc_signal<int> * r_dcache_fsm; //[m_nb_dcache]
	292	sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache]
	293	sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache]
	294	sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache]
	295	sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache]
	296	sc_signal<int> * r_dcache_type_save; //[m_nb_dcache]
	297	sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache]
	298	sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache]
	299	sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache]
	300	sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache]
	301	sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache]
	302	sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache]
	303	sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache]
	304	sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache]
	305	sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache]
	306	sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache]
	307	sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache]
	308	sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu]
	309	sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu]
	310	sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu]
	311	sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache]
	312	sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache]
	313
	314	sc_signal<int> * r_icache_fsm; //[m_nb_icache]
	315	sc_signal<int> * r_icache_fsm_save; //[m_nb_icache]
	316	sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache]
	317	sc_signal<bool> * r_icache_miss_req; //[m_nb_icache]
	318	sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache]
	319	sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache]
	320	sc_signal<bool> * r_icache_unc_req; //[m_nb_icache]
	321	sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache]
	322	sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache]
	323	sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache]
	324	sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache]
	325	sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache]
[2]	326
	327	sc_signal<int> r_vci_cmd_fsm;
	328	sc_signal<size_t> r_vci_cmd_min;
	329	sc_signal<size_t> r_vci_cmd_max;
	330	sc_signal<size_t> r_vci_cmd_cpt;
[134]	331	sc_signal<bool> r_vci_cmd_dcache_prior;
[140]	332	sc_signal<uint32_t> r_vci_cmd_num_cache;
	333
[2]	334	sc_signal<int> r_vci_rsp_fsm;
	335	sc_signal<size_t> r_vci_rsp_cpt;
[140]	336	bool s_vci_rsp_ack;
	337	sc_signal<uint32_t> r_vci_rsp_num_cache;
	338	sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache]
	339	sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache]
[2]	340
[143]	341	#if (CC_XCACHE_WRAPPER_FIFO_RSP==1)
[140]	342	std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache]
	343	std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache]
[143]	344	#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2)
	345	typedef struct
	346	{
	347	data_t data;
	348	uint32_t num_cache;
	349	} miss_buf_t;
	350
	351	std::queue<miss_buf_t> r_icache_miss_buf;
	352	std::queue<miss_buf_t> r_dcache_miss_buf;
[134]	353	#else
[140]	354	bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words]
	355	data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words]
	356	bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words]
	357	data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words]
[134]	358	#endif
[140]	359	data_t * r_tgt_buf; //[m_cache_words]
	360	be_t * r_tgt_be; //[m_cache_words]
[134]	361	#if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
	362	sc_signal<uint32_t> r_cache_word;
	363	#endif
[2]	364
	365	sc_signal<int> r_vci_tgt_fsm;
[140]	366	sc_signal<addr_40> r_tgt_iaddr;
	367	sc_signal<addr_40> r_tgt_daddr;
[2]	368	sc_signal<size_t> r_tgt_word;
	369	sc_signal<bool> r_tgt_update;
	370	sc_signal<bool> r_tgt_update_data;
[134]	371	//sc_signal<bool> r_tgt_brdcast;
[2]	372	sc_signal<size_t> r_tgt_srcid;
	373	sc_signal<size_t> r_tgt_pktid;
	374	sc_signal<size_t> r_tgt_trdid;
[134]	375	//sc_signal<size_t> r_tgt_plen;
[140]	376	sc_signal<uint32_t> r_tgt_num_cache;
	377	sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache]
	378	sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache]
	379	sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache]
	380	sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache]
[2]	381
[134]	382	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
[140]	383	sc_signal<uint32_t> r_cleanup_num_cache;
	384	sc_signal<bool> r_cleanup_icache;
[134]	385
[140]	386	MultiWriteBuffer<addr_40>** r_wbuf;
	387	GenericCache<vci_addr_t> ** r_icache;
	388	GenericCache<vci_addr_t> ** r_dcache;
[2]	389
[140]	390	#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	391	std::ofstream * log_transaction_file_icache; //[m_nb_cpu]
	392	std::ofstream * log_transaction_file_dcache; //[m_nb_cpu]
	393	std::ofstream log_transaction_file_cmd;
	394	std::ofstream log_transaction_file_tgt;
	395	std::ofstream log_transaction_file_cleanup;
[134]	396	#endif
	397
[2]	398	// Activity counters
[140]	399	uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ
	400	uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE
	401	uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ
	402	uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE
	403
	404	uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ
	405	uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE
	406	uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ
	407	uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE
	408
	409	uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache)
	410	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache)
	411	uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets
	412	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets
	413	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets
	414	uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
	415	uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
	416
	417	uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen
	418	uint32_t m_cpt_total_cycles; // total number of cycles
	419
	420	uint32_t m_cpt_data_read; // number of data read
	421	uint32_t m_cpt_data_read_miss; // number of data read miss
	422	uint32_t m_cpt_data_read_uncached; // number of data read uncached
	423	uint32_t m_cpt_data_write; // number of data write
	424	uint32_t m_cpt_data_write_miss; // number of data write miss
	425	uint32_t m_cpt_data_write_uncached; // number of data write uncached
	426	uint32_t m_cpt_ins_miss; // * number of instruction miss
	427
	428	uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer
	429	uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss
	430	uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read
	431	uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss
	432
	433	uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions
	434	uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions
	435	uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions
	436	uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions
	437
	438	uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions
	439	uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions
	440	uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions
	441	uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions
	442	uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions
[2]	443
[140]	444	uint32_t * m_cpt_icache_access; //[m_nb_icache]
	445	uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
[2]	446
[140]	447	uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache]
	448	uint32_t ** m_cpt_fsm_icache; //[m_nb_icache]
	449	uint32_t * m_cpt_fsm_cmd;
	450	uint32_t * m_cpt_fsm_rsp;
	451	uint32_t * m_cpt_fsm_tgt;
	452	uint32_t * m_cpt_fsm_cleanup;
[2]	453
[140]	454	// Non blocking multi-cache
	455	typename iss_t::InstructionRequest * ireq ; //[m_nb_icache]
	456	typename iss_t::InstructionResponse * irsp ; //[m_nb_icache]
	457	bool * ireq_cached ; //[m_nb_icache]
	458	uint32_t * ireq_num_cpu; //[m_nb_dcache]
	459	typename iss_t::DataRequest * dreq ; //[m_nb_dcache]
	460	typename iss_t::DataResponse * drsp ; //[m_nb_dcache]
	461	bool * dreq_cached ; //[m_nb_dcache]
	462	uint32_t * dreq_num_cpu; //[m_nb_dcache]
[2]	463
[140]	464	const uint32_t m_num_cache_LSB;
	465	const uint32_t m_num_cache_MSB;
	466	addr_40 m_num_cache_LSB_mask;
	467	addr_40 m_num_cache_mask;
[2]	468
	469	protected:
	470	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
	471
	472	public:
	473
	474	VciCcXCacheWrapperV4(
	475	sc_module_name insname,
	476	int proc_id,
	477	const soclib::common::MappingTable &mtp,
	478	const soclib::common::MappingTable &mtc,
	479	const soclib::common::IntTab &initiator_index_rw,
	480	const soclib::common::IntTab &initiator_index_c,
	481	const soclib::common::IntTab &target_index,
[140]	482	size_t nb_cpu,
	483	size_t nb_cache,
[2]	484	size_t icache_ways,
	485	size_t icache_sets,
	486	size_t icache_words,
	487	size_t dcache_ways,
	488	size_t dcache_sets,
[134]	489	size_t dcache_words,
	490	size_t wbuf_nwords,
	491	size_t wbuf_nlines,
	492	size_t wbuf_timeout
	493	);
[2]	494
	495	~VciCcXCacheWrapperV4();
	496
[118]	497	void print_trace(size_t mode = 0);
[2]	498	void print_cpi();
	499	void print_stats();
	500
[134]	501	// #if CC_XCACHE_WRAPPER_STOP_SIMULATION
	502	void stop_simulation (uint32_t);
	503	// #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
	504
[2]	505	private:
	506
	507	void transition();
	508	void genMoore();
	509
[140]	510	uint32_t get_num_cache (addr_40 & addr);
	511	uint32_t get_num_cache_only(addr_40 addr);
	512	void set_num_cache (addr_40 & addr, uint32_t num_cache);
	513	addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache);
	514
	515	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
[2]	516	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
	517	};
	518
	519	}}
	520
	521	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
	522
	523	// Local Variables:
	524	// tab-width: 4
	525	// c-basic-offset: 4
	526	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	527	// indent-tabs-mode: nil
	528	// End:
	529
	530	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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