Changeset 143 for trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h

Timestamp:

Mar 28, 2011, 6:46:33 PM (13 years ago)

Author:

kane

Message:

fix bug in ccxcachev4, save cpu_info in memcachev4

File:

• trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (modified) (8 diffs)

trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h

@@ -43 +43 @@
 
 /*
- * CC_XCACHE_WRAPPER_SELECT_VICTIM :
- *   The selection and the update of cache (after a read miss)
- *   are separated in two step
- *   Also, the cleanup can be send in parallel at the read miss.
- *
  * CC_XCACHE_WRAPPER_FIFO_RSP
  *   Two simple fifo (each 2x32 depth) receive the cache line from
  *   RAM. Instead of two buffers (m_icache_words and m_dcache_words)
+ *    1     - nb_icache+nb_dcache simple fifo
+ *    2     - 2 simple fifo
+ *    else  - two buffers  (m_icache_words and m_dcache_words)
  *   
  * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
@@ -67 +65 @@
  * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
  *   Write buffer access is conditionnal with dcache_miss_req and icache_miss_req
- *     1    - two access authorized
- *     2    - one access with static priority (dcache prior)
- *     3    - one access with static priority (icache prior)
- *     4    - one access with round robin priority
+ *     1    - one access with static priority (dcache prior)
+ *     2    - one access with static priority (icache prior)
+ *     3    - one access with round robin priority
+ *     4    - two access authorized
  * 
  * CC_XCACHE_WRAPPER_MULTI_CACHE :
@@ -95 +93 @@
 
 // implementation
-#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM
-#define CC_XCACHE_WRAPPER_SELECT_VICTIM               1
-#endif
 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP
 #define CC_XCACHE_WRAPPER_FIFO_RSP                    1
@@ -111 +106 @@
 #endif
 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
-#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY            4
+#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY            3
 #endif  
 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
 #define CC_XCACHE_WRAPPER_MULTI_CACHE                 2
-#endif  
+// if multi_cache : 
+// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
+// <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h          : CC_XCACHE_MULTI_CACHE 1
+#endif
+  
 // debugging
+#ifndef CC_XCACHE_WRAPPER_VERBOSE
+#define CC_XCACHE_WRAPPER_VERBOSE                     1
+#endif
 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
 #define CC_XCACHE_WRAPPER_STOP_SIMULATION             1
@@ -124 +126 @@
 #endif
 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
-#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN             949900
+#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN             1500
 #endif
 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
@@ -158 +160 @@
         DCACHE_IDLE,
         DCACHE_WRITE_UPDT,
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
         DCACHE_MISS_VICTIM,
-#endif
         DCACHE_MISS_WAIT,
         DCACHE_MISS_UPDT,
@@ -176 +176 @@
     enum icache_fsm_state_e {
         ICACHE_IDLE,
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
         ICACHE_MISS_VICTIM,
-#endif
         ICACHE_MISS_WAIT,
         ICACHE_MISS_UPDT,
@@ -341 +339 @@
     sc_signal<bool>       * r_vci_rsp_data_error; //[m_nb_dcache]
 
-#if CC_XCACHE_WRAPPER_FIFO_RSP
+#if   (CC_XCACHE_WRAPPER_FIFO_RSP==1)
     std::queue<data_t>    * r_icache_miss_buf;    //[m_nb_icache]
     std::queue<data_t>    * r_dcache_miss_buf;    //[m_nb_dcache]
+#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2)
+    typedef struct 
+    {
+        data_t   data;
+        uint32_t num_cache;
+    } miss_buf_t;
+
+    std::queue<miss_buf_t>  r_icache_miss_buf;
+    std::queue<miss_buf_t>  r_dcache_miss_buf;
 #else
     bool                 ** r_icache_miss_val;    //[m_nb_icache][m_icache_words]