[1044] | 1 | #!/usr/bin/env python |
---|
| 2 | |
---|
[1045] | 3 | from arch_classes import * |
---|
[1044] | 4 | |
---|
| 5 | ######################################################################################### |
---|
[1045] | 6 | # file : arch_info.py for the tsar_generic_iob architecture) |
---|
| 7 | # date : august 2016 |
---|
[1044] | 8 | # author : Alain Greiner |
---|
| 9 | ######################################################################################### |
---|
| 10 | # This python script defines a specific instance of "tsar_generic_iob" architecture |
---|
[1053] | 11 | # for the ALMOS-MKH operating system. It is used to generate the "hard_config.h" file, |
---|
| 12 | # used to configure the hardware architecture, and the "arch_info.bin" file, used by |
---|
| 13 | # the ALMOS-MK bootloader. |
---|
[1044] | 14 | # |
---|
[1045] | 15 | # The constructor prototype format is imposed by the genarch.py application, |
---|
| 16 | # and should not be modified. |
---|
| 17 | # |
---|
[1044] | 18 | # The "tsar_generic_iob" architecture includes 7 external peripherals, accessed |
---|
| 19 | # through an IOB components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. |
---|
| 20 | # Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC. |
---|
| 21 | # All clusters contain (nb_cores) processors, one L2 cache, one XCU, and |
---|
| 22 | # one optional hardware coprocessor connected to a MWMR controller. |
---|
| 23 | # |
---|
[1045] | 24 | # As the "tsar_generic_iob" architecture is generic, the following parameters |
---|
| 25 | # are defined as constructor arguments and can be redefined in the Makefile when |
---|
| 26 | # a new kernel image is generated : |
---|
[1044] | 27 | # - x_size : number of clusters in a row (from 1 to 16) |
---|
| 28 | # - y_size : number of clusters in a column (from & to 16) |
---|
| 29 | # - nb_cores : number of processors per cluster (from 1 to 4) |
---|
| 30 | # - nb_ttys : number of TTY channels (can be from 1 to 8) |
---|
[1045] | 31 | # - nb_nics : number of NIC channels (from 1 to 2) |
---|
[1044] | 32 | # - fbf_width : frame_buffer width = frame_buffer heigth |
---|
| 33 | # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' |
---|
| 34 | # |
---|
| 35 | # The following parameters are imposed by the "tsar_generic_iob" architecture: |
---|
| 36 | # - devices_max : max number of devices per cluster |
---|
| 37 | # - x_width : number of bits for x coordinate |
---|
| 38 | # - y_width : number of bits for y coordinate |
---|
| 39 | # - paddr_width : number of bits for physical address |
---|
[1045] | 40 | # - p_width : number of bits for local processor index |
---|
[1044] | 41 | # - irqs_per_core : number of input IRQs per processor |
---|
[1053] | 42 | # - io_cxy : IO cluster identifier |
---|
| 43 | # - boot_cxy : boot cluster identifier |
---|
| 44 | # - cache_line : number of bytes in cache line (in 16,32,64) |
---|
[1044] | 45 | ######################################################################################## |
---|
| 46 | |
---|
| 47 | ############################ |
---|
| 48 | def arch( x_size = 2, |
---|
| 49 | y_size = 2, |
---|
| 50 | nb_cores = 2, |
---|
| 51 | nb_ttys = 1, |
---|
[1045] | 52 | nb_nics = 1, |
---|
[1044] | 53 | fbf_width = 128, |
---|
[1053] | 54 | ioc_type = 'IOC_BDV'): |
---|
[1044] | 55 | |
---|
| 56 | ### architecture constants |
---|
| 57 | |
---|
| 58 | p_width = 2 |
---|
| 59 | x_width = 4 |
---|
| 60 | y_width = 4 |
---|
| 61 | paddr_width = 40 |
---|
| 62 | irqs_per_core = 4 |
---|
| 63 | devices_max = 16 |
---|
[1053] | 64 | boot_cxy = 0 |
---|
| 65 | cache_line = 64 |
---|
| 66 | io_cxy = ((x_size-1)<<y_width) + (y_size-1) # upper right cluster |
---|
[1044] | 67 | |
---|
| 68 | ### constructor parameters checking |
---|
| 69 | |
---|
| 70 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
---|
| 71 | or (x_size == 8) or (x_size == 16) ) |
---|
| 72 | |
---|
| 73 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
---|
| 74 | or (y_size == 8) or (y_size == 16) ) |
---|
| 75 | |
---|
| 76 | assert( nb_cores <= 4 ) |
---|
| 77 | |
---|
| 78 | assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) |
---|
| 79 | |
---|
| 80 | assert( (nb_nics >= 1) and (nb_nics <= 2) ) |
---|
| 81 | |
---|
| 82 | assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) |
---|
| 83 | |
---|
| 84 | assert( (io_cxy == 0) or (io_cxy == ((x_size-1)<<y_width) + (y_size-1)) ) |
---|
| 85 | |
---|
| 86 | assert( ((boot_cxy >> y_width) < x_size) and ((boot_cxy & ((1<<y_width)-1)) < y_size) ) |
---|
[1050] | 87 | |
---|
| 88 | assert( (cache_line == 16) or (cache_line == 32) or (cache_line == 64) ) |
---|
[1044] | 89 | |
---|
| 90 | ### define platform name |
---|
| 91 | |
---|
| 92 | platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_cores ) |
---|
| 93 | |
---|
| 94 | ### define physical segments replicated in all clusters |
---|
| 95 | |
---|
| 96 | ram_base = 0x0000000000 |
---|
[1050] | 97 | ram_size = 0x800000 # 8 Mbytes |
---|
[1044] | 98 | |
---|
| 99 | xcu_base = 0x00B0000000 |
---|
| 100 | xcu_size = 0x1000 # 4 Kbytes |
---|
| 101 | |
---|
[1051] | 102 | dma_base = 0x00B1000000 |
---|
| 103 | dma_size = 0x1000 # 4 Kbytes |
---|
[1044] | 104 | |
---|
| 105 | mmc_base = 0x00B2000000 |
---|
| 106 | mmc_size = 0x1000 # 4 Kbytes |
---|
| 107 | |
---|
| 108 | ### define physical segments for external peripherals |
---|
| 109 | ## These segments are only defined in cluster_io |
---|
| 110 | |
---|
| 111 | ioc_base = 0x00B3000000 |
---|
| 112 | ioc_size = 0x1000 # 4 Kbytes |
---|
| 113 | |
---|
| 114 | tty_base = 0x00B4000000 |
---|
| 115 | tty_size = 0x4000 # 16 Kbytes |
---|
| 116 | |
---|
| 117 | nic_base = 0x00B5000000 |
---|
[1050] | 118 | nic_size = 0x4000 # 16 kbytes |
---|
[1044] | 119 | |
---|
| 120 | fbf_base = 0x00B7000000 |
---|
| 121 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
---|
| 122 | |
---|
| 123 | pic_base = 0x00B8000000 |
---|
| 124 | pic_size = 0x1000 # 4 Kbytes |
---|
| 125 | |
---|
| 126 | iob_base = 0x00BE000000 |
---|
| 127 | iob_size = 0x1000 # 4 bytes |
---|
| 128 | |
---|
| 129 | rom_base = 0x00BFC00000 |
---|
| 130 | rom_size = 0x4000 # 16 Kbytes |
---|
| 131 | |
---|
| 132 | ############################ |
---|
| 133 | ### call Header constructor |
---|
| 134 | ############################ |
---|
| 135 | |
---|
[1045] | 136 | archi = Archinfo( name = platform_name, |
---|
| 137 | x_size = x_size, |
---|
| 138 | y_size = y_size, |
---|
| 139 | cores_max = nb_cores, |
---|
| 140 | devices_max = devices_max, |
---|
| 141 | paddr_width = paddr_width, |
---|
| 142 | x_width = x_width, |
---|
| 143 | y_width = y_width, |
---|
| 144 | irqs_per_core = irqs_per_core, |
---|
| 145 | io_cxy = io_cxy, |
---|
| 146 | boot_cxy = boot_cxy, |
---|
[1050] | 147 | cache_line = cache_line, |
---|
[1046] | 148 | reset_address = rom_base, |
---|
| 149 | p_width = p_width ) |
---|
[1044] | 150 | |
---|
[1045] | 151 | #################################################### |
---|
| 152 | ### construct hardware components for each cluster |
---|
| 153 | #################################################### |
---|
[1044] | 154 | |
---|
| 155 | for x in xrange( x_size ): |
---|
| 156 | for y in xrange( y_size ): |
---|
[1045] | 157 | cxy = (x << y_width) + y; |
---|
| 158 | offset = cxy << (paddr_width - x_width - y_width) |
---|
[1044] | 159 | |
---|
[1050] | 160 | # define internal devices |
---|
| 161 | ram = archi.addDevice( ptype = 'RAM_SCL' , |
---|
[1044] | 162 | base = ram_base + offset, |
---|
| 163 | size = ram_size ) |
---|
| 164 | |
---|
[1050] | 165 | xcu = archi.addDevice( ptype = 'ICU_XCU', |
---|
[1044] | 166 | base = xcu_base + offset, |
---|
| 167 | size = xcu_size, |
---|
[1050] | 168 | channels = 1, |
---|
[1051] | 169 | arg0 = 16, # number of HWIs |
---|
| 170 | arg1 = 16, # number of WTIs |
---|
| 171 | arg2 = 16, # number of PTIs |
---|
| 172 | arg3 = 16 ) # number of output IRQs |
---|
[1044] | 173 | |
---|
[1050] | 174 | mmc = archi.addDevice( ptype = 'MMC_TSR', |
---|
[1044] | 175 | base = mmc_base + offset, |
---|
| 176 | size = mmc_size ) |
---|
| 177 | |
---|
[1050] | 178 | archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc ) |
---|
| 179 | |
---|
[1051] | 180 | dma = archi.addDevice( ptype = 'DMA_SCL', |
---|
| 181 | base = dma_base + offset, |
---|
| 182 | size = dma_size, |
---|
| 183 | channels = nb_cores ) |
---|
[1044] | 184 | |
---|
[1053] | 185 | for i in xrange( nb_cores ): |
---|
| 186 | archi.addIrq( dstdev = xcu, port = i+1 , srcdev = dma, channel = i ) |
---|
[1044] | 187 | |
---|
[1050] | 188 | # define external devices |
---|
[1045] | 189 | if( cxy == io_cxy ): |
---|
[1044] | 190 | |
---|
[1051] | 191 | pic = archi.addDevice( ptype ='PIC_TSR', |
---|
| 192 | base = pic_base + offset, |
---|
| 193 | size = pic_size, |
---|
| 194 | arg0 = 32 ) # number of input IRQs |
---|
| 195 | |
---|
[1050] | 196 | iob = archi.addDevice( ptype = 'IOB_TSR', |
---|
[1045] | 197 | base = iob_base + offset, |
---|
| 198 | size = iob_size ) |
---|
[1044] | 199 | |
---|
[1045] | 200 | ioc = archi.addDevice( ptype = ioc_type, |
---|
| 201 | base = ioc_base + offset, |
---|
| 202 | size = ioc_size ) |
---|
[1044] | 203 | |
---|
[1050] | 204 | tty = archi.addDevice( ptype = 'TXT_TTY', |
---|
[1045] | 205 | base = tty_base + offset, |
---|
| 206 | size = tty_size, |
---|
| 207 | channels = nb_ttys ) |
---|
[1044] | 208 | |
---|
[1050] | 209 | nic = archi.addDevice( ptype = 'NIC_CBF', |
---|
[1045] | 210 | base = nic_base + offset, |
---|
| 211 | size = nic_size, |
---|
| 212 | channels = nb_nics ) |
---|
[1044] | 213 | |
---|
[1050] | 214 | fbf = archi.addDevice( ptype = 'FBF_SCL', |
---|
[1045] | 215 | base = fbf_base + offset, |
---|
| 216 | size = fbf_size, |
---|
| 217 | arg0 = fbf_width, |
---|
| 218 | arg1 = fbf_width ) |
---|
[1044] | 219 | |
---|
[1050] | 220 | rom = archi.addDevice( ptype = 'ROM_SCL', |
---|
[1045] | 221 | base = rom_base + offset, |
---|
| 222 | size = rom_size ) |
---|
[1044] | 223 | |
---|
[1055] | 224 | # we describe the largest config : (nb_nics = 4) & (nb_ttys = 8) |
---|
[1050] | 225 | archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True ) |
---|
| 226 | archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, channel = 1 , is_rx = True ) |
---|
| 227 | archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, channel = 2 , is_rx = True ) |
---|
| 228 | archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, channel = 3 , is_rx = True ) |
---|
[1044] | 229 | |
---|
[1050] | 230 | archi.addIrq( dstdev = pic, port = 4 , srcdev = nic, channel = 0 , is_rx = False ) |
---|
| 231 | archi.addIrq( dstdev = pic, port = 5 , srcdev = nic, channel = 1 , is_rx = False ) |
---|
| 232 | archi.addIrq( dstdev = pic, port = 6 , srcdev = nic, channel = 2 , is_rx = False ) |
---|
| 233 | archi.addIrq( dstdev = pic, port = 7 , srcdev = nic, channel = 3 , is_rx = False ) |
---|
[1044] | 234 | |
---|
[1050] | 235 | archi.addIrq( dstdev = pic, port = 12, srcdev = ioc ) |
---|
| 236 | |
---|
| 237 | archi.addIrq( dstdev = pic, port = 16, srcdev = tty, channel = 0 , is_rx = True ) |
---|
| 238 | archi.addIrq( dstdev = pic, port = 17, srcdev = tty, channel = 1 , is_rx = True ) |
---|
| 239 | archi.addIrq( dstdev = pic, port = 18, srcdev = tty, channel = 2 , is_rx = True ) |
---|
| 240 | archi.addIrq( dstdev = pic, port = 19, srcdev = tty, channel = 3 , is_rx = True ) |
---|
| 241 | archi.addIrq( dstdev = pic, port = 20, srcdev = tty, channel = 4 , is_rx = True ) |
---|
| 242 | archi.addIrq( dstdev = pic, port = 21, srcdev = tty, channel = 5 , is_rx = True ) |
---|
| 243 | archi.addIrq( dstdev = pic, port = 22, srcdev = tty, channel = 6 , is_rx = True ) |
---|
| 244 | archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True ) |
---|
| 245 | |
---|
[1053] | 246 | archi.addIrq( dstdev = pic, port = 24, srcdev = tty, channel = 0 , is_rx = False ) |
---|
| 247 | archi.addIrq( dstdev = pic, port = 25, srcdev = tty, channel = 1 , is_rx = False ) |
---|
| 248 | archi.addIrq( dstdev = pic, port = 26, srcdev = tty, channel = 2 , is_rx = False ) |
---|
| 249 | archi.addIrq( dstdev = pic, port = 27, srcdev = tty, channel = 3 , is_rx = False ) |
---|
| 250 | archi.addIrq( dstdev = pic, port = 28, srcdev = tty, channel = 4 , is_rx = False ) |
---|
| 251 | archi.addIrq( dstdev = pic, port = 29, srcdev = tty, channel = 5 , is_rx = False ) |
---|
| 252 | archi.addIrq( dstdev = pic, port = 30, srcdev = tty, channel = 6 , is_rx = False ) |
---|
| 253 | archi.addIrq( dstdev = pic, port = 31, srcdev = tty, channel = 7 , is_rx = False ) |
---|
| 254 | |
---|
[1050] | 255 | # define cores |
---|
[1045] | 256 | for p in xrange ( nb_cores ): |
---|
[1050] | 257 | core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware id |
---|
| 258 | (x<<y_width) + y, # cluster |
---|
[1045] | 259 | p ) # local index |
---|
[1044] | 260 | |
---|
| 261 | return archi |
---|
| 262 | |
---|
| 263 | ################################# platform test #################################### |
---|
| 264 | |
---|
| 265 | if __name__ == '__main__': |
---|
| 266 | |
---|
| 267 | archi = arch() |
---|
| 268 | |
---|
| 269 | print archi.xml() |
---|
| 270 | |
---|
| 271 | |
---|
| 272 | # Local Variables: |
---|
| 273 | # tab-width: 4; |
---|
| 274 | # c-basic-offset: 4; |
---|
| 275 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
---|
| 276 | # indent-tabs-mode: nil; |
---|
| 277 | # End: |
---|
| 278 | # |
---|
| 279 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 280 | |
---|