Changeset 1050 for trunk/platforms/tsar_generic_iob/arch_info.py
- Timestamp:
- Apr 6, 2017, 5:01:31 PM (7 years ago)
- File:
-
- 1 edited
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trunk/platforms/tsar_generic_iob/arch_info.py (modified) (14 diffs)
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trunk/platforms/tsar_generic_iob/arch_info.py
r1046 r1050 29 29 # - nb_ttys : number of TTY channels (can be from 1 to 8) 30 30 # - nb_nics : number of NIC channels (from 1 to 2) 31 # - nb_cmas : number of CMA channels (from 1 to 4)32 31 # - fbf_width : frame_buffer width = frame_buffer heigth 33 32 # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' … … 35 34 # - io_cxy : IO cluster identifier 36 35 # - boot_cxy : boot cluster identifier 36 # - cache_line : number of bytes in cache line (in 16,32,64) 37 37 # 38 38 # The following parameters are imposed by the "tsar_generic_iob" architecture: … … 51 51 nb_ttys = 1, 52 52 nb_nics = 1, 53 nb_cmas = 2,54 53 fbf_width = 128, 55 54 ioc_type = 'IOC_BDV', 56 55 mwr_type = 'MWR_CPY', 57 56 io_cxy = 0, 58 boot_cxy = 0 ): 57 boot_cxy = 0, 58 cache_line = 64): 59 59 60 60 ### architecture constants … … 81 81 assert( (nb_nics >= 1) and (nb_nics <= 2) ) 82 82 83 assert( (nb_cmas >= 1) and (nb_cmas <= 4) )84 85 83 assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) 86 84 … … 90 88 91 89 assert( ((boot_cxy >> y_width) < x_size) and ((boot_cxy & ((1<<y_width)-1)) < y_size) ) 90 91 assert( (cache_line == 16) or (cache_line == 32) or (cache_line == 64) ) 92 92 93 93 ### define platform name … … 98 98 99 99 ram_base = 0x0000000000 100 ram_size = 0x 4000000 # 64Mbytes100 ram_size = 0x800000 # 8 Mbytes 101 101 102 102 xcu_base = 0x00B0000000 … … 119 119 120 120 nic_base = 0x00B5000000 121 nic_size = 0x80000 # 512 kbytes 122 123 cma_base = 0x00B6000000 124 cma_size = 0x1000 * nb_cmas # 4 kbytes * nb_cmas 121 nic_size = 0x4000 # 16 kbytes 125 122 126 123 fbf_base = 0x00B7000000 … … 151 148 io_cxy = io_cxy, 152 149 boot_cxy = boot_cxy, 150 cache_line = cache_line, 153 151 reset_address = rom_base, 154 152 p_width = p_width ) … … 163 161 offset = cxy << (paddr_width - x_width - y_width) 164 162 165 # builddevices166 ram = archi.addDevice( ptype = 'RAM ' ,163 # define internal devices 164 ram = archi.addDevice( ptype = 'RAM_SCL' , 167 165 base = ram_base + offset, 168 166 size = ram_size ) 169 167 170 xcu = archi.addDevice( ptype = ' XCU',168 xcu = archi.addDevice( ptype = 'ICU_XCU', 171 169 base = xcu_base + offset, 172 170 size = xcu_size, 173 channels = nb_cores * irqs_per_core,171 channels = 1, 174 172 arg0 = 16, 175 173 arg1 = 16, 176 arg2 = 16 ) 177 178 mmc = archi.addDevice( ptype = 'MMC', 174 arg2 = 16, 175 arg3 = 16 ) 176 177 mmc = archi.addDevice( ptype = 'MMC_TSR', 179 178 base = mmc_base + offset, 180 179 size = mmc_size ) 181 archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc, isrtype = 'ISR_MMC' ) 180 181 archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc ) 182 182 183 183 if ( mwr_type == 'MWR_GCD' ): … … 189 189 arg2 = 1, 190 190 arg3 = 0 ) 191 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr , isrtype = 'ISR_MWR')191 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 192 192 193 193 if ( mwr_type == 'MWR_DCT' ): … … 199 199 arg2 = 1, 200 200 arg3 = 0 ) 201 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr , isrtype = 'ISR_MWR')201 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 202 202 203 203 if ( mwr_type == 'MWR_CPY' ): … … 209 209 arg2 = 1, 210 210 arg3 = 0 ) 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) 212 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr ) 212 213 # define external devices 213 214 if( cxy == io_cxy ): 214 215 215 iob = archi.addDevice( ptype = 'IOB ',216 iob = archi.addDevice( ptype = 'IOB_TSR', 216 217 base = iob_base + offset, 217 218 size = iob_size ) … … 221 222 size = ioc_size ) 222 223 223 tty = archi.addDevice( ptype = 'T TY',224 tty = archi.addDevice( ptype = 'TXT_TTY', 224 225 base = tty_base + offset, 225 226 size = tty_size, 226 227 channels = nb_ttys ) 227 228 228 nic = archi.addDevice( ptype = 'NIC ',229 nic = archi.addDevice( ptype = 'NIC_CBF', 229 230 base = nic_base + offset, 230 231 size = nic_size, 231 232 channels = nb_nics ) 232 233 233 cma = archi.addDevice( ptype = 'CMA', 234 base = cma_base + offset, 235 size = cma_size, 236 channels = nb_cmas ) 237 238 fbf = archi.addDevice( ptype = 'FBF', 234 fbf = archi.addDevice( ptype = 'FBF_SCL', 239 235 base = fbf_base + offset, 240 236 size = fbf_size, … … 242 238 arg1 = fbf_width ) 243 239 244 rom = archi.addDevice( ptype = 'ROM ',240 rom = archi.addDevice( ptype = 'ROM_SCL', 245 241 base = rom_base + offset, 246 242 size = rom_size ) 247 243 248 pic = archi.addDevice( ptype ='PIC ',244 pic = archi.addDevice( ptype ='PIC_TSR', 249 245 base = pic_base + offset, 250 246 size = pic_size, 251 247 arg0 = 32 ) 252 248 253 if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' 254 elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' 255 elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' 256 elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' 257 else : isr_ioc = 'ISR_DEFAULT' 258 259 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) 260 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) 261 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) 262 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) 263 archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) 264 archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) 265 archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) 266 archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) 267 archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) 268 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) 269 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) 270 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) 271 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) 272 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) 273 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) 274 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) 275 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) 276 277 # build cores 249 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True ) 250 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, channel = 1 , is_rx = True ) 251 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, channel = 2 , is_rx = True ) 252 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, channel = 3 , is_rx = True ) 253 254 archi.addIrq( dstdev = pic, port = 4 , srcdev = nic, channel = 0 , is_rx = False ) 255 archi.addIrq( dstdev = pic, port = 5 , srcdev = nic, channel = 1 , is_rx = False ) 256 archi.addIrq( dstdev = pic, port = 6 , srcdev = nic, channel = 2 , is_rx = False ) 257 archi.addIrq( dstdev = pic, port = 7 , srcdev = nic, channel = 3 , is_rx = False ) 258 259 archi.addIrq( dstdev = pic, port = 12, srcdev = ioc ) 260 261 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, channel = 0 , is_rx = True ) 262 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, channel = 1 , is_rx = True ) 263 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, channel = 2 , is_rx = True ) 264 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, channel = 3 , is_rx = True ) 265 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, channel = 4 , is_rx = True ) 266 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, channel = 5 , is_rx = True ) 267 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, channel = 6 , is_rx = True ) 268 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True ) 269 270 # define cores 278 271 for p in xrange ( nb_cores ): 279 core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware id entifier280 (x<<y_width) + y, # cluster identifier272 core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware id 273 (x<<y_width) + y, # cluster 281 274 p ) # local index 282 275
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