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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 1030

Last change on this file since 1030 was 1030, checked in by alain, 8 years ago

Fix a bug in debug_procid_id definition.
-This line, and those below, will be ignored--

M tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
M tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
M tsar_generic_iob/top.cpp

File size: 42.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define MWR_COPROC_CPY 0
18	#define MWR_COPROC_DCT 1
19	#define MWR_COPROC_GCD 2
20
21	#define tmpl(x) \
22	template<typename vci_param_int , typename vci_param_ext,\
23	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
24	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
25	x TsarIobCluster<\
26	vci_param_int , vci_param_ext,\
27	dspin_int_cmd_width, dspin_int_rsp_width,\
28	dspin_ram_cmd_width, dspin_ram_rsp_width>
29
30	namespace soclib { namespace caba {
31
32	/////////////////////////////////////////////////////////////////////////////
33	tmpl(/**/)::TsarIobCluster(
34	/////////////////////////////////////////////////////////////////////////////
35	sc_module_name insname,
36	size_t nb_procs,
37	size_t x_id,
38	size_t y_id,
39	size_t xmax,
40	size_t ymax,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49	size_t p_width,
50
51	size_t int_memc_tgt_id, // local index
52	size_t int_xicu_tgt_id, // local index
53	size_t int_mwmr_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mwmr_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79
80	size_t coproc_type,
81
82	const Loader &loader,
83
84	uint32_t frozen_cycles,
85	bool debug_ok,
86	uint32_t debug_start_cycle,
87	uint32_t debug_proc_id,
88	uint32_t debug_memc_id,
89	bool debug_iob )
90	: soclib::caba::BaseModule(insname),
91	p_clk("clk"),
92	p_resetn("resetn")
93	{
94	assert( (x_id < xmax) and (y_id < ymax) and
95	"Error in tsar_iob_cluster : Illegal cluster coordinates");
96
97	size_t cluster_id = (x_id<<4) + y_id;
98
99	// Vectors of DSPIN ports for inter-cluster communications
100	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4);
101	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4);
102
103	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4);
104	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4);
105
106	p_dspin_int_m2p_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_m2p_in", 4);
107	p_dspin_int_m2p_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_m2p_out", 4);
108
109	p_dspin_int_p2m_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_p2m_in", 4);
110	p_dspin_int_p2m_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_p2m_out", 4);
111
112	p_dspin_int_cla_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cla_in", 4);
113	p_dspin_int_cla_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cla_out", 4);
114
115	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
116	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
117
118	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
119	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
120
121	// VCI ports from IOB to IOX network (only in IO clusters)
122	if ( is_io )
123	{
124	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
125	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
126	}
127
128	//////////////////////////////////////////////////////////////////////////////////
129	// Hardware components
130	//////////////////////////////////////////////////////////////////////////////////
131
132	size_t x_debug;
133	size_t y_debug;
134	size_t p_debug;
135
136	//////////// PROCS /////////////////////////////////////////////////////////////
137	for (size_t p = 0; p < nb_procs; p++)
138	{
139	std::ostringstream s_proc;
140	x_debug = (debug_proc_id >> (y_width + p_width)) & ((1<<x_width)-1);
141	y_debug = (debug_proc_id >> p_width ) & ((1<<y_width)-1);
142	p_debug = (debug_proc_id ) & ((1<<p_width)-1);
143
144
145	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
146	proc[p] = new VciCcVCacheWrapper<vci_param_int,
147	dspin_int_cmd_width,
148	dspin_int_rsp_width,
149	GdbServer<Mips32ElIss> >(
150	s_proc.str().c_str(),
151	(cluster_id << p_width) + p, // GLOBAL PROC_ID
152	mt_int, // Mapping Table INT network
153	IntTab(cluster_id,p), // SRCID
154	(cluster_id << l_width) + p, // CC_GLOBAL_ID
155	8, // ITLB ways
156	8, // ITLB sets
157	8, // DTLB ways
158	8, // DTLB sets
159	l1_i_ways, l1_i_sets, 16, // ICACHE size
160	l1_d_ways, l1_d_sets, 16, // DCACHE size
161	4, // WBUF nlines
162	4, // WBUF nwords
163	x_width,
164	y_width,
165	frozen_cycles, // max frozen cycles
166	debug_start_cycle,
167	debug_ok and (x_id == x_debug) and (y_id == y_debug) and (p_debug == p) );
168	}
169
170	//////////// MEMC /////////////////////////////////////////////////////////////
171	std::ostringstream s_memc;
172	s_memc << "memc_" << x_id << "_" << y_id;
173	x_debug = (debug_memc_id >> y_width) & ((1<<x_width)-1);
174	y_debug = (debug_memc_id ) & ((1<<y_width)-1);
175	memc = new VciMemCache<vci_param_int,
176	vci_param_ext,
177	dspin_int_rsp_width,
178	dspin_int_cmd_width>(
179	s_memc.str().c_str(),
180	mt_int, // Mapping Table INT network
181	mt_ram, // Mapping Table RAM network
182	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
183	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
184	x_width, // number of bits for x coordinate
185	y_width, // number of bits for y coordinate
186	memc_ways, memc_sets, 16, // CACHE SIZE
187	3, // MAX NUMBER OF COPIES
188	4096, // HEAP SIZE
189	8, // TRANSACTION TABLE DEPTH
190	8, // UPDATE TABLE DEPTH
191	8, // INVALIDATE TABLE DEPTH
192	debug_start_cycle,
193	debug_ok and (x_id == x_debug) and (y_id = y_debug) );
194
195	std::ostringstream s_wi_memc;
196	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
197	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
198	dspin_ram_cmd_width,
199	dspin_ram_rsp_width>(
200	s_wi_memc.str().c_str(),
201	x_width + y_width + l_width);
202
203	/////////// XICU //////////////////////////////////////////////////////////////
204	std::ostringstream s_xicu;
205	s_xicu << "xicu_" << x_id << "_" << y_id;
206	xicu = new VciXicu<vci_param_int>(
207	s_xicu.str().c_str(),
208	mt_int, // mapping table INT network
209	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
210	xcu_nb_pti, // number of timer IRQs
211	xcu_nb_hwi, // number of hard IRQs
212	xcu_nb_wti, // number of soft IRQs
213	xcu_nb_out); // number of output IRQs
214
215	//////////// MWMR controller and COPROC ////////////////////////////////////////
216	std::ostringstream s_mwmr;
217	std::ostringstream s_copro;
218	s_mwmr << "mwmr_" << x_id << "_" << y_id;
219
220	if ( coproc_type == MWR_COPROC_CPY)
221	{
222	s_copro << "cpy_" << x_id << "_" << y_id;
223	cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size
224
225	mwmr = new VciMwmrDma<vci_param_int>(
226	s_mwmr.str().c_str(),
227	mt_int,
228	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
229	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
230	1, // nb to_coproc ports
231	1, // nb from_coproc ports
232	1, // nb config registers
233	0, // nb status registers
234	64 ); // burst size (bytes)
235	}
236	if ( coproc_type == MWR_COPROC_DCT )
237	{
238	s_copro << "dct_" << x_id << "_" << y_id;
239	dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency
240
241	mwmr = new VciMwmrDma<vci_param_int>(
242	s_mwmr.str().c_str(),
243	mt_int,
244	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
245	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
246	1, // nb to_coproc ports
247	1, // nb from_coproc ports
248	1, // nb config registers
249	0, // nb status registers
250	64 ); // burst size (bytes)
251	}
252	if ( coproc_type == MWR_COPROC_GCD )
253	{
254	s_copro << "gcd_" << x_id << "_" << y_id;
255	gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size
256
257	mwmr = new VciMwmrDma<vci_param_int>(
258	s_mwmr.str().c_str(),
259	mt_int,
260	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
261	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
262	2, // nb to_coproc ports
263	1, // nb from_coproc ports
264	1, // nb config registers
265	0, // nb status registers
266	64 ); // burst size (bytes)
267	}
268
269	/////////// VCI INT_CMD/RSP LOCAL_XBAR //////////////////////////////////////
270	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
271	size_t nb_direct_targets = is_io ? 4 : 3;
272
273	std::ostringstream s_int_xbar_d;
274	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
275	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
276	s_int_xbar_d.str().c_str(),
277	mt_int, // mapping table
278	cluster_id, // cluster id
279	nb_direct_initiators, // number of local initiators
280	nb_direct_targets, // number of local targets
281	0 ); // default target
282
283	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
284	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
285	<< x_id << "_" << y_id;
286	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
287	dspin_int_cmd_width,
288	dspin_int_rsp_width>(
289	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
290	x_width + y_width + l_width);
291
292	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
293	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
294	<< x_id << "_" << y_id;
295	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
296	dspin_int_cmd_width,
297	dspin_int_rsp_width>(
298	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
299	x_width + y_width + l_width);
300
301	//////////// DSPIN INT_M2P LOCAL_XBAR ////////////////////////////////////////
302	std::ostringstream s_int_xbar_m2p_c;
303	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
304	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
305	s_int_xbar_m2p_c.str().c_str(),
306	mt_int, // mapping table
307	x_id, y_id, // cluster coordinates
308	x_width, y_width, l_width, // several dests
309	1, // number of local sources
310	nb_procs, // number of local dests
311	2, 2, // fifo depths
312	true, // pseudo CMD
313	false, // no routing table
314	true ); // broacast
315
316	//////////// DSPIN INT_P2M LOCAL_XBAR ////////////////////////////////////////
317	std::ostringstream s_int_xbar_p2m_c;
318	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
319	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
320	s_int_xbar_p2m_c.str().c_str(),
321	mt_int, // mapping table
322	x_id, y_id, // cluster coordinates
323	x_width, y_width, 0, // only one dest
324	nb_procs, // number of local sources
325	1, // number of local dests
326	2, 2, // fifo depths
327	false, // pseudo RSP
328	false, // no routing table
329	false ); // no broacast
330
331	//////////// DSPIN INT_CLA LOCAL_XBAR ////////////////////////////////////////
332	std::ostringstream s_int_xbar_clack_c;
333	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
334	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
335	s_int_xbar_clack_c.str().c_str(),
336	mt_int, // mapping table
337	x_id, y_id, // cluster coordinates
338	x_width, y_width, l_width,
339	1, // number of local sources
340	nb_procs, // number of local targets
341	1, 1, // fifo depths
342	true, // CMD
343	false, // no routing table
344	false); // broadcast
345
346	//////////// DSPIN INT_CMD ROUTER ////////////////////////////////////////////
347	std::ostringstream s_int_router_cmd;
348	s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id;
349	int_router_cmd = new DspinRouter<dspin_int_cmd_width>(
350	s_int_router_cmd.str().c_str(),
351	x_id,y_id, // coordinate in the mesh
352	x_width, y_width, // x & y fields width
353	4,4); // input & output fifo depths
354
355	//////////// DSPIN INT_RSP ROUTER ////////////////////////////////////////////
356	std::ostringstream s_int_router_rsp;
357	s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id;
358	int_router_rsp = new DspinRouter<dspin_int_rsp_width>(
359	s_int_router_rsp.str().c_str(),
360	x_id,y_id, // coordinates in mesh
361	x_width, y_width, // x & y fields width
362	4,4); // input & output fifo depths
363
364	//////////// DSPIN INT_M2P ROUTER ////////////////////////////////////////////
365	std::ostringstream s_int_router_m2p;
366	s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id;
367	int_router_m2p = new DspinRouter<dspin_int_cmd_width>(
368	s_int_router_m2p.str().c_str(),
369	x_id,y_id, // coordinate in the mesh
370	x_width, y_width, // x & y fields width
371	4,4, // input & output fifo depths
372	true); // broadcast supported
373
374	//////////// DSPIN INT_P2M ROUTER ////////////////////////////////////////////
375	std::ostringstream s_int_router_p2m;
376	s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id;
377	int_router_p2m = new DspinRouter<dspin_int_rsp_width>(
378	s_int_router_p2m.str().c_str(),
379	x_id,y_id, // coordinates in mesh
380	x_width, y_width, // x & y fields width
381	4,4); // input & output fifo depths
382
383	//////////// DSPIN INT_CLA ROUTER ////////////////////////////////////////////
384	std::ostringstream s_int_router_cla;
385	s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id;
386	int_router_cla = new DspinRouter<dspin_int_cmd_width>(
387	s_int_router_cla.str().c_str(),
388	x_id,y_id, // coordinate in the mesh
389	x_width, y_width, // x & y fields width
390	4,4); // input & output fifo depths
391
392	////////////// XRAM /////////////////////////////////////////////////////////
393	std::ostringstream s_xram;
394	s_xram << "xram_" << x_id << "_" << y_id;
395	xram = new VciSimpleRam<vci_param_ext>(
396	s_xram.str().c_str(),
397	IntTab(cluster_id, ram_xram_tgt_id),
398	mt_ram,
399	loader,
400	xram_latency);
401
402	std::ostringstream s_wt_xram;
403	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
404	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
405	dspin_ram_cmd_width,
406	dspin_ram_rsp_width>(
407	s_wt_xram.str().c_str(),
408	x_width + y_width + l_width);
409
410	//////////// DSPIN RAM_CMD ROUTER ///////////////////////////////////////////
411	std::ostringstream s_ram_router_cmd;
412	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
413	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
414	s_ram_router_cmd.str().c_str(),
415	x_id, y_id, // router coordinates in mesh
416	x_width, // x field width in first flit
417	y_width, // y field width in first flit
418	4, 4); // input & output fifo depths
419
420	//////////// DSPIN RAM_RSP ROUTER ///////////////////////////////////////////
421	std::ostringstream s_ram_router_rsp;
422	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
423	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
424	s_ram_router_rsp.str().c_str(),
425	x_id, y_id, // coordinates in mesh
426	x_width, // x field width in first flit
427	y_width, // y field width in first flit
428	4, 4); // input & output fifo depths
429
430
431	////////////////////// I/O CLUSTER ONLY ///////////////////////////////////
432	if ( is_io )
433	{
434	/////////// IO_BRIDGE ////////////////////////////////////////////////////
435	std::ostringstream s_iob;
436	s_iob << "iob_" << x_id << "_" << y_id;
437	iob = new VciIoBridge<vci_param_int,
438	vci_param_ext>(
439	s_iob.str().c_str(),
440	mt_ram, // EXT network maptab
441	mt_int, // INT network maptab
442	mt_iox, // IOX network maptab
443	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
444	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
445	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
446	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
447	16, // cache line words
448	8, // IOTLB ways
449	8, // IOTLB sets
450	debug_start_cycle,
451	debug_iob );
452
453	std::ostringstream s_iob_ram_wi;
454	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
455	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
456	dspin_ram_cmd_width,
457	dspin_ram_rsp_width>(
458	s_iob_ram_wi.str().c_str(),
459	vci_param_int::S);
460
461	//////////// DSPIN RAM_CMD LOCAL_XBAR ///////////////////////////////////
462	std::ostringstream s_ram_xbar_cmd;
463	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
464	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
465	s_ram_xbar_cmd.str().c_str(), // name
466	mt_ram, // mapping table
467	x_id, y_id, // x, y
468	x_width, y_width, l_width, // x_width, y_width, l_width
469	2, 0, // local inputs, local outputs
470	2, 2, // in fifo, out fifo depths
471	true, // is cmd ?
472	false, // use routing table ?
473	false); // support broadcast ?
474
475	//////////// DSPIN RAM_RSP LOCAL_XBAR ///////////////////////////////////
476	std::ostringstream s_ram_xbar_rsp;
477	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
478	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
479	s_ram_xbar_rsp.str().c_str(), // name
480	mt_ram, // mapping table
481	x_id, y_id, // x, y
482	x_width, y_width, l_width, // x_width, y_width, l_width
483	0, 2, // local inputs, local outputs
484	2, 2, // in fifo, out fifo depths
485	false, // is cmd ?
486	true, // use routing table ?
487	false); // support broadcast ?
488
489	} // end if IO
490
491	////////////////////////////////////
492	// Connections are defined here
493	////////////////////////////////////
494
495	// on coherence network : local srcid[proc] in [0...nb_procs-1]
496	// : local srcid[memc] = nb_procs
497
498	//////////////////////////////////// Processors
499	for (size_t p = 0; p < nb_procs; p++)
500	{
501	proc[p]->p_clk (this->p_clk);
502	proc[p]->p_resetn (this->p_resetn);
503
504	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
505	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
506	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
507	proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]);
508
509	for ( size_t j = 0 ; j < 6 ; j++)
510	{
511	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
512	else proc[p]->p_irq[j] (signal_false);
513	}
514	}
515
516	std::cout << " - processors connected" << std::endl;
517
518	///////////////////////////////////// XICU
519	xicu->p_clk (this->p_clk);
520	xicu->p_resetn (this->p_resetn);
521	xicu->p_vci (signal_int_vci_tgt_xicu);
522	for ( size_t i=0 ; i < xcu_nb_out ; i++)
523	{
524	xicu->p_irq[i] (signal_proc_it[i]);
525	}
526	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
527	{
528	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
529	else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr);
530	else xicu->p_hwi[i] (signal_false);
531	}
532
533	std::cout << " - xcu connected" << std::endl;
534
535	///////////////////////////////////// MEMC
536	memc->p_clk (this->p_clk);
537	memc->p_resetn (this->p_resetn);
538	memc->p_vci_ixr (signal_ram_vci_ini_memc);
539	memc->p_vci_tgt (signal_int_vci_tgt_memc);
540	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
541	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
542	memc->p_dspin_clack (signal_int_dspin_cla_memc);
543	memc->p_irq (signal_irq_memc);
544
545	// wrapper to RAM network
546	memc_ram_wi->p_clk (this->p_clk);
547	memc_ram_wi->p_resetn (this->p_resetn);
548	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
549	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
550	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
551
552	std::cout << " - memc connected" << std::endl;
553
554	//////////////////////////////////// XRAM
555	xram->p_clk (this->p_clk);
556	xram->p_resetn (this->p_resetn);
557	xram->p_vci (signal_ram_vci_tgt_xram);
558
559	// wrapper to RAM network
560	xram_ram_wt->p_clk (this->p_clk);
561	xram_ram_wt->p_resetn (this->p_resetn);
562	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
563	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
564	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
565
566	std::cout << " - xram connected" << std::endl;
567
568	/////////////////////////////////// GCD coprocessor
569	if ( coproc_type == MWR_COPROC_GCD )
570	{
571	gcd->p_clk (this->p_clk);
572	gcd->p_resetn (this->p_resetn);
573	gcd->p_opa (signal_to_coproc[0]);
574	gcd->p_opb (signal_to_coproc[1]);
575	gcd->p_res (signal_from_coproc[0]);
576	gcd->p_config (signal_config_coproc[0]);
577
578	mwmr->p_clk (this->p_clk);
579	mwmr->p_resetn (this->p_resetn);
580	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
581	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
582	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
583	mwmr->p_to_coproc[1] (signal_to_coproc[1]);
584	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
585	mwmr->p_config[0] (signal_config_coproc[0]);
586	mwmr->p_irq (signal_irq_mwmr);
587	}
588
589	/////////////////////////////////// DCT coprocessor
590	if ( coproc_type == MWR_COPROC_DCT )
591	{
592	dct->p_clk (this->p_clk);
593	dct->p_resetn (this->p_resetn);
594	dct->p_in (signal_to_coproc[0]);
595	dct->p_out (signal_from_coproc[0]);
596	dct->p_config (signal_config_coproc[0]);
597
598	mwmr->p_clk (this->p_clk);
599	mwmr->p_resetn (this->p_resetn);
600	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
601	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
602	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
603	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
604	mwmr->p_config[0] (signal_config_coproc[0]);
605	mwmr->p_irq (signal_irq_mwmr);
606	}
607
608	std::cout << " - coproc connected" << std::endl;
609
610	/////////////////////////////////// CPY coprocessor
611	if ( coproc_type == MWR_COPROC_CPY )
612	{
613	cpy->p_clk (this->p_clk);
614	cpy->p_resetn (this->p_resetn);
615	cpy->p_load (signal_to_coproc[0]);
616	cpy->p_store (signal_from_coproc[0]);
617	cpy->p_config (signal_config_coproc[0]);
618
619	mwmr->p_clk (this->p_clk);
620	mwmr->p_resetn (this->p_resetn);
621	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
622	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
623	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
624	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
625	mwmr->p_config[0] (signal_config_coproc[0]);
626	mwmr->p_irq (signal_irq_mwmr);
627	}
628
629	//////////////////////////// RAM NETWORK ROUTERS
630	ram_router_cmd->p_clk (this->p_clk);
631	ram_router_cmd->p_resetn (this->p_resetn);
632	ram_router_rsp->p_clk (this->p_clk);
633	ram_router_rsp->p_resetn (this->p_resetn);
634
635	for( size_t n=0 ; n<4 ; n++)
636	{
637	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
638	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
639	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
640	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
641	}
642
643	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
644	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
645
646	if ( is_io )
647	{
648	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
649	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
650	}
651	else
652	{
653	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
654	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
655	}
656
657	///////////////////////////// INT NETWORK ROUTERS
658	int_router_cmd->p_clk (this->p_clk);
659	int_router_cmd->p_resetn (this->p_resetn);
660	int_router_rsp->p_clk (this->p_clk);
661	int_router_rsp->p_resetn (this->p_resetn);
662	int_router_m2p->p_clk (this->p_clk);
663	int_router_m2p->p_resetn (this->p_resetn);
664	int_router_p2m->p_clk (this->p_clk);
665	int_router_p2m->p_resetn (this->p_resetn);
666	int_router_cla->p_clk (this->p_clk);
667	int_router_cla->p_resetn (this->p_resetn);
668
669	// loop on N/S/E/W ports
670	for (size_t i = 0; i < 4; i++)
671	{
672	int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]);
673	int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]);
674
675	int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]);
676	int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]);
677
678	int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]);
679	int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]);
680
681	int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]);
682	int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]);
683
684	int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]);
685	int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]);
686	}
687
688	int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d);
689	int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d);
690
691	int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d);
692	int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d);
693
694	int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c);
695	int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c);
696
697	int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c);
698	int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c);
699
700	int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c);
701	int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c);
702
703	std::cout << " - internal routers connected" << std::endl;
704
705
706	///////////////////// CMD DSPIN local crossbar direct
707	int_xbar_d->p_clk (this->p_clk);
708	int_xbar_d->p_resetn (this->p_resetn);
709	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
710	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
711
712	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
713	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
714	int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr);
715	int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr);
716	for (size_t p = 0; p < nb_procs; p++)
717	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
718
719	if ( is_io )
720	{
721	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
722	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
723	}
724
725	int_wi_gate_d->p_clk (this->p_clk);
726	int_wi_gate_d->p_resetn (this->p_resetn);
727	int_wi_gate_d->p_vci (signal_int_vci_l2g);
728	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
729	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
730
731	int_wt_gate_d->p_clk (this->p_clk);
732	int_wt_gate_d->p_resetn (this->p_resetn);
733	int_wt_gate_d->p_vci (signal_int_vci_g2l);
734	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
735	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
736
737	////////////////////// M2P DSPIN local crossbar coherence
738	int_xbar_m2p_c->p_clk (this->p_clk);
739	int_xbar_m2p_c->p_resetn (this->p_resetn);
740	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
741	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
742	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
743	for (size_t p = 0; p < nb_procs; p++)
744	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
745
746	////////////////////////// P2M DSPIN local crossbar coherence
747	int_xbar_p2m_c->p_clk (this->p_clk);
748	int_xbar_p2m_c->p_resetn (this->p_resetn);
749	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
750	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
751	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
752	for (size_t p = 0; p < nb_procs; p++)
753	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
754
755	////////////////////// CLACK DSPIN local crossbar coherence
756	int_xbar_clack_c->p_clk (this->p_clk);
757	int_xbar_clack_c->p_resetn (this->p_resetn);
758	int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c);
759	int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c);
760	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc);
761	for (size_t p = 0; p < nb_procs; p++)
762	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]);
763
764
765	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
766	if ( is_io )
767	{
768	// IO bridge
769	iob->p_clk (this->p_clk);
770	iob->p_resetn (this->p_resetn);
771	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
772	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
773	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
774	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
775	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
776
777	// initiator wrapper to RAM network
778	iob_ram_wi->p_clk (this->p_clk);
779	iob_ram_wi->p_resetn (this->p_resetn);
780	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
781	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
782	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
783
784	// crossbar between MEMC and IOB to RAM network
785	ram_xbar_cmd->p_clk (this->p_clk);
786	ram_xbar_cmd->p_resetn (this->p_resetn);
787	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
788	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
789	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
790	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
791
792	ram_xbar_rsp->p_clk (this->p_clk);
793	ram_xbar_rsp->p_resetn (this->p_resetn);
794	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
795	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
796	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
797	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
798	}
799
800	SC_METHOD(init);
801
802	} // end constructor
803
804	tmpl(void)::init()
805	{
806	signal_ram_dspin_cmd_false.write = false;
807	signal_ram_dspin_rsp_false.read = true;
808	}
809
810	}}
811
812
813	// Local Variables:
814	// tab-width: 3
815	// c-basic-offset: 3
816	// c-file-offsets:((innamespace . 0)(inline-open . 0))
817	// indent-tabs-mode: nil
818	// End:
819
820	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
821

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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