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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 959

Last change on this file since 959 was 959, checked in by alain, 9 years ago
Fix a bug in platform tsar_generic_iob to support more than 4 processors per cluster. The hard_config.h file format has also been enriched.
File size: 32.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	//////////////////////////////////////////////////////////////////////////
33	sc_module_name insname,
34	size_t nb_procs,
35	size_t nb_dmas,
36	size_t x_id,
37	size_t y_id,
38	size_t xmax,
39	size_t ymax,
40
41	const soclib::common::MappingTable &mt_int,
42	const soclib::common::MappingTable &mt_ram,
43	const soclib::common::MappingTable &mt_iox,
44
45	size_t x_width,
46	size_t y_width,
47	size_t l_width,
48	size_t p_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_iobx_tgt_id, // local index
54
55	size_t int_proc_ini_id, // local index
56	size_t int_mdma_ini_id, // local index
57	size_t int_iobx_ini_id, // local index
58
59	size_t ram_xram_tgt_id, // local index
60	size_t ram_memc_ini_id, // local index
61	size_t ram_iobx_ini_id, // local index
62
63	bool is_io, // is IO cluster (IOB)?
64	size_t iox_iobx_tgt_id, // local_index
65	size_t iox_iobx_ini_id, // local index
66
67	size_t memc_ways,
68	size_t memc_sets,
69	size_t l1_i_ways,
70	size_t l1_i_sets,
71	size_t l1_d_ways,
72	size_t l1_d_sets,
73	size_t xram_latency,
74	size_t xcu_nb_hwi,
75	size_t xcu_nb_pti,
76	size_t xcu_nb_wti,
77	size_t xcu_nb_out,
78
79	const Loader &loader,
80
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok,
85	bool iob_debug_ok )
86	: soclib::caba::BaseModule(insname),
87	p_clk("clk"),
88	p_resetn("resetn")
89	{
90	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
91
92	size_t cluster_id = (x_id<<4) + y_id;
93
94	// Vectors of DSPIN ports for inter-cluster communications
95	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
96	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
97	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
98	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
99
100	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
101	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
102	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
103	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
104
105	// VCI ports from IOB to IOX network (only in IO clusters)
106	if ( is_io )
107	{
108	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
109	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
110	}
111
112	/////////////////////////////////////////////////////////////////////////////
113	// Hardware components
114	/////////////////////////////////////////////////////////////////////////////
115
116	//////////// PROCS
117	for (size_t p = 0; p < nb_procs; p++)
118	{
119	std::ostringstream s_proc;
120	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
121	proc[p] = new VciCcVCacheWrapper<vci_param_int,
122	dspin_int_cmd_width,
123	dspin_int_rsp_width,
124	GdbServer<Mips32ElIss> >(
125	s_proc.str().c_str(),
126	(cluster_id << p_width) + p, // GLOBAL PROC_ID
127	mt_int, // Mapping Table INT network
128	IntTab(cluster_id,p), // SRCID
129	(cluster_id << l_width) + p, // CC_GLOBAL_ID
130	8, // ITLB ways
131	8, // ITLB sets
132	8, // DTLB ways
133	8, // DTLB sets
134	l1_i_ways, l1_i_sets, 16, // ICACHE size
135	l1_d_ways, l1_d_sets, 16, // DCACHE size
136	4, // WBUF nlines
137	4, // WBUF nwords
138	x_width,
139	y_width,
140	frozen_cycles, // max frozen cycles
141	debug_start_cycle,
142	proc_debug_ok);
143	}
144
145	/////////// MEMC
146	std::ostringstream s_memc;
147	s_memc << "memc_" << x_id << "_" << y_id;
148	memc = new VciMemCache<vci_param_int,
149	vci_param_ext,
150	dspin_int_rsp_width,
151	dspin_int_cmd_width>(
152	s_memc.str().c_str(),
153	mt_int, // Mapping Table INT network
154	mt_ram, // Mapping Table RAM network
155	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
156	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
157	x_width, // number of bits for x coordinate
158	y_width, // number of bits for y coordinate
159	memc_ways, memc_sets, 16, // CACHE SIZE
160	3, // MAX NUMBER OF COPIES
161	4096, // HEAP SIZE
162	8, // TRANSACTION TABLE DEPTH
163	8, // UPDATE TABLE DEPTH
164	8, // INVALIDATE TABLE DEPTH
165	debug_start_cycle,
166	memc_debug_ok );
167
168	std::ostringstream s_wi_memc;
169	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
170	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
171	dspin_ram_cmd_width,
172	dspin_ram_rsp_width>(
173	s_wi_memc.str().c_str(),
174	x_width + y_width + l_width);
175
176	/////////// XICU
177	std::ostringstream s_xicu;
178	s_xicu << "xicu_" << x_id << "_" << y_id;
179	xicu = new VciXicu<vci_param_int>(
180	s_xicu.str().c_str(),
181	mt_int, // mapping table INT network
182	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
183	xcu_nb_pti, // number of timer IRQs
184	xcu_nb_hwi, // number of hard IRQs
185	xcu_nb_wti, // number of soft IRQs
186	xcu_nb_out); // number of output IRQs
187
188	//////////// MDMA
189	std::ostringstream s_mdma;
190	s_mdma << "mdma_" << x_id << "_" << y_id;
191	mdma = new VciMultiDma<vci_param_int>(
192	s_mdma.str().c_str(),
193	mt_int,
194	IntTab(cluster_id, nb_procs), // SRCID
195	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
196	64, // burst size
197	nb_dmas); // number of IRQs
198
199	/////////// Direct LOCAL_XBAR(S)
200	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
201	size_t nb_direct_targets = is_io ? 4 : 3;
202
203	std::ostringstream s_int_xbar_d;
204	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
205	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
206	s_int_xbar_d.str().c_str(),
207	mt_int, // mapping table
208	cluster_id, // cluster id
209	nb_direct_initiators, // number of local initiators
210	nb_direct_targets, // number of local targets
211	0 ); // default target
212
213	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
214	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
215	<< x_id << "_" << y_id;
216	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
217	dspin_int_cmd_width,
218	dspin_int_rsp_width>(
219	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
220	x_width + y_width + l_width);
221
222	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
223	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
224	<< x_id << "_" << y_id;
225	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
226	dspin_int_cmd_width,
227	dspin_int_rsp_width>(
228	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
229	x_width + y_width + l_width);
230
231	//////////// Coherence LOCAL_XBAR(S)
232	std::ostringstream s_int_xbar_m2p_c;
233	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
234	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
235	s_int_xbar_m2p_c.str().c_str(),
236	mt_int, // mapping table
237	x_id, y_id, // cluster coordinates
238	x_width, y_width, l_width, // several dests
239	1, // number of local sources
240	nb_procs, // number of local dests
241	2, 2, // fifo depths
242	true, // pseudo CMD
243	false, // no routing table
244	true ); // broacast
245
246	std::ostringstream s_int_xbar_p2m_c;
247	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
248	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
249	s_int_xbar_p2m_c.str().c_str(),
250	mt_int, // mapping table
251	x_id, y_id, // cluster coordinates
252	x_width, y_width, 0, // only one dest
253	nb_procs, // number of local sources
254	1, // number of local dests
255	2, 2, // fifo depths
256	false, // pseudo RSP
257	false, // no routing table
258	false ); // no broacast
259
260	std::ostringstream s_int_xbar_clack_c;
261	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
262	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
263	s_int_xbar_clack_c.str().c_str(),
264	mt_int, // mapping table
265	x_id, y_id, // cluster coordinates
266	x_width, y_width, l_width,
267	1, // number of local sources
268	nb_procs, // number of local targets
269	1, 1, // fifo depths
270	true, // CMD
271	false, // no routing table
272	false); // broadcast
273
274	////////////// INT ROUTER(S)
275	std::ostringstream s_int_router_cmd;
276	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
277	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
278	s_int_router_cmd.str().c_str(),
279	x_id,y_id, // coordinate in the mesh
280	x_width, y_width, // x & y fields width
281	3, // nb virtual channels
282	4,4); // input & output fifo depths
283
284	std::ostringstream s_int_router_rsp;
285	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
286	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
287	s_int_router_rsp.str().c_str(),
288	x_id,y_id, // router coordinates in mesh
289	x_width, y_width, // x & y fields width
290	2, // nb virtual channels
291	4,4); // input & output fifo depths
292
293	////////////// XRAM
294	std::ostringstream s_xram;
295	s_xram << "xram_" << x_id << "_" << y_id;
296	xram = new VciSimpleRam<vci_param_ext>(
297	s_xram.str().c_str(),
298	IntTab(cluster_id, ram_xram_tgt_id),
299	mt_ram,
300	loader,
301	xram_latency);
302
303	std::ostringstream s_wt_xram;
304	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
305	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
306	dspin_ram_cmd_width,
307	dspin_ram_rsp_width>(
308	s_wt_xram.str().c_str(),
309	x_width + y_width + l_width);
310
311	///////////// RAM ROUTER(S)
312	std::ostringstream s_ram_router_cmd;
313	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
314	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
315	s_ram_router_cmd.str().c_str(),
316	x_id, y_id, // router coordinates in mesh
317	x_width, // x field width in first flit
318	y_width, // y field width in first flit
319	4, 4); // input & output fifo depths
320
321	std::ostringstream s_ram_router_rsp;
322	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
323	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
324	s_ram_router_rsp.str().c_str(),
325	x_id, y_id, // coordinates in mesh
326	x_width, // x field width in first flit
327	y_width, // y field width in first flit
328	4, 4); // input & output fifo depths
329
330
331	////////////////////// I/O CLUSTER ONLY ///////////////////////
332	if ( is_io )
333	{
334	/////////// IO_BRIDGE
335	std::ostringstream s_iob;
336	s_iob << "iob_" << x_id << "_" << y_id;
337	iob = new VciIoBridge<vci_param_int,
338	vci_param_ext>(
339	s_iob.str().c_str(),
340	mt_ram, // EXT network maptab
341	mt_int, // INT network maptab
342	mt_iox, // IOX network maptab
343	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
344	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
345	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
346	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
347	16, // cache line words
348	8, // IOTLB ways
349	8, // IOTLB sets
350	debug_start_cycle,
351	iob_debug_ok );
352
353	std::ostringstream s_iob_ram_wi;
354	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
355	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
356	dspin_ram_cmd_width,
357	dspin_ram_rsp_width>(
358	s_iob_ram_wi.str().c_str(),
359	vci_param_int::S);
360
361	std::ostringstream s_ram_xbar_cmd;
362	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
363	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
364	s_ram_xbar_cmd.str().c_str(), // name
365	mt_ram, // mapping table
366	x_id, y_id, // x, y
367	x_width, y_width, l_width, // x_width, y_width, l_width
368	2, 0, // local inputs, local outputs
369	2, 2, // in fifo, out fifo depths
370	true, // is cmd ?
371	false, // use routing table ?
372	false); // support broadcast ?
373
374	std::ostringstream s_ram_xbar_rsp;
375	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
376	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
377	s_ram_xbar_rsp.str().c_str(), // name
378	mt_ram, // mapping table
379	x_id, y_id, // x, y
380	x_width, y_width, l_width, // x_width, y_width, l_width
381	0, 2, // local inputs, local outputs
382	2, 2, // in fifo, out fifo depths
383	false, // is cmd ?
384	true, // use routing table ?
385	false); // support broadcast ?
386	} // end if IO
387
388	////////////////////////////////////
389	// Connections are defined here
390	////////////////////////////////////
391
392	// on coherence network : local srcid[proc] in [0...nb_procs-1]
393	// : local srcid[memc] = nb_procs
394
395	//////////////////////// internal CMD & RSP routers
396	int_router_cmd->p_clk (this->p_clk);
397	int_router_cmd->p_resetn (this->p_resetn);
398	int_router_rsp->p_clk (this->p_clk);
399	int_router_rsp->p_resetn (this->p_resetn);
400
401	for (int i = 0; i < 4; i++)
402	{
403	for(int k = 0; k < 3; k++)
404	{
405	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
406	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
407	}
408
409	for(int k = 0; k < 2; k++)
410	{
411	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
412	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
413	}
414	}
415
416	// local ports
417	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
418	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
419	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
420	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
421	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
422	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
423
424	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
425	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
426	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
427	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
428
429	///////////////////// CMD DSPIN local crossbar direct
430	int_xbar_d->p_clk (this->p_clk);
431	int_xbar_d->p_resetn (this->p_resetn);
432	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
433	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
434
435	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
436	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
437	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
438	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
439	for (size_t p = 0; p < nb_procs; p++)
440	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
441
442	if ( is_io )
443	{
444	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
445	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
446	}
447
448	int_wi_gate_d->p_clk (this->p_clk);
449	int_wi_gate_d->p_resetn (this->p_resetn);
450	int_wi_gate_d->p_vci (signal_int_vci_l2g);
451	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
452	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
453
454	int_wt_gate_d->p_clk (this->p_clk);
455	int_wt_gate_d->p_resetn (this->p_resetn);
456	int_wt_gate_d->p_vci (signal_int_vci_g2l);
457	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
458	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
459
460	////////////////////// M2P DSPIN local crossbar coherence
461	int_xbar_m2p_c->p_clk (this->p_clk);
462	int_xbar_m2p_c->p_resetn (this->p_resetn);
463	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
464	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
465	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
466	for (size_t p = 0; p < nb_procs; p++)
467	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
468
469	////////////////////////// P2M DSPIN local crossbar coherence
470	int_xbar_p2m_c->p_clk (this->p_clk);
471	int_xbar_p2m_c->p_resetn (this->p_resetn);
472	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
473	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
474	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
475	for (size_t p = 0; p < nb_procs; p++)
476	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
477
478	////////////////////// CLACK DSPIN local crossbar coherence
479	int_xbar_clack_c->p_clk (this->p_clk);
480	int_xbar_clack_c->p_resetn (this->p_resetn);
481	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
482	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
483	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
484	for (size_t p = 0; p < nb_procs; p++)
485	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
486
487	//////////////////////////////////// Processors
488	for (size_t p = 0; p < nb_procs; p++)
489	{
490	proc[p]->p_clk (this->p_clk);
491	proc[p]->p_resetn (this->p_resetn);
492	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
493	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
494	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
495	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
496
497	for ( size_t j = 0 ; j < 6 ; j++)
498	{
499	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
500	else proc[p]->p_irq[j] (signal_false);
501	}
502	}
503
504	///////////////////////////////////// XICU
505	xicu->p_clk (this->p_clk);
506	xicu->p_resetn (this->p_resetn);
507	xicu->p_vci (signal_int_vci_tgt_xicu);
508	for ( size_t i=0 ; i < xcu_nb_out ; i++)
509	{
510	xicu->p_irq[i] (signal_proc_it[i]);
511	}
512	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
513	{
514	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
515	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
516	else xicu->p_hwi[i] (signal_false);
517	}
518
519	///////////////////////////////////// MEMC
520	memc->p_clk (this->p_clk);
521	memc->p_resetn (this->p_resetn);
522	memc->p_vci_ixr (signal_ram_vci_ini_memc);
523	memc->p_vci_tgt (signal_int_vci_tgt_memc);
524	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
525	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
526	memc->p_dspin_clack (signal_int_dspin_clack_memc);
527	memc->p_irq (signal_irq_memc);
528
529	// wrapper to RAM network
530	memc_ram_wi->p_clk (this->p_clk);
531	memc_ram_wi->p_resetn (this->p_resetn);
532	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
533	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
534	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
535
536	//////////////////////////////////// XRAM
537	xram->p_clk (this->p_clk);
538	xram->p_resetn (this->p_resetn);
539	xram->p_vci (signal_ram_vci_tgt_xram);
540
541	// wrapper to RAM network
542	xram_ram_wt->p_clk (this->p_clk);
543	xram_ram_wt->p_resetn (this->p_resetn);
544	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
545	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
546	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
547
548	/////////////////////////////////// MDMA
549	mdma->p_clk (this->p_clk);
550	mdma->p_resetn (this->p_resetn);
551	mdma->p_vci_target (signal_int_vci_tgt_mdma);
552	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
553	for (size_t i=0 ; i<nb_dmas ; i++)
554	mdma->p_irq[i] (signal_irq_mdma[i]);
555
556	//////////////////////////// RAM network CMD & RSP routers
557	ram_router_cmd->p_clk (this->p_clk);
558	ram_router_cmd->p_resetn (this->p_resetn);
559	ram_router_rsp->p_clk (this->p_clk);
560	ram_router_rsp->p_resetn (this->p_resetn);
561	for( size_t n=0 ; n<4 ; n++)
562	{
563	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
564	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
565	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
566	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
567	}
568
569	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
570	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
571
572	if ( is_io )
573	{
574	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
575	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
576	}
577	else
578	{
579	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
580	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
581	}
582
583	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
584	if ( is_io )
585	{
586	// IO bridge
587	iob->p_clk (this->p_clk);
588	iob->p_resetn (this->p_resetn);
589	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
590	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
591	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
592	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
593	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
594
595	// initiator wrapper to RAM network
596	iob_ram_wi->p_clk (this->p_clk);
597	iob_ram_wi->p_resetn (this->p_resetn);
598	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
599	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
600	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
601
602	// crossbar between MEMC and IOB to RAM network
603	ram_xbar_cmd->p_clk (this->p_clk);
604	ram_xbar_cmd->p_resetn (this->p_resetn);
605	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
606	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
607	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
608	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
609
610	ram_xbar_rsp->p_clk (this->p_clk);
611	ram_xbar_rsp->p_resetn (this->p_resetn);
612	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
613	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
614	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
615	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
616	}
617
618	SC_METHOD(init);
619
620	} // end constructor
621
622	tmpl(void)::init()
623	{
624	signal_ram_dspin_cmd_false.write = false;
625	signal_ram_dspin_rsp_false.read = true;
626	} // end init
627
628	}}
629
630
631	// Local Variables:
632	// tab-width: 3
633	// c-basic-offset: 3
634	// c-file-offsets:((innamespace . 0)(inline-open . 0))
635	// indent-tabs-mode: nil
636	// End:
637
638	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
639

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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