| [345] | 1 | |
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| 2 | # -*- python -*- |
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| 3 | |
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| [437] | 4 | Module('caba:tsar_xbar_cluster', |
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| [779] | 5 | classname = 'soclib::caba::TsarXbarCluster', |
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| 6 | tmpl_parameters = [ |
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| 7 | parameter.Int('dspin_cmd_width'), |
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| 8 | parameter.Int('dspin_rsp_width'), |
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| [437] | 9 | parameter.Module('vci_param_int', default = 'caba:vci_param', |
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| [779] | 10 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 11 | parameter.Module('vci_param_ext', default = 'caba:vci_param', |
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| [779] | 12 | cell_size = parameter.Reference('vci_data_width_ext')), |
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| [437] | 13 | ], |
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| [428] | 14 | |
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| [779] | 15 | header_files = [ '../source/include/tsar_xbar_cluster.h', ], |
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| [396] | 16 | |
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| [779] | 17 | implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], |
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| [396] | 18 | |
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| [779] | 19 | uses = [ |
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| 20 | Uses('caba:base_module'), |
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| 21 | Uses('common:mapping_table'), |
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| 22 | Uses('common:iss2'), |
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| [396] | 23 | |
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| [779] | 24 | Uses('caba:vci_cc_vcache_wrapper', |
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| 25 | cell_size = parameter.Reference('vci_data_width_int'), |
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| 26 | dspin_in_width = parameter.Reference('dspin_cmd_width'), |
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| 27 | dspin_out_width = parameter.Reference('dspin_rsp_width'), |
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| 28 | iss_t = 'common:gdb_iss', |
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| 29 | gdb_iss_t = 'common:mips32el'), |
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| [396] | 30 | |
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| [779] | 31 | Uses('caba:vci_mem_cache', |
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| 32 | memc_cell_size_int = parameter.Reference('vci_data_width_int'), |
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| 33 | memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), |
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| [836] | 34 | memc_dspin_in_width = parameter.Reference('dspin_rsp_width'), |
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| 35 | memc_dspin_out_width = parameter.Reference('dspin_cmd_width')), |
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| [437] | 36 | |
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| [779] | 37 | Uses('caba:vci_simple_rom', |
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| 38 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 39 | |
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| [779] | 40 | Uses('caba:vci_simple_ram', |
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| 41 | cell_size = parameter.Reference('vci_data_width_ext')), |
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| [437] | 42 | |
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| [779] | 43 | Uses('caba:vci_simple_ram', |
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| 44 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [547] | 45 | |
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| [779] | 46 | Uses('caba:vci_xicu', |
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| 47 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [706] | 48 | |
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| [779] | 49 | Uses('caba:vci_local_crossbar', |
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| 50 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 51 | |
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| [779] | 52 | Uses('caba:dspin_local_crossbar', |
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| 53 | flit_width = parameter.Reference('dspin_cmd_width')), |
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| [437] | 54 | |
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| [779] | 55 | Uses('caba:dspin_local_crossbar', |
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| 56 | flit_width = parameter.Reference('dspin_rsp_width')), |
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| [437] | 57 | |
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| [885] | 58 | Uses('caba:dspin_router', |
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| [779] | 59 | flit_width = parameter.Reference('dspin_cmd_width')), |
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| [468] | 60 | |
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| [885] | 61 | Uses('caba:dspin_router', |
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| [779] | 62 | flit_width = parameter.Reference('dspin_rsp_width')), |
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| [437] | 63 | |
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| [779] | 64 | Uses('caba:vci_multi_tty', |
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| 65 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 66 | |
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| [779] | 67 | Uses('caba:vci_framebuffer', |
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| 68 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 69 | |
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| [779] | 70 | Uses('caba:vci_multi_nic', |
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| 71 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [475] | 72 | |
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| [779] | 73 | Uses('caba:vci_chbuf_dma', |
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| 74 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 75 | |
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| [779] | 76 | Uses('caba:vci_block_device_tsar', |
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| 77 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 78 | |
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| [779] | 79 | Uses('caba:vci_multi_dma', |
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| 80 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [437] | 81 | |
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| [779] | 82 | Uses('caba:vci_dspin_target_wrapper', |
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| 83 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [396] | 84 | |
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| [779] | 85 | Uses('caba:vci_dspin_initiator_wrapper', |
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| 86 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [396] | 87 | |
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| [779] | 88 | Uses('caba:vci_simhelper', |
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| 89 | cell_size = parameter.Reference('vci_data_width_int')), |
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| [547] | 90 | |
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| [779] | 91 | Uses('common:elf_file_loader'), |
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| 92 | ], |
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| [345] | 93 | |
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| [779] | 94 | ports = [ |
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| 95 | Port('caba:bit_in', 'p_resetn', auto = 'resetn'), |
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| 96 | Port('caba:clock_in', 'p_clk', auto = 'clock'), |
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| [885] | 97 | |
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| 98 | Port('caba:dspin_output', 'p_cmd_out', [4], |
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| 99 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| 100 | Port('caba:dspin_input', 'p_cmd_in', [4], |
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| 101 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| 102 | |
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| 103 | Port('caba:dspin_output', 'p_rsp_out', [4], |
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| 104 | dspin_data_size = parameter.Reference('dspin_rsp_width')), |
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| 105 | Port('caba:dspin_input', 'p_rsp_in', [4], |
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| 106 | dspin_data_size = parameter.Reference('dspin_rsp_width')), |
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| 107 | |
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| 108 | Port('caba:dspin_output', 'p_m2p_out', [4], |
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| 109 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| 110 | Port('caba:dspin_input', 'p_m2p_in', [4], |
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| 111 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| 112 | |
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| 113 | Port('caba:dspin_output', 'p_p2m_out', [4], |
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| 114 | dspin_data_size = parameter.Reference('dspin_rsp_width')), |
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| 115 | Port('caba:dspin_input', 'p_p2m_in', [4], |
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| 116 | dspin_data_size = parameter.Reference('dspin_rsp_width')), |
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| 117 | |
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| 118 | Port('caba:dspin_output', 'p_cla_out', [4], |
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| 119 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| 120 | Port('caba:dspin_input', 'p_cla_in', [4], |
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| 121 | dspin_data_size = parameter.Reference('dspin_cmd_width')), |
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| [779] | 122 | ], |
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| [885] | 123 | ) |
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| [437] | 124 | |
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| [779] | 125 | |
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